diff --git a/src/sst/elements/ariel/frontend/simple/examples/multicore.py b/src/sst/elements/ariel/frontend/simple/examples/multicore.py index d9dc09e316..1669b1a280 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/multicore.py +++ b/src/sst/elements/ariel/frontend/simple/examples/multicore.py @@ -46,7 +46,7 @@ "L1" : 1, } ) ariel_l1d_link = sst.Link("cpu_cache_link_" + str(x)) - ariel_l1d_link.connect( (ariel, "cache_link_" + str(x), "50ps"), (l1d, "high_network_0", "50ps") ) + ariel_l1d_link.connect( (ariel, "cache_link_" + str(x), "50ps"), (l1d, "highlink", "50ps") ) # Private L2s # 128KB, 8-way set associative, 64B line, 5 cycle access @@ -63,10 +63,10 @@ }) l1d_l2_link = sst.Link("l1_l2_link_" + str(x)) - l1d_l2_link.connect( (l1d, "low_network_0", "50ps"), (l2, "high_network_0", "50ps") ) + l1d_l2_link.connect( (l1d, "lowlink", "50ps"), (l2, "highlink", "50ps") ) l2_bus_link = sst.Link("l2_bus_link_" + str(x)) - l2_bus_link.connect( (l2, "low_network_0", "50ps"), (membus, "high_network_" + str(x), "50ps") ) + l2_bus_link.connect( (l2, "lowlink", "50ps"), (membus, "highlink" + str(x), "50ps") ) # Shared L3 # 1MB*cores, 16-way set associative, 64B line, 15 cycle access @@ -83,7 +83,7 @@ } ) l3_bus_link = sst.Link("l3_bus_link") -l3_bus_link.connect( (l3, "high_network_0", "50ps"), (membus, "low_network_0", "50ps") ) +l3_bus_link.connect( (l3, "highlink", "50ps"), (membus, "lowlink0", "50ps") ) # Memory/Controller # Using "simpleMem" memory model @@ -97,6 +97,6 @@ }) memory_bus_link = sst.Link("memory_bus_link") -memory_bus_link.connect( (l3, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +memory_bus_link.connect( (l3, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) print("Done configuring SST model") diff --git a/src/sst/elements/ariel/frontend/simple/examples/opal/mlm_test.py b/src/sst/elements/ariel/frontend/simple/examples/opal/mlm_test.py index 9fce1454af..444056e404 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/opal/mlm_test.py +++ b/src/sst/elements/ariel/frontend/simple/examples/opal/mlm_test.py @@ -288,15 +288,18 @@ } dc_params = { - "memNIC.interleave_size": str(mem_interleave_size) + "B", - "memNIC.interleave_step": str((groups * memory_controllers_per_group) * (mem_interleave_size)) + "B", "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize "clock": memory_clock, - "memNIC.network_bw": ring_bandwidth, + "interleave_size": str(mem_interleave_size) + "B", + "interleave_step": str((groups * memory_controllers_per_group) * (mem_interleave_size)) + "B", # Default params # "coherence_protocol": coherence_protocol, } +nic_params = { + "network_bw": ring_bandwidth, +} + router_map = {} print("Configuring Ring Network-on-Chip...") @@ -340,9 +343,12 @@ l3cache.addParams({ "slice_id" : str(next_l3_cache_id) }) + l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l3_nic.addParams(nic_params) + l3_nic.addParam("group", 2) l3_ring_link = sst.Link("l3_" + str(next_l3_cache_id) + "_link") - l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) ) + l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) ) next_l3_cache_id = next_l3_cache_id + 1 next_network_id = next_network_id + 1 @@ -365,13 +371,17 @@ l2.addParams(l2_params) else: l2.addParams(l2_dummy_params) + + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) #l2.addParams(l2_prefetch_params) ''' arielL1Link = sst.Link("cpu_cache_link_" + str(next_core_id)) - arielL1Link.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + arielL1Link.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielL1Link.setNoCut() ''' @@ -387,23 +397,23 @@ if next_core_id < cores_per_group*groups//2: arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) ArielOpalLink.connect((ariel, "opal_link_%d"%next_core_id, ring_latency), (opal, "requestLink%d"%(next_core_id + cores_per_group*groups//2), ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) PTWOpalLink.connect( (mmu, "ptw_to_opal%d"%next_core_id, "50ps"), (opal, "requestLink%d"%next_core_id, "50ps") ) arielMMULink.setNoCut() PTWOpalLink.setNoCut() MMUCacheLink.setNoCut() else: - PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core_id-cores_per_group*groups//2), ring_latency), (l1, "high_network_0", ring_latency)) + PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core_id-cores_per_group*groups//2), ring_latency), (l1, "highlink", ring_latency)) #''' l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_core_link.setNoCut() l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -417,9 +427,13 @@ l3cache.addParams({ "slice_id" : str(next_l3_cache_id) }) + + l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l3_nic.addParams(nic_params) + l3_nic.addParam("group", 2) l3_ring_link = sst.Link("l3_" + str(next_l3_cache_id) + "_link") - l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) ) + l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency) ) next_l3_cache_id = next_l3_cache_id + 1 next_network_id = next_network_id + 1 @@ -429,6 +443,10 @@ mem = sst.Component("memory_" + str(next_memory_ctrl_id), "memHierarchy.MemController") mem.addParams(mem_params) + mem.addParams({ + "addr_range_start" : next_memory_ctrl_id * mem_interleave_size, + "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size) + }) messier_inst = sst.Component("NVMmemory_" + str(next_memory_ctrl_id), "Messier") messier_inst.addParams(messier_params) @@ -439,17 +457,20 @@ dc = sst.Component("dc_" + str(next_memory_ctrl_id), "memHierarchy.DirectoryController") dc.addParams({ - "memNIC.addr_range_start" : next_memory_ctrl_id * mem_interleave_size, - "memNIC.addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size) + "addr_range_start" : next_memory_ctrl_id * mem_interleave_size, + "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size) }) dc.addParams(dc_params) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams(nic_params) + dc_nic.addParam("group", 3) memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id)) - memLink.connect((mem, "direct_link", ring_latency), (dc, "memory", ring_latency)) + memLink.connect((mem, "highlink", ring_latency), (dc, "lowlink", ring_latency)) netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id)) - netLink.connect((dc, "network", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency)) + netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr." + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_memory_ctrl_id = next_memory_ctrl_id + 1 diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_ivb.py b/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_ivb.py index c1e0544271..36bbf449ee 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_ivb.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_ivb.py @@ -116,7 +116,6 @@ dc_params = { "coherence_protocol": coherence_protocol, - "memNIC.network_bw": memory_network_bandwidth, "interleave_size": str(mem_interleave_size) + "B", "interleave_step": str((groups * memory_controllers_per_group) * mem_interleave_size) + "B", "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize @@ -124,6 +123,8 @@ "debug": 1, } +nic_params = { "network_bw" : memory_network_bandwidth } + print("Configuring Ariel processor model (" + str(groups * cores_per_group) + " cores)...") ariel = sst.Component("A0", "ariel.ariel") @@ -186,15 +187,18 @@ l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache") l2.addParams(l2_params) l2.addParams(l1_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) - ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) + ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -209,15 +213,18 @@ l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache") l2.addParams(l2_params) l2.addParams(l2_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) - ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) + ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -231,9 +238,13 @@ l3cache.addParams({ "slice_id" : str((next_group * l3cache_blocks_per_group) + next_l3_cache_block) }) + + l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l3_nic.addParams(nic_params) + l3_nic.addParam("group", 2) l3_ring_link = sst.Link("l3_ring_link_" + str((next_group * l3cache_blocks_per_group) + next_l3_cache_block)) - l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) ) + l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) ) next_network_id = next_network_id + 1 @@ -255,12 +266,15 @@ "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size) }) dc.addParams(dc_params) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams(nic_params) + dc_nic.addParam("group", 3) memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id)) - memLink.connect((memctrl, "direct_link", ring_latency), (dc, "memory", ring_latency)) + memLink.connect((memctrl, "highlink", ring_latency), (dc, "lowlink", ring_latency)) netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id)) - netLink.connect((dc, "network", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_memory_ctrl_id = next_memory_ctrl_id + 1 diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb.py b/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb.py index 6a89c9882a..32d9c0afbf 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb.py @@ -115,7 +115,6 @@ dc_params = { "coherence_protocol": coherence_protocol, - "memNIC.network_bw": memory_network_bandwidth, "interleave_size": str(mem_interleave_size) + "B", "interleave_step": str((groups * memory_controllers_per_group) * mem_interleave_size) + "B", "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize @@ -123,6 +122,10 @@ "debug": 1, } +nic_params = { + "network_bw": memory_network_bandwidth, + } + print("Configuring Ariel processor model (" + str(groups * cores_per_group) + " cores)...") ariel = sst.Component("A0", "ariel.ariel") @@ -182,15 +185,18 @@ l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache") l2.addParams(l2_params) l2.addParams(l1_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) - ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) + ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -205,15 +211,18 @@ l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache") l2.addParams(l2_params) l2.addParams(l2_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) - ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) + ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -227,9 +236,12 @@ l3cache.addParams({ "slice_id" : str((next_group * l3cache_blocks_per_group) + next_l3_cache_block) }) + l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l3_nic.addParams(nic_params) + l3_nic.addParam("group", 2) l3_ring_link = sst.Link("l3_ring_link_" + str((next_group * l3cache_blocks_per_group) + next_l3_cache_block)) - l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) ) + l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) ) next_network_id = next_network_id + 1 @@ -251,12 +263,15 @@ "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size) }) dc.addParams(dc_params) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams(nic_params) + dc_nic.addParam("group", 3) memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id)) - memLink.connect((memctrl, "direct_link", ring_latency), (dc, "memory", ring_latency)) + memLink.connect((memctrl, "highlink", ring_latency), (dc, "lowlink", ring_latency)) netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id)) - netLink.connect((dc, "network", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_memory_ctrl_id = next_memory_ctrl_id + 1 diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb_mlm.py b/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb_mlm.py index 5f931e0573..77c9b9c2c3 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb_mlm.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/ariel_snb_mlm.py @@ -116,7 +116,6 @@ dc_params = { "coherence_protocol": coherence_protocol, - "memNIC.network_bw": memory_network_bandwidth, "interleave_size": str(mem_interleave_size) + "B", "interleave_step": str((groups * memory_controllers_per_group) * mem_interleave_size) + "B", "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize @@ -124,6 +123,10 @@ "debug": 1, } +nic_params = { + "network_bw": memory_network_bandwidth, + } + print("Configuring Ariel processor model (" + str(groups * cores_per_group) + " cores)...") ariel = sst.Component("A0", "ariel.ariel") @@ -187,15 +190,18 @@ l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache") l2.addParams(l2_params) l2.addParams(l1_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) - ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) + ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -210,15 +216,18 @@ l2 = sst.Component("l2cache_" + str(next_core_id), "memHierarchy.Cache") l2.addParams(l2_params) l2.addParams(l2_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams(nic_params) + l2_nic.addParam("group", 1) ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) - ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) + ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) l2_core_link = sst.Link("l2cache_" + str(next_core_id) + "_link") - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highlink", ring_latency)) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core_id)) - l2_ring_link.connect((l2, "cache", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_core_id = next_core_id + 1 @@ -232,9 +241,12 @@ l3cache.addParams({ "slice_id" : str((next_group * l3cache_blocks_per_group) + next_l3_cache_block) }) + l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l3_nic.addParams(nic_params) + l3_nic.addParam("group", 2) l3_ring_link = sst.Link("l3_ring_link_" + str((next_group * l3cache_blocks_per_group) + next_l3_cache_block)) - l3_ring_link.connect( (l3cache, "directory", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) ) + l3_ring_link.connect( (l3_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency) ) next_network_id = next_network_id + 1 @@ -257,12 +269,15 @@ "addr_range_end" : (memory_capacity * 1024 * 1024) - (groups * memory_controllers_per_group * mem_interleave_size) + (next_memory_ctrl_id * mem_interleave_size) }) dc.addParams(dc_params) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams(nic_params) + dc_nic.addParam("group", 3) memLink = sst.Link("mem_link_" + str(next_memory_ctrl_id)) - memLink.connect((mem, "direct_link", ring_latency), (dc, "memory", ring_latency)) + memLink.connect((mem, "highlink", ring_latency), (dc, "lowlink", ring_latency)) netLink = sst.Link("dc_link_" + str(next_memory_ctrl_id)) - netLink.connect((dc, "network", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) + netLink.connect((dc_nic, "port", ring_latency), (router_map["rtr_" + str(next_network_id)], "port2", ring_latency)) next_network_id = next_network_id + 1 next_memory_ctrl_id = next_memory_ctrl_id + 1 diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/memHstream.py b/src/sst/elements/ariel/frontend/simple/examples/stream/memHstream.py index 44ea262521..a69c448797 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/memHstream.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/memHstream.py @@ -148,11 +148,11 @@ def genMemHierarchy(cores): ## SST Links # Ariel -> L1(PRIVATE) -> L2(PRIVATE) -> L3 (SHARED) -> DRAM ArielL1Link = sst.Link("cpu_cache_%d"%core) - ArielL1Link.connect((ariel, "cache_link_%d"%core, busLat), (l1, "high_network_0", busLat)) + ArielL1Link.connect((ariel, "cache_link_%d"%core, busLat), (l1, "highlink", busLat)) L1L2Link = sst.Link("l1_l2_%d"%core) - L1L2Link.connect((l1, "low_network_0", busLat), (l2, "high_network_0", busLat)) + L1L2Link.connect((l1, "lowlink", busLat), (l2, "highlink", busLat)) L2MembusLink = sst.Link("l2_membus_%d"%core) - L2MembusLink.connect((l2, "low_network_0", busLat), (membus, "high_network_%d"%core, busLat)) + L2MembusLink.connect((l2, "lowlink", busLat), (membus, "highlink%d"%core, busLat)) l3 = sst.Component("L3cache", "memHierarchy.Cache") @@ -174,9 +174,9 @@ def genMemHierarchy(cores): # Bus to L3 and L3 <-> MM BusL3Link = sst.Link("bus_L3") - BusL3Link.connect((membus, "low_network_0", busLat), (l3, "high_network_0", busLat)) + BusL3Link.connect((membus, "lowlink0", busLat), (l3, "highlink", busLat)) L3MemCtrlLink = sst.Link("L3MemCtrl") - L3MemCtrlLink.connect((l3, "low_network_0", busLat), (memctrl, "direct_link", busLat)) + L3MemCtrlLink.connect((l3, "lowlink", busLat), (memctrl, "highlink", busLat)) genMemHierarchy(corecount) diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/runstream.py b/src/sst/elements/ariel/frontend/simple/examples/stream/runstream.py index a103317927..5b67c44b92 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/runstream.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/runstream.py @@ -55,10 +55,10 @@ }) cpu_cache_link = sst.Link("cpu_cache_link") -cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "high_network_0", "50ps") ) +cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "highlink", "50ps") ) memory_link = sst.Link("mem_bus_link") -memory_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +memory_link.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) # Set the Statistic Load Level; Statistics with Enable Levels (set in diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamNB.py b/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamNB.py index dc56f99559..a227a62aa0 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamNB.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamNB.py @@ -53,10 +53,10 @@ "mem_size" : "2048MiB", }) cpu_cache_link = sst.Link("cpu_cache_link") -cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "high_network_0", "50ps") ) +cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "highlink", "50ps") ) memory_link = sst.Link("mem_bus_link") -memory_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +memory_link.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) # Set the Statistic Load Level; Statistics with Enable Levels (set in # elementInfoStatistic) lower or equal to the load can be enabled (default = 0) diff --git a/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamSt.py b/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamSt.py index c0672502d3..74bf79202c 100644 --- a/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamSt.py +++ b/src/sst/elements/ariel/frontend/simple/examples/stream/runstreamSt.py @@ -59,10 +59,10 @@ }) cpu_cache_link = sst.Link("cpu_cache_link") -cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "high_network_0", "50ps") ) +cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "highlink", "50ps") ) memory_link = sst.Link("mem_bus_link") -memory_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +memory_link.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) # Set the Statistic Load Level; Statistics with Enable Levels (set in # elementInfoStatistic) lower or equal to the load can be enabled (default = 0) diff --git a/src/sst/elements/ariel/tests/testIO/runtestio.py b/src/sst/elements/ariel/tests/testIO/runtestio.py index 1deacc413e..4d70b83862 100644 --- a/src/sst/elements/ariel/tests/testIO/runtestio.py +++ b/src/sst/elements/ariel/tests/testIO/runtestio.py @@ -81,10 +81,10 @@ }) cpu_cache_link = sst.Link("cpu_cache_link") -cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "high_network_0", "50ps") ) +cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cache, "highlink", "50ps") ) memory_link = sst.Link("mem_bus_link") -memory_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +memory_link.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) # Set the Statistic Load Level; Statistics with Enable Levels (set in diff --git a/src/sst/elements/ariel/tests/testMPI/ariel-reduce.py b/src/sst/elements/ariel/tests/testMPI/ariel-reduce.py index 356feb82b5..64b7441d35 100644 --- a/src/sst/elements/ariel/tests/testMPI/ariel-reduce.py +++ b/src/sst/elements/ariel/tests/testMPI/ariel-reduce.py @@ -100,9 +100,9 @@ ######################################################################### ## Connect components with the links ######################################################################### -[core_cache[i].connect( (core, "cache_link_"+str(i), "100ps"), (cache[i], "high_network_0", "100ps") ) for i in range(ncores)] -[cache_bus[i].connect( (cache[i], "low_network_0", "100ps"), (bus, "high_network_"+str(i), "100ps") ) for i in range(ncores)] -bus_mem.connect( (bus, "low_network_0", "100ps"), (memctrl, "direct_link", "100ps") ) +[core_cache[i].connect( (core, "cache_link_"+str(i), "100ps"), (cache[i], "highlink", "100ps") ) for i in range(ncores)] +[cache_bus[i].connect( (cache[i], "lowlink", "100ps"), (bus, "highlink"+str(i), "100ps") ) for i in range(ncores)] +bus_mem.connect( (bus, "lowlink0", "100ps"), (memctrl, "highlink", "100ps") ) sst.setStatisticOutput("sst.statoutputtxt") diff --git a/src/sst/elements/ariel/tests/testMPI/demo1.py b/src/sst/elements/ariel/tests/testMPI/demo1.py index e5d3871d63..1f01b2e26f 100644 --- a/src/sst/elements/ariel/tests/testMPI/demo1.py +++ b/src/sst/elements/ariel/tests/testMPI/demo1.py @@ -84,9 +84,9 @@ ######################################################################### ## Connect components with the links ######################################################################### -[core_cache[i].connect( (core, "cache_link_"+str(i), "100ps"), (cache[i], "high_network_0", "100ps") ) for i in range(ncores)] -[cache_bus[i].connect( (cache[i], "low_network_0", "100ps"), (bus, "high_network_"+str(i), "100ps") ) for i in range(ncores)] -bus_mem.connect( (bus, "low_network_0", "100ps"), (memctrl, "direct_link", "100ps") ) +[core_cache[i].connect( (core, "cache_link_"+str(i), "100ps"), (cache[i], "highlink", "100ps") ) for i in range(ncores)] +[cache_bus[i].connect( (cache[i], "lowlink", "100ps"), (bus, "highlink"+str(i), "100ps") ) for i in range(ncores)] +bus_mem.connect( (bus, "lowlink0", "100ps"), (memctrl, "highlink", "100ps") ) sst.setStatisticOutput("sst.statoutputtxt") diff --git a/src/sst/elements/ariel/tests/testMPI/test-mpi.py b/src/sst/elements/ariel/tests/testMPI/test-mpi.py index 8ddad8a1cc..470f5affb8 100644 --- a/src/sst/elements/ariel/tests/testMPI/test-mpi.py +++ b/src/sst/elements/ariel/tests/testMPI/test-mpi.py @@ -125,9 +125,9 @@ ######################################################################### ## Connect components with the links ######################################################################### -[core_cache[i].connect( (core, "cache_link_"+str(i), "100ps"), (cache[i], "high_network_0", "100ps") ) for i in range(ncores)] -[cache_bus[i].connect( (cache[i], "low_network_0", "100ps"), (bus, "high_network_"+str(i), "100ps") ) for i in range(ncores)] -bus_mem.connect( (bus, "low_network_0", "100ps"), (memctrl, "direct_link", "100ps") ) +[core_cache[i].connect( (core, "cache_link_"+str(i), "100ps"), (cache[i], "highlink", "100ps") ) for i in range(ncores)] +[cache_bus[i].connect( (cache[i], "lowlink", "100ps"), (bus, "highlink"+str(i), "100ps") ) for i in range(ncores)] +bus_mem.connect( (bus, "lowlink0", "100ps"), (memctrl, "highlink", "100ps") ) ######################################################################### ## Define SST core options diff --git a/src/sst/elements/cacheTracer/tests/test_cacheTracer_1.py b/src/sst/elements/cacheTracer/tests/test_cacheTracer_1.py index 18ed93f45a..f3f3f355a9 100644 --- a/src/sst/elements/cacheTracer/tests/test_cacheTracer_1.py +++ b/src/sst/elements/cacheTracer/tests/test_cacheTracer_1.py @@ -78,14 +78,14 @@ # define the simulation links link_cpu_tracer = sst.Link("link_cpu_tracer") -link_cpu_tracer.connect((iface, "port", "100ps"), (comp_tracer, "northBus", "100ps")) +link_cpu_tracer.connect((iface, "lowlink", "100ps"), (comp_tracer, "northBus", "100ps")) link_tracer_l1cache = sst.Link("link_tracer_l1cache") -link_tracer_l1cache.connect((comp_tracer, "southBus", "100ps"), (comp_l1cache, "high_network_0", "100ps")) +link_tracer_l1cache.connect((comp_tracer, "southBus", "100ps"), (comp_l1cache, "highlink", "100ps")) link_l1cache_l2cache = sst.Link("link_l1cache_l2cache") -link_l1cache_l2cache.connect((comp_l1cache, "low_network_0", "100ps"), (comp_l2cache, "high_network_0", "100ps")) +link_l1cache_l2cache.connect((comp_l1cache, "lowlink", "100ps"), (comp_l2cache, "highlink", "100ps")) link_l2cache_mem = sst.Link("link_l2cache_mem") -link_l2cache_mem.connect((comp_l2cache, "low_network_0", "100ps"), (comp_memory, "direct_link", "100ps")) +link_l2cache_mem.connect((comp_l2cache, "lowlink", "100ps"), (comp_memory, "highlink", "100ps")) diff --git a/src/sst/elements/cacheTracer/tests/test_cacheTracer_2.py b/src/sst/elements/cacheTracer/tests/test_cacheTracer_2.py index 2fa96ef83a..20fec3bb69 100644 --- a/src/sst/elements/cacheTracer/tests/test_cacheTracer_2.py +++ b/src/sst/elements/cacheTracer/tests/test_cacheTracer_2.py @@ -83,14 +83,14 @@ # define the simulation links link_cpu_l1cache = sst.Link("link_cpu_l1cache") -link_cpu_l1cache.connect((iface, "port", "100ps"),(comp_l1cache, "high_network_0", "100ps")) +link_cpu_l1cache.connect((iface, "lowlink", "100ps"),(comp_l1cache, "highlink", "100ps")) link_l1cache_l2cache = sst.Link("link_l1cache_l2cache") -link_l1cache_l2cache.connect((comp_l1cache, "low_network_0", "100ps"), (comp_l2cache, "high_network_0", "100ps")) +link_l1cache_l2cache.connect((comp_l1cache, "lowlink", "100ps"), (comp_l2cache, "highlink", "100ps")) link_l2cache_tracer = sst.Link("link_l2cache_tracer") -link_l2cache_tracer.connect((comp_l2cache, "low_network_0", "100ps"), (comp_tracer, "northBus", "100ps")) +link_l2cache_tracer.connect((comp_l2cache, "lowlink", "100ps"), (comp_tracer, "northBus", "100ps")) link_tracer_mem = sst.Link("link_tracer_mem") -link_tracer_mem.connect((comp_tracer, "southBus", "100ps"), (comp_memory, "direct_link", "100ps")) +link_tracer_mem.connect((comp_tracer, "southBus", "100ps"), (comp_memory, "highlink", "100ps")) diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out index 7706cc1614..8caca25747 100644 --- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out +++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nbp.out @@ -71,13 +71,16 @@ Completed @ 11134750 ns l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 89831; SumSQ.u64 = 89831; Count.u64 = 89831; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10169; SumSQ.u64 = 10169; Count.u64 = 10169; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -85,7 +88,7 @@ Completed @ 11134750 ns l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 7133; SumSQ.u64 = 7133; Count.u64 = 7133; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ Completed @ 11134750 ns l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 38117; SumSQ.u64 = 38117; Count.u64 = 38117; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 4213; SumSQ.u64 = 4213; Count.u64 = 4213; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -152,14 +156,18 @@ Completed @ 11134750 ns l1cache.Write_recv : Accumulator : Sum.u64 = 10169; SumSQ.u64 = 10169; Count.u64 = 10169; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 84125355; SumSQ.u64 = 679626559; Count.u64 = 22269500; Min.u64 = 0; Max.u64 = 11; diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out index c519606193..af5b3d0639 100644 --- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out +++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_nopf.out @@ -66,13 +66,16 @@ Completed @ 11524920 ns l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 89828; SumSQ.u64 = 89828; Count.u64 = 89828; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10172; SumSQ.u64 = 10172; Count.u64 = 10172; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -80,7 +83,7 @@ Completed @ 11524920 ns l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 7144; SumSQ.u64 = 7144; Count.u64 = 7144; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -99,6 +102,7 @@ Completed @ 11524920 ns l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 6120; SumSQ.u64 = 6120; Count.u64 = 6120; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -142,14 +146,18 @@ Completed @ 11524920 ns l1cache.Write_recv : Accumulator : Sum.u64 = 10172; SumSQ.u64 = 10172; Count.u64 = 10172; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 115283365; SumSQ.u64 = 807452637; Count.u64 = 23049840; Min.u64 = 0; Max.u64 = 10; diff --git a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out index 5b9b13792c..a33c6a5197 100644 --- a/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out +++ b/src/sst/elements/cassini/tests/refFiles/test_cassini_prefetch_sp.out @@ -72,13 +72,16 @@ Completed @ 11074943 ns l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 89847; SumSQ.u64 = 89847; Count.u64 = 89847; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10153; SumSQ.u64 = 10153; Count.u64 = 10153; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -86,7 +89,7 @@ Completed @ 11074943 ns l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 7115; SumSQ.u64 = 7115; Count.u64 = 7115; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ Completed @ 11074943 ns l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 10147; SumSQ.u64 = 10147; Count.u64 = 10147; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1146; SumSQ.u64 = 1146; Count.u64 = 1146; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -153,14 +157,18 @@ Completed @ 11074943 ns l1cache.Write_recv : Accumulator : Sum.u64 = 10153; SumSQ.u64 = 10153; Count.u64 = 10153; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 12500; SumSQ.u64 = 12500; Count.u64 = 12500; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 119147895; SumSQ.u64 = 867571311; Count.u64 = 22149886; Min.u64 = 0; Max.u64 = 12; diff --git a/src/sst/elements/cassini/tests/streamcpu-nbp.py b/src/sst/elements/cassini/tests/streamcpu-nbp.py index fae2aaf636..4ee8743a90 100644 --- a/src/sst/elements/cassini/tests/streamcpu-nbp.py +++ b/src/sst/elements/cassini/tests/streamcpu-nbp.py @@ -49,6 +49,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/cassini/tests/streamcpu-nopf.py b/src/sst/elements/cassini/tests/streamcpu-nopf.py index c7b3b0b4bf..e0be7fe0f7 100644 --- a/src/sst/elements/cassini/tests/streamcpu-nopf.py +++ b/src/sst/elements/cassini/tests/streamcpu-nopf.py @@ -46,6 +46,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/cassini/tests/streamcpu-pp.py b/src/sst/elements/cassini/tests/streamcpu-pp.py index d5db7b0b4f..043ba2f749 100644 --- a/src/sst/elements/cassini/tests/streamcpu-pp.py +++ b/src/sst/elements/cassini/tests/streamcpu-pp.py @@ -46,6 +46,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/cassini/tests/streamcpu-sp.py b/src/sst/elements/cassini/tests/streamcpu-sp.py index 94328b9c40..7e498585e4 100644 --- a/src/sst/elements/cassini/tests/streamcpu-sp.py +++ b/src/sst/elements/cassini/tests/streamcpu-sp.py @@ -49,6 +49,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/cramSim/tests/ariel_cramsim.py b/src/sst/elements/cramSim/tests/ariel_cramsim.py index c94a8a2266..b1ef1fd04b 100644 --- a/src/sst/elements/cramSim/tests/ariel_cramsim.py +++ b/src/sst/elements/cramSim/tests/ariel_cramsim.py @@ -175,11 +175,11 @@ def genMemHierarchy(cores): ## SST Links # Ariel -> L1(PRIVATE) -> L2(PRIVATE) -> L3 (SHARED) -> DRAM ArielL1Link = sst.Link("cpu_cache_%d"%core) - ArielL1Link.connect((ariel, "cache_link_%d"%core, busLat), (l1, "high_network_0", busLat)) + ArielL1Link.connect((ariel, "cache_link_%d"%core, busLat), (l1, "highlink", busLat)) L1L2Link = sst.Link("l1_l2_%d"%core) - L1L2Link.connect((l1, "low_network_0", busLat), (l2, "high_network_0", busLat)) + L1L2Link.connect((l1, "lowlink", busLat), (l2, "highlink", busLat)) L2MembusLink = sst.Link("l2_membus_%d"%core) - L2MembusLink.connect((l2, "low_network_0", busLat), (membus, "high_network_%d"%core, busLat)) + L2MembusLink.connect((l2, "lowlink", busLat), (membus, "highlink%d"%core, busLat)) l3 = sst.Component("L3cache", "memHierarchy.Cache") @@ -199,9 +199,9 @@ def genMemHierarchy(cores): # Bus to L3 and L3 <-> MM BusL3Link = sst.Link("bus_L3") - BusL3Link.connect((membus, "low_network_0", busLat), (l3, "high_network_0", busLat)) + BusL3Link.connect((membus, "lowlink0", busLat), (l3, "highlink", busLat)) L3MemCtrlLink = sst.Link("L3MemCtrl") - L3MemCtrlLink.connect((l3, "low_network_0", busLat), (memory, "direct_link", busLat)) + L3MemCtrlLink.connect((l3, "lowlink", busLat), (memory, "highlink", busLat)) # txn gen --> memHierarchy Bridge comp_memhBridge = sst.Component("memh_bridge", "cramSim.c_MemhBridge") diff --git a/src/sst/elements/ember/run/configurations/3LevelModel.py b/src/sst/elements/ember/run/configurations/3LevelModel.py index a5398da62a..cf50e0ebb6 100644 --- a/src/sst/elements/ember/run/configurations/3LevelModel.py +++ b/src/sst/elements/ember/run/configurations/3LevelModel.py @@ -43,11 +43,11 @@ def _createThreads(self, prefix, bus, numThreads, cpu_params, l1_params ): link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_" + str(i),"1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink" + str(i),"1000ps") ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -68,11 +68,11 @@ def _createNic( self, prefix, bus, num, cpu_params, l1_params ): link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_" + str(num),"1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink" + str(num),"1000ps") ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -102,7 +102,7 @@ def build(self,nodeID,ransPerNode): # Connect L3 to Memory link = sst.Link( prefix + "l3_mem_link") link.setNoCut(); - link.connect( (l3, "low_network_0", "50ps"), (memory, "direct_link", "50ps") ) + link.connect( (l3, "lowlink", "50ps"), (memory, "highlink", "50ps") ) # Create L2 @@ -112,7 +112,7 @@ def build(self,nodeID,ransPerNode): # Connect L2 to L3 link = sst.Link( prefix + "l2_l3_link") link.setNoCut(); - link.connect( (l2, "low_network_0", "50ps"), (l3, "high_network_0", "50ps") ) + link.connect( (l2, "lowlink", "50ps"), (l3, "highlink", "50ps") ) # Create Bus bus = sst.Component( prefix + "bus", "memHierarchy.Bus") @@ -121,7 +121,7 @@ def build(self,nodeID,ransPerNode): # Connect Bus to L2 link = sst.Link( prefix + "bus_l2_link") link.setNoCut(); - link.connect( (bus, "low_network_0", "50ps"), (l2, "high_network_0", "50ps") ) + link.connect( (bus, "lowlink0", "50ps"), (l2, "highlink", "50ps") ) for i in range(ransPerNode): name = prefix + "core" + str(i) + "_" diff --git a/src/sst/elements/ember/run/configurations/basicDetailedModel.py b/src/sst/elements/ember/run/configurations/basicDetailedModel.py index 3fa0a68e58..9e36b407cb 100644 --- a/src/sst/elements/ember/run/configurations/basicDetailedModel.py +++ b/src/sst/elements/ember/run/configurations/basicDetailedModel.py @@ -40,11 +40,11 @@ def _createThreads(self, prefix, bus, numThreads, cpu_params, l1_params ): link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_" + str(i),"1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink" + str(i),"1000ps") ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -64,11 +64,11 @@ def _createNic( self, prefix, bus, num, cpu_params, l1_params ): link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_" + str(num),"1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink" + str(num),"1000ps") ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -97,11 +97,11 @@ def build(self,nodeID,ransPerNode): link = sst.Link( prefix + "bus_l2_link") link.setNoCut(); - link.connect( (bus, "low_network_0", "50ps"), (l2, "high_network_0", "50ps") ) + link.connect( (bus, "lowlink0", "50ps"), (l2, "highlink", "50ps") ) link = sst.Link( prefix + "l2_mem_link") link.setNoCut(); - link.connect( (l2, "low_network_0", "50ps"), (memory, "direct_link", "50ps") ) + link.connect( (l2, "lowlink", "50ps"), (memory, "highlink", "50ps") ) for i in range(ransPerNode): name = prefix + "core" + str(i) + "_" diff --git a/src/sst/elements/ember/run/configurations/snb.py b/src/sst/elements/ember/run/configurations/snb.py index 43f3edbad9..33468beeb0 100644 --- a/src/sst/elements/ember/run/configurations/snb.py +++ b/src/sst/elements/ember/run/configurations/snb.py @@ -53,26 +53,27 @@ def _configureL1L2(prefix, id, l1_params, l1_prefetch_params, l2_params, l2_pref name = prefix + "l2cache_" + id #print 'create', name l2 = sst.Component(name, "memHierarchy.Cache") - l2.addParams({ - "network_address" : network_id }) l2.addParams(l2_params) l2.addParams(l2_prefetch_params) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParam("group",1) + l2_nic.addParams("network_bw" : l2_params["network_bw"]) name = prefix + "l2cache_" + id+ "_link" #print 'create', name l2_core_link = sst.Link(name) - l2_core_link.connect((l1, "low_network_0", ring_latency), (l2, "high_network_0", ring_latency)) + l2_core_link.connect((l1, "lowlink", ring_latency), (l2, "highink", ring_latency)) name = prefix + "l2_ring_link_" + id #print 'create', name l2_ring_link = sst.Link(name) - l2_ring_link.connect((l2, "cache", ring_latency), (rtr, "port2", ring_latency)) + l2_ring_link.connect((l2_nic, "port", ring_latency), (rtr, "port2", ring_latency)) return l1 #ariel_cache_link = sst.Link("ariel_cache_link_" + str(next_core_id)) -#ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "high_network_0", ring_latency) ) +#ariel_cache_link.connect( (ariel, "cache_link_" + str(next_core_id), ring_latency), (l1, "highlink", ring_latency) ) def _configureL3( prefix, id, l3_params, network_id, ring_latency, rtr ): @@ -83,14 +84,16 @@ def _configureL3( prefix, id, l3_params, network_id, ring_latency, rtr ): l3cache.addParams(l3_params) l3cache.addParams({ - "network_address" : network_id, "slice_id" : id }) + l3_nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l3_nic.addParam("group",2) + l3_nic.addParams("network_bw" : l3_params["network_bw"]) name = prefix + "l3_ring_link_" + id #print 'create', name l3_ring_link = sst.Link(name) - l3_ring_link.connect( (l3cache, "directory", ring_latency), (rtr, "port2", ring_latency) ) + l3_ring_link.connect( (l3_nic, "port", ring_latency), (rtr, "port2", ring_latency) ) @@ -105,21 +108,23 @@ def _configureMemCtrl( prefix, id, dc_params, mem_params, start_addr, end_addr, #print 'create' , name dc = sst.Component(name, "memHierarchy.DirectoryController") dc.addParams({ - "network_address" : network_id, "addr_range_start" : start_addr, "addr_range_end" : end_addr, }) dc.addParams(dc_params) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParam("group",2) + dc_nic.addParams("network_bw" : dc_params["network_bw"]) name = prefix + "mem_link_" + id #print 'create', name memLink = sst.Link(name) - memLink.connect((mem, "direct_link", ring_latency), (dc, "memory", ring_latency)) + memLink.connect((mem, "highlink", ring_latency), (dc, "lowlink", ring_latency)) name = prefix + "dc_ring_link_" + id #print 'create', name netLink = sst.Link(name) - netLink.connect((dc, "network", ring_latency), (rtr, "port2", ring_latency)) + netLink.connect((dc_nic, "port", ring_latency), (rtr, "port2", ring_latency)) def _configCache( prefix, diff --git a/src/sst/elements/ember/test/basicDetailedModel.py b/src/sst/elements/ember/test/basicDetailedModel.py index 0d4612ea82..e7fd0c47a3 100644 --- a/src/sst/elements/ember/test/basicDetailedModel.py +++ b/src/sst/elements/ember/test/basicDetailedModel.py @@ -42,11 +42,11 @@ def createThreads(self, prefix, bus, numThreads, cpu_params, l1_params ): link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_" + str(i+2),"1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink" + str(i+2),"1000ps") ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -66,15 +66,15 @@ def createNic( self, prefix, op, bus, cpu_params, l1_params ): link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); if op == 'read': - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_0","1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink0","1000ps") ) if op == 'write': - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_1","1000ps") ) + link.connect( ( l1, "lowlink", "50ps" ) , (bus,"highlink1","1000ps") ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -108,11 +108,11 @@ def build(self,nodeID,numCores): link = sst.Link( prefix + "bus_l2_link") link.setNoCut(); - link.connect( (bus, "low_network_0", "50ps"), (l2, "high_network_0", "50ps") ) + link.connect( (bus, "lowlink0", "50ps"), (l2, "highlink", "50ps") ) link = sst.Link( prefix + "l2_mem_link") link.setNoCut(); - link.connect( (l2, "low_network_0", "50ps"), (memory, "direct_link", "50ps") ) + link.connect( (l2, "lowlink", "50ps"), (memory, "highlink", "50ps") ) for i in range(numCores): name = prefix + "core" + str(i) + "_" diff --git a/src/sst/elements/ember/test/detailedShmemModel.py b/src/sst/elements/ember/test/detailedShmemModel.py index 2d28b07ca5..8d20d92f5f 100644 --- a/src/sst/elements/ember/test/detailedShmemModel.py +++ b/src/sst/elements/ember/test/detailedShmemModel.py @@ -42,12 +42,12 @@ def createThreads(self, prefix, bus, offset, numThreads, cpu_params, l1_params ) link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"high_network_0","1000ps") ) + link.connect( ( cpu, "cache_link", "100ps" ) , (l1,"highlink","1000ps") ) link = sst.Link( name + "l1_bus_link") link.setNoCut(); - portName = "high_network_" + str(offset+i) - link.connect( ( l1, "low_network_0", "50ps" ) , ( bus, portName, "1000ps" ) ) + portName = "highlink" + str(offset+i) + link.connect( ( l1, "lowlink", "50ps" ) , ( bus, portName, "1000ps" ) ) link = sst.Link( name + "src_link" ) link.setNoCut(); @@ -65,12 +65,12 @@ def createNic( self, prefix, bus, cpu_params, l1_params ): link = sst.Link( name + "l1_bus_link") link.setNoCut(); - link.connect( ( l1, "low_network_0", "50ps" ) , (bus,"high_network_0","1000ps") ) + link.connect( ( l1, "lowlink0", "50ps" ) , (bus,"highlink0","1000ps") ) link = sst.Link( name + "cpu_l1_link") link.setNoCut(); - l1.addLink( link, "high_network_0", "1000ps" ); + l1.addLink( link, "highlink", "1000ps" ); return link @@ -94,7 +94,7 @@ def build(self,nodeID,numCores): link = sst.Link( prefix + "bus_l2_link") link.setNoCut(); - link.connect( (bus, "low_network_0", "50ps"), (l2, "high_network_0", "50ps") ) + link.connect( (bus, "lowlink0", "50ps"), (l2, "highlink", "50ps") ) memory = sst.Component( prefix + "memory", "memHierarchy.MemController") memory.addParams( self.params['memory_params']) @@ -132,7 +132,7 @@ def build(self,nodeID,numCores): link = sst.Link( prefix + "l2_mem_link") link.setNoCut(); - link.connect( (l2, "low_network_0", "50ps"), (memory, "direct_link", "50ps") ) + link.connect( (l2, "lowlink", "50ps"), (memory, "highlink", "50ps") ) numThreads = int(self.params['numThreads']) for i in range(numCores): diff --git a/src/sst/elements/gensa/tests/test.py b/src/sst/elements/gensa/tests/test.py index 557ea8cfc9..b7958d0c91 100644 --- a/src/sst/elements/gensa/tests/test.py +++ b/src/sst/elements/gensa/tests/test.py @@ -61,7 +61,7 @@ # Define the simulation links link_gna_cache = sst.Link("link_gna_mem") -link_gna_cache.connect( (comp_gna, "mem_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_gna_cache.connect( (comp_gna, "mem_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/gensa/tests/test_gensa_1.py b/src/sst/elements/gensa/tests/test_gensa_1.py index 194f8ee22e..df36b2603c 100644 --- a/src/sst/elements/gensa/tests/test_gensa_1.py +++ b/src/sst/elements/gensa/tests/test_gensa_1.py @@ -37,7 +37,7 @@ }) link_core_memory = sst.Link("link_core_memory") -link_core_memory.connect( (core, "mem_link", "50ps"), (memoryController, "direct_link", "50ps") ) +link_core_memory.connect( (core, "mem_link", "50ps"), (memoryController, "highlink", "50ps") ) link_core_memory.setNoCut() # put memory on same partition with core msg_size = "8B" diff --git a/src/sst/elements/iris/sumi/sim_transport.cc b/src/sst/elements/iris/sumi/sim_transport.cc index 3af60045a7..112522d227 100644 --- a/src/sst/elements/iris/sumi/sim_transport.cc +++ b/src/sst/elements/iris/sumi/sim_transport.cc @@ -204,7 +204,7 @@ SimTransport::SimTransport(SST::Params& params, SST::Hg::App* parent) : rdma_pin_latency_ = TimeDelta(params.find("rdma_pin_latency", "0s").getValue().toDouble()); rdma_page_delay_ = TimeDelta(params.find("rdma_page_delay", "0s").getValue().toDouble()); pin_delay_ = rdma_pin_latency_.ticks() || rdma_page_delay_.ticks(); - page_size_ = params.find("rdma_page_size", "4096").getRoundedValue(); + page_size_ = params.find("rdma_page_size", "4096 B").getRoundedValue(); output.output("%d", sid().app_); nproc_ = os_->nranks(); diff --git a/src/sst/elements/llyr/tests/llyr_test.py b/src/sst/elements/llyr/tests/llyr_test.py index d964153950..3a67fab391 100644 --- a/src/sst/elements/llyr/tests/llyr_test.py +++ b/src/sst/elements/llyr/tests/llyr_test.py @@ -65,10 +65,10 @@ # Define the simulation links link_df_cache_link = sst.Link("link_cpu_cache_link") -link_df_cache_link.connect( (iface, "port", "1ps"), (df_l1cache, "high_network_0", "1ps") ) +link_df_cache_link.connect( (iface, "lowlink", "1ps"), (df_l1cache, "highlink", "1ps") ) link_df_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (df_l1cache, "low_network_0", "5ps"), (df_memory, "direct_link", "5ps") ) +link_mem_bus_link.connect( (df_l1cache, "lowlink", "5ps"), (df_memory, "highlink", "5ps") ) diff --git a/src/sst/elements/mask-mpi/mpi_api.cc b/src/sst/elements/mask-mpi/mpi_api.cc index b5371280f0..38efdb36e1 100644 --- a/src/sst/elements/mask-mpi/mpi_api.cc +++ b/src/sst/elements/mask-mpi/mpi_api.cc @@ -188,12 +188,13 @@ MpiApi::~MpiApi() delete comm; } - //people can be sloppy cleaning up requests - //clean up for them - for (auto& pair : req_map_){ - MpiRequest* req = pair.second; - delete req; - } + // This causes a "pointer being freed was not allocated" error + // //people can be sloppy cleaning up requests + // //clean up for them + // for (auto& pair : req_map_){ + // MpiRequest* req = pair.second; + // delete req; + // } if (qos_analysis_) delete qos_analysis_; } diff --git a/src/sst/elements/mask-mpi/tests/platform_file_mask_mpi_test.py b/src/sst/elements/mask-mpi/tests/platform_file_mask_mpi_test.py index 832930924a..d56a94fc89 100644 --- a/src/sst/elements/mask-mpi/tests/platform_file_mask_mpi_test.py +++ b/src/sst/elements/mask-mpi/tests/platform_file_mask_mpi_test.py @@ -17,6 +17,7 @@ platdef.addParamSet("nic",{ "verbose" : "0", + "mtu" : "4096 B", }) platdef.addParamSet("operating_system",{ @@ -30,21 +31,21 @@ }) platdef.addParamSet("network_interface",{ - "link_bw" : "12 GB/s", - "input_buf_size" : "16kB", - "output_buf_size" : "16kB" + "link_bw" : "11.25 GB/s", + "input_buf_size" : "32kB", + "output_buf_size" : "32kB" }) platdef.addClassType("network_interface","sst.merlin.interface.ReorderLinkControl") platdef.addParamSet("router",{ - "link_bw" : "12 GB/s", + "link_bw" : "11.25 GB/s", "flit_size" : "8B", "xbar_bw" : "50GB/s", "input_latency" : "20ns", "output_latency" : "20ns", - "input_buf_size" : "16kB", - "output_buf_size" : "16kB", + "input_buf_size" : "32kB", + "output_buf_size" : "32kB", "num_vns" : 1, "xbar_arb" : "merlin.xbar_arb_lru", }) @@ -52,12 +53,15 @@ platdef.addParamSet("operating_system", { "ncores" : "24", "nsockets" : "4", - "app1.post_rdma_delay" : "88us", - "app1.post_header_delay" : "0.36us", + "app1.post_rdma_delay" : "1.5us", + "app1.post_header_delay" : "0.5us", "app1.poll_delay" : "0us", "app1.rdma_pin_latency" : "5.43us", "app1.rdma_page_delay" : "50.50ns", "app1.rdma_page_size" : "4096", + "app1.max_vshort_msg_size" : "4096 B", + "app1.max_eager_msg_size" : "32768 B", + "app1.use_put_window" : "false", "app1.compute_library_access_width" : "64", "app1.compute_library_loop_overhead" : "1.0", }) diff --git a/src/sst/elements/mask-mpi/tests/refFiles/test_allgather.out b/src/sst/elements/mask-mpi/tests/refFiles/test_allgather.out index 9f48ad5a07..9be92ead41 100644 --- a/src/sst/elements/mask-mpi/tests/refFiles/test_allgather.out +++ b/src/sst/elements/mask-mpi/tests/refFiles/test_allgather.out @@ -6,4 +6,4 @@ recv_values[4]=4 recv_values[5]=5 recv_values[6]=6 recv_values[7]=7 -Simulation is complete, simulated time: 5.31875 us +Simulation is complete, simulated time: 6.99895 us diff --git a/src/sst/elements/mask-mpi/tests/refFiles/test_alltoall.out b/src/sst/elements/mask-mpi/tests/refFiles/test_alltoall.out index b8b9c93434..c8dda13d2f 100644 --- a/src/sst/elements/mask-mpi/tests/refFiles/test_alltoall.out +++ b/src/sst/elements/mask-mpi/tests/refFiles/test_alltoall.out @@ -1022,4 +1022,4 @@ recv_values[1020]=7 recv_values[1021]=7 recv_values[1022]=7 recv_values[1023]=7 -Simulation is complete, simulated time: 270.615 us +Simulation is complete, simulated time: 12.795 us diff --git a/src/sst/elements/mask-mpi/tests/refFiles/test_halo3d26.out b/src/sst/elements/mask-mpi/tests/refFiles/test_halo3d26.out index c769d568a7..538a0bc976 100644 --- a/src/sst/elements/mask-mpi/tests/refFiles/test_halo3d26.out +++ b/src/sst/elements/mask-mpi/tests/refFiles/test_halo3d26.out @@ -1,2 +1,2 @@ halo3d-26 executed successfully -Simulation is complete, simulated time: 53.62 ms +Simulation is complete, simulated time: 1.1873 ms diff --git a/src/sst/elements/mask-mpi/tests/refFiles/test_reduce.out b/src/sst/elements/mask-mpi/tests/refFiles/test_reduce.out index 88bd030396..1089cf7b20 100644 --- a/src/sst/elements/mask-mpi/tests/refFiles/test_reduce.out +++ b/src/sst/elements/mask-mpi/tests/refFiles/test_reduce.out @@ -6,4 +6,4 @@ recv_values[4]=4 recv_values[5]=5 recv_values[6]=6 recv_values[7]=7 -Simulation is complete, simulated time: 6.63875 us +Simulation is complete, simulated time: 8.73895 us diff --git a/src/sst/elements/mask-mpi/tests/refFiles/test_sendrecv.out b/src/sst/elements/mask-mpi/tests/refFiles/test_sendrecv.out index d037cc1878..54d24b8b02 100644 --- a/src/sst/elements/mask-mpi/tests/refFiles/test_sendrecv.out +++ b/src/sst/elements/mask-mpi/tests/refFiles/test_sendrecv.out @@ -6,4 +6,4 @@ A[4] = 4 A[5] = 5 A[6] = 6 A[7] = 7 -Simulation is complete, simulated time: 2.21875 us +Simulation is complete, simulated time: 2.91879 us diff --git a/src/sst/elements/memHierarchy/Makefile.am b/src/sst/elements/memHierarchy/Makefile.am index 83dc247e77..ac69a07c41 100644 --- a/src/sst/elements/memHierarchy/Makefile.am +++ b/src/sst/elements/memHierarchy/Makefile.am @@ -131,6 +131,7 @@ EXTRA_DIST = \ tests/testsuite_default_memHierarchy_hybridsim.py \ tests/testsuite_default_memHierarchy_memHA.py \ tests/testsuite_default_memHierarchy_sdl.py \ + tests/testsuite_default_memHierarchy_coherence.py \ tests/testsuite_default_memHierarchy_memHSieve.py \ tests/testsuite_sweep_memHierarchy_dir3LevelSweep.py \ tests/testsuite_sweep_memHierarchy_dirSweep.py \ @@ -165,8 +166,10 @@ EXTRA_DIST = \ tests/sdl9-1.py \ tests/sdl9-2.py \ tests/test_hybridsim.py \ - tests/sdl4-2-ramulator.py \ - tests/sdl5-1-ramulator.py \ + tests/test_coherence_1core.py \ + tests/test_coherence_2core_3level.py \ + tests/test_coherence_4core_5level.py \ + tests/test_coherence_1core.py \ tests/testBackendChaining.py \ tests/testBackendDelayBuffer.py \ tests/testBackendDramsim3.py \ @@ -174,6 +177,8 @@ EXTRA_DIST = \ tests/testBackendHBMDramsim.py \ tests/testBackendHBMPagedMulti.py \ tests/testBackendPagedMulti.py \ + tests/testBackendRamulator-1.py \ + tests/testBackendRamulator-2.py \ tests/testBackendReorderRow.py \ tests/testBackendReorderSimple.py \ tests/testBackendSimpleDRAM-1.py \ @@ -230,6 +235,8 @@ EXTRA_DIST = \ tests/refFiles/test_memHA_BackendHBMDramsim.out \ tests/refFiles/test_memHA_BackendHBMPagedMulti.out \ tests/refFiles/test_memHA_BackendPagedMulti.out \ + tests/refFiles/test_memHA_BackendRamulator_1.out \ + tests/refFiles/test_memHA_BackendRamulator_2.out \ tests/refFiles/test_memHA_BackendReorderRow.out \ tests/refFiles/test_memHA_BackendReorderSimple.out \ tests/refFiles/test_memHA_BackendSimpleDRAM_1.out \ @@ -269,15 +276,36 @@ EXTRA_DIST = \ tests/refFiles/test_memHA_StdMem_mmio.out \ tests/refFiles/test_memHA_StdMem_noninclusive.out \ tests/refFiles/test_memHA_ThroughputThrottling.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case0_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case1_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case2_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case3_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case4_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case5_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_1core_case6_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case0_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case1_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case2_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case3_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case4_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case5_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case6_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case7_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case8_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case9_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case10_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_2core_3level_case11_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_4core_5level_case0_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_4core_5level_case1_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_4core_5level_case2_mesi.out \ + tests/refFiles/test_memHierarchy_coherence_4core_5level_case3_mesi.out \ tests/refFiles/test_memHierarchy_sdl2_1.out \ tests/refFiles/test_memHierarchy_sdl3_1.out \ tests/refFiles/test_memHierarchy_sdl3_2.out \ tests/refFiles/test_memHierarchy_sdl3_3.out \ tests/refFiles/test_memHierarchy_sdl4_1.out \ tests/refFiles/test_memHierarchy_sdl4_2.out \ - tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out \ tests/refFiles/test_memHierarchy_sdl5_1.out \ - tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out \ tests/refFiles/test_memHierarchy_sdl8_1.out \ tests/refFiles/test_memHierarchy_sdl8_3.out \ tests/refFiles/test_memHierarchy_sdl8_4.out \ diff --git a/src/sst/elements/memHierarchy/README.md b/src/sst/elements/memHierarchy/README.md new file mode 100644 index 0000000000..b58a920098 --- /dev/null +++ b/src/sst/elements/memHierarchy/README.md @@ -0,0 +1,3 @@ +MemHierarchy contains SST elements for cache and memory system simulation. + +Documentation is available [here](http://sst-simulator.org/sst-docs/docs/elements/memHierarchy/intro). diff --git a/src/sst/elements/memHierarchy/Sieve/sieveController.cc b/src/sst/elements/memHierarchy/Sieve/sieveController.cc index bb225dd69f..93555bf311 100644 --- a/src/sst/elements/memHierarchy/Sieve/sieveController.cc +++ b/src/sst/elements/memHierarchy/Sieve/sieveController.cc @@ -183,7 +183,7 @@ void Sieve::init(unsigned int phase) { MemRegion region; region.setDefault(); for (int i = 0; i < cpuLinkCount_; i++) { - cpuLinks_[i]->sendUntimedData(new MemEventInitRegion(getName(), region ,false)); + cpuLinks_[i]->sendUntimedData(new MemEventInitRegion(getName(), region , MemEventInitRegion::ReachableGroup::Dest)); } } diff --git a/src/sst/elements/memHierarchy/bus.cc b/src/sst/elements/memHierarchy/bus.cc index c505a12709..d1f56196ad 100644 --- a/src/sst/elements/memHierarchy/bus.cc +++ b/src/sst/elements/memHierarchy/bus.cc @@ -88,12 +88,12 @@ void Bus::broadcastEvent(SST::Event* ev) { MemEventBase* memEvent = static_cast(ev); SST::Link* srcLink = lookupNode(memEvent->getSrc()); - for (int i = 0; i < numHighNetPorts_; i++) { + for (int i = 0; i < numHighPorts_; i++) { if (highNetPorts_[i] == srcLink) continue; highNetPorts_[i]->send(memEvent->clone()); } - for (int i = 0; i < numLowNetPorts_; i++) { + for (int i = 0; i < numLowPorts_; i++) { if (lowNetPorts_[i] == srcLink) continue; lowNetPorts_[i]->send(memEvent->clone()); } @@ -142,30 +142,39 @@ SST::Link* Bus::lookupNode(const std::string& name) { } void Bus::configureLinks() { + std::string linkprefix = "highlink"; + if (isPortConnected("high_network_0")) { + dbg_.output("%s, DEPRECATION WARNING: The 'high_network_%%d' ports on MemHierarchy Buses have been renamed to 'highlink%%d'. MemHierarchy port names are being standardized. The 'high_network_%%d' ports will be removed in SST 16.\n", getName().c_str()); + linkprefix = "high_network_"; + } + SST::Link* link; - std::string linkprefix = "high_network_"; std::string linkname = linkprefix + "0"; while (isPortConnected(linkname)) { link = configureLink(linkname, new Event::Handler(this, &Bus::processIncomingEvent)); if (!link) dbg_.fatal(CALL_INFO, -1, "%s, Error: unable to configure link on port '%s'\n", getName().c_str(), linkname.c_str()); highNetPorts_.push_back(link); - numHighNetPorts_++; - linkname = linkprefix + std::to_string(numHighNetPorts_); + numHighPorts_++; + linkname = linkprefix + std::to_string(numHighPorts_); + } + + linkprefix = "lowlink"; + if (isPortConnected("low_network_0")) { + dbg_.output("%s, DEPRECATION WARNING: The 'low_network_%%d' ports on MemHierarchy Buses have been renamed to 'lowlink%%d'. MemHierarchy port names are being standardized. The 'low_network_%%d' ports will be removed in SST 16.\n", getName().c_str()); + linkprefix = "low_network_"; } - - linkprefix = "low_network_"; linkname = linkprefix + "0"; while (isPortConnected(linkname)) { - link = configureLink(linkname, "50 ps", new Event::Handler(this, &Bus::processIncomingEvent)); + link = configureLink(linkname, new Event::Handler(this, &Bus::processIncomingEvent)); if (!link) dbg_.fatal(CALL_INFO, -1, "%s, Error: unable to configure link on port '%s'\n", getName().c_str(), linkname.c_str()); lowNetPorts_.push_back(link); - numLowNetPorts_++; - linkname = linkprefix + std::to_string(numLowNetPorts_); + numLowPorts_++; + linkname = linkprefix + std::to_string(numLowPorts_); } - if (numLowNetPorts_ < 1 || numHighNetPorts_ < 1) dbg_.fatal(CALL_INFO, -1,"couldn't find number of Ports (numPorts)\n"); + if (numLowPorts_ < 1 || numHighPorts_ < 1) dbg_.fatal(CALL_INFO, -1,"couldn't find number of Ports (numPorts)\n"); } @@ -180,61 +189,92 @@ void Bus::configureParameters(SST::Params& params) { for (std::vector::iterator it = addrArr.begin(); it != addrArr.end(); it++) DEBUG_ADDR.insert(*it); - numHighNetPorts_ = 0; - numLowNetPorts_ = 0; + numHighPorts_ = 0; + numLowPorts_ = 0; - latency_ = params.find("bus_latency_cycles", 1); idleMax_ = params.find("idle_max", 6); - busFrequency_ = params.find("bus_frequency", "Invalid"); + std::string frequency = params.find("bus_frequency", "Invalid"); broadcast_ = params.find("broadcast", 0); - fanout_ = params.find("fanout", 0); /* TODO: Fanout: Only send messages to lower level caches */ drain_ = params.find("drain_bus", false); - if (busFrequency_ == "Invalid") dbg_.fatal(CALL_INFO, -1, "Bus Frequency was not specified\n"); + if (frequency == "Invalid") dbg_.fatal(CALL_INFO, -1, "Bus Frequency was not specified\n"); /* Multiply Frequency times two. This is because an SST Bus components has 2 SST Links (highNEt & LowNet) and thus it takes a least 2 cycles for any transaction (a real bus should be allowed to have 1 cycle latency). To overcome this we clock the bus 2x the speed of the cores */ - UnitAlgebra uA = UnitAlgebra(busFrequency_); + UnitAlgebra uA = UnitAlgebra(frequency); uA = uA * 2; - busFrequency_ = uA.toString(); + frequency = uA.toString(); clockHandler_ = new Clock::Handler(this, &Bus::clockTick); - defaultTimeBase_ = registerClock(busFrequency_, clockHandler_); + defaultTimeBase_ = registerClock(frequency, clockHandler_); } void Bus::init(unsigned int phase) { SST::Event *ev; - for (int i = 0; i < numHighNetPorts_; i++) { + for (int i = 0; i < numHighPorts_; i++) { while ((ev = highNetPorts_[i]->recvUntimedData())) { MemEventInit* memEvent = dynamic_cast(ev); if (memEvent && memEvent->getCmd() == Command::NULLCMD) { - dbg_.debug(_L10_, "bus %s broadcasting upper event to lower ports (%d): %s\n", getName().c_str(), numLowNetPorts_, memEvent->getVerboseString().c_str()); + dbg_.debug(_L10_, "bus %s broadcasting upper event to lower ports (%d): %s\n", getName().c_str(), numLowPorts_, memEvent->getVerboseString().c_str()); mapNodeEntry(memEvent->getSrc(), highNetPorts_[i]); - for (int k = 0; k < numLowNetPorts_; k++) - lowNetPorts_[k]->sendUntimedData(memEvent->clone()); + + if (memEvent->getInitCmd() == MemEventInit::InitCommand::Region) { + MemEventInitRegion * mEvReg = static_cast(memEvent); + mEvReg->setGroup(MemEventInitRegion::ReachableGroup::Source); + + for (int k = 0; k < numLowPorts_; k++) { + lowNetPorts_[k]->sendUntimedData(memEvent->clone()); + } + + mEvReg->setGroup(MemEventInitRegion::ReachableGroup::Peer); + for (int k = 0; k < numHighPorts_; k++) { + if (k == i) continue; + highNetPorts_[k]->sendUntimedData(memEvent->clone()); + } + } else { + for (int k = 0; k < numLowPorts_; k++) { + lowNetPorts_[k]->sendUntimedData(memEvent->clone()); + } + } } else if (memEvent) { - dbg_.debug(_L10_, "bus %s broadcasting upper event to lower ports (%d): %s\n", getName().c_str(), numLowNetPorts_, memEvent->getVerboseString().c_str()); - for (int k = 0; k < numLowNetPorts_; k++) + dbg_.debug(_L10_, "bus %s broadcasting upper event to lower ports (%d): %s\n", getName().c_str(), numLowPorts_, memEvent->getVerboseString().c_str()); + for (int k = 0; k < numLowPorts_; k++) lowNetPorts_[k]->sendUntimedData(memEvent->clone()); } delete memEvent; } } - for (int i = 0; i < numLowNetPorts_; i++) { + for (int i = 0; i < numLowPorts_; i++) { while ((ev = lowNetPorts_[i]->recvUntimedData())) { MemEventInit* memEvent = dynamic_cast(ev); if (!memEvent) delete memEvent; else if (memEvent->getCmd() == Command::NULLCMD) { - dbg_.debug(_L10_, "bus %s broadcasting lower event to upper ports (%d): %s\n", getName().c_str(), numHighNetPorts_, memEvent->getVerboseString().c_str()); + dbg_.debug(_L10_, "bus %s broadcasting lower event to upper ports (%d): %s\n", getName().c_str(), numHighPorts_, memEvent->getVerboseString().c_str()); mapNodeEntry(memEvent->getSrc(), lowNetPorts_[i]); - for (int i = 0; i < numHighNetPorts_; i++) { - highNetPorts_[i]->sendUntimedData(memEvent->clone()); + + if (memEvent->getInitCmd() == MemEventInit::InitCommand::Region) { + MemEventInitRegion * mEvReg = static_cast(memEvent); + mEvReg->setGroup(MemEventInitRegion::ReachableGroup::Dest); + + for (int k = 0; k < numHighPorts_; k++) { + highNetPorts_[k]->sendUntimedData(memEvent->clone()); + } + + mEvReg->setGroup(MemEventInitRegion::ReachableGroup::Peer); + for (int k = 0; k < numLowPorts_; k++) { + if (k == i) continue; + lowNetPorts_[k]->sendUntimedData(memEvent->clone()); + } + } else { + for (int i = 0; i < numHighPorts_; i++) { + highNetPorts_[i]->sendUntimedData(memEvent->clone()); + } } delete memEvent; } diff --git a/src/sst/elements/memHierarchy/bus.h b/src/sst/elements/memHierarchy/bus.h index 4771b75a50..ccb0b68a01 100644 --- a/src/sst/elements/memHierarchy/bus.h +++ b/src/sst/elements/memHierarchy/bus.h @@ -51,8 +51,6 @@ class Bus : public SST::Component { SST_ELI_DOCUMENT_PARAMS( {"bus_frequency", "(string) Bus clock frequency"}, {"broadcast", "(bool) If set, messages are broadcast to all other ports", "0"}, - {"fanout", "(bool) If set, messages from the high network are replicated and sent to all low network ports", "0"}, - {"bus_latency_cycles", "(uint) Bus latency in cycles", "0"}, {"idle_max", "(uint) Bus temporarily turns off clock after this number of idle cycles", "6"}, {"drain_bus", "(bool) Drain bus on every cycle", "0"}, {"debug", "(uint) Output location for debug statements. Requires core configuration flag '--enable-debug'. --0[None], 1[STDOUT], 2[STDERR], 3[FILE]--", "0"}, @@ -60,8 +58,10 @@ class Bus : public SST::Component { {"debug_addr", "(comma separated uints) Address(es) to be debugged. Leave empty for all, otherwise specify one or more comma separated values. Start and end string with brackets", ""} ) SST_ELI_DOCUMENT_PORTS( - {"low_network_%(low_network_ports)d", "Ports connected to lower level caches (closer to main memory)", {"memHierarchy.MemEventBase"} }, - {"high_network_%(high_network_ports)d", "Ports connected to higher level caches (closer to CPU)", {"memHierarchy.MemEventBase"} } ) + {"low_network_%(low_network_ports)d", "DEPRECATED. Use 'lowlink\%d' instead. Ports connected to lower level caches (closer to main memory)", {"memHierarchy.MemEventBase"} }, + {"high_network_%(high_network_ports)d", "DEPRECATED. Use 'highlink\%d' instead. Ports connected to higher level caches (closer to processor)", {"memHierarchy.MemEventBase"} }, + {"lowlink%(lowlink_ports)d", "Ports connected to components on the lower/memory side of the bus (i.e., lower level caches, directories, memory, etc.)", {"memHierarchy.MemEventBase"} }, + {"highlink%(highlink_ports)d", "Ports connected to components on the upper/processor side of the bus (i.e., upper level caches, processors, etc.)", {"memHierarchy.MemEventBase"} } ) /* Class definition */ @@ -96,20 +96,16 @@ class Bus : public SST::Component { Output dbg_; std::set DEBUG_ADDR; - int numHighNetPorts_; - int numLowNetPorts_; + int numHighPorts_; + int numLowPorts_; uint64_t idleCount_; - uint64_t latency_; uint64_t idleMax_; - bool fanout_; bool broadcast_; bool busOn_; bool drain_; Clock::Handler* clockHandler_; TimeConverter* defaultTimeBase_; - std::string busFrequency_; - std::string bus_latency_cycles_; std::vector highNetPorts_; std::vector lowNetPorts_; std::map nameMap_; diff --git a/src/sst/elements/memHierarchy/cacheArray.h b/src/sst/elements/memHierarchy/cacheArray.h index f1fce1f106..6fdd5cd455 100644 --- a/src/sst/elements/memHierarchy/cacheArray.h +++ b/src/sst/elements/memHierarchy/cacheArray.h @@ -89,6 +89,23 @@ class CacheArray { void setSliceAware(Addr size, Addr step); void setBanked(unsigned int numBanks); void printCacheArray(Output &out); + + /**** Cache iterators */ + struct cache_itr { + public: + cache_itr(const CacheArray* c, unsigned idx) : cache_(c), idx_(idx) {} + bool operator!=(const cache_itr& rhs) const { return idx_ != rhs.idx_; } + bool operator==(const cache_itr& rhs) const { return idx_ == rhs.idx_; } + const cache_itr& operator++() { ++idx_; return *this; } + const cache_itr& operator--() { --idx_; return *this; } + const T* operator*() const { return cache_->lines_[idx_]; } + T* operator*() { return cache_->lines_[idx_]; } + private: + const CacheArray* cache_; + unsigned idx_; + }; + cache_itr begin() const { return cache_itr(this, 0); } + cache_itr end() const { return cache_itr(this, numLines_); } }; /************* Function definitions *****************/ diff --git a/src/sst/elements/memHierarchy/cacheController.cc b/src/sst/elements/memHierarchy/cacheController.cc index 7637813e72..a54454ae92 100644 --- a/src/sst/elements/memHierarchy/cacheController.cc +++ b/src/sst/elements/memHierarchy/cacheController.cc @@ -57,6 +57,8 @@ void Cache::handleEvent(SST::Event * ev) { } eventBuffer_.push_back(event); + //printf("DBG: %s, inserted <%" PRIu64 ", %d>, size=%zu\n", getName().c_str(), event->getID().first, event->getID().second, eventBuffer_.size()); + } /* @@ -150,6 +152,7 @@ bool Cache::clockTick(Cycle_t time) { while (it != eventBuffer_.end()) { if (accepted == maxRequestsPerCycle_) break; + Event::id_type id = (*it)->getID(); Command cmd = (*it)->getCmd(); if (is_debug_event((*it))) { dbg_->debug(_L3_, "E: %-20" PRIu64 " %-20" PRIu64 " %-20s Event:New (%s)\n", @@ -160,8 +163,10 @@ bool Cache::clockTick(Cycle_t time) { accepted++; statRecvEvents->addData(1); it = eventBuffer_.erase(it); + //printf("DBG: %s, erased <%" PRIu64 ", %d>, it=%d, size=%zu\n", getName().c_str(), id.first, id.second, it == eventBuffer_.end(), eventBuffer_.size()); } else { it++; + //printf("DBG: %s, left <%" PRIu64 ", %d>, it=%d, size=%zu\n", getName().c_str(), id.first, id.second, it == eventBuffer_.end(), eventBuffer_.size()); } } while (!prefetchBuffer_.empty()) { @@ -230,7 +235,7 @@ void Cache::turnClockOff() { * * Returns: whether event was accepted/can be popped off event queue */ -bool Cache::processEvent(MemEventBase* ev, bool inMSHR) { +bool Cache::processEvent(MemEventBase* ev, bool retry) { // Global noncacheable request flag if (allNoncacheableRequests_) { ev->setFlag(MemEvent::F_NONCACHEABLE); @@ -263,79 +268,94 @@ bool Cache::processEvent(MemEventBase* ev, bool inMSHR) { switch (event->getCmd()) { case Command::GetS: - accepted = coherenceMgr_->handleGetS(event, inMSHR); + accepted = coherenceMgr_->handleGetS(event, retry); break; case Command::GetX: - accepted = coherenceMgr_->handleGetX(event, inMSHR); + accepted = coherenceMgr_->handleGetX(event, retry); break; case Command::Write: - accepted = coherenceMgr_->handleWrite(event, inMSHR); + accepted = coherenceMgr_->handleWrite(event, retry); break; case Command::GetSX: - accepted = coherenceMgr_->handleGetSX(event, inMSHR); + accepted = coherenceMgr_->handleGetSX(event, retry); break; case Command::FlushLine: - accepted = coherenceMgr_->handleFlushLine(event, inMSHR); + accepted = coherenceMgr_->handleFlushLine(event, retry); break; case Command::FlushLineInv: - accepted = coherenceMgr_->handleFlushLineInv(event, inMSHR); + accepted = coherenceMgr_->handleFlushLineInv(event, retry); + break; + case Command::FlushAll: + accepted = coherenceMgr_->handleFlushAll(event, retry); break; case Command::GetSResp: - accepted = coherenceMgr_->handleGetSResp(event, inMSHR); + accepted = coherenceMgr_->handleGetSResp(event, retry); break; case Command::WriteResp: - accepted = coherenceMgr_->handleWriteResp(event, inMSHR); + accepted = coherenceMgr_->handleWriteResp(event, retry); break; case Command::GetXResp: - accepted = coherenceMgr_->handleGetXResp(event, inMSHR); + accepted = coherenceMgr_->handleGetXResp(event, retry); break; case Command::FlushLineResp: - accepted = coherenceMgr_->handleFlushLineResp(event, inMSHR); + accepted = coherenceMgr_->handleFlushLineResp(event, retry); + break; + case Command::FlushAllResp: + accepted = coherenceMgr_->handleFlushAllResp(event, retry); break; case Command::PutS: - accepted = coherenceMgr_->handlePutS(event, inMSHR); + accepted = coherenceMgr_->handlePutS(event, retry); break; case Command::PutX: - accepted = coherenceMgr_->handlePutX(event, inMSHR); + accepted = coherenceMgr_->handlePutX(event, retry); break; case Command::PutE: - accepted = coherenceMgr_->handlePutE(event, inMSHR); + accepted = coherenceMgr_->handlePutE(event, retry); break; case Command::PutM: - accepted = coherenceMgr_->handlePutM(event, inMSHR); + accepted = coherenceMgr_->handlePutM(event, retry); break; case Command::FetchInv: - accepted = coherenceMgr_->handleFetchInv(event, inMSHR); + accepted = coherenceMgr_->handleFetchInv(event, retry); break; case Command::FetchInvX: - accepted = coherenceMgr_->handleFetchInvX(event, inMSHR); + accepted = coherenceMgr_->handleFetchInvX(event, retry); break; case Command::ForceInv: - accepted = coherenceMgr_->handleForceInv(event, inMSHR); + accepted = coherenceMgr_->handleForceInv(event, retry); break; case Command::Inv: - accepted = coherenceMgr_->handleInv(event, inMSHR); + accepted = coherenceMgr_->handleInv(event, retry); break; case Command::Fetch: - accepted = coherenceMgr_->handleFetch(event, inMSHR); + accepted = coherenceMgr_->handleFetch(event, retry); break; case Command::FetchResp: - accepted = coherenceMgr_->handleFetchResp(event, inMSHR); + accepted = coherenceMgr_->handleFetchResp(event, retry); break; case Command::FetchXResp: - accepted = coherenceMgr_->handleFetchXResp(event, inMSHR); + accepted = coherenceMgr_->handleFetchXResp(event, retry); break; case Command::AckInv: - accepted = coherenceMgr_->handleAckInv(event, inMSHR); + accepted = coherenceMgr_->handleAckInv(event, retry); break; case Command::AckPut: - accepted = coherenceMgr_->handleAckPut(event, inMSHR); + accepted = coherenceMgr_->handleAckPut(event, retry); + break; + case Command::ForwardFlush: + accepted = coherenceMgr_->handleForwardFlush(event, retry); + break; + case Command::AckFlush: + accepted = coherenceMgr_->handleAckFlush(event, retry); + break; + case Command::UnblockFlush: + accepted = coherenceMgr_->handleUnblockFlush(event, retry); break; case Command::NACK: - accepted = coherenceMgr_->handleNACK(event, inMSHR); + accepted = coherenceMgr_->handleNACK(event, retry); break; case Command::NULLCMD: - accepted = coherenceMgr_->handleNULLCMD(event, inMSHR); + accepted = coherenceMgr_->handleNULLCMD(event, retry); break; default: out_->fatal(CALL_INFO, -1, "%s, Error: Received an unsupported command. Event: %s. Time = %" PRIu64 "ns.\n", @@ -528,6 +548,7 @@ void Cache::setup() { // Enqueue the first wakeup event to check for deadlock if (timeout_ != 0) timeoutSelfLink_->send(1, nullptr); + coherenceMgr_->setup(); } diff --git a/src/sst/elements/memHierarchy/cacheController.h b/src/sst/elements/memHierarchy/cacheController.h index e9e11f603a..4b1b9ce179 100644 --- a/src/sst/elements/memHierarchy/cacheController.h +++ b/src/sst/elements/memHierarchy/cacheController.h @@ -89,28 +89,33 @@ class Cache : public SST::Component { {"cache_line_size", "(uint) Size of a cache line [aka cache block] in bytes.", "64"}, {"force_noncacheable_reqs", "(bool) Used for verification purposes. All requests are considered to be 'noncacheable'. Options: 0[off], 1[on]", "false"}, {"min_packet_size", "(string) Number of bytes in a request/response not including payload (e.g., addr + cmd). Specify in B.", "8B"}, - {"banks", "(uint) Number of cache banks: One access per bank per cycle. Use '0' to simulate no bank limits (only limits on bandwidth then are max_requests_per_cycle and *_link_width", "0"}, - /* Old parameters - deprecated or moved */ - {"network_address", "DEPRECATED - Now auto-detected by link control."}, // Remove 9.0 - {"network_bw", "MOVED - Now a member of the MemNIC subcomponent.", "80GiB/s"}, // Remove 9.0 - {"network_input_buffer_size", "MOVED - Now a member of the MemNIC subcomponent.", "1KiB"}, // Remove 9.0 - {"network_output_buffer_size", "MOVED - Now a member of the MemNIC subcomponent.", "1KiB"}, // Remove 9.0 - {"prefetcher", "MOVED - Prefetcher subcomponent, instead specify by putting it in the 'prefetcher' subcomponent slot", ""}, - {"replacement_policy", "MOVED - Cache replacement policy, now a subcomponent so specify by putting in the index 0 of the 'replacement' subcomponent slot in the input config", ""}, - {"noninclusive_directory_repl", "MOVED - Replacement policy for noninclusive directory, now a subcomponent, specify by putting in the index 1 of the 'replacement' subcomponent slot in the input config", ""}, - {"hash_function", "MOVED - Hash function for mapping addresses to cache lines, now a subcomponent, specify by filling the 'hash' slot (default/unfilled is none)", ""}) + {"banks", "(uint) Number of cache banks: One access per bank per cycle. Use '0' to simulate no bank limits (only limits on bandwidth then are max_requests_per_cycle and *_link_width", "0"}) SST_ELI_DOCUMENT_PORTS( - {"low_network_0", "Port connected to lower level caches (closer to main memory)", {"memHierarchy.MemEventBase"} }, - {"high_network_0", "Port connected to higher level caches (closer to CPU)", {"memHierarchy.MemEventBase"} }, - {"directory", "Network link port to directory; doubles as request network port for split networks", {"memHierarchy.MemRtrEvent"} }, - {"directory_ack", "For split networks, response/ack network port to directory", {"memHierarchy.MemRtrEvent"} }, - {"directory_fwd", "For split networks, forward request network port to directory", {"memHierarchy.MemRtrEvent"} }, - {"directory_data", "For split networks, data network port to directory", {"memHierarchy.MemRtrEvent"} }, - {"cache", "Network link port to cache; doubles as request network port for split networks", {"memHierarchy.MemRtrEvent"} }, - {"cache_ack", "For split networks, response/ack network port to cache", {"memHierarchy.MemRtrEvent"} }, - {"cache_fwd", "For split networks, forward request network port to cache", {"memHierarchy.MemRtrEvent"} }, - {"cache_data", "For split networks, data network port to cache", {"memHierarchy.MemRtrEvent"} }) + {"highlink", "Non-network upper/processor-side link (i.e., link towards the core/accelerator/etc.). This port loads the 'memHierarchy.MemLink' manager. " + "To connect to a network component or to use non-default parameters on the MemLink subcomponent, fill the 'highlink' subcomponent slot instead of connecting this port.", {"memHierarchy.MemEventBase"} }, + {"lowlink", "Non-network lower/memory-side link (i.e., link towards memory). This port loads the 'memHierarchy.MemLink' manager. " + "To connect to a network component or use non-default parameters on the MemLink subcomponent, fill the 'lowlink' subcomponent slot instead of connecting this port.", {"memHierarchy.MemEventBase"} }, + {"low_network_0", "DEPRECATED: Use the 'lowlink' port or fill the 'lowlink' subcomponent slot with 'memHierarchy.MemLink' instead. " + "Non-network connection to lower level caches (closer to main memory)", {"memHierarchy.MemEventBase"} }, + {"high_network_0", "DEPRECATED: Use the 'highlink' port or fill the 'highlink' subcomponent slot with 'memHierarchy.MemLink' instead. " + "Non-network connection to higher level caches (closer to CPU)", {"memHierarchy.MemEventBase"} }, + {"directory", "DEPRECATED: Use MemNIC or MemNICFour subcomponent in the 'lowlink' subcomponent slot instead. " + "Network link port to directory; doubles as request network port for split networks", {"memHierarchy.MemRtrEvent"} }, + {"directory_ack", "DEPRECATED: Use MemNICFour subcomponent in the 'lowlink' subcomponent slot instead. " + "For split networks, response/ack network port to directory", {"memHierarchy.MemRtrEvent"} }, + {"directory_fwd", "DEPRECATED: Use MemNICFour subcomponent in the 'lowlink' subcomponent slot instead. " + "For split networks, forward request network port to directory", {"memHierarchy.MemRtrEvent"} }, + {"directory_data", "DEPRECATED: Use MemNICFour subcomponent in the 'lowlink' subcomponent slot instead. " + "For split networks, data network port to directory", {"memHierarchy.MemRtrEvent"} }, + {"cache", "DEPRECATED: Use MemNIC or MemNICFour subcomponent in the 'highlink' subcomponent slot instead. " + "Network link port to cache; doubles as request network port for split networks", {"memHierarchy.MemRtrEvent"} }, + {"cache_ack", "DEPRECATED: Use MemNICFour subcomponent in the 'highlink' subcomponent slot instead. " + "For split networks, response/ack network port to cache.", {"memHierarchy.MemRtrEvent"} }, + {"cache_fwd", "DEPRECATED: Use MemNICFour subcomponent in the 'highlink' subcomponent slot instead. " + "For split networks, forward request network port to cache", {"memHierarchy.MemRtrEvent"} }, + {"cache_data", "DEPRECATED: Use MemNICFour subcomponent in the 'highlink' subcomponent slot instead. " + "For split networks, data network port to cache", {"memHierarchy.MemRtrEvent"} }) SST_ELI_DOCUMENT_STATISTICS( /* Cache hits and misses */ @@ -143,7 +148,12 @@ class Cache : public SST::Component { {"AckPut_recv", "Event received: AckPut", "count", 2}, {"FlushLine_recv", "Event received: FlushLine", "count", 2}, {"FlushLineInv_recv", "Event received: FlushLineInv", "count", 2}, + {"FlushAll_recv", "Event received: FlushAll", "count", 2}, + {"ForwardFlush_recv", "Event received: ForwardFlush", "count", 2}, + {"UnblockFlush_recv", "Event received: UnblockFlush", "count", 2}, {"FlushLineResp_recv", "Event received: FlushLineResp", "count", 2}, + {"FlushAllResp_recv", "Event received: FlushAllResp", "count", 2}, + {"AckFlush_recv", "Event received: AckFlush", "count", 2}, {"NACK_recv", "Event: NACK received", "count", 2}, {"NULLCMD_recv", "Event: NULLCMD received", "count", 2}, {"Get_uncache_recv", "Noncacheable Event: Get received", "count", 6}, @@ -160,13 +170,15 @@ class Cache : public SST::Component { {"default_stat", "Default statistic used for unexpected events/cases/etc. Should be 0, if not, check for missing statistic registrations.", "none", 7}) SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS( - {"cpulink", "CPU-side link manager, for single-link caches, use this one only", "SST::MemHierarchy::MemLinkBase"}, - {"memlink", "Memory-side link manager", "SST::MemHierarchy::MemLinkBase"}, - {"coherence", "Coherence protocol", "SST::MemHierarchy::CoherenceController"}, + {"highlink", "Port manager on the upper/processor-side (i.e., where requests typically come from). If you use this subcomponent slot, you do not need to connect the cache's highlink port. Do connect this subcomponent's ports instead. For caches with a single link, use this subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"lowlink", "Port manager on the lower/memory side (i.e., where cache misses should be sent to). If you use this subcomponent slot, you do not need to connect the cache's lowlink port. Do connect this subcomponent's ports instead. For caches with a single link, use the 'highlink' subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"cpulink", "DEPRECATED. To standardize naming, use the 'highlink' slot instead. Port manager on the CPU-side (i.e., where requests typically come from). If you use this subcomponent slot, you do not need to connect the cache's ports. Do connect this subcomponent's ports instead. For caches with a single link, use this subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"memlink", "DEPRECATED. To standardize naming, use the 'lowlink' slot instead. Port manager on the memory side (i.e., where cache misses should be sent to). If you use this subcomponent slot, you do not need to connect the cache's ports. Do connect this subcomponent's ports instead. For caches with a single link, use the 'highlink' subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, {"prefetcher", "Prefetcher(s)", "SST::MemHierarchy::CacheListener"}, {"listener", "Cache listener(s) for statistics, tracing, etc. In contrast to prefetcher, cannot send events to cache", "SST::MemHierarchy::CacheListener"}, - {"replacement", "Replacement policies, slot 0 is for cache, slot 1 is for directory (if it exists)", "SST::MemHierarchy::ReplacementPolicy"}, - {"hash", "Hash function for mapping addresses to cache lines", "SST::MemHierarchy::HashFunction"} ) + {"replacement", "Replacement policies. Slot 0 is for cache. In caches that include a directory, use slot 1 to specify the directory's replacement policy. ", "SST::MemHierarchy::ReplacementPolicy"}, + {"hash", "Hash function for mapping addresses to cache lines", "SST::MemHierarchy::HashFunction"}, + {"coherence", "Coherence protocol. The cache will fill this slot automatically based on cache parameters. Do not use this slot directly.", "SST::MemHierarchy::CoherenceController"}) /* Class definition */ friend class InstructionStream; // TODO what is this? diff --git a/src/sst/elements/memHierarchy/cacheFactory.cc b/src/sst/elements/memHierarchy/cacheFactory.cc index b0584a9c77..58009e19a9 100644 --- a/src/sst/elements/memHierarchy/cacheFactory.cc +++ b/src/sst/elements/memHierarchy/cacheFactory.cc @@ -67,11 +67,18 @@ Cache::Cache(ComponentId_t id, Params ¶ms) : Component(id) { maxRequestsPerCycle_ = params.find("max_requests_per_cycle",-1); string packetSize = params.find("min_packet_size", "8B"); - UnitAlgebra packetSize_ua(packetSize); - if (!packetSize_ua.hasUnits("B")) { - out_->fatal(CALL_INFO, -1, "%s, Invalid param: min_packet_size - must have units of bytes (B). Ex: '8B'. SI units are ok. You specified '%s'\n", this->Component::getName().c_str(), packetSize.c_str()); + try { + UnitAlgebra packetSize_ua(packetSize); + + if (!packetSize_ua.hasUnits("B")) { + out_->fatal(CALL_INFO, -1, "%s, Invalid param: min_packet_size - must have units of bytes (B). Ex: '8B'. SI units are ok. You specified '%s'\n", this->Component::getName().c_str(), packetSize.c_str()); + } + } catch (UnitAlgebra::UnitAlgebraException& exc) { + out_->fatal(CALL_INFO, -1, "%s, Invalid param: Exception occurred while parsing 'min_packet_size'. '%s'\n", getName().c_str(), exc.what()); } + + if (maxRequestsPerCycle_ == 0) { maxRequestsPerCycle_ = -1; // Simplify compare } @@ -212,26 +219,48 @@ void Cache::createCoherenceManager(Params ¶ms) { /* * Configure links to components above (closer to CPU) and below (closer to memory) - * Check for connected ports to determine which links to use - * Valid port combos: - * high_network_0 & low_network_%d : connected to core/cache/bus above and cache/bus below - * high_network_0 & cache : connected to core/cache/bus above and network talking to a cache below - * high_network_0 & directory : connected to core/cache/bus above and network talking to a directory below - * directory : connected to a network talking to a cache above and a directory below (single network connection) - * cache & low_network_0 : connected to network above talking to a cache and core/cache/bus below + * Check for connected ports or port managers + * + * Complicated because of so many deprecations. Will be simpler as of SST 16 when deprecated + * names are removed. */ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { - linkUp_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, tc); - if (linkUp_) + bool highlink = isPortConnected("highlink"); + bool lowlink = isPortConnected("lowlink"); + + linkUp_ = loadUserSubComponent("highlink", ComponentInfo::SHARE_NONE, tc); + if (!linkUp_) { + linkUp_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, tc); + if (linkUp_) { + out_->output("%s, DEPRECATION WARNING: The 'cpulink' subcomponent slot has been renamed to 'highlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } else if (highlink) { + Params p; + p.insert("port", "highlink"); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, p, tc); + } + } + if (linkUp_) { linkUp_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); - - linkDown_ = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, tc); - if (linkDown_) + } + + linkDown_ = loadUserSubComponent("lowlink", ComponentInfo::SHARE_NONE, tc); + if (!linkDown_) { + linkDown_ = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, tc); + if (linkDown_) { + out_->output("%s, DEPRECATION WARNING: The 'memlink' subcomponent slot has been renamed to 'lowlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } else if (lowlink) { + Params p; + p.insert("port", "lowlink"); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, p, tc); + } + } + if (linkDown_) { linkDown_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); + } if (linkUp_ || linkDown_) { if (!linkUp_ || !linkDown_) - out_->verbose(_L3_, "%s, Detected user defined subcomponent for either the cpu or mem link but not both. Assuming this component has just one link.\n", getName().c_str()); + out_->verbose(_L3_, "%s, Detected use of either the highlink or lowlink but not both. Assuming this component has just one link.\n", getName().c_str()); if (!linkUp_) linkUp_ = linkDown_; if (!linkDown_) @@ -267,16 +296,27 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { std::string istep = params.find("interleave_step", "0B", found); gotRegion |= found; - if (!UnitAlgebra(isize).hasUnits("B")) { - out_->fatal(CALL_INFO, -1, "Invalid param(%s): interleave_size - must be specified in bytes with units (SI units OK). For example, '1KiB'. You specified '%s'\n", - getName().c_str(), isize.c_str()); + try { + UnitAlgebra isize_ua = UnitAlgebra(isize); + if (!isize_ua.hasUnits("B")) { + out_->fatal(CALL_INFO, -1, "Invalid param(%s): interleave_size - must be specified in bytes with units (SI units OK). For example, '1KiB'. You specified '%s'\n", + getName().c_str(), isize.c_str()); + } + region_.interleaveSize = isize_ua.getRoundedValue(); + } catch (UnitAlgebra::UnitAlgebraException& exc) { + out_->fatal(CALL_INFO, -1, "%s, Invalid param: Exception occurred while parsing 'interleave_size'. '%s'\n", getName().c_str(), exc.what()); } - if (!UnitAlgebra(istep).hasUnits("B")) { - out_->fatal(CALL_INFO, -1, "Invalid param(%s): interleave_step - must be specified in bytes with units (SI units OK). For example, '1KiB'. You specified '%s'\n", - getName().c_str(), istep.c_str()); + + try { + UnitAlgebra istep_ua = UnitAlgebra(istep); + if (!istep_ua.hasUnits("B")) { + out_->fatal(CALL_INFO, -1, "Invalid param(%s): interleave_step - must be specified in bytes with units (SI units OK). For example, '1KiB'. You specified '%s'\n", + getName().c_str(), istep.c_str()); + } + region_.interleaveStep = istep_ua.getRoundedValue(); + } catch (UnitAlgebra::UnitAlgebraException& exc) { + out_->fatal(CALL_INFO, -1, "%s, Invalid param: Exception occurred while parsing 'interleave_step'. '%s'\n", getName().c_str(), exc.what()); } - region_.interleaveSize = UnitAlgebra(isize).getRoundedValue(); - region_.interleaveStep = UnitAlgebra(istep).getRoundedValue(); if (!gotRegion && sliceCount > 1) { gotRegion = true; @@ -316,41 +356,59 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { } + // This is the "old" path for figuring out how the cache is connected to other components + // To update a python input file: + // (1) Add the subcomponent load line for the port(s) below + // (2) Connect the subcomponent's ports instead of the cache's ports + // + // Old Port | New method (put this in python, replace 'cache' with the component instance) + // ===================== + // high_network_0 | cache.loadSubComponent("highlink", "memHierarchy.MemLink") OR connect 'highlink' port + // low_network_0 | cache.loadSubComponent("lowlink", "memHierarchy.MemLink") OR connect 'lowlink' port + // cache | cache.loadSubComponent("highlink", "memHierarchy.MemNIC") + // directory | cache.loadSubComponent("lowlink", "memHierarchy.MemNIC") + // cache, cache_ack, cache_fwd, cache_data | cache.loadSubComponent("highlink", "memHierarchy.MemNICFour") + // directory, directory_ack, directory_fwd, directory_data | cache.loadSubComponent("lowlink", "memHierarchy.MemNICFour") + // bool highNetExists = false; // high_network_0 is connected -> direct link toward CPU (to bus or directly to other component) bool lowCacheExists = false; // cache is connected -> direct link towards memory to cache bool lowDirExists = false; // directory is connected -> network link towards memory to directory - bool lowNetExists = false; // low_network_%d port(s) are connected -> direct link towards memory (to bus or other component) + bool lowNetExists = false; // low_network_0 port is connected -> direct link towards memory (or to bus or other component) highNetExists = isPortConnected("high_network_0"); lowCacheExists = isPortConnected("cache"); lowDirExists = isPortConnected("directory"); lowNetExists = isPortConnected("low_network_0"); + + out_->output("%s, DEPRECATION WARNING: The following ports on MemHierarchy Caches are deprecated: high_network_0, cache, directory, low_network_0. MemHierarchy port names are being standardized. To connect to a non-network component, use the 'highlink' and/or 'lowlink' ports or fill the subcomponent slots of the same name with 'memHierarchy.MemLink'. To connect to a network component, fill the 'highlink' and/or 'lowlink' subcomponent slots with 'memHierarchy.MemNIC' or 'memHierarchy.MemNICFour'. When using the subcomponent slots, do not connect this cache's ports and instead connect the subcomponent's port(s). The high_network_0, low_network_0, cache, and directory ports will be removed in future versions of SST.\n", getName().c_str()); /* Check for valid port combos */ if (highNetExists) { - if (!lowCacheExists && !lowDirExists && !lowNetExists) - out_->fatal(CALL_INFO,-1,"%s, Error: no connected low ports detected. Please connect one of 'cache' or 'directory' or connect N components to 'low_network_n' where n is in the range 0 to N-1\n", + if (!lowCacheExists && !lowDirExists && !lowNetExists) { + out_->fatal(CALL_INFO,-1,"%s, Error: no connected low ports detected. Please connect 'lowlink'\n", getName().c_str()); + } if ((lowCacheExists && (lowDirExists || lowNetExists)) || (lowDirExists && lowNetExists)) - out_->fatal(CALL_INFO,-1,"%s, Error: multiple connected low port types detected. Please only connect one of 'cache', 'directory', or connect N components to 'low_network_n' where n is in the range 0 to N-1\n", + out_->fatal(CALL_INFO,-1,"%s, Error: multiple connected low port types detected. Please only connect one of 'lowlink' or fill the 'lowlink' subcomponent slot. To connect to multiple other components, use a bus or network.\n", getName().c_str()); if (isPortConnected("high_network_1")) out_->fatal(CALL_INFO,-1,"%s, Error: multiple connected high ports detected. Use the 'Bus' component to connect multiple entities to port 'high_network_0' (e.g., connect 2 L1s to a bus and connect the bus to the L2)\n", getName().c_str()); } else { if (!lowCacheExists && !lowDirExists) - out_->fatal(CALL_INFO,-1,"%s, Error: no connected ports detected. Valid ports are high_network_0, cache, directory, and low_network_n\n", + out_->fatal(CALL_INFO,-1,"%s, Error: no connected ports detected. Valid ports are highlink and lowlink or alternately, the highlink and lowlink subcomponent slots can be filled with an appropriate subcomponent such as memHierarchy.MemLink\n", getName().c_str()); } + region_.start = 0; region_.end = region_.REGION_MAX; region_.interleaveSize = 0; region_.interleaveStep = 0; - // Fix up parameters for creating NIC - eventually we'll stop doing this + // Fix up parameters for creating NIC - eventually we'll stop doing this - at SST 16 when the old config path goes away bool found; if (fixupParam(params, "network_bw", "memNIC.network_bw")) - out_->output(CALL_INFO, "Note (%s): Changed 'network_bw' to 'memNIC.network_bw' in params. Change your input file to remove this notice.\n", getName().c_str()); + out_->output(CALL_INFO, "Note (%s): Changed 'network_bw' to 'kemNIC.network_bw' in params. Change your input file to remove this notice.\n", getName().c_str()); if (fixupParam(params, "network_input_buffer_size", "memNIC.network_input_buffer_size")) out_->output(CALL_INFO, "Note (%s): Changed 'network_input_buffer_size' to 'memNIC.network_input_buffer_size' in params. Change your input file to remove this notice.\n", getName().c_str()); if (fixupParam(params, "network_output_buffer_size", "memNIC.network_output_buffer_size")) @@ -367,28 +425,28 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { nicParams.insert("shared_memory", opalShMem); nicParams.insert("local_memory_size", opalSize); - Params memlink = params.get_scoped_params("memlink"); - memlink.insert("port", "low_network_0"); - memlink.insert("node", opalNode); - memlink.insert("shared_memory", opalShMem); - memlink.insert("local_memory_size", opalSize); + Params memlinkParams = params.get_scoped_params("memlink"); + memlinkParams.insert("port", "low_network_0"); + memlinkParams.insert("node", opalNode); + memlinkParams.insert("shared_memory", opalShMem); + memlinkParams.insert("local_memory_size", opalSize); - Params cpulink = params.get_scoped_params("cpulink"); - cpulink.insert("port", "high_network_0"); - cpulink.insert("node", opalNode); - cpulink.insert("shared_memory", opalShMem); - cpulink.insert("local_memory_size", opalSize); + Params cpulinkParams = params.get_scoped_params("cpulink"); + cpulinkParams.insert("port", "high_network_0"); + cpulinkParams.insert("node", opalNode); + cpulinkParams.insert("shared_memory", opalShMem); + cpulinkParams.insert("local_memory_size", opalSize); /* Finally configure the links */ if (highNetExists && lowNetExists) { dbg_->debug(_INFO_,"Configuring cache with a direct link above and below\n"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "memlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, memlink, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, memlinkParams, tc); linkDown_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, cpulink, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, cpulinkParams, tc); linkUp_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); clockUpLink_ = clockDownLink_ = false; /* Region given to each should be identical so doesn't matter which we pull but force them to be identical */ @@ -403,6 +461,7 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { if (!found) nicParams.insert("group", "1"); if (isPortConnected("cache_ack") && isPortConnected("cache_fwd") && isPortConnected("cache_data")) { + dbg_->output("%s, WARNING: Use of the cache* ports is deprecated. Instead, place a 'memHierarchy.MemNICFour' subcomponent in this cache's 'highlink' subcomponent slot and connect the subcomponent's ports. These ports will be removed in SST 16.0.\n", getName().c_str()); nicParams.find("req.port", "", found); if (!found) nicParams.insert("req.port", "cache"); nicParams.find("ack.port", "", found); @@ -411,17 +470,17 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { if (!found) nicParams.insert("fwd.port", "cache_fwd"); nicParams.find("data.port", "", found); if (!found) nicParams.insert("data.port", "cache_data"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "memlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } else { nicParams.find("port", "", found); if (!found) nicParams.insert("port", "cache"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "memlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } linkDown_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); // Configure high link - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, cpulink, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, cpulinkParams, tc); linkUp_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); clockDownLink_ = true; clockUpLink_ = false; @@ -444,17 +503,17 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { if (!found) nicParams.insert("fwd.port", "cache_fwd"); nicParams.find("data.port", "", found); if (!found) nicParams.insert("data.port", "cache_data"); - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } else { nicParams.find("port", "", found); if (!found) nicParams.insert("port", "cache"); - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } linkUp_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); // Configure high link - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "memlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, memlink, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, memlinkParams, tc); linkDown_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); clockUpLink_ = true; clockDownLink_ = false; @@ -479,17 +538,17 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { if (!found) nicParams.insert("fwd.port", "directory_fwd"); nicParams.find("data.port", "", found); if (!found) nicParams.insert("data.port", "directory_data"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "memlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } else { nicParams.find("port", "", found); if (!found) nicParams.insert("port", "directory"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "memlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "lowlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } // Configure low link linkDown_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); // Configure high link - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, cpulink, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, cpulinkParams, tc); linkUp_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); clockDownLink_ = true; clockUpLink_ = false; @@ -498,7 +557,7 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { linkUp_->setRegion(region_); } else { // lowDirExists - + dbg_->debug(_INFO_, "Configuring cache with a network to talk to both a cache above and a directory below\n"); nicParams.find("group", "", found); @@ -554,11 +613,11 @@ void Cache::configureLinks(Params ¶ms, TimeConverter* tc) { if (!found) nicParams.insert("fwd.port", "directory_fwd"); nicParams.find("data.port", "", found); if (!found) nicParams.insert("data.port", "directory_data"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } else { nicParams.find("port", "", found); if (!found) nicParams.insert("port", "directory"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "cpulink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "highlink", 0, ComponentInfo::INSERT_STATS | ComponentInfo::SHARE_PORTS, nicParams, tc); } linkDown_->setRecvHandler(new Event::Handler(this, &Cache::handleEvent)); @@ -697,12 +756,17 @@ void Cache::createCacheArray(Params ¶ms) { /* Fix up parameters */ fixByteUnits(sizeStr); - UnitAlgebra ua(sizeStr); - if (!ua.hasUnits("B")) { - out_->fatal(CALL_INFO, -1, "%s, Invalid param: cache_size - must have units of bytes(B). Ex: '32KiB'. SI units are ok. You specified '%s'.", getName().c_str(), sizeStr.c_str()); - } + uint64_t cacheSize; + try { + UnitAlgebra ua(sizeStr); + if (!ua.hasUnits("B")) { + out_->fatal(CALL_INFO, -1, "%s, Invalid param: cache_size - must have units of bytes(B). Ex: '32KiB'. SI units are ok. You specified '%s'.", getName().c_str(), sizeStr.c_str()); + } + cacheSize = ua.getRoundedValue(); - uint64_t cacheSize = ua.getRoundedValue(); + } catch (UnitAlgebra::UnitAlgebraException& exc) { + out_->fatal(CALL_INFO, -1, "%s, Invalid param: Exception occurred while parsing 'cache_size'. '%s'\n", getName().c_str(), exc.what()); + } if (lineSize_ > cacheSize) out_->fatal(CALL_INFO, -1, "%s, Invalid param combo: cache_line_size cannot be greater than cache_size. You specified: cache_size = '%s', cache_line_size = '%" PRIu64 "'\n", diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.cc b/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.cc index 5238265eb6..ab701309cf 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.cc +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.cc @@ -199,7 +199,7 @@ bool MESIInclusive::handleGetS(MemEvent * event, bool inMSHR) { if (!localPrefetch) sendNACK(event); else - return false; + return false; /* Cannot NACK a prefetch, this will cause controller to drop it */ } return true; @@ -586,6 +586,213 @@ bool MESIInclusive::handleFlushLineInv(MemEvent * event, bool inMSHR) { return true; } +/* + * 1 source -> always send + * 2+ sources + peers -> only the min peer sends + * 2+ sources + no peers -> always send + * + * 1. Flush Manager contacts *all* coherence entities and forces a transition to flush + * -> as soon as contacted, L1s do flush. They DO NOT transition out of flush state when done + * -> Private cache -> flush when ack received. + * -> Shared cache -> forward flush + */ +bool MESIInclusive::handleFlushAll(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAll, "", 0, State::NP); + + if (!flush_manager_) { + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, false, true); + if (status == MemEventStatus::Reject) { + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { + eventDI.action = "Stall"; + // Don't forward if there's already a waiting FlushAll so we don't risk re-ordering + return true; + } + } + // Forward flush to flush manager + MemEvent* flush = new MemEvent(*event); // Copy event for forwarding + flush->setDst(flush_dest_); + forwardByDestination(flush, timestamp_ + mshrLatency_); + eventDI.action = "Forward"; + return true; + } + + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, false); + if (status == MemEventStatus::Reject) { /* No room for flush in MSHR */ + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { /* Stall for current flush */ + eventDI.action = "Stall"; + eventDI.reason = "Flush in progress"; + return true; + } + } + + switch (flush_state_) { + case FlushState::Ready: + { + /* Forward requests up (and, if flush manager to peers as well), transition to FlushState::Forward */ + // Broadcast ForwardFlush to all sources + // Broadcast ForwardFlush to all peers (if flush_manager) + // Wait for Ack from all sources & peers -> retry when count == 0 + int count = broadcastMemEventToSources(Command::ForwardFlush, event, timestamp_ + 1); + mshr_->incrementFlushCount(count); + flush_state_ = FlushState::Forward; + eventDI.action = "Begin"; + break; + } + case FlushState::Forward: + case FlushState::Drain: // Unused state in this coherence protocol, fall-thru with Forward + { + /* Have received all acks, do local flush and have all peers flush as well */ + int count = broadcastMemEventToPeers(Command::ForwardFlush, event, timestamp_ + 1); + + for (auto it : *cacheArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + count++; + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (count > 0) { + mshr_->incrementFlushCount(count); + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + break; + } /* else fall-thru */ + } + case FlushState::Invalidate: + /* Have finished invalidating */ + // Unblock/respond to sources & peers + sendResponseUp(event, nullptr, true, timestamp_); + broadcastMemEventToSources(Command::UnblockFlush, event, timestamp_ + 1); + mshr_->removeFlush(); + delete event; + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + flush_state_ = FlushState::Ready; + break; + } + + return true; +} + + +bool MESIInclusive::handleForwardFlush(MemEvent * event, bool inMSHR) { + /* Flushes are ordered by the FlushManager and coordinated by the FlushHelper at each level + * of the hierarchy. Only one cache in a set of distributed caches is the FlushHelper; + * whereas private caches and monolithic shared caches are the FlushHelper. + * + * If FlushHelper - propagate Flush upwards and notify peers when done + * If not FlushHelper - wait to be contacted by FlushHelper before flushing locally + */ + eventDI.prefill(event->getID(), Command::ForwardFlush, "", 0, State::NP); + + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, true); + if (status == MemEventStatus::Reject) { /* No room for flush in MSHR */ + sendNACK(event); + return true; + } + } + + if ( flush_helper_ ) { + switch (flush_state_) { + case FlushState::Ready: + { + int count = broadcastMemEventToSources(Command::ForwardFlush, event, timestamp_ + 1); + flush_state_ = FlushState::Forward; + mshr_->incrementFlushCount(count); + eventDI.action = "Begin"; + break; + } + case FlushState::Drain: // Unused state in this coherence protocol, fall-thru with Forward + case FlushState::Forward: + { + /* Have received all acks, do local flush and have all peers flush as well */ + int count = broadcastMemEventToPeers(Command::ForwardFlush, event, timestamp_ + 1); + mshr_->incrementFlushCount(count); + bool evictionNeeded = (count != 0); + for (auto it : *cacheArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + evictionNeeded = true; + mshr_->incrementFlushCount(); + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (evictionNeeded) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + break; + } /* else fall-thru */ + } + case FlushState::Invalidate: + /* All blocks written back and peers have ack'd - respond */ + sendResponseDown(event, nullptr, false, false); + mshr_->removeFlush(); + delete event; + flush_state_ = FlushState::Ready; + break; + } /* End switch */ + return true; + + /* Not the flush helper; Event is from flush helper */ + } else if ( isPeer(event->getSrc()) ) { + bool evictionNeeded = false; + for (auto it : *cacheArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + evictionNeeded = true; + mshr_->incrementFlushCount(); + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (evictionNeeded) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + } else { + sendResponseUp(event, nullptr, true, timestamp_); + mshr_->removeFlush(); + delete event; + flush_state_ = FlushState::Forward; + /* A bit backwards from flush helper/manager - here Forward means OK to execute another ForwardFlush */ + if ( mshr_->getFlush() != nullptr ) { + retryBuffer_.push_back(mshr_->getFlush()); + } + } + + /* Already handled ForwardFlush from flush helper/manager, retire ForwardFlush from peer */ + } else if (flush_state_ == FlushState::Forward) { + if (inMSHR) mshr_->removeFlush(); + sendResponseDown(event, nullptr, false, false); + delete event; + flush_state_ = FlushState::Ready; + return true; + } + /* Remaining case: This is a peer to the flush helper/manager and event is not from the helper/manager + * Wait until we've handled the event from peer helper/manager before handling this event + */ + + return true; +} + bool MESIInclusive::handlePutS(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); @@ -1478,6 +1685,27 @@ bool MESIInclusive::handleFlushLineResp(MemEvent * event, bool inMSHR) { } +bool MESIInclusive::handleFlushAllResp(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAllResp, "", 0, State::NP); + + MemEvent* flush_request = static_cast(mshr_->getFlush()); + mshr_->removeFlush(); // Remove FlushAll + + eventDI.action = "Respond"; + + sendResponseUp(flush_request, nullptr, true, timestamp_); + + delete flush_request; + delete event; + + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + return true; +} + + bool MESIInclusive::handleFetchResp(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); SharedCacheLine * line = cacheArray_->lookup(addr, false); @@ -1557,6 +1785,30 @@ bool MESIInclusive::handleFetchXResp(MemEvent * event, bool inMSHR) { } +bool MESIInclusive::handleAckFlush(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::AckFlush, "", 0, State::NP); + + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + delete event; + return true; +} + +bool MESIInclusive::handleUnblockFlush(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::UnblockFlush, "", 0, State::NP); + + if (flush_helper_) { + broadcastMemEventToSources(Command::UnblockFlush, event, timestamp_ + 1); + } + delete event; + + return true; +} + + bool MESIInclusive::handleAckInv(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); SharedCacheLine * line = cacheArray_->lookup(addr, false); @@ -1657,15 +1909,23 @@ bool MESIInclusive::handleNULLCMD(MemEvent* event, bool inMSHR) { if (evicted) { notifyListenerOfEvict(line->getAddr(), lineSize_, event->getInstructionPointer()); cacheArray_->deallocate(line); - retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); - mshr_->addPendingRetry(newAddr); - if (mshr_->removeEvictPointer(oldAddr, newAddr)) - retry(oldAddr); - if (is_debug_addr(newAddr)) { - eventDI.action = "Retry"; - std::stringstream reason; - reason << "0x" << std::hex << newAddr; - eventDI.reason = reason.str(); + + if (oldAddr != newAddr) { /* Reallocating a line to a new address */ + retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); + mshr_->addPendingRetry(newAddr); + if (mshr_->removeEvictPointer(oldAddr, newAddr)) + retry(oldAddr); + if (is_debug_addr(newAddr)) { + eventDI.action = "Retry"; + std::stringstream reason; + reason << "0x" << std::hex << newAddr; + eventDI.reason = reason.str(); + } + } else { /* Deallocating a line for a cache flush */ + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } } } else { // Check if we're waiting for a new address if (is_debug_addr(newAddr)) { @@ -1711,17 +1971,23 @@ bool MESIInclusive::handleNACK(MemEvent * event, bool inMSHR) { case Command::PutS: case Command::PutE: case Command::PutM: + case Command::FlushAll: resendEvent(nackedEvent, false); // Resend towards memory break; /* These *probably* need to get retried but need to handle races with Invs */ case Command::FlushLine: resendEvent(nackedEvent, false); break; + /* These always need to get retried */ + case Command::ForwardFlush: + resendEvent(nackedEvent, true); + break; /* These get retried unless there's been a race with an eviction/writeback */ case Command::FetchInv: case Command::FetchInvX: case Command::Inv: case Command::ForceInv: + if (responses.find(addr) != responses.end() && responses.find(addr)->second.find(nackedEvent->getDst()) != responses.find(addr)->second.end() && responses.find(addr)->second.find(nackedEvent->getDst())->second == nackedEvent->getID()) { diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.h b/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.h index b91d44203c..2538edd8c5 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.h +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_Inclusive.h @@ -70,7 +70,12 @@ class MESIInclusive : public CoherenceController { {"eventSent_NACK", "Number of NACKs sent", "events", 2}, {"eventSent_FlushLine", "Number of FlushLine requests sent", "events", 2}, {"eventSent_FlushLineInv", "Number of FlushLineInv requests sent", "events", 2}, + {"eventSent_FlushAll", "Number of FlushAll requests sent", "events", 2}, + {"eventSent_ForwardFlush", "Number of ForwardFlush requests sent", "events", 2}, + {"eventSent_AckFlush", "Number of AckFlush requests sent", "events", 2}, + {"eventSent_UnblockFlush", "Number of UnblockFlush requests sent", "events", 2}, {"eventSent_FlushLineResp", "Number of FlushLineResp responses sent", "events", 2}, + {"eventSent_FlushAllResp", "Number of FlushAllResp responses sent", "events", 2}, {"eventSent_Put", "Number of Put requests sent", "events", 6}, {"eventSent_Get", "Number of Get requests sent", "events", 6}, {"eventSent_AckMove", "Number of AckMove responses sent", "events", 6}, @@ -230,6 +235,7 @@ class MESIInclusive : public CoherenceController { {"latency_GetSX_upgrade", "Latency for read-exclusive misses, block present but in Shared state (includes invs in S)", "cycles", 1}, {"latency_FlushLine", "Latency for flush requests", "cycles", 1}, {"latency_FlushLineInv", "Latency for flush+invalidate requests", "cycles", 1}, + {"latency_FlushAll", "Latency for flush+all requests", "cycles", 1}, /* Track what happens to prefetched blocks */ {"prefetch_useful", "Prefetched block had a subsequent hit (useful prefetch)", "count", 2}, {"prefetch_evict", "Prefetched block was evicted/flushed before being accessed", "count", 2}, @@ -252,6 +258,8 @@ class MESIInclusive : public CoherenceController { protocolState_ = E; else protocolState_ = S; + + flush_state_ = FlushState::Ready; // Cache Array uint64_t lines = params.find("lines"); @@ -371,8 +379,11 @@ class MESIInclusive : public CoherenceController { stat_eventSent[(int)Command::Write] = registerStatistic("eventSent_Write"); stat_eventSent[(int)Command::PutS] = registerStatistic("eventSent_PutS"); stat_eventSent[(int)Command::PutM] = registerStatistic("eventSent_PutM"); + stat_eventSent[(int)Command::AckPut] = registerStatistic("eventSent_AckPut"); stat_eventSent[(int)Command::FlushLine] = registerStatistic("eventSent_FlushLine"); stat_eventSent[(int)Command::FlushLineInv] = registerStatistic("eventSent_FlushLineInv"); + stat_eventSent[(int)Command::FlushAll] = registerStatistic("eventSent_FlushAll"); + stat_eventSent[(int)Command::ForwardFlush] = registerStatistic("eventSent_ForwardFlush"); stat_eventSent[(int)Command::FetchResp] = registerStatistic("eventSent_FetchResp"); stat_eventSent[(int)Command::FetchXResp] = registerStatistic("eventSent_FetchXResp"); stat_eventSent[(int)Command::AckInv] = registerStatistic("eventSent_AckInv"); @@ -381,6 +392,9 @@ class MESIInclusive : public CoherenceController { stat_eventSent[(int)Command::GetXResp] = registerStatistic("eventSent_GetXResp"); stat_eventSent[(int)Command::WriteResp] = registerStatistic("eventSent_WriteResp"); stat_eventSent[(int)Command::FlushLineResp] = registerStatistic("eventSent_FlushLineResp"); + stat_eventSent[(int)Command::FlushAllResp] = registerStatistic("eventSent_FlushAllResp"); + stat_eventSent[(int)Command::AckFlush] = registerStatistic("eventSent_AckFlush"); + stat_eventSent[(int)Command::UnblockFlush] = registerStatistic("eventSent_UnblockFlush"); stat_eventSent[(int)Command::Fetch] = registerStatistic("eventSent_Fetch"); stat_eventSent[(int)Command::FetchInv] = registerStatistic("eventSent_FetchInv"); stat_eventSent[(int)Command::ForceInv] = registerStatistic("eventSent_ForceInv"); @@ -405,6 +419,7 @@ class MESIInclusive : public CoherenceController { stat_latencyGetSX[LatType::UPGRADE] = registerStatistic("latency_GetSX_upgrade"); stat_latencyFlushLine = registerStatistic("latency_FlushLine"); stat_latencyFlushLineInv = registerStatistic("latency_FlushLineInv"); + stat_latencyFlushAll = registerStatistic("latency_FlushAll"); stat_hit[0][0] = registerStatistic("GetSHit_Arrival"); stat_hit[1][0] = registerStatistic("GetXHit_Arrival"); stat_hit[2][0] = registerStatistic("GetSXHit_Arrival"); @@ -481,6 +496,8 @@ class MESIInclusive : public CoherenceController { virtual bool handleGetSX(MemEvent * event, bool inMSHR); virtual bool handleFlushLine(MemEvent * event, bool inMSHR); virtual bool handleFlushLineInv(MemEvent * event, bool inMSHR); + virtual bool handleFlushAll(MemEvent * event, bool inMSHR); + virtual bool handleForwardFlush(MemEvent * event, bool inMSHR); virtual bool handlePutS(MemEvent * event, bool inMSHR); virtual bool handlePutX(MemEvent * event, bool inMSHR); virtual bool handlePutE(MemEvent * event, bool inMSHR); @@ -493,10 +510,13 @@ class MESIInclusive : public CoherenceController { virtual bool handleGetSResp(MemEvent * event, bool inMSHR); virtual bool handleGetXResp(MemEvent * event, bool inMSHR); virtual bool handleFlushLineResp(MemEvent * event, bool inMSHR); + virtual bool handleFlushAllResp(MemEvent * event, bool inMSHR); virtual bool handleFetchResp(MemEvent * event, bool inMSHR); virtual bool handleFetchXResp(MemEvent * event, bool inMSHR); virtual bool handleAckInv(MemEvent * event, bool inMSHR); virtual bool handleAckPut(MemEvent * event, bool inMSHR); + virtual bool handleAckFlush(MemEvent * event, bool inMSHR); + virtual bool handleUnblockFlush(MemEvent * event, bool inMSHR); virtual bool handleNACK(MemEvent * event, bool inMSHR); virtual bool handleNULLCMD(MemEvent * event, bool inMSHR); @@ -514,6 +534,8 @@ class MESIInclusive : public CoherenceController { Command::Write, Command::FlushLine, Command::FlushLineInv, + Command::FlushAll, + Command::ForwardFlush, Command::PutS, Command::PutE, Command::PutX, @@ -528,10 +550,13 @@ class MESIInclusive : public CoherenceController { Command::GetXResp, Command::WriteResp, Command::FlushLineResp, + Command::FlushAllResp, Command::FetchResp, Command::FetchXResp, Command::AckInv, Command::AckPut, + Command::AckFlush, + Command::UnblockFlush, Command::NACK }; return cmds; } @@ -594,6 +619,8 @@ class MESIInclusive : public CoherenceController { bool protocol_; // True for MESI, false for MSI std::map > responses; + + FlushState flush_state_; /* Statistics */ Statistic* stat_latencyGetS[3]; // HIT, MISS, INV @@ -601,6 +628,7 @@ class MESIInclusive : public CoherenceController { Statistic* stat_latencyGetSX[4]; Statistic* stat_latencyFlushLine; Statistic* stat_latencyFlushLineInv; + Statistic* stat_latencyFlushAll; Statistic* stat_hit[3][2]; Statistic* stat_miss[3][2]; Statistic* stat_hits; diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.cc b/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.cc index 0ac3583736..5c1c90cf6c 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.cc +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.cc @@ -58,10 +58,15 @@ bool MESIL1::handleGetS(MemEvent * event, bool inMSHR) { eventDI.reason = "hit"; } + if (isFlushing_ && !inMSHR) { + eventDI.action = "Reject"; + eventDI.reason = "Cache flush in progress"; + return false; + } + switch (state) { case I: /* Miss */ status = processCacheMiss(event, line, inMSHR); // Attempt to allocate an MSHR entry and/or line - if (status == MemEventStatus::OK) { line = cacheArray_->lookup(addr, false); //eventProfileAndNotify(event, I, NotifyAccessType::READ, NotifyResultType::MISS, true, LatType::MISS); @@ -152,6 +157,13 @@ bool MESIL1::handleGetX(MemEvent* event, bool inMSHR) { if (inMSHR) mshr_->removePendingRetry(addr); + // Any event other than an unlock or store-conditional needs to stall for a cache flush + if (isFlushing_ && !inMSHR && !event->isStoreConditional() && !event->queryFlag(MemEvent::F_LOCKED)) { + eventDI.action = "Reject"; + eventDI.reason = "Cache flush in progress"; + return false; + } + /* Special case - if this is the last coherence level (e.g., just mem below), * can upgrade without forwarding request */ if (state == S && lastLevel_) { @@ -296,6 +308,12 @@ bool MESIL1::handleGetSX(MemEvent* event, bool inMSHR) { if (is_debug_addr(addr)) eventDI.prefill(event->getID(), event->getThreadID(), Command::GetSX, (event->isLoadLink() ? "-LL" : ""), addr, state); + + if (isFlushing_ && !inMSHR) { + eventDI.action = "Reject"; + eventDI.reason = "Cache flush in progress"; + return false; + } /* Special case - if this is the last coherence level (e.g., just mem below), * can upgrade without forwarding request */ @@ -400,6 +418,12 @@ bool MESIL1::handleFlushLine(MemEvent* event, bool inMSHR) { if (is_debug_addr(addr)) eventDI.prefill(event->getID(), event->getThreadID(), Command::FlushLine, "", addr, state); + + if (isFlushing_ && !inMSHR) { + eventDI.action = "Reject"; + eventDI.reason = "Cache flush in progress"; + return false; + } if (!inMSHR && mshr_->exists(addr)) { return (allocateMSHR(event, false) == MemEventStatus::Reject) ? false : true; @@ -460,6 +484,12 @@ bool MESIL1::handleFlushLineInv(MemEvent* event, bool inMSHR) { if (is_debug_addr(addr)) eventDI.prefill(event->getID(), event->getThreadID(), Command::FlushLineInv, "", addr, state); + + if (isFlushing_ && !inMSHR) { + eventDI.action = "Reject"; + eventDI.reason = "Cache flush in progress"; + return false; + } if (!inMSHR && mshr_->exists(addr)) { return (allocateMSHR(event, false) != MemEventStatus::Reject); @@ -515,6 +545,176 @@ bool MESIL1::handleFlushLineInv(MemEvent* event, bool inMSHR) { return true; } + +bool MESIL1::handleFlushAll(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAll, "", 0, State::NP); + + // A core shouldn't send another FlushAll while one is outstanding but just in case + if (!inMSHR) { + if (isFlushing_) { + eventDI.action = "Reject"; + eventDI.reason = "Flush in progress"; + return false; + } + + if (mshr_->insertFlush(event, false) == MemEventStatus::Reject) { + return false; + } + + isFlushing_ = true; + if (!flush_manager_) { + // Forward flush to flush manager + MemEvent* flush = new MemEvent(*event); // Copy event for forwarding + flush->setDst(flush_dest_); + forwardByDestination(flush, timestamp_ + mshrLatency_); // Time to insert event in MSHR + eventDI.action = "forward"; + return true; + } + } + + if (!flush_manager_) { + debug->fatal(CALL_INFO, -1, "%s, ERROR: Trying to retry a flushall but not the flush manager...\n", getName().c_str()); + } + + if (mshr_->getFlushSize() != mshr_->getSize()) { /* Wait for MSHR to drain */ + eventDI.action = "Drain MSHR"; + flushDrain_ = true; + return true; + } + + flushDrain_ = false; + + bool success = true; + bool evictionNeeded = false; + for (auto it : *cacheArray_) { + if (it->isLocked(timestamp_)) { + success = false; // No good, should not have issued a FlushAll between a lock/unlock! + evictionNeeded = false; + break; + } + + switch (it->getState()) { + case I: + break; + case S: + case E: + case M: + { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + evictionNeeded = true; + mshr_->incrementFlushCount(); + break; + } + default: + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + break; + } + } + + if (!evictionNeeded) { + isFlushing_ = false; + sendResponseUp(event, nullptr, true, timestamp_, success); + cleanUpAfterFlush(event); // Remove FlushAll + eventDI.action = "Respond"; + } else { + eventDI.action = "Flush"; + } + + return true; +} + + +bool MESIL1::handleForwardFlush(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::ForwardFlush, "", 0, State::NP); + MemEventStatus status = MemEventStatus::OK; + + if (!inMSHR) { + status = mshr_->insertFlush(event, true); + if (status == MemEventStatus::Reject) { + return false; /* No room for flush in MSHR */ + } else if (status == MemEventStatus::Stall) { + eventDI.action = "Stall"; + eventDI.reason = "Flush in progress"; + return true; + } + } + isFlushing_ = true; + + if (mshr_->getFlushSize() != mshr_->getSize()) { /* Wait for MSHR to drain */ + eventDI.action = "Drain MSHR"; + flushDrain_ = true; + return true; + } + + flushDrain_ = false; + + bool success = true; + bool evictionNeeded = false; + for (auto it : *cacheArray_) { + if (it->isLocked(timestamp_)) { + // Retry in a few cycles + success = false; + continue; + } + + switch (it->getState()) { + case I: + break; + case S: + case E: + case M: + { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + evictionNeeded = true; + mshr_->incrementFlushCount(); + break; + } + default: + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s, Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + break; + } + } + + if (evictionNeeded) { + // if unsuccessful that is OK, we'll retry when the evictions complete + eventDI.action = "Flush"; + } else if (!success) { // No choice but to keep retrying until the unlock occurs + retryBuffer_.push_back(event); + eventDI.action = "Retry"; + } else { + MemEvent * responseEvent = event->makeResponse(); + uint64_t deliverTime = std::max(timestamp_ + tagLatency_, flush_complete_timestamp_ + 1); + forwardByDestination(responseEvent, deliverTime); + eventDI.action = "Respond"; + + mshr_->removeFlush(); // Remove ForwardFlush + delete event; + + MemEventBase* next_flush = mshr_->getFlush(); + if (next_flush != nullptr && next_flush->getCmd() == Command::ForwardFlush) { + retryBuffer_.push_back(next_flush); + } + } + + return true; +} + + +bool MESIL1::handleUnblockFlush(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::UnblockFlush, "", 0, State::NP); + + if (mshr_->getFlush() == nullptr) + isFlushing_ = false; + delete event; + + return true; +} + + bool MESIL1::handleFetch(MemEvent* event, bool inMSHR) { Addr addr = event->getBaseAddr(); L1CacheLine* line = cacheArray_->lookup(addr, false); @@ -1021,6 +1221,26 @@ bool MESIL1::handleFlushLineResp(MemEvent * event, bool inMSHR) { } +bool MESIL1::handleFlushAllResp(MemEvent * event, bool inMSHR) { + MemEvent* flush_req = static_cast(mshr_->getFlush()); + mshr_->removeFlush(); // Remove FlushAll + + eventDI.prefill(event->getID(), flush_req->getThreadID(), Command::FlushAllResp, "", 0, State::NP); + eventDI.action = "Respond"; + + sendResponseUp(flush_req, nullptr, true, timestamp_); + + delete flush_req; + delete event; + + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + return true; +} + + bool MESIL1::handleAckPut(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); L1CacheLine * line = cacheArray_->lookup(addr, false); @@ -1037,14 +1257,14 @@ bool MESIL1::handleAckPut(MemEvent * event, bool inMSHR) { } -/* We're using NULLCMD to signal an internally generated event - in thsi case an eviction */ +/* We're using NULLCMD to signal an internally generated event - in this case an eviction */ bool MESIL1::handleNULLCMD(MemEvent * event, bool inMSHR) { Addr oldAddr = event->getAddr(); Addr newAddr = event->getBaseAddr(); L1CacheLine * line = cacheArray_->lookup(oldAddr, false); - bool evicted = handleEviction(newAddr, line); + bool evicted = handleEviction(newAddr, line, oldAddr == newAddr); if (is_debug_addr(newAddr)) { eventDI.prefill(event->getID(), Command::NULLCMD, "", line->getAddr(), evictDI.oldst); @@ -1055,15 +1275,23 @@ bool MESIL1::handleNULLCMD(MemEvent * event, bool inMSHR) { if (evicted) { notifyListenerOfEvict(line->getAddr(), lineSize_, event->getInstructionPointer()); cacheArray_->deallocate(line); - retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); - mshr_->addPendingRetry(newAddr); - if (mshr_->removeEvictPointer(oldAddr, newAddr)) - retry(oldAddr); - if (is_debug_addr(newAddr)) { - eventDI.action = "Retry"; - std::stringstream reason; - reason << "0x" << std::hex << newAddr; - eventDI.reason = reason.str(); + + if (oldAddr != newAddr) { /* Reallocating a line to a new address */ + retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); + mshr_->addPendingRetry(newAddr); + if (mshr_->removeEvictPointer(oldAddr, newAddr)) + retry(oldAddr); + if (is_debug_addr(newAddr)) { + eventDI.action = "Retry"; + std::stringstream reason; + reason << "0x" << std::hex << newAddr; + eventDI.reason = reason.str(); + } + } else { /* Deallocating a line for a cache flush */ + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } } } else { // Could be stalling for a new address or locked line if (is_debug_addr(newAddr)) { @@ -1161,7 +1389,7 @@ MemEventStatus MESIL1::checkMSHRCollision(MemEvent* event, bool inMSHR) { * Allocate a new cache line */ L1CacheLine* MESIL1::allocateLine(MemEvent* event, L1CacheLine* line) { - bool evicted = handleEviction(event->getBaseAddr(), line); + bool evicted = handleEviction(event->getBaseAddr(), line, false); if (evicted) { notifyListenerOfEvict(line->getAddr(), lineSize_, event->getInstructionPointer()); @@ -1185,7 +1413,7 @@ L1CacheLine* MESIL1::allocateLine(MemEvent* event, L1CacheLine* line) { * Evict a cacheline * Return whether successful and return line pointer via input parameters */ -bool MESIL1::handleEviction(Addr addr, L1CacheLine*& line) { +bool MESIL1::handleEviction(Addr addr, L1CacheLine*& line, bool flush) { if (!line) { line = cacheArray_->findReplacementCandidate(addr); } @@ -1210,7 +1438,7 @@ bool MESIL1::handleEviction(Addr addr, L1CacheLine*& line) { case S: if (!mshr_->getPendingRetries(line->getAddr())) { if (!silentEvictClean_) { - sendWriteback(Command::PutS, line, false); + sendWriteback(Command::PutS, line, false, flush); if (recvWritebackAck_) { mshr_->insertWriteback(line->getAddr(), false); } @@ -1225,7 +1453,7 @@ bool MESIL1::handleEviction(Addr addr, L1CacheLine*& line) { case E: if (!mshr_->getPendingRetries(line->getAddr())) { if (!silentEvictClean_) { - sendWriteback(Command::PutE, line, false); + sendWriteback(Command::PutE, line, false, flush); if (recvWritebackAck_) { mshr_->insertWriteback(line->getAddr(), false); } @@ -1239,7 +1467,7 @@ bool MESIL1::handleEviction(Addr addr, L1CacheLine*& line) { } case M: if (!mshr_->getPendingRetries(line->getAddr())) { - sendWriteback(Command::PutM, line, true); + sendWriteback(Command::PutM, line, true, flush); if (recvWritebackAck_) mshr_->insertWriteback(line->getAddr(), false); if (is_debug_addr(line->getAddr())) @@ -1278,7 +1506,7 @@ void MESIL1::cleanUpAfterRequest(MemEvent * event, bool inMSHR) { } delete event; - + /* Replay any waiting events */ if (mshr_->exists(addr)) { if (mshr_->getFrontType(addr) == MSHREntryType::Event) { @@ -1295,6 +1523,8 @@ void MESIL1::cleanUpAfterRequest(MemEvent * event, bool inMSHR) { } } } + } else if (isFlushing_ && flushDrain_ && mshr_->getSize() == mshr_->getFlushSize()) { + retryBuffer_.push_back(mshr_->getFlush()); } } @@ -1328,6 +1558,23 @@ void MESIL1::cleanUpAfterResponse(MemEvent* event, bool inMSHR) { retryBuffer_.push_back(ev); } } + } else if (isFlushing_ && flushDrain_ && mshr_->getSize() == mshr_->getFlushSize()) { + retryBuffer_.push_back(mshr_->getFlush()); + } +} + + +/* Clean up MSHR state after a FlushAll or ForwardFlush completes */ +void MESIL1::cleanUpAfterFlush(MemEvent* req, MemEvent* resp, bool inMSHR) { + if (inMSHR) mshr_->removeFlush(); + + delete req; + if (resp) delete resp; + + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } else { + isFlushing_ = false; } } @@ -1466,7 +1713,7 @@ void MESIL1::forwardFlush(MemEvent* event, L1CacheLine* line, bool evict) { * Send a writeback * Latency: cache access + tag to read data that is being written back and update coherence state */ -void MESIL1::sendWriteback(Command cmd, L1CacheLine * line, bool dirty) { +void MESIL1::sendWriteback(Command cmd, L1CacheLine * line, bool dirty, bool flush) { MemEvent* writeback = new MemEvent(cachename_, line->getAddr(), line->getAddr(), cmd); writeback->setSize(lineSize_); @@ -1483,12 +1730,20 @@ void MESIL1::sendWriteback(Command cmd, L1CacheLine * line, bool dirty) { latency = accessLatency_; } + writeback->setRqstr(cachename_); uint64_t baseTime = (timestamp_ > line->getTimestamp()) ? timestamp_ : line->getTimestamp(); uint64_t deliveryTime = baseTime + latency; forwardByAddress(writeback, deliveryTime); line->setTimestamp(deliveryTime-1); + + // If a full cache flush, we need to order flush w.r.t. *all* evictions + if (flush && deliveryTime > flush_complete_timestamp_) { + flush_complete_timestamp_ = deliveryTime; + } + + } @@ -1585,6 +1840,8 @@ std::set MESIL1::getValidReceiveEvents() { cmds.insert(Command::GetSX); cmds.insert(Command::FlushLine); cmds.insert(Command::FlushLineInv); + cmds.insert(Command::FlushAll); + cmds.insert(Command::ForwardFlush); cmds.insert(Command::Inv); cmds.insert(Command::ForceInv); cmds.insert(Command::Fetch); @@ -1594,6 +1851,8 @@ std::set MESIL1::getValidReceiveEvents() { cmds.insert(Command::GetSResp); cmds.insert(Command::GetXResp); cmds.insert(Command::FlushLineResp); + cmds.insert(Command::FlushAllResp); + cmds.insert(Command::UnblockFlush); cmds.insert(Command::AckPut); cmds.insert(Command::NACK ); diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.h b/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.h index f9a556f8f6..2c33d08fa6 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.h +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_L1.h @@ -66,7 +66,10 @@ class MESIL1 : public CoherenceController { {"eventSent_NACK", "Number of NACKs sent ", "events", 2}, {"eventSent_FlushLine", "Number of FlushLine requests sent", "events", 2}, {"eventSent_FlushLineInv", "Number of FlushLineInv requests sent", "events", 2}, + {"eventSent_FlushAll", "Number of FlushAll requests sent", "events", 2}, {"eventSent_FlushLineResp", "Number of FlushLineResp responses sent", "events", 2}, + {"eventSent_FlushAllResp", "Number of FlushAllResp responses sent", "events", 2}, + {"eventSent_AckFlush", "Number of AckFlush responses sent", "events", 2}, {"eventSent_Put", "Number of Put requests sent", "events", 6}, {"eventSent_Get", "Number of Get requests sent", "events", 6}, {"eventSent_AckMove", "Number of AckMove responses sent", "events", 6}, @@ -164,6 +167,7 @@ class MESIL1 : public CoherenceController { {"latency_FlushLine_fail", "Latency for Flush requests that failed (e.g., line was locked)", "cycles", 2}, {"latency_FlushLineInv", "Latency for Flush and Invalidate requests", "cycles", 2}, {"latency_FlushLineInv_fail", "Latency for Flush and Invalidate requests that failed (e.g., line was locked)", "cycles", 2}, + {"latency_FlushAll", "Latency for FlushAll (full cache) requests", "cycles", 2}, /* Track what happens to prefetched blocks */ {"prefetch_useful", "Prefetched block had a subsequent hit (useful prefetch)", "count", 2}, {"prefetch_evict", "Prefetched block was evicted/flushed before being accessed", "count", 2}, @@ -200,6 +204,11 @@ class MESIL1 : public CoherenceController { protocolReadState_ = S; // State to transition to when a GetXResp/clean is received in response to a read (GetS) protocolExclState_ = M; // State to transition to on a Read-exclusive/read-for-ownership } + + isFlushing_ = false; + flushDrain_ = false; + flush_complete_timestamp_ = 0; + // Cache Array uint64_t lines = params.find("lines", 0); uint64_t assoc = params.find("associativity", 0); @@ -276,13 +285,16 @@ class MESIL1 : public CoherenceController { stat_eventSent[(int)Command::NACK] = registerStatistic("eventSent_NACK"); stat_eventSent[(int)Command::FlushLine] = registerStatistic("eventSent_FlushLine"); stat_eventSent[(int)Command::FlushLineInv] = registerStatistic("eventSent_FlushLineInv"); + stat_eventSent[(int)Command::FlushAll] = registerStatistic("eventSent_FlushAll"); stat_eventSent[(int)Command::FetchResp] = registerStatistic("eventSent_FetchResp"); stat_eventSent[(int)Command::FetchXResp] = registerStatistic("eventSent_FetchXResp"); stat_eventSent[(int)Command::AckInv] = registerStatistic("eventSent_AckInv"); + stat_eventSent[(int)Command::AckFlush] = registerStatistic("eventSent_AckFlush"); stat_eventSent[(int)Command::GetSResp] = registerStatistic("eventSent_GetSResp"); stat_eventSent[(int)Command::GetXResp] = registerStatistic("eventSent_GetXResp"); stat_eventSent[(int)Command::WriteResp] = registerStatistic("eventSent_WriteResp"); stat_eventSent[(int)Command::FlushLineResp] = registerStatistic("eventSent_FlushLineResp"); + stat_eventSent[(int)Command::FlushAllResp] = registerStatistic("eventSent_FlushAllResp"); stat_eventSent[(int)Command::Put] = registerStatistic("eventSent_Put"); stat_eventSent[(int)Command::Get] = registerStatistic("eventSent_Get"); stat_eventSent[(int)Command::AckMove] = registerStatistic("eventSent_AckMove"); @@ -310,6 +322,7 @@ class MESIL1 : public CoherenceController { stat_latencyFlushLine[LatType::MISS] = registerStatistic("latency_FlushLine_fail"); stat_latencyFlushLineInv[LatType::HIT] = registerStatistic("latency_FlushLineInv"); stat_latencyFlushLineInv[LatType::MISS] = registerStatistic("latency_FlushLineInv_fail"); + stat_latencyFlushAll = registerStatistic("latency_FlushAll"); stat_hit[0][0] = registerStatistic("GetSHit_Arrival"); stat_hit[1][0] = registerStatistic("GetXHit_Arrival"); stat_hit[2][0] = registerStatistic("GetSXHit_Arrival"); @@ -371,6 +384,8 @@ class MESIL1 : public CoherenceController { bool handleGetSX(MemEvent * event, bool inMSHR); bool handleFlushLine(MemEvent * event, bool inMSHR); bool handleFlushLineInv(MemEvent * event, bool inMSHR); + bool handleFlushAll(MemEvent * event, bool inMSHR); + bool handleForwardFlush(MemEvent * event, bool inMSHR); bool handleFetch(MemEvent * event, bool inMSHR); bool handleInv(MemEvent * event, bool inMSHR); bool handleForceInv(MemEvent * event, bool inMSHR); @@ -379,6 +394,8 @@ class MESIL1 : public CoherenceController { bool handleGetSResp(MemEvent * event, bool inMSHR); bool handleGetXResp(MemEvent * event, bool inMSHR); bool handleFlushLineResp(MemEvent * event, bool inMSHR); + bool handleFlushAllResp(MemEvent * event, bool inMSHR); + bool handleUnblockFlush(MemEvent * event, bool inMSHR); bool handleAckPut(MemEvent * event, bool inMSHR); bool handleNULLCMD(MemEvent * event, bool inMSHR); bool handleNACK(MemEvent * event, bool inMSHR); @@ -410,9 +427,10 @@ class MESIL1 : public CoherenceController { MemEventStatus processCacheMiss(MemEvent * event, L1CacheLine * line, bool inMSHR); MemEventStatus checkMSHRCollision(MemEvent* event, bool inMSHR); L1CacheLine* allocateLine(MemEvent * event, L1CacheLine * line); - bool handleEviction(Addr addr, L1CacheLine *& line); + bool handleEviction(Addr addr, L1CacheLine *& line, bool flush); void cleanUpAfterRequest(MemEvent * event, bool inMSHR); void cleanUpAfterResponse(MemEvent * event, bool inMSHR); + void cleanUpAfterFlush(MemEvent * req, MemEvent * resp = nullptr, bool inMSHR = true); void retry(Addr addr); void handleLoadLinkExpiration(SST::Event* ev); @@ -420,7 +438,7 @@ class MESIL1 : public CoherenceController { uint64_t sendResponseUp(MemEvent * event, vector* data, bool inMSHR, uint64_t time, bool success = true); void sendResponseDown(MemEvent * event, L1CacheLine * line, bool data); void forwardFlush(MemEvent * event, L1CacheLine * line, bool evict); - void sendWriteback(Command cmd, L1CacheLine * line, bool dirty); + void sendWriteback(Command cmd, L1CacheLine * line, bool dirty, bool flush); void snoopInvalidation(MemEvent * event, L1CacheLine * line); void forwardByAddress(MemEventBase* ev, Cycle_t timestamp); void forwardByDestination(MemEventBase* ev, Cycle_t timestamp); @@ -432,7 +450,10 @@ class MESIL1 : public CoherenceController { /** Miscellaneous */ void printLine(Addr addr); - + + bool isFlushing_; + bool flushDrain_; + Cycle_t flush_complete_timestamp_; bool snoopL1Invs_; State protocolReadState_; // E for MESI, S for MSI State protocolExclState_; // E for MESI, M for MSI @@ -448,6 +469,7 @@ class MESIL1 : public CoherenceController { Statistic* stat_latencyGetSX[4]; Statistic* stat_latencyFlushLine[2]; Statistic* stat_latencyFlushLineInv[2]; + Statistic* stat_latencyFlushAll; Statistic* stat_hit[3][2]; Statistic* stat_miss[3][2]; Statistic* stat_hits; diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.cc b/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.cc index af9807e0f3..baaa0f538e 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.cc +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.cc @@ -485,6 +485,166 @@ bool MESIPrivNoninclusive::handleFlushLineInv(MemEvent * event, bool inMSHR) { } +bool MESIPrivNoninclusive::handleFlushAll(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAll, "", 0, State::NP); + + if (!flush_manager_) { + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, false, true); + if (status == MemEventStatus::Reject) { + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { + eventDI.action = "Stall"; + // Don't forward if there's already a waiting FlushAll so we don't risk re-ordering + return true; + } + } + // Forward flush to flush manager + MemEvent* flush = new MemEvent(*event); // Copy event for forwarding + flush->setDst(flush_dest_); + forwardByDestination(flush, timestamp_ + mshrLatency_); + eventDI.action = "Forward"; + return true; + } + + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, false); + if (status == MemEventStatus::Reject) { /* No room for flush in MSHR */ + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { /* Stall for current flush */ + eventDI.action = "Stall"; + eventDI.reason = "Flush in progress"; + return true; + } + } + + switch (flush_state_) { + case FlushState::Ready: + { + /* Forward requests up, transition to FlushState::Forward */ + // Broadcast ForwardFlush to all sources + // Wait for Ack from all sources -> retry when count == 0 + int count = broadcastMemEventToSources(Command::ForwardFlush, event, timestamp_ + 1); + mshr_->incrementFlushCount(count); + flush_state_ = FlushState::Forward; + eventDI.action = "Begin"; + break; + } + case FlushState::Forward: + { + if (mshr_->getSize() != mshr_->getFlushSize()) { + mshr_->incrementFlushCount(mshr_->getSize() - mshr_->getFlushSize()); + eventDI.action = "Drain"; + flush_state_ = FlushState::Drain; + break; + } /* else fall-thru */ + } + case FlushState::Drain: + { + /* Have received all acks, do local flush. No peers since this is a private cache. */ + bool eviction_needed = false; + + for (auto it : *cacheArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + mshr_->incrementFlushCount(); + eviction_needed = true; + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (eviction_needed) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + break; + } /* else fall-thru */ + } + case FlushState::Invalidate: + /* Have finished invalidating */ + // Unblock/respond to sources + sendResponseUp(event, nullptr, true, timestamp_); + broadcastMemEventToSources(Command::UnblockFlush, event, timestamp_ + 1); + mshr_->removeFlush(); + delete event; + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + flush_state_ = FlushState::Ready; + break; + } + + return true; +} + + +bool MESIPrivNoninclusive::handleForwardFlush(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::ForwardFlush, "", 0, State::NP); + + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, true); + if (status == MemEventStatus::Reject) { /* No room for flush in MSHR */ + sendNACK(event); + return true; + } + } + + switch (flush_state_) { + case FlushState::Ready: + { + int count = broadcastMemEventToSources(Command::ForwardFlush, event, timestamp_ + 1); + flush_state_ = FlushState::Forward; + mshr_->incrementFlushCount(count); + eventDI.action = "Begin"; + break; + } + case FlushState::Forward: + { + if (mshr_->getSize() != mshr_->getFlushSize()) { + mshr_->incrementFlushCount(mshr_->getSize() - mshr_->getFlushSize()); + eventDI.action = "Drain"; + flush_state_ = FlushState::Drain; + break; + } /* else fall-thru */ + } + case FlushState::Drain: + { + /* Have received all acks, do local flush. No peers since this is a private cache. */ + bool eviction_needed = false; + for (auto it : *cacheArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + eviction_needed = true; + mshr_->incrementFlushCount(); + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (eviction_needed) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + break; + } /* else fall-thru */ + } + case FlushState::Invalidate: + /* All blocks written back - respond */ + sendResponseDown(event, 0, nullptr, false); + mshr_->removeFlush(); + delete event; + flush_state_ = FlushState::Ready; + break; + } /* End switch */ + + return true; +} + bool MESIPrivNoninclusive::handlePutS(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); PrivateCacheLine* line = cacheArray_->lookup(addr, false); @@ -612,7 +772,7 @@ bool MESIPrivNoninclusive::handlePutE(MemEvent * event, bool inMSHR) { event->setCmd(Command::PutS); event->setDirty(false); retry(addr); - status = allocateMSHR(event, false, 1, true); + status = allocateMSHR(event, false, 1, false); } else { mshr_->setData(addr, event->getPayload(), false); mshr_->decrementAcksNeeded(addr); @@ -1581,6 +1741,26 @@ bool MESIPrivNoninclusive::handleFlushLineResp(MemEvent * event, bool inMSHR) { } +bool MESIPrivNoninclusive::handleFlushAllResp(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAllResp, "", 0, State::NP); + + MemEvent* flush_request = static_cast(mshr_->getFlush()); + mshr_->removeFlush(); // Remove FlushAll + + eventDI.action = "Respond"; + + sendResponseUp(flush_request, nullptr, true, timestamp_); + + delete flush_request; + delete event; + + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + return true; +} + // Response to a Fetch or FetchInv bool MESIPrivNoninclusive::handleFetchResp(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); @@ -1673,6 +1853,29 @@ bool MESIPrivNoninclusive::handleFetchXResp(MemEvent * event, bool inMSHR) { } +bool MESIPrivNoninclusive::handleAckFlush(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::AckFlush, "", 0, State::NP); + + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + delete event; + return true; +} + + +bool MESIPrivNoninclusive::handleUnblockFlush(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::UnblockFlush, "", 0, State::NP); + + broadcastMemEventToSources(Command::UnblockFlush, event, timestamp_ + 1); + delete event; + + return true; +} + + bool MESIPrivNoninclusive::handleAckInv(MemEvent * event, bool inMSHR) { Addr addr = event->getAddr(); PrivateCacheLine * line = cacheArray_->lookup(addr, false); @@ -1768,14 +1971,24 @@ bool MESIPrivNoninclusive::handleNULLCMD(MemEvent* event, bool inMSHR) { } if (evicted) { notifyListenerOfEvict(line->getAddr(), lineSize_, event->getInstructionPointer()); - if (mshr_->exists(newAddr) && mshr_->getStalledForEvict(newAddr)) { - debug->debug(_L5_, "%s, Retry for 0x%" PRIx64 "\n", cachename_.c_str(), newAddr); - retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); - mshr_->addPendingRetry(newAddr); - mshr_->setStalledForEvict(newAddr, false); + if (oldAddr != newAddr) { + if (mshr_->exists(newAddr) && mshr_->getStalledForEvict(newAddr)) { + debug->debug(_L5_, "%s, Retry for 0x%" PRIx64 "\n", cachename_.c_str(), newAddr); + retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); + mshr_->addPendingRetry(newAddr); + mshr_->setStalledForEvict(newAddr, false); + if (is_debug_addr(newAddr)) { + } + } + if (mshr_->removeEvictPointer(oldAddr, newAddr)) + retry(oldAddr); + } else { + cacheArray_->deallocate(line); + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } } - if (mshr_->removeEvictPointer(oldAddr, newAddr)) - retry(oldAddr); } else { // Check if we're waiting for a new address if (oldAddr != line ->getAddr()) { // We're waiting for a new line now... if (is_debug_addr(oldAddr) || is_debug_addr(line->getAddr()) || is_debug_addr(newAddr)) { @@ -1822,6 +2035,7 @@ bool MESIPrivNoninclusive::handleNACK(MemEvent* event, bool inMSHR) { case Command::PutE: case Command::PutM: case Command::PutX: + case Command::FlushAll: resendEvent(nackedEvent, false); // Resend towards memory break; case Command::FetchInv: @@ -1850,6 +2064,9 @@ bool MESIPrivNoninclusive::handleNACK(MemEvent* event, bool inMSHR) { delete nackedEvent; } break; + case Command::ForwardFlush: + resendEvent(nackedEvent, true); // Resend towards CPU + break; default: debug->fatal(CALL_INFO,-1,"%s, Error: Received NACK with unhandled command type. Event: %s. NackedEvent: %s Time = %" PRIu64 "ns\n", getName().c_str(), event->getVerboseString().c_str(), nackedEvent ? nackedEvent->getVerboseString().c_str() : "nullptr", getCurrentSimTimeNano()); @@ -1886,9 +2103,12 @@ MemEventStatus MESIPrivNoninclusive::allocateLine(MemEvent * event, PrivateCache return MemEventStatus::OK; } else { if (inMSHR || mshr_->insertEvent(event->getBaseAddr(), event, -1, false, true) != -1) { + + mshr_->insertEviction(line->getAddr(), event->getBaseAddr()); // Since we're private we never start an eviction (e.g., send invs) so it's safe to ignore an attempted eviction - if (inMSHR) + if (inMSHR) { mshr_->setStalledForEvict(event->getBaseAddr(), true); + } if (is_debug_event(event) || is_debug_addr(line->getAddr())) { stringstream reason; reason << "New evict target 0x" << std::hex << line->getAddr(); @@ -1934,7 +2154,9 @@ bool MESIPrivNoninclusive::handleEviction(Addr addr, PrivateCacheLine*& line, db if (!line->getShared() && !silentEvictClean_) { uint64_t sendTime = sendWriteback(line->getAddr(), lineSize_, Command::PutS, line->getData(), false, line->getTimestamp()); line->setTimestamp(sendTime-1); - mshr_->insertWriteback(line->getAddr(), false); + if (!lastLevel_) { + mshr_->insertWriteback(line->getAddr(), false); + } if (is_debug_addr(line->getAddr())) printDebugAlloc(false, line->getAddr(), "Writeback"); if (is_debug_addr(addr) || is_debug_addr(line->getAddr())) { @@ -1953,7 +2175,9 @@ bool MESIPrivNoninclusive::handleEviction(Addr addr, PrivateCacheLine*& line, db if (line->getShared()) { uint64_t sendTime = sendWriteback(line->getAddr(), lineSize_, Command::PutX, line->getData(), false, line->getTimestamp()); line->setTimestamp(sendTime-1); - mshr_->insertWriteback(line->getAddr(), true); + if (!lastLevel_) { + mshr_->insertWriteback(line->getAddr(), true); + } if (is_debug_addr(addr) || is_debug_addr(line->getAddr())) diStruct.action = "Writeback"; if (is_debug_addr(line->getAddr())) @@ -1961,7 +2185,9 @@ bool MESIPrivNoninclusive::handleEviction(Addr addr, PrivateCacheLine*& line, db } else if (!line->getOwned() && !silentEvictClean_) { uint64_t sendTime = sendWriteback(line->getAddr(), lineSize_, Command::PutE, line->getData(), false, line->getTimestamp()); line->setTimestamp(sendTime-1); - mshr_->insertWriteback(line->getAddr(), false); + if (!lastLevel_) { + mshr_->insertWriteback(line->getAddr(), false); + } if (is_debug_addr(line->getAddr())) printDebugAlloc(false, line->getAddr(), "Writeback"); if (is_debug_addr(addr) || is_debug_addr(line->getAddr())) @@ -1979,7 +2205,9 @@ bool MESIPrivNoninclusive::handleEviction(Addr addr, PrivateCacheLine*& line, db if (line->getShared()) { uint64_t sendTime = sendWriteback(line->getAddr(), lineSize_, Command::PutX, line->getData(), true, line->getTimestamp()); line->setTimestamp(sendTime-1); - mshr_->insertWriteback(line->getAddr(), true); + if (!lastLevel_) { + mshr_->insertWriteback(line->getAddr(), true); + } if (is_debug_addr(addr) || is_debug_addr(line->getAddr())) diStruct.action = "Writeback"; if (is_debug_addr(line->getAddr())) @@ -1987,7 +2215,9 @@ bool MESIPrivNoninclusive::handleEviction(Addr addr, PrivateCacheLine*& line, db } else if (!line->getOwned()) { uint64_t sendTime = sendWriteback(line->getAddr(), lineSize_, Command::PutM, line->getData(), true, line->getTimestamp()); line->setTimestamp(sendTime-1); - mshr_->insertWriteback(line->getAddr(), false); + if (!lastLevel_) { + mshr_->insertWriteback(line->getAddr(), false); + } if (is_debug_addr(addr) || is_debug_addr(line->getAddr())) { diStruct.action = "Writeback"; } @@ -2051,6 +2281,14 @@ void MESIPrivNoninclusive::cleanUpEvent(MemEvent* event, bool inMSHR) { /* Remove from MSHR */ if (inMSHR) { mshr_->removeFront(addr); + + if (flush_state_ == FlushState::Drain) { + mshr_->decrementFlushCount(); + // Retry flush if done draining + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } + } } delete event; @@ -2181,7 +2419,6 @@ uint64_t MESIPrivNoninclusive::sendResponseUp(MemEvent * event, vector if (!success) responseEvent->setFail(); - // Compute latency, accounting for serialization of requests to the address if (time < timestamp_) time = timestamp_; uint64_t deliveryTime = time + (inMSHR ? mshrLatency_ : accessLatency_); diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.h b/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.h index 7c992248af..68053d6194 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.h +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_Private_Noninclusive.h @@ -71,6 +71,11 @@ class MESIPrivNoninclusive : public CoherenceController { {"eventSent_FlushLine", "Number of FlushLine requests sent", "events", 2}, {"eventSent_FlushLineInv", "Number of FlushLineInv requests sent", "events", 2}, {"eventSent_FlushLineResp", "Number of FlushLineResp responses sent", "events", 2}, + {"eventSent_FlushAll", "Number of FlushAll requests sent", "events", 2}, + {"eventSent_FlushAllResp", "Number of FlushAllResp responses sent", "events", 2}, + {"eventSent_ForwardFlush", "Number of ForwardFlush requests sent", "events", 2}, + {"eventSent_UnblockFlush", "Number of UnblockFlush requests sent", "events", 2}, + {"eventSent_AckFlush", "Number of AckFlush requests sent", "events", 2}, {"eventSent_Put", "Number of Put requests sent", "events", 6}, {"eventSent_Get", "Number of Get requests sent", "events", 6}, {"eventSent_AckMove", "Number of AckMove responses sent", "events", 6}, @@ -232,6 +237,8 @@ class MESIPrivNoninclusive : public CoherenceController { cacheArray_ = new CacheArray(debug, lines, assoc, lineSize_, rmgr, ht); cacheArray_->setBanked(params.find("banks", 0)); + flush_state_ = FlushState::Ready; + stat_evict[I] = registerStatistic("evict_I"); stat_evict[S] = registerStatistic("evict_S"); stat_evict[M] = registerStatistic("evict_M"); @@ -323,6 +330,11 @@ class MESIPrivNoninclusive : public CoherenceController { stat_eventSent[(int)Command::PutX] = registerStatistic("eventSent_PutX"); stat_eventSent[(int)Command::FlushLine] = registerStatistic("eventSent_FlushLine"); stat_eventSent[(int)Command::FlushLineInv] = registerStatistic("eventSent_FlushLineInv"); + stat_eventSent[(int)Command::FlushAll] = registerStatistic("eventSent_FlushAll"); + stat_eventSent[(int)Command::FlushAllResp] = registerStatistic("eventSent_FlushAllResp"); + stat_eventSent[(int)Command::ForwardFlush] = registerStatistic("eventSent_ForwardFlush"); + stat_eventSent[(int)Command::UnblockFlush] = registerStatistic("eventSent_UnblockFlush"); + stat_eventSent[(int)Command::AckFlush] = registerStatistic("eventSent_AckFlush"); stat_eventSent[(int)Command::FetchResp] = registerStatistic("eventSent_FetchResp"); stat_eventSent[(int)Command::FetchXResp] = registerStatistic("eventSent_FetchXResp"); stat_eventSent[(int)Command::AckInv] = registerStatistic("eventSent_AckInv"); @@ -418,43 +430,50 @@ class MESIPrivNoninclusive : public CoherenceController { *---------------------------------------------------------------------------------------------------------------------*/ /* Event handlers */ - virtual bool handleGetS(MemEvent * event, bool inMSHR); - virtual bool handleGetX(MemEvent * event, bool inMSHR); - virtual bool handleGetSX(MemEvent * event, bool inMSHR); - virtual bool handleFlushLine(MemEvent * event, bool inMSHR); - virtual bool handleFlushLineInv(MemEvent * event, bool inMSHR); - virtual bool handlePutS(MemEvent * event, bool inMSHR); - virtual bool handlePutE(MemEvent * event, bool inMSHR); - virtual bool handlePutM(MemEvent * event, bool inMSHR); - virtual bool handlePutX(MemEvent * event, bool inMSHR); - virtual bool handleFetch(MemEvent * event, bool inMSHR); - virtual bool handleInv(MemEvent * event, bool inMSHR); - virtual bool handleForceInv(MemEvent * event, bool inMSHR); - virtual bool handleFetchInv(MemEvent * event, bool inMSHR); - virtual bool handleFetchInvX(MemEvent * event, bool inMSHR); - virtual bool handleGetSResp(MemEvent * event, bool inMSHR); - virtual bool handleGetXResp(MemEvent * event, bool inMSHR); - virtual bool handleFlushLineResp(MemEvent * event, bool inMSHR); - virtual bool handleFetchResp(MemEvent * event, bool inMSHR); - virtual bool handleFetchXResp(MemEvent * event, bool inMSHR); - virtual bool handleAckInv(MemEvent * event, bool inMSHR); - virtual bool handleAckPut(MemEvent * event, bool inMSHR); - virtual bool handleNULLCMD(MemEvent * event, bool inMSHR); - virtual bool handleNACK(MemEvent* event, bool inMSHR); - - virtual Addr getBank(Addr addr) { return cacheArray_->getBank(addr); } - virtual void setSliceAware(uint64_t size, uint64_t step) { cacheArray_->setSliceAware(size, step); } + virtual bool handleGetS(MemEvent * event, bool inMSHR) override; + virtual bool handleGetX(MemEvent * event, bool inMSHR) override; + virtual bool handleGetSX(MemEvent * event, bool inMSHR) override; + virtual bool handleFlushLine(MemEvent * event, bool inMSHR) override; + virtual bool handleFlushLineInv(MemEvent * event, bool inMSHR) override; + virtual bool handleFlushAll(MemEvent * event, bool inMSHR) override; + virtual bool handleForwardFlush(MemEvent * event, bool inMSHR) override; + virtual bool handlePutS(MemEvent * event, bool inMSHR) override; + virtual bool handlePutE(MemEvent * event, bool inMSHR) override; + virtual bool handlePutM(MemEvent * event, bool inMSHR) override; + virtual bool handlePutX(MemEvent * event, bool inMSHR) override; + virtual bool handleFetch(MemEvent * event, bool inMSHR) override; + virtual bool handleInv(MemEvent * event, bool inMSHR) override; + virtual bool handleForceInv(MemEvent * event, bool inMSHR) override; + virtual bool handleFetchInv(MemEvent * event, bool inMSHR) override; + virtual bool handleFetchInvX(MemEvent * event, bool inMSHR) override; + virtual bool handleGetSResp(MemEvent * event, bool inMSHR) override; + virtual bool handleGetXResp(MemEvent * event, bool inMSHR) override; + virtual bool handleFlushLineResp(MemEvent * event, bool inMSHR) override; + virtual bool handleFlushAllResp(MemEvent * event, bool inMSHR) override; + virtual bool handleFetchResp(MemEvent * event, bool inMSHR) override; + virtual bool handleFetchXResp(MemEvent * event, bool inMSHR) override; + virtual bool handleAckFlush(MemEvent * event, bool inMSHR) override; + virtual bool handleUnblockFlush(MemEvent * event, bool inMSHR) override; + virtual bool handleAckInv(MemEvent * event, bool inMSHR) override; + virtual bool handleAckPut(MemEvent * event, bool inMSHR) override; + virtual bool handleNULLCMD(MemEvent * event, bool inMSHR) override; + virtual bool handleNACK(MemEvent* event, bool inMSHR) override; + + virtual Addr getBank(Addr addr) override { return cacheArray_->getBank(addr); } + virtual void setSliceAware(uint64_t size, uint64_t step) override { cacheArray_->setSliceAware(size, step); } /* Initialization */ - virtual void hasUpperLevelCacheName(std::string cachename); - MemEventInitCoherence* getInitCoherenceEvent(); + virtual void hasUpperLevelCacheName(std::string cachename) override; + MemEventInitCoherence* getInitCoherenceEvent() override; - std::set getValidReceiveEvents() { + std::set getValidReceiveEvents() override { std::set cmds = { Command::GetS, Command::GetX, Command::GetSX, Command::FlushLine, Command::FlushLineInv, + Command::FlushAll, + Command::ForwardFlush, Command::PutS, Command::PutE, Command::PutM, @@ -468,8 +487,11 @@ class MESIPrivNoninclusive : public CoherenceController { Command::GetSResp, Command::GetXResp, Command::FlushLineResp, + Command::FlushAllResp, Command::FetchResp, Command::FetchXResp, + Command::AckFlush, + Command::UnblockFlush, Command::AckInv, Command::AckPut, Command::Write, @@ -496,7 +518,7 @@ class MESIPrivNoninclusive : public CoherenceController { uint64_t sendFwdRequest(MemEvent * event, Command cmd, std::string dst, uint32_t size, uint64_t startTime, bool inMSHR); /** Send response up (to processor) */ - uint64_t sendResponseUp(MemEvent * event, vector* data, bool inMSHR, uint64_t baseTime, Command cmd = Command::GetSResp, bool success = true); + uint64_t sendResponseUp(MemEvent * event, vector* data, bool inMSHR, uint64_t baseTime, Command cmd = Command::NULLCMD, bool success = true); uint64_t sendExclusiveResponse(MemEvent * event, vector* data, bool inMSHR, uint64_t baseTime, bool dirty); /** Send response down (towards memory) */ @@ -512,19 +534,20 @@ class MESIPrivNoninclusive : public CoherenceController { void forwardMessageUp(MemEvent * event); /** Call through to coherenceController with statistic recording */ - void forwardByAddress(MemEventBase* ev, Cycle_t timestamp); - void forwardByDestination(MemEventBase* ev, Cycle_t timestamp); + void forwardByAddress(MemEventBase* ev, Cycle_t timestamp) override; + void forwardByDestination(MemEventBase* ev, Cycle_t timestamp) override; /* Miscellaneous */ void printLine(Addr addr); /* Statistics */ - void recordLatency(Command cmd, int type, uint64_t latency); + void recordLatency(Command cmd, int type, uint64_t latency) override; /* Private data members */ CacheArray * cacheArray_; // Cache array bool protocol_; // True for MESI, false for MSI State protocolState_; + FlushState flush_state_; std::string upperCacheName_; // Private so only one diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.cc b/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.cc index d0b3ee55c9..c23ebb14bf 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.cc +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.cc @@ -480,7 +480,6 @@ bool MESISharNoninclusive::handleFlushLine(MemEvent* event, bool inMSHR) { return true; } - /* Flush a line from cache & invalidate it */ bool MESISharNoninclusive::handleFlushLineInv(MemEvent* event, bool inMSHR) { Addr addr = event->getBaseAddr(); @@ -618,6 +617,229 @@ bool MESISharNoninclusive::handleFlushLineInv(MemEvent* event, bool inMSHR) { } +bool MESISharNoninclusive::handleFlushAll(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAll, "", 0, State::NP); + + if (!flush_manager_) { + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, false, true); + if (status == MemEventStatus::Reject) { + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { + eventDI.action = "Stall"; + // Don't forward if there's already a waiting FlushAll so we don't risk re-ordering + return true; + } + } + // Forward flush to flush manager + MemEvent* flush = new MemEvent(*event); // Copy event for forwarding + flush->setDst(flush_dest_); + forwardByDestination(flush, timestamp_ + mshrLatency_); + eventDI.action = "Forward"; + return true; + } + + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, false); + if (status == MemEventStatus::Reject) { /* No room for flush in MSHR */ + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { /* Stall for current flush */ + eventDI.action = "Stall"; + eventDI.reason = "Flush in progress"; + return true; + } + } + + switch (flush_state_) { + case FlushState::Ready: + { + /* Forward requests up (and, if flush manager to peers as well), transition to FlushState::Forward */ + // Broadcast ForwardFlush to all sources + // Broadcast ForwardFlush to all peers (if flush_manager) + // Wait for Ack from all sources & peers -> retry when count == 0 + int count = broadcastMemEventToSources(Command::ForwardFlush, event, timestamp_ + 1); + mshr_->incrementFlushCount(count); + flush_state_ = FlushState::Forward; + eventDI.action = "Begin"; + break; + } + case FlushState::Forward: + { + int count = broadcastMemEventToPeers(Command::ForwardFlush, event, timestamp_ + 1); + mshr_->incrementFlushCount(count); + + if (mshr_->getSize() != mshr_->getFlushSize()) { + mshr_->incrementFlushCount(mshr_->getSize() - mshr_->getFlushSize()); + eventDI.action = "Drain"; + flush_state_ = FlushState::Drain; + break; + } /* else fall-thru */ + } + case FlushState::Drain: + { + /* Have received all acks and drained MSHR if needed, do local flush */ + /* OK if peers have not all ack'd yet */ + for (auto it : *dirArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + mshr_->incrementFlushCount(); + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (mshr_->getFlushCount() != 0) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + break; + } /* else fall-thru */ + } + case FlushState::Invalidate: + /* Have finished invalidating and all peers have flushed */ + // Unblock/respond to sources & peers + sendResponseUp(event, nullptr, true, timestamp_); + broadcastMemEventToSources(Command::UnblockFlush, event, timestamp_ + 1); + mshr_->removeFlush(); + delete event; + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + flush_state_ = FlushState::Ready; + break; + } + + return true; + + +} + +bool MESISharNoninclusive::handleForwardFlush(MemEvent* event, bool inMSHR) { + /* Flushes are ordered by the FlushManager and coordinated by the FlushHelper at each level + * of the hierarchy. Only one cache in a set of distributed caches is the FlushHelper; + * whereas private caches and monolithic shared caches are the FlushHelper. + * + * If FlushHelper - propagate Flush upwards and notify peers when done + * If not FlushHelper - wait to be contacted by FlushHelper before flushing locally + */ + eventDI.prefill(event->getID(), Command::ForwardFlush, "", 0, State::NP); + + if (!inMSHR) { + MemEventStatus status = mshr_->insertFlush(event, true); + if (status == MemEventStatus::Reject) { /* No room for flush in MSHR */ + sendNACK(event); + return true; + } + } + + if ( flush_helper_ ) { + switch (flush_state_) { + case FlushState::Ready: + { + int count = broadcastMemEventToSources(Command::ForwardFlush, event, timestamp_ + 1); + flush_state_ = FlushState::Forward; + mshr_->incrementFlushCount(count); + eventDI.action = "Begin"; + break; + } + case FlushState::Forward: + { + int count = broadcastMemEventToPeers(Command::ForwardFlush, event, timestamp_ + 1); + mshr_->incrementFlushCount(count); + + if (mshr_->getSize() != mshr_->getFlushSize()) { + mshr_->incrementFlushCount(mshr_->getSize() - mshr_->getFlushSize()); + eventDI.action = "Drain"; + flush_state_ = FlushState::Drain; + break; + } /* else fall-thru */ + } + case FlushState::Drain: + { + /* Have received all acks and drained MSHR if needed, do local flush */ + /* OK if peers have not all ack'd yet */ + for (auto it : *dirArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + mshr_->incrementFlushCount(); + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (mshr_->getFlushCount()) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + break; + } /* else fall-thru */ + } + case FlushState::Invalidate: + /* All blocks written back and peers have ack'd - respond */ + sendResponseDown(event, nullptr, false, false); + mshr_->removeFlush(); + delete event; + flush_state_ = FlushState::Ready; + break; + } /* End switch */ + return true; + + /* Not the flush helper; Event is from flush helper */ + } else if ( isPeer(event->getSrc()) ) { + if (mshr_->getSize() != mshr_->getFlushSize()) { // Drain outstanding Put* before invalidating cache + mshr_->incrementFlushCount(mshr_->getSize() - mshr_->getFlushSize()); + eventDI.action = "Drain"; + flush_state_ = FlushState::Drain; + + } else { + bool evictionNeeded = false; + for (auto it : *dirArray_) { + if (it->getState() == I) continue; + if (it->getState() == S || it->getState() == E || it->getState() == M) { + MemEvent * ev = new MemEvent(cachename_, it->getAddr(), it->getAddr(), Command::NULLCMD); + retryBuffer_.push_back(ev); + evictionNeeded = true; + mshr_->incrementFlushCount(); + } else { + debug->fatal(CALL_INFO, -1, "%s, Error: Attempting to flush a cache line that is in a transient state '%s'. Addr = 0x%" PRIx64 ". Event: %s. Time: %" PRIu64 "ns\n", + cachename_.c_str(), StateString[it->getState()], it->getAddr(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + } + } + if (evictionNeeded) { + eventDI.action = "Flush"; + flush_state_ = FlushState::Invalidate; + } else { + sendResponseUp(event, nullptr, true, timestamp_); + mshr_->removeFlush(); + delete event; + flush_state_ = FlushState::Forward; + /* A bit backwards from flush helper/manager - here Forward means OK to execute another ForwardFlush */ + if ( mshr_->getFlush() != nullptr ) { + retryBuffer_.push_back(mshr_->getFlush()); + } + } + } + + /* Already handled ForwardFlush from flush helper/manager, retire ForwardFlush from peer */ + } else if (flush_state_ == FlushState::Forward) { + if (inMSHR) mshr_->removeFlush(); + sendResponseDown(event, nullptr, false, false); + delete event; + flush_state_ = FlushState::Ready; + return true; + } + /* Remaining case: This is a peer to the flush helper/manager and event is not from the helper/manager + * Wait until we've handled the event from peer helper/manager before handling this event + */ + + return true; +} + + bool MESISharNoninclusive::handlePutS(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); DirectoryLine * tag = dirArray_->lookup(addr, false); @@ -646,7 +868,7 @@ bool MESISharNoninclusive::handlePutS(MemEvent * event, bool inMSHR) { status = processDataMiss(event, tag, data, true); if (status != MemEventStatus::OK) { if (!mshr_->getProfiled(addr)) { - stat_eventState[(int)Command::PutS][I]->addData(1); + stat_eventState[(int)Command::PutS][state]->addData(1); mshr_->setProfiled(addr); } if (state == S) tag->setState(SA); @@ -661,7 +883,7 @@ bool MESISharNoninclusive::handlePutS(MemEvent * event, bool inMSHR) { inMSHR = true; } if (!inMSHR || !mshr_->getProfiled(addr)) { - stat_eventState[(int)Command::PutS][I]->addData(1); + stat_eventState[(int)Command::PutS][state]->addData(1); } tag->removeSharer(event->getSrc()); sendWritebackAck(event); @@ -672,15 +894,17 @@ bool MESISharNoninclusive::handlePutS(MemEvent * event, bool inMSHR) { case M_Inv: case SM_Inv: removeSharerViaInv(event, tag, data, true); - if (mshr_->decrementAcksNeeded(addr)) { - tag->setState(NextState[state]); - retry(addr); - } sendWritebackAck(event); if (inMSHR || !mshr_->getProfiled(addr)) { stat_eventState[(int)Command::PutS][state]->addData(1); } - cleanUpAfterRequest(event, inMSHR); + if (mshr_->decrementAcksNeeded(addr)) { + tag->setState(NextState[state]); + retry(addr); + cleanUpEvent(event, inMSHR); + } else { + cleanUpAfterRequest(event, inMSHR); + } break; case S_B: case E_B: @@ -831,7 +1055,6 @@ bool MESISharNoninclusive::handlePutE(MemEvent * event, bool inMSHR) { case E_Inv: case M_Inv: tag->removeOwner(); - mshr_->decrementAcksNeeded(addr); if (!data && !mshr_->hasData(addr)) mshr_->setData(addr, event->getPayload()); responses.find(addr)->second.erase(event->getSrc()); @@ -839,7 +1062,14 @@ bool MESISharNoninclusive::handlePutE(MemEvent * event, bool inMSHR) { responses.erase(addr); sendWritebackAck(event); tag->setState(NextState[state]); - cleanUpAfterRequest(event, inMSHR); + + if (mshr_->decrementAcksNeeded(addr)) { + retry(addr); + cleanUpEvent(event, inMSHR); + } else { + cleanUpAfterRequest(event, inMSHR); + } + if (!inMSHR || !mshr_->getProfiled(addr)) { stat_eventState[(int)Command::PutE][state]->addData(1); } @@ -879,9 +1109,16 @@ bool MESISharNoninclusive::handlePutM(MemEvent * event, bool inMSHR) { case E: case M: if (!data) { // Need to allocate line - status = inMSHR ? MemEventStatus::OK : allocateMSHR(event, false, -1); - if (status != MemEventStatus::OK) + status = inMSHR ? MemEventStatus::OK : allocateMSHR(event, false, -1); // In case we need to stall dataline allocation + if (status == MemEventStatus::Reject) { break; + } else if (status == MemEventStatus::Stall) { + if (is_debug_event(event)) { + eventDI.action = "Stall"; + eventDI.reason = "MSHR conflict"; + } + break; + } if (!inMSHR || !mshr_->getProfiled(addr)) { stat_eventState[(int)Command::PutM][state]->addData(1); mshr_->setProfiled(addr); @@ -889,16 +1126,20 @@ bool MESISharNoninclusive::handlePutM(MemEvent * event, bool inMSHR) { status = processDataMiss(event, tag, data, true); if (status != MemEventStatus::OK) { tag->setState(MA); + if (is_debug_event(event)) { + eventDI.action = "Stall"; + eventDI.reason = "Data line miss"; + } break; } - data = dataArray_->lookup(addr, true); - data->setData(event->getPayload(), 0); - if (is_debug_addr(addr)) - printDataValue(addr, &(event->getPayload()), true); inMSHR = true; } else if (!inMSHR || !mshr_->getProfiled(addr)) { stat_eventState[(int)Command::PutM][state]->addData(1); } + if (is_debug_addr(addr)) + printDataValue(addr, &(event->getPayload()), true); + data = dataArray_->lookup(addr, true); + data->setData(event->getPayload(), 0); if (is_debug_event(event)) eventDI.reason = "hit"; @@ -909,6 +1150,7 @@ bool MESISharNoninclusive::handlePutM(MemEvent * event, bool inMSHR) { break; case E_InvX: case M_InvX: + { tag->removeOwner(); mshr_->decrementAcksNeeded(addr); responses.find(addr)->second.erase(event->getSrc()); @@ -937,18 +1179,19 @@ bool MESISharNoninclusive::handlePutM(MemEvent * event, bool inMSHR) { status = allocateMSHR(event, false, 2); // Retry the waiting event and waiting forward request, then handle this replacement else status = allocateMSHR(event, false, 1); // Retry the waiting event, then handle this replacement - - retry(addr); } + retry(addr); break; + } case E_Inv: case M_Inv: if (!inMSHR || !mshr_->getProfiled(addr)) { stat_eventState[(int)Command::PutM][state]->addData(1); } - // Handle the coherence state part and buffer the data in the MSHR, we won't need a line because we're either losing the data or one of our children wants it + // Handle the coherence state part and buffer the data in the MSHR. + // We won't need a line because we're either deallocating the data or one of our children wants it tag->removeOwner(); - mshr_->decrementAcksNeeded(addr); + if (!data && !mshr_->hasData(addr)) mshr_->setData(addr, event->getPayload()); responses.find(addr)->second.erase(event->getSrc()); @@ -956,7 +1199,13 @@ bool MESISharNoninclusive::handlePutM(MemEvent * event, bool inMSHR) { responses.erase(addr); sendWritebackAck(event); tag->setState(M); - cleanUpAfterRequest(event, inMSHR); + + if (mshr_->decrementAcksNeeded(addr)) { + retry(addr); + cleanUpEvent(event, inMSHR); + } else { + cleanUpAfterRequest(event, inMSHR); + } break; default: debug->fatal(CALL_INFO,-1,"%s, Error: Received PutM in unhandled state '%s'. Event: %s. Time = %" PRIu64 "ns\n", @@ -1198,14 +1447,16 @@ bool MESISharNoninclusive::handleInv(MemEvent * event, bool inMSHR) { delete event; break; case S: - if (tag->hasSharers() && !inMSHR) + if (tag->hasSharers() && !inMSHR) { status = allocateMSHR(event, true, 0); + inMSHR = status != MemEventStatus::Reject; + } if (status == MemEventStatus::OK) { - if (!mshr_->getProfiled(addr)) { + if (!inMSHR || !mshr_->getProfiled(addr)) { recordPrefetchResult(tag, statPrefetchInv); stat_eventState[(int)Command::Inv][state]->addData(1); - mshr_->setProfiled(addr); + if (inMSHR) mshr_->setProfiled(addr); } if (tag->hasSharers()) { @@ -2029,6 +2280,27 @@ bool MESISharNoninclusive::handleFlushLineResp(MemEvent * event, bool inMSHR) { } +bool MESISharNoninclusive::handleFlushAllResp(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAllResp, "", 0, State::NP); + + MemEvent* flush_request = static_cast(mshr_->getFlush()); + mshr_->removeFlush(); // Remove FlushAll + + eventDI.action = "Respond"; + + sendResponseUp(flush_request, nullptr, true, timestamp_); + + delete flush_request; + delete event; + + if (mshr_->getFlush() != nullptr) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + return true; +} + + bool MESISharNoninclusive::handleFetchResp(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); DirectoryLine * tag = dirArray_->lookup(addr, false); @@ -2173,6 +2445,31 @@ bool MESISharNoninclusive::handleFetchXResp(MemEvent * event, bool inMSHR) { } +bool MESISharNoninclusive::handleAckFlush(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::AckFlush, "", 0, State::NP); + + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } + + delete event; + return true; +} + + +bool MESISharNoninclusive::handleUnblockFlush(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::UnblockFlush, "", 0, State::NP); + + if (flush_helper_) { + broadcastMemEventToSources(Command::UnblockFlush, event, timestamp_ + 1); + } + delete event; + + return true; +} + + bool MESISharNoninclusive::handleAckInv(MemEvent * event, bool inMSHR) { Addr addr = event->getAddr(); DirectoryLine * tag = dirArray_->lookup(addr, false); @@ -2236,17 +2533,21 @@ bool MESISharNoninclusive::handleNULLCMD(MemEvent* event, bool inMSHR) { Addr newAddr = event->getBaseAddr(); // Is this a data eviction or directory eviction? - bool dirEvict = evictionType_.find(std::make_pair(oldAddr,newAddr))->second; + bool dirEvict = oldAddr != newAddr ? evictionType_.find(std::make_pair(oldAddr,newAddr))->second : false; bool evicted; // Tag/directory array eviction if (dirEvict) { DirectoryLine * tag = dirArray_->lookup(oldAddr, false); - if (is_debug_event(event)) { - eventDI.prefill(event->getID(), Command::NULLCMD, "", oldAddr, evictDI.oldst); - } evicted = handleDirEviction(newAddr, tag); + + if (is_debug_addr(newAddr) || is_debug_addr(evictDI.addr)) { + eventDI.prefill(event->getID(), Command::NULLCMD, "", evictDI.addr, evictDI.oldst); + eventDI.newst = tag->getState(); + eventDI.verboseline = tag->getString(); + } + if (evicted) { notifyListenerOfEvict(tag->getAddr(), lineSize_, event->getInstructionPointer()); retryBuffer_.push_back(mshr_->getFrontEvent(newAddr)); @@ -2279,16 +2580,19 @@ bool MESISharNoninclusive::handleNULLCMD(MemEvent* event, bool inMSHR) { } } } + } else { // Data array eviction - // Races can mean that this eviction is no longer neccessary but we can't tell if we haven't started the eviction + // Races can mean that this eviction is no longer necessary but we can't tell if we haven't started the eviction // or if we're finishing. So finish it, but only replace if we currently need an eviction // (the event waiting for eviction now and the one that triggered this eviction might not be the same) - } else { DirectoryLine * tag = dirArray_->lookup(newAddr, false); DataLine * data = dataArray_->lookup(oldAddr, false); evicted = handleDataEviction(newAddr, data); - if (is_debug_event(event)) { - eventDI.prefill(event->getID(), Command::NULLCMD, "", data->getAddr(), evictDI.oldst); + + if (is_debug_addr(newAddr) || is_debug_addr(evictDI.addr)) { + eventDI.prefill(event->getID(), Command::NULLCMD, "", evictDI.addr, evictDI.oldst); + eventDI.newst = data ? data->getState() : I; + eventDI.verboseline = data ? data->getString() : ""; } if (evicted) { if (tag && (tag->getState() == IA || tag->getState() == SA || tag->getState() == EA || tag->getState() == MA)) { @@ -2310,15 +2614,22 @@ bool MESISharNoninclusive::handleNULLCMD(MemEvent* event, bool inMSHR) { } else { dataArray_->deallocate(data); } - - if (mshr_->removeEvictPointer(oldAddr, newAddr)) - retry(oldAddr); - evictionType_.erase(std::make_pair(oldAddr, newAddr)); - - if (is_debug_event(event)) { - eventDI.action = "Retry"; - eventDI.newst = data->getState(); + if (oldAddr != newAddr) { + if (mshr_->removeEvictPointer(oldAddr, newAddr)) + retry(oldAddr); + evictionType_.erase(std::make_pair(oldAddr, newAddr)); + if (is_debug_event(event)) { + eventDI.action = "Retry"; + eventDI.newst = tag->getState(); + } + } else { + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + eventDI.action = "Retry"; + } } + } else { if (is_debug_event(event)) { eventDI.action = "Stall"; @@ -2371,6 +2682,7 @@ bool MESISharNoninclusive::handleNACK(MemEvent* event, bool inMSHR) { case Command::PutS: case Command::PutE: case Command::PutM: + case Command::FlushAll: resendEvent(nackedEvent, false); // Resend towards memory break; case Command::FetchInv: @@ -2391,6 +2703,9 @@ bool MESISharNoninclusive::handleNACK(MemEvent* event, bool inMSHR) { delete nackedEvent; } break; + case Command::ForwardFlush: + resendEvent(nackedEvent, true); // Resend towards CPU + break; default: debug->fatal(CALL_INFO,-1,"%s, Error: Received NACK with unhandled command type. Event: %s. Time = %" PRIu64 "ns\n", getName().c_str(), nackedEvent->getVerboseString().c_str(), getCurrentSimTimeNano()); @@ -2483,8 +2798,10 @@ bool MESISharNoninclusive::handleDirEviction(Addr addr, DirectoryLine*& tag) { tag = dirArray_->findReplacementCandidate(addr); State state = tag->getState(); - if (is_debug_addr(tag->getAddr())) + if (is_debug_addr(tag->getAddr())) { evictDI.oldst = tag->getState(); + evictDI.addr = tag->getAddr(); + } stat_evict[state]->addData(1); @@ -2602,8 +2919,10 @@ bool MESISharNoninclusive::handleDataEviction(Addr addr, DataLine *&data) { data = dataArray_->findReplacementCandidate(addr); State state = data->getState(); - if (is_debug_addr(data->getAddr())) + if (is_debug_addr(data->getAddr())) { evictDI.oldst = data->getState(); + evictDI.addr = data->getAddr(); + } DirectoryLine* tag; @@ -2628,6 +2947,7 @@ bool MESISharNoninclusive::handleDataEviction(Addr addr, DataLine *&data) { } else if (is_debug_addr(data->getAddr())) { printDebugAlloc(false, data->getAddr(), "Data, Drop"); } + dataArray_->deallocate(data); return true; } case E: @@ -2648,6 +2968,8 @@ bool MESISharNoninclusive::handleDataEviction(Addr addr, DataLine *&data) { } else if (is_debug_addr(data->getAddr())) { printDebugAlloc(false, data->getAddr(), "Data, Drop"); } + dataArray_->deallocate(data); + return true; } case M: @@ -2668,6 +2990,7 @@ bool MESISharNoninclusive::handleDataEviction(Addr addr, DataLine *&data) { } else if (is_debug_addr(data->getAddr())) { printDebugAlloc(false, data->getAddr(), "Data, Drop"); } + dataArray_->deallocate(data); return true; } default: @@ -2691,6 +3014,13 @@ void MESISharNoninclusive::cleanUpEvent(MemEvent* event, bool inMSHR) { if (inMSHR) { if (event->isPrefetch() && event->getRqstr() == cachename_) outstandingPrefetches_--; mshr_->removeFront(addr); + + if (flush_state_ == FlushState::Drain) { + mshr_->decrementFlushCount(); + if (mshr_->getFlushCount() == 0) { + retryBuffer_.push_back(mshr_->getFlush()); + } + } } delete event; diff --git a/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.h b/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.h index 101183169f..177c26d97c 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.h +++ b/src/sst/elements/memHierarchy/coherencemgr/MESI_Shared_Noninclusive.h @@ -72,6 +72,11 @@ class MESISharNoninclusive : public CoherenceController { {"eventSent_FlushLine", "Number of FlushLine requests sent", "events", 2}, {"eventSent_FlushLineInv", "Number of FlushLineInv requests sent", "events", 2}, {"eventSent_FlushLineResp", "Number of FlushLineResp responses sent", "events", 2}, + {"eventSent_FlushAll", "Number of FlushAll requests sent", "events", 2}, + {"eventSent_ForwardFlush", "Number of ForwardFlush requests sent", "events", 2}, + {"eventSent_FlushAllResp", "Number of FlushAllResp requests sent", "events", 2}, + {"eventSent_UnblockFlush", "Number of UnblockFlush requests sent", "events", 2}, + {"eventSent_AckFlush", "Number of AckFlush requests sent", "events", 2}, {"eventSent_Put", "Number of Put requests sent", "events", 6}, {"eventSent_Get", "Number of Get requests sent", "events", 6}, {"eventSent_AckMove", "Number of AckMove responses sent", "events", 6}, @@ -232,6 +237,8 @@ class MESISharNoninclusive : public CoherenceController { {"evict_MInvX", "Eviction: Attempted to evict a block in state M_InvX", "count", 3}, {"evict_IB", "Eviction: Attempted to evict a block in state S_B", "count", 3}, {"evict_SB", "Eviction: Attempted to evict a block in state I_B", "count", 3}, + {"evict_ED", "Eviction: Attempted to evict a block in state E_D", "count", 3}, + {"evict_MA", "Eviction: Attempted to evict a block in state MA", "count", 3}, /* Latency for different kinds of misses*/ {"latency_GetS_hit", "Latency for read hits", "cycles", 1}, {"latency_GetS_miss", "Latency for read misses, block not present", "cycles", 1}, @@ -287,6 +294,8 @@ class MESISharNoninclusive : public CoherenceController { dirArray_ = new CacheArray(debug, dLines, dAssoc, lineSize_, drmgr, ht); dirArray_->setBanked(params.find("banks", 0)); + flush_state_ = FlushState::Ready; + /* Statistics */ stat_evict[I] = registerStatistic("evict_I"); stat_evict[IS] = registerStatistic("evict_IS"); @@ -298,6 +307,7 @@ class MESISharNoninclusive : public CoherenceController { stat_evict[S_Inv] = registerStatistic("evict_SInv"); stat_evict[SM_Inv] = registerStatistic("evict_SMInv"); stat_evict[M] = registerStatistic("evict_M"); + stat_evict[MA] = registerStatistic("evict_MA"); stat_evict[M_Inv] = registerStatistic("evict_MInv"); stat_evict[M_InvX] = registerStatistic("evict_MInvX"); stat_eventState[(int)Command::GetS][I] = registerStatistic("stateEvent_GetS_I"); @@ -407,6 +417,10 @@ class MESISharNoninclusive : public CoherenceController { stat_eventSent[(int)Command::PutM] = registerStatistic("eventSent_PutM"); stat_eventSent[(int)Command::FlushLine] = registerStatistic("eventSent_FlushLine"); stat_eventSent[(int)Command::FlushLineInv] = registerStatistic("eventSent_FlushLineInv"); + stat_eventSent[(int)Command::FlushAll] = registerStatistic("eventSent_FlushAll"); + stat_eventSent[(int)Command::ForwardFlush] = registerStatistic("eventSent_ForwardFlush"); + stat_eventSent[(int)Command::UnblockFlush] = registerStatistic("eventSent_UnblockFlush"); + stat_eventSent[(int)Command::AckFlush] = registerStatistic("eventSent_AckFlush"); stat_eventSent[(int)Command::FetchResp] = registerStatistic("eventSent_FetchResp"); stat_eventSent[(int)Command::FetchXResp] = registerStatistic("eventSent_FetchXResp"); stat_eventSent[(int)Command::AckInv] = registerStatistic("eventSent_AckInv"); @@ -415,6 +429,7 @@ class MESISharNoninclusive : public CoherenceController { stat_eventSent[(int)Command::GetXResp] = registerStatistic("eventSent_GetXResp"); stat_eventSent[(int)Command::WriteResp] = registerStatistic("eventSent_WriteResp"); stat_eventSent[(int)Command::FlushLineResp] = registerStatistic("eventSent_FlushLineResp"); + stat_eventSent[(int)Command::FlushAllResp] = registerStatistic("eventSent_FlushAllResp"); stat_eventSent[(int)Command::Inv] = registerStatistic("eventSent_Inv"); stat_eventSent[(int)Command::Fetch] = registerStatistic("eventSent_Fetch"); stat_eventSent[(int)Command::FetchInv] = registerStatistic("eventSent_FetchInv"); @@ -467,6 +482,7 @@ class MESISharNoninclusive : public CoherenceController { /* MESI-specific statistics (as opposed to MSI) */ if (protocol_) { stat_evict[E] = registerStatistic("evict_E"); + stat_evict[E_D] = registerStatistic("evict_ED"); stat_evict[E_Inv] = registerStatistic("evict_EInv"); stat_evict[E_InvX] = registerStatistic("evict_EInvX"); stat_eventState[(int)Command::GetS][E] = registerStatistic("stateEvent_GetS_E"); @@ -514,45 +530,52 @@ class MESISharNoninclusive : public CoherenceController { ~MESISharNoninclusive() {} /** Event handlers */ - virtual bool handleGetS(MemEvent* event, bool inMSHR); - virtual bool handleGetX(MemEvent* event, bool inMSHR); - virtual bool handleGetSX(MemEvent* event, bool inMSHR); - virtual bool handleFlushLine(MemEvent* event, bool inMSHR); - virtual bool handleFlushLineInv(MemEvent* event, bool inMSHR); - virtual bool handlePutS(MemEvent* event, bool inMSHR); - virtual bool handlePutE(MemEvent* event, bool inMSHR); - virtual bool handlePutX(MemEvent* event, bool inMSHR); - virtual bool handlePutM(MemEvent* event, bool inMSHR); - virtual bool handleInv(MemEvent * event, bool inMSHR); - virtual bool handleForceInv(MemEvent * event, bool inMSHR); - virtual bool handleFetch(MemEvent * event, bool inMSHR); - virtual bool handleFetchInv(MemEvent * event, bool inMSHR); - virtual bool handleFetchInvX(MemEvent * event, bool inMSHR); - virtual bool handleNULLCMD(MemEvent* event, bool inMSHR); - virtual bool handleGetSResp(MemEvent* event, bool inMSHR); - virtual bool handleGetXResp(MemEvent* event, bool inMSHR); - virtual bool handleFlushLineResp(MemEvent* event, bool inMSHR); - virtual bool handleFetchResp(MemEvent* event, bool inMSHR); - virtual bool handleFetchXResp(MemEvent* event, bool inMSHR); - virtual bool handleAckInv(MemEvent* event, bool inMSHR); - virtual bool handleAckPut(MemEvent* event, bool inMSHR); - virtual bool handleNACK(MemEvent* event, bool inMSHR); + virtual bool handleGetS(MemEvent* event, bool inMSHR) override; + virtual bool handleGetX(MemEvent* event, bool inMSHR) override; + virtual bool handleGetSX(MemEvent* event, bool inMSHR) override; + virtual bool handleFlushLine(MemEvent* event, bool inMSHR) override; + virtual bool handleFlushLineInv(MemEvent* event, bool inMSHR) override; + virtual bool handleFlushAll(MemEvent* event, bool inMSHR) override; + virtual bool handleForwardFlush(MemEvent* event, bool inMSHR) override; + virtual bool handlePutS(MemEvent* event, bool inMSHR) override; + virtual bool handlePutE(MemEvent* event, bool inMSHR) override; + virtual bool handlePutX(MemEvent* event, bool inMSHR) override; + virtual bool handlePutM(MemEvent* event, bool inMSHR) override; + virtual bool handleInv(MemEvent * event, bool inMSHR) override; + virtual bool handleForceInv(MemEvent * event, bool inMSHR) override; + virtual bool handleFetch(MemEvent * event, bool inMSHR) override; + virtual bool handleFetchInv(MemEvent * event, bool inMSHR) override; + virtual bool handleFetchInvX(MemEvent * event, bool inMSHR) override; + virtual bool handleNULLCMD(MemEvent* event, bool inMSHR) override; + virtual bool handleGetSResp(MemEvent* event, bool inMSHR) override; + virtual bool handleGetXResp(MemEvent* event, bool inMSHR) override; + virtual bool handleFlushLineResp(MemEvent* event, bool inMSHR) override; + virtual bool handleFlushAllResp(MemEvent* event, bool inMSHR) override; + virtual bool handleFetchResp(MemEvent* event, bool inMSHR) override; + virtual bool handleFetchXResp(MemEvent* event, bool inMSHR) override; + virtual bool handleAckFlush(MemEvent* event, bool inMSHR) override; + virtual bool handleUnblockFlush(MemEvent* event, bool inMSHR) override; + virtual bool handleAckInv(MemEvent* event, bool inMSHR) override; + virtual bool handleAckPut(MemEvent* event, bool inMSHR) override; + virtual bool handleNACK(MemEvent* event, bool inMSHR) override; // Initialization event - MemEventInitCoherence* getInitCoherenceEvent(); + MemEventInitCoherence* getInitCoherenceEvent() override; - virtual Addr getBank(Addr addr) { return dirArray_->getBank(addr); } - virtual void setSliceAware(uint64_t size, uint64_t step) { + virtual Addr getBank(Addr addr) override { return dirArray_->getBank(addr); } + virtual void setSliceAware(uint64_t size, uint64_t step) override { dirArray_->setSliceAware(size, step); dataArray_->setSliceAware(size, step); } - std::set getValidReceiveEvents() { + std::set getValidReceiveEvents() override { std::set cmds = { Command::GetS, Command::GetX, Command::GetSX, Command::FlushLine, Command::FlushLineInv, + Command::FlushAll, + Command::ForwardFlush, Command::PutS, Command::PutE, Command::PutM, @@ -566,8 +589,11 @@ class MESISharNoninclusive : public CoherenceController { Command::GetSResp, Command::GetXResp, Command::FlushLineResp, + Command::FlushAllResp, Command::FetchResp, Command::FetchXResp, + Command::UnblockFlush, + Command::AckFlush, Command::AckInv, Command::AckPut, Command::NACK }; @@ -610,8 +636,8 @@ class MESISharNoninclusive : public CoherenceController { uint64_t sendFetch(Command cmd, MemEvent * event, std::string dst, bool inMSHR, uint64_t ts); /** Call through to coherenceController with statistic recording */ - void forwardByAddress(MemEventBase* ev, Cycle_t timestamp); - void forwardByDestination(MemEventBase* ev, Cycle_t timestamp); + void forwardByAddress(MemEventBase* ev, Cycle_t timestamp) override; + void forwardByDestination(MemEventBase* ev, Cycle_t timestamp) override; /** Helpers */ void removeSharerViaInv(MemEvent* event, DirectoryLine * tag, DataLine * data, bool remove); @@ -621,10 +647,10 @@ class MESISharNoninclusive : public CoherenceController { /* Miscellaneous */ void printLine(Addr addr); - void printStatus(Output &out); + void printStatus(Output &out) override; /* Statistics */ - void recordLatency(Command cmd, int type, uint64_t latency); + void recordLatency(Command cmd, int type, uint64_t latency) override; void recordPrefetchResult(DirectoryLine * line, Statistic * stat); /* Private data members */ @@ -639,6 +665,8 @@ class MESISharNoninclusive : public CoherenceController { // Map an outstanding eviction (key = replaceAddr,newAddr) to whether it is a directory eviction (true) or data eviction (false) std::map, bool> evictionType_; + FlushState flush_state_; + /* Statistics */ Statistic* stat_latencyGetS[3]; Statistic* stat_latencyGetX[4]; diff --git a/src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc b/src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc index 3e93eb8375..d44918c8e8 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc +++ b/src/sst/elements/memHierarchy/coherencemgr/coherenceController.cc @@ -168,6 +168,7 @@ HashFunction* CoherenceController::createHashFunction(Params& params) { return ht; } + /******************************************************************************* * Event handlers - one per event type * Handlers return whether event was accepted (true) or rejected (false) @@ -208,6 +209,18 @@ bool CoherenceController::handleFlushLineInv(MemEvent* event, bool inMSHR) { return false; } +bool CoherenceController::handleFlushAll(MemEvent* event, bool inMSHR) { + debug->fatal(CALL_INFO, -1, "%s, Error: FlushAll events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", + getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + return false; +} + +bool CoherenceController::handleForwardFlush(MemEvent* event, bool inMSHR) { + debug->fatal(CALL_INFO, -1, "%s, Error: ForwardFlush events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", + getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + return false; +} + bool CoherenceController::handlePutS(MemEvent* event, bool inMSHR) { debug->fatal(CALL_INFO, -1, "%s, Error: PutS events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); @@ -256,6 +269,24 @@ bool CoherenceController::handleFlushLineResp(MemEvent* event, bool inMSHR) { return false; } +bool CoherenceController::handleFlushAllResp(MemEvent* event, bool inMSHR) { + debug->fatal(CALL_INFO, -1, "%s, Error: FlushAllResp events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", + getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + return false; +} + +bool CoherenceController::handleAckFlush(MemEvent* event, bool inMSHR) { + debug->fatal(CALL_INFO, -1, "%s, Error: AckFlush events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", + getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + return false; +} + +bool CoherenceController::handleUnblockFlush(MemEvent* event, bool inMSHR) { + debug->fatal(CALL_INFO, -1, "%s, Error: UnblockFlush events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", + getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); + return false; +} + bool CoherenceController::handleAckPut(MemEvent* event, bool inMSHR) { debug->fatal(CALL_INFO, -1, "%s, Error: AckPut events are not handled by this coherence manager. Event: %s. Time: %" PRIu64 "ns.\n", getName().c_str(), event->getVerboseString().c_str(), getCurrentSimTimeNano()); @@ -327,7 +358,7 @@ bool CoherenceController::handleNACK(MemEvent* event, bool inMSHR) { * Send events *******************************************************************************/ -/* Send commands when their timestampe expires. Return whether queue is empty or not. */ +/* Send commands when their timestamp expires. Return whether queue is empty or not. */ bool CoherenceController::sendOutgoingEvents() { // Update timestamp timestamp_++; @@ -443,6 +474,35 @@ void CoherenceController::forwardByDestination(MemEventBase * event, Cycle_t ts) } } +/* Broadcast an event to all sources */ +int CoherenceController::broadcastMemEventToSources(Command cmd, MemEvent* metadata, Cycle_t ts) { + std::set* sources = linkUp_->getSources(); + for (auto it = sources->begin(); it != sources->end(); it++) { + MemEvent* event = new MemEvent(cachename_, cmd); + if (metadata) event->copyMetadata(metadata); + event->setSrc(cachename_); + event->setDst(it->name); + forwardByDestination(event, ts); + } + return sources->size(); +} + +int CoherenceController::broadcastMemEventToPeers(Command cmd, MemEvent* metadata, Cycle_t ts) { + std::set* peers = linkUp_->getPeers(); + int sent = 0; + for (auto it = peers->begin(); it != peers->end(); it++) { + if (it->name == cachename_) continue; + + MemEvent* event = new MemEvent(cachename_, cmd); + if (metadata) event->copyMetadata(metadata); + event->setSrc(cachename_); + event->setDst(it->name); + forwardByDestination(event, ts); + sent++; + } + return sent; +} + /******************************************************************************* * Initialization/finish functions used by parent *******************************************************************************/ @@ -482,6 +542,38 @@ void CoherenceController::processInitCoherenceEvent(MemEventInitCoherence* event recvWritebackAck_ ? "Y" : "N"); } +void CoherenceController::setup() { + /* Identify if this cache is the flush manager, and, if not, the destination for any flushes */ + flush_manager_ = lastLevel_; + flush_helper_ = true; + bool global_peer = lastLevel_; + /* Identify the local flush helper in our group of peers */ + MemLinkBase::EndpointInfo min = linkUp_->getEndpointInfo(); + auto peers = linkUp_->getPeers(); + for (auto it = peers->begin(); it != peers->end(); it++) { + if (*it < min) { + min = *it; + flush_manager_ = false; + flush_helper_ = false; + } + } + + if (flush_manager_) { + flush_dest_ = getName(); + } else if (lastLevel_) { // If true, the global flush manager is one of our peers + flush_dest_ = min.name; + } else { + auto dests = linkDown_->getDests(); + min = *(dests->begin()); + for (auto it = dests->begin(); it != dests->end(); it++) { + if (*it < min) { + min = *it; + } + } + flush_dest_ = min.name; + } +} + /* Retry buffer */ std::vector* CoherenceController::getRetryBuffer() { return &retryBuffer_; @@ -778,6 +870,10 @@ void CoherenceController::addToOutgoingQueueUp(Response& resp) { } +/* Return whether the component is a peer */ +bool CoherenceController::isPeer(std::string name) { + return linkUp_->isPeer(name); +} /**************************************/ /******** Statistics handling *********/ diff --git a/src/sst/elements/memHierarchy/coherencemgr/coherenceController.h b/src/sst/elements/memHierarchy/coherencemgr/coherenceController.h index 01877b8de6..7f7d52f8d1 100644 --- a/src/sst/elements/memHierarchy/coherencemgr/coherenceController.h +++ b/src/sst/elements/memHierarchy/coherencemgr/coherenceController.h @@ -65,6 +65,8 @@ class CoherenceController : public SST::SubComponent { virtual bool handlePutM(MemEvent * event, bool inMSHR); virtual bool handleFlushLine(MemEvent * event, bool inMSHR); virtual bool handleFlushLineInv(MemEvent * event, bool inMSHR); + virtual bool handleFlushAll(MemEvent * event, bool inMSHR); + virtual bool handleForwardFlush(MemEvent * event, bool inMSHR); virtual bool handleFetch(MemEvent * event, bool inMSHR); virtual bool handleInv(MemEvent * event, bool inMSHR); virtual bool handleFetchInvX(MemEvent * event, bool inMSHR); @@ -74,8 +76,11 @@ class CoherenceController : public SST::SubComponent { virtual bool handleGetXResp(MemEvent * event, bool inMSHR); virtual bool handleWriteResp(MemEvent * event, bool inMSHR); virtual bool handleFlushLineResp(MemEvent * event, bool inMSHR); + virtual bool handleFlushAllResp(MemEvent * event, bool inMSHR); virtual bool handleAckPut(MemEvent * event, bool inMSHR); virtual bool handleAckInv(MemEvent * event, bool inMSHR); + virtual bool handleAckFlush(MemEvent * event, bool inMSHR); + virtual bool handleUnblockFlush(MemEvent * event, bool inMSHR); virtual bool handleFetchResp(MemEvent * event, bool inMSHR); virtual bool handleFetchXResp(MemEvent * event, bool inMSHR); virtual bool handleNACK(MemEvent * event, bool inMSHR); @@ -96,10 +101,13 @@ class CoherenceController : public SST::SubComponent { virtual void forwardByDestination(MemEventBase * event); // Send time will be 1 + timestamp_ virtual void forwardByDestination(MemEventBase * event, Cycle_t ts); // ts specifies the send time + /* Broadcast an event to a group of components */ + int broadcastMemEventToSources(Command cmd, MemEvent* metadata, Cycle_t ts); + int broadcastMemEventToPeers(Command cmd, MemEvent* metadata, Cycle_t ts); + /* Send a NACK event */ void sendNACK(MemEvent * event); - /********************************************************************************* * Miscellaneous functions used by parent *********************************************************************************/ @@ -118,6 +126,9 @@ class CoherenceController : public SST::SubComponent { * Initialization/finish functions used by parent *********************************************************************************/ + /* Setup function from BaseComponent API */ + virtual void setup() override; + /* * Get the InitCoherenceEvent * Event contains information about the protocol configuration and so is generated by coherence managers @@ -182,7 +193,7 @@ class CoherenceController : public SST::SubComponent { virtual void recordMiss(SST::Event::id_type id); // Called by owner during printStatus/emergencyShutdown - virtual void printStatus(Output &out); + virtual void printStatus(Output &out) override; protected: @@ -200,6 +211,9 @@ class CoherenceController : public SST::SubComponent { /* Insert event into MSHR */ MemEventStatus allocateMSHR(MemEvent * event, bool fwdReq, int pos = -1, bool stallEvict = false); + /* Insight into link status */ + bool isPeer(std::string name); + /* Statistics */ virtual void recordLatencyType(SST::Event::id_type id, int latencytype); virtual void recordPrefetchLatency(SST::Event::id_type, int latencytype); @@ -288,6 +302,9 @@ class CoherenceController : public SST::SubComponent { bool recvWritebackAck_; // Whether we should expect writeback acks bool sendWritebackAck_; // Whether we should send writeback acks bool lastLevel_; // Whether we are the lowest coherence level and should not send coherence messages down + bool flush_manager_; // Whether this cache will manage (order) FlushAll events - one per system, may be a directory + bool flush_helper_; // Whether this cache will locally manage (order) FlushAll events - one per shared group of caches + std::string flush_dest_; // Destination for FlushAll requests /* Response structure - used for outgoing event queues */ struct Response { diff --git a/src/sst/elements/memHierarchy/directoryController.cc b/src/sst/elements/memHierarchy/directoryController.cc index d5962cda9d..f0065db287 100644 --- a/src/sst/elements/memHierarchy/directoryController.cc +++ b/src/sst/elements/memHierarchy/directoryController.cc @@ -45,13 +45,8 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : dbg.init("", debugLevel, 0, (Output::output_location_t)params.find("debug", 0)); // Detect deprecated parameters and warn/fatal - // Currently deprecated - network_num_vc bool found; out.init("", params.find("verbose", 1), 0, Output::STDOUT); - params.find("network_num_vc", 0, found); - if (found) { - out.output("%s, ** Found deprecated parameter: network_num_vc ** MemHierarchy does not use multiple virtual channels. Remove this parameter from your input deck to eliminate this message.\n", getName().c_str()); - } // Debug address std::vector addrArr; @@ -129,32 +124,58 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : * the MCs their own region. We cannot error check from the parameters... */ - cpuLink = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, defaultTimeBase); - memLink = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, defaultTimeBase); - if (cpuLink || memLink) { - if (!cpuLink) { - cpuLink = memLink; - memLink = nullptr; + upLink = loadUserSubComponent("highlink", ComponentInfo::SHARE_NONE, defaultTimeBase); + if (!upLink) { + upLink = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, defaultTimeBase); + if (upLink) { + out.output("%s, DEPRECATION WARNING: The 'cpulink' subcomponent slot has been renamed to 'highlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + + if (!upLink && isPortConnected("highlink")) { + Params p; + p.insert("port", "highlink"); + upLink = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, p, defaultTimeBase); + } + } + + downLink = loadUserSubComponent("lowlink", ComponentInfo::SHARE_NONE, defaultTimeBase); + if (!downLink) { + downLink = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, defaultTimeBase); + if (downLink) { + out.output("%s, DEPRECATION WARNING: The 'memlink' subcomponent slot has been renamed to 'lowlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + + if (!downLink && isPortConnected("lowlink")) { + Params p; + p.insert("port", "lowlink"); + downLink = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, p, defaultTimeBase); + } + } + + if (upLink || downLink) { + if (!upLink) { + upLink = downLink; + downLink = nullptr; } if (gotRegion) { - cpuLink->setRegion(region); + upLink->setRegion(region); } else { - if (cpuLink->getRegion() != region) { - out.output(CALL_INFO, "%s, Warning: getting region parameters (addr_range_start/end, interleave_step/size) from link subcomponent." - " In the future this will not be supported and region parameters should be declared in the directory's parameters instead.\n", getName().c_str()); + if (upLink->getRegion() != region) { + out.output(CALL_INFO, "%s, DEPRECATION WARNING: getting region parameters (addr_range_start/end, interleave_step/size) from link subcomponent." + " In SST 16 this will not be supported and region parameters should be declared in the directory's parameters instead.\n", getName().c_str()); } - region = cpuLink->getRegion(); + region = upLink->getRegion(); } - if (memLink) - memLink->setRegion(region); + if (downLink) + downLink->setRegion(region); - cpuLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); - if (!memLink) { + upLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); + if (!downLink) { if (params.find("net_memory_name", "") != "") dbg.fatal(CALL_INFO, -1, "%s, Error: parameter 'net_memory_name' is no longer supported. Memory and directory components should specify their own address regions (address_range_start/end, interleave_step/size) and mapping will be inferred from that. Remove this parameter from your input deck to eliminate this error.\n", getName().c_str()); } else { - memLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); + downLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); } } else { /* Set up links/network to cache & memory the old way -> and fixup params accordingly */ @@ -175,6 +196,10 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : nicParams.insert("destinations", std::to_string(cl + 1), false); // Determine which ports are connected + // Acceptable port configurations are + // 1. network (memory optional) + // 2. network, network_ack, network_fwd, network_data (memory optional) + // 3. cpulink + memlink unsigned int portCount = 1; if (isPortConnected("network_ack")) portCount++; if (isPortConnected("network_fwd")) portCount++; @@ -184,40 +209,60 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : nicParams.insert("ack.port", "network_ack"); nicParams.insert("fwd.port", "network_fwd"); nicParams.insert("data.port", "network_data"); - cpuLink = loadAnonymousSubComponent("memHierarchy.MemNICFour", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, defaultTimeBase); - } else { + upLink = loadAnonymousSubComponent("memHierarchy.MemNICFour", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, defaultTimeBase); + out.output("%s, DEPRECATION WARNING: The 'network', 'network_ack', 'network_fwd', and 'network_data' ports are deprecated. Instead, in your input file, fill the directory's 'highlink' subcomponent slot with 'memHierarchy.MemNICFour'.\n", getName().c_str()); + + } else if (isPortConnected("network")) { nicParams.insert("port", "network"); - cpuLink = loadAnonymousSubComponent("memHierarchy.MemNIC", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, defaultTimeBase); + upLink = loadAnonymousSubComponent("memHierarchy.MemNIC", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, defaultTimeBase); + out.output("%s, DEPRECATION WARNING: The 'network' port is deprecated. Instead, in your input file, fill the directory's 'highlink' subcomponent slot with 'memHierarchy.MemNIC'.\n", getName().c_str()); + } else if (isPortConnected("highlink")) { + Params linkParams; + linkParams.insert("port", "highlink"); + upLink = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, linkParams, defaultTimeBase); + } else { + dbg.fatal(CALL_INFO, -1, "%s, Error: Either this component's 'highlink' port must be connected OR the 'highlink' subcomponent slot must be filled\n", getName().c_str()); } - cpuLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); + upLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); if (isPortConnected("memory")) { Params memParams = params.get_scoped_params("memlink"); memParams.insert("port", "memory"); - memParams.insert("latency", "1ns"); + memParams.insert("latency", "1ns"); // Leaving this here since this port is deprecated but it should not be here. Instead use the link latency. memParams.insert("addr_range_start", std::to_string(region.start), false); memParams.insert("addr_range_end", std::to_string(region.end), false); memParams.insert("interleave_size", ilSize, false); memParams.insert("interleave_step", ilStep, false); - memLink = loadAnonymousSubComponent("memHierarchy.MemLink", "memlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, memParams, defaultTimeBase); - memLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); - if (!memLink) { + downLink = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, memParams, defaultTimeBase); + if (!downLink) { dbg.fatal(CALL_INFO, -1, "%s, Error creating link to memory from directory controller\n", getName().c_str()); } + downLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); + out.output("%s, DEPRECATION WARNING: The 'memory' port is deprecated. Use the 'lowlink' port instead.\n", getName().c_str()); + } else if (isPortConnected("lowlink")) { + Params memParams; + memParams.insert("port", "lowlink"); + memParams.insert("addr_range_start", std::to_string(region.start), false); + memParams.insert("addr_range_end", std::to_string(region.end), false); + memParams.insert("interleave_size", ilSize, false); + memParams.insert("interleave_step", ilStep, false); + downLink = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, memParams, defaultTimeBase); + if (!downLink) { + dbg.fatal(CALL_INFO, -1, "%s, Error creating link to memory from directory controller\n", getName().c_str()); + } + downLink->setRecvHandler(new Event::Handler(this, &DirectoryController::handlePacket)); } else { - if (params.find("net_memory_name", "") != "") - dbg.fatal(CALL_INFO, -1, "%s, Error: parameter 'net_memory_name' is no longer supported. Memory and directory components should specify their own address regions (address_range_start/end, interleave_step/size) and mapping will be inferred from that. Remove this parameter from your input deck to eliminate this error.\n", getName().c_str()); - - memLink = nullptr; + // No downLink, traffic to/from memory will use the upLink + downLink = nullptr; } } - if (memLink) - clockMemLink = memLink->isClocked(); + if (downLink) + clockDownLink = downLink->isClocked(); else - clockMemLink = false; - clockCpuLink = cpuLink->isClocked(); + clockDownLink = false; + clockUpLink = upLink->isClocked(); // Requests per cycle maxRequestsPerCycle = params.find("max_requests_per_cycle", 0); @@ -258,8 +303,10 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : stat_eventRecv[(int)Command::ForceInv] = registerStatistic("ForceInv_recv"); stat_eventRecv[(int)Command::FetchInv] = registerStatistic("FetchInv_recv"); stat_eventRecv[(int)Command::AckInv] = registerStatistic("AckInv_recv"); + stat_eventRecv[(int)Command::AckFlush] = registerStatistic("AckFlush_recv"); stat_eventRecv[(int)Command::FlushLine] = registerStatistic("FlushLine_recv"); stat_eventRecv[(int)Command::FlushLineInv] = registerStatistic("FlushLineInv_recv"); + stat_eventRecv[(int)Command::FlushAll] = registerStatistic("FlushAll_recv"); stat_eventRecv[(int)Command::FlushLineResp] = registerStatistic("FlushLineResp_recv"); stat_noncacheRecv[(int)Command::GetS] = registerStatistic("GetS_uncache_recv"); stat_noncacheRecv[(int)Command::Write] = registerStatistic("Write_uncache_recv"); @@ -279,6 +326,7 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : stat_eventSent[(int)Command::FetchInv] = registerStatistic("eventSent_FetchInv"); stat_eventSent[(int)Command::FetchInvX] = registerStatistic("eventSent_FetchInvX"); stat_eventSent[(int)Command::ForceInv] = registerStatistic("eventSent_ForceInv"); + stat_eventSent[(int)Command::ForwardFlush] = registerStatistic("eventSent_ForwardFlush"); stat_eventSent[(int)Command::NACK] = registerStatistic("eventSent_NACK"); stat_eventSent[(int)Command::GetSResp] = registerStatistic("eventSent_GetSResp"); stat_eventSent[(int)Command::GetXResp] = registerStatistic("eventSent_GetXResp"); @@ -289,6 +337,8 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : stat_eventSent[(int)Command::FlushLine] = registerStatistic("eventSent_FlushLine"); stat_eventSent[(int)Command::FlushLineInv] = registerStatistic("eventSent_FlushLineInv"); stat_eventSent[(int)Command::FlushLineResp] = registerStatistic("eventSent_FlushLineResp"); + stat_eventSent[(int)Command::FlushAllResp] = registerStatistic("eventSent_FlushAllResp"); + stat_eventSent[(int)Command::UnblockFlush] = registerStatistic("eventSent_UnblockFlush"); // Memory writes from directory stat_dirEntryReads = registerStatistic("eventSent_read_directory_entry"); stat_dirEntryWrites = registerStatistic("eventSent_write_directory_entry"); @@ -296,8 +346,8 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : // Coherence part - if (!memLink) - memLink = cpuLink; + if (!downLink) + downLink = upLink; // TODO implement the cache properly using the cacheArray entryCacheMaxSize = params.find("entry_cache_size", 32768); @@ -316,6 +366,8 @@ DirectoryController::DirectoryController(ComponentId_t id, Params ¶ms) : /* Get latencies */ accessLatency = params.find("access_latency_cycles", 0); mshrLatency = params.find("mshr_latency_cycles", 0); + + flush_state_ = FlushState::Ready; } @@ -368,10 +420,10 @@ bool DirectoryController::clock(SST::Cycle_t cycle){ sendOutgoingEvents(); bool idle = true; - if (clockCpuLink) - idle &= cpuLink->clock(); - if (clockMemLink) - idle &= memLink->clock(); + if (clockUpLink) + idle &= upLink->clock(); + if (clockDownLink) + idle &= downLink->clock(); int requestsThisCycle = 0; @@ -436,7 +488,7 @@ bool DirectoryController::processPacket(MemEvent * ev, bool replay) { if(! isRequestAddressValid(ev->getAddr()) ) { dbg.fatal(CALL_INFO, -1, "%s, Error: Request address is not valid. Event: %s. Time = %" PRIu64 "ns.\nRegion is %s\n", - getName().c_str(), ev->getVerboseString(dlevel).c_str(), getCurrentSimTimeNano(), cpuLink->getRegion().toString().c_str()); + getName().c_str(), ev->getVerboseString(dlevel).c_str(), getCurrentSimTimeNano(), upLink->getRegion().toString().c_str()); } Addr addr = ev->getBaseAddr(); @@ -496,6 +548,9 @@ bool DirectoryController::processPacket(MemEvent * ev, bool replay) { case Command::FlushLine: retval = handleFlushLine(ev, replay); break; + case Command::FlushAll: + retval = handleFlushAll(ev, replay); + break; case Command::FetchInv: retval = handleFetchInv(ev, replay); break; @@ -514,6 +569,9 @@ bool DirectoryController::processPacket(MemEvent * ev, bool replay) { case Command::FlushLineResp: retval = handleFlushLineResp(ev, replay); break; + case Command::AckFlush: + retval = handleAckFlush(ev, replay); + break; case Command::AckInv: retval = handleAckInv(ev, replay); break; @@ -589,14 +647,14 @@ void DirectoryController::printStatus(Output &statusOut) { mshr->printStatus(statusOut); } - if (cpuLink) { + if (upLink) { statusOut.output(" NIC Status: "); - cpuLink->printStatus(statusOut); + upLink->printStatus(statusOut); } - if (memLink != cpuLink) { + if (downLink != upLink) { statusOut.output(" Memory Link Status: "); - memLink->printStatus(statusOut); + downLink->printStatus(statusOut); } statusOut.output(" Directory entries:\n"); @@ -613,13 +671,13 @@ void DirectoryController::emergencyShutdown() { out.setOutputLocation(Output::STDERR); printStatus(out); out.output(" Checking for unreceived events on network link:\n"); - cpuLink->emergencyShutdownDebug(out); + upLink->emergencyShutdownDebug(out); } } bool DirectoryController::isRequestAddressValid(Addr addr){ - return cpuLink->isRequestAddressValid(addr); + return upLink->isRequestAddressValid(addr); } @@ -634,20 +692,20 @@ void DirectoryController::turnClockOn() { void DirectoryController::init(unsigned int phase) { - cpuLink->init(phase); - if (cpuLink != memLink) memLink->init(phase); + upLink->init(phase); + if (upLink != downLink) downLink->init(phase); // Must happen after network init or merlin croaks // InitData: Name, NULLCMD, Endpoint type, inclusive of all upper levels, will send writeback acks, line size if (!phase) { - if (cpuLink != memLink) - cpuLink->sendUntimedData(new MemEventInitCoherence(getName(), Endpoint::Directory, true, true, false, cacheLineSize, true)); - memLink->sendUntimedData(new MemEventInitCoherence(getName(), Endpoint::Directory, true, true, false, cacheLineSize, true)); + if (upLink != downLink) + upLink->sendUntimedData(new MemEventInitCoherence(getName(), Endpoint::Directory, true, true, false, cacheLineSize, true)); + downLink->sendUntimedData(new MemEventInitCoherence(getName(), Endpoint::Directory, true, true, false, cacheLineSize, true)); } /* Pass data on to memory */ - while(MemEventInit *ev = cpuLink->recvUntimedData()) { + while(MemEventInit *ev = upLink->recvUntimedData()) { if (ev->getCmd() == Command::NULLCMD) { dbg.debug(_L10_, "I: %-20s Event:Init (%s)\n", getName().c_str(), ev->getVerboseString(dlevel).c_str()); @@ -655,13 +713,13 @@ void DirectoryController::init(unsigned int phase) { MemEventInitCoherence * mEv = static_cast(ev); if (mEv->getType() == Endpoint::Scratchpad) waitWBAck = true; - if (!(mEv->getTracksPresence()) && cpuLink->isSource(mEv->getSrc())) { + if (!(mEv->getTracksPresence()) && upLink->isSource(mEv->getSrc())) { incoherentSrc.insert(mEv->getSrc()); } } else if (ev->getInitCmd() == MemEventInit::InitCommand::Endpoint) { MemEventInit * mEv = ev->clone(); mEv->setSrc(getName()); - memLink->sendUntimedData(mEv); + downLink->sendUntimedData(mEv); } delete ev; } else { @@ -670,7 +728,7 @@ void DirectoryController::init(unsigned int phase) { if (isRequestAddressValid(ev->getAddr())){ dbg.debug(_L10_, "I: %-20s Event:SendInitData %" PRIx64 "\n", getName().c_str(), ev->getAddr()); - memLink->sendUntimedData(ev, false); + downLink->sendUntimedData(ev, false); } else delete ev; @@ -679,8 +737,8 @@ void DirectoryController::init(unsigned int phase) { } SST::Event * ev; - if (cpuLink != memLink) { - while ((ev = memLink->recvUntimedData())) { + if (upLink != downLink) { + while ((ev = downLink->recvUntimedData())) { MemEventInit * initEv = dynamic_cast(ev); if (initEv && initEv->getCmd() == Command::NULLCMD) { dbg.debug(_L10_, "I: %-20s Event:Init (%s)\n", @@ -693,7 +751,7 @@ void DirectoryController::init(unsigned int phase) { } else if (initEv->getInitCmd() == MemEventInit::InitCommand::Endpoint) { MemEventInit * mEv = initEv->clone(); mEv->setSrc(getName()); - cpuLink->sendUntimedData(mEv); + upLink->sendUntimedData(mEv); } } delete ev; @@ -704,16 +762,25 @@ void DirectoryController::init(unsigned int phase) { void DirectoryController::finish(void){ - cpuLink->finish(); + upLink->finish(); } void DirectoryController::setup(void){ - cpuLink->setup(); - if (cpuLink != memLink) - memLink->setup(); - //MemLinkBase * mem = memLink ? memLink : network; + upLink->setup(); + if (upLink != downLink) + downLink->setup(); + + auto peers = upLink->getPeers(); + MemLinkBase::EndpointInfo min = upLink->getEndpointInfo(); + bool isFlushManager = true; + for (auto it = peers->begin(); it != peers->end(); it++) { + if (*it < min) { + isFlushManager = false; + min = *it; + } + } } @@ -1294,6 +1361,68 @@ bool DirectoryController::handleFlushLineInv(MemEvent* event, bool inMSHR) { return true; } +bool DirectoryController::handleFlushAll(MemEvent * event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::FlushAll, false, 0, State::NP); + /* If directory receives a FlushAll, it is the flush manager + * The cache flushes will be sufficient to flush data to memory + * so the directory only needs to order FlushAll requests + */ + if (!inMSHR) { + MemEventStatus status = mshr->insertFlush(event, false); + if (status == MemEventStatus::Reject) { + sendNACK(event); + return true; + } else if (status == MemEventStatus::Stall) { + eventDI.action = "Stall"; + eventDI.reason = "Flush in progress"; + return true; + } + } + + switch (flush_state_) { + case FlushState::Ready: + { + /* Broadcast request up, transition to FlushState::Forward */ + std::set* sources = upLink->getSources(); + for (auto it = sources->begin(); it != sources->end(); it++) { + MemEvent* bcast_event = new MemEvent(getName(), Command::ForwardFlush); + bcast_event->copyMetadata(event); + bcast_event->setSrc(getName()); + bcast_event->setDst(it->name); + forwardByDestination(bcast_event, timestamp + mshrLatency); + } + mshr->incrementFlushCount(sources->size()); + flush_state_ = FlushState::Forward; + eventDI.action = "Begin"; + break; + } + case FlushState::Forward: + { + /* Have received all acks, signal that flush is done */ + sendResponse(event); + std::set* sources = upLink->getSources(); + for (auto it = sources->begin(); it != sources->end(); it++) { + MemEvent* bcast_event = new MemEvent(getName(), Command::UnblockFlush); + bcast_event->copyMetadata(event); + bcast_event->setSrc(getName()); + bcast_event->setDst(it->name); + forwardByDestination(bcast_event, timestamp + mshrLatency); + } + mshr->removeFlush(); + delete event; + if (mshr->getFlush() != nullptr) { + retryBuffer.push_back(static_cast(mshr->getFlush())); + } + flush_state_ = FlushState::Ready; + break; + } + default: + break; + } + + return true; +} + bool DirectoryController::handlePutS(MemEvent * event, bool inMSHR) { Addr addr = event->getBaseAddr(); DirEntry* entry = getDirEntry(addr); @@ -1932,6 +2061,18 @@ bool DirectoryController::handleFlushLineResp(MemEvent * event, bool inMSHR) { return true; } +bool DirectoryController::handleAckFlush(MemEvent* event, bool inMSHR) { + eventDI.prefill(event->getID(), Command::AckFlush, "", 0, State::NP); + + mshr->decrementFlushCount(); + if (mshr->getFlushCount() == 0) { + retryBuffer.push_back(static_cast(mshr->getFlush())); + } + + delete event; + return true; +} + bool DirectoryController::handleAckPut(MemEvent* event, bool inMSHR) { Addr addr = event->getBaseAddr(); DirEntry* entry = getDirEntry(addr); @@ -2094,6 +2235,7 @@ bool DirectoryController::handleNACK(MemEvent* event, bool inMSHR) { case Command::PutM: case Command::FlushLine: case Command::FlushLineInv: + case Command::ForwardFlush: // Always retry break; case Command::FetchInv: @@ -2315,7 +2457,7 @@ void DirectoryController::sendEntryToMemory(DirEntry *entry) { me->setFlag(MemEventBase::F_NORESPONSE); uint64_t deliveryTime = timestamp + accessLatency; - me->setDst(memLink->getTargetDestination(0)); + me->setDst(downLink->getTargetDestination(0)); memMsgQueue.insert(std::make_pair(deliveryTime, MemMsg(me, true))); } @@ -2505,7 +2647,7 @@ void DirectoryController::sendOutgoingEvents() { startTimes.erase(ev->getResponseToID()); } stat_eventSent[(int)ev->getCmd()]->addData(1); - cpuLink->send(ev); + upLink->send(ev); cpuMsgQueue.erase(cpuMsgQueue.begin()); } @@ -2525,7 +2667,7 @@ void DirectoryController::sendOutgoingEvents() { } else { stat_eventSent[(int)ev->getCmd()]->addData(1); } - memLink->send(ev); + downLink->send(ev); memMsgQueue.erase(memMsgQueue.begin()); } @@ -2535,18 +2677,18 @@ void DirectoryController::sendOutgoingEvents() { * dirAccess has default value of false */ void DirectoryController::forwardByAddress(MemEventBase * ev, Cycle_t ts, bool dirAccess) { - std::string dst = memLink->findTargetDestination(ev->getRoutingAddress()); + std::string dst = downLink->findTargetDestination(ev->getRoutingAddress()); if (dst != "") { /* Common case */ ev->setDst(dst); memMsgQueue.insert(std::make_pair(ts, MemMsg(ev, dirAccess))); } else { - dst = cpuLink->findTargetDestination(ev->getRoutingAddress()); + dst = upLink->findTargetDestination(ev->getRoutingAddress()); if (dst != "") { ev->setDst(dst); cpuMsgQueue.insert(std::make_pair(ts, ev)); } else { - std::string availableDests = "cpulink:\n" + cpuLink->getAvailableDestinationsAsString(); - if (cpuLink != memLink) availableDests = availableDests + "memlink:\n" + memLink->getAvailableDestinationsAsString(); + std::string availableDests = "highlink:\n" + upLink->getAvailableDestinationsAsString(); + if (upLink != downLink) availableDests = availableDests + "lowlink:\n" + downLink->getAvailableDestinationsAsString(); out.fatal(CALL_INFO, -1, "%s, Error: Unable to find destination for address 0x%" PRIx64 ". Event: %s\nKnown Destinations: %s\n", getName().c_str(), ev->getRoutingAddress(), ev->getVerboseString(dlevel).c_str(), availableDests.c_str()); } @@ -2557,9 +2699,9 @@ void DirectoryController::forwardByAddress(MemEventBase * ev, Cycle_t ts, bool d * dirAccess has default value of false */ void DirectoryController::forwardByDestination(MemEventBase* ev, Cycle_t ts, bool dirAccess) { - if (cpuLink->isReachable(ev->getDst())) { + if (upLink->isReachable(ev->getDst())) { cpuMsgQueue.insert(std::make_pair(ts, ev)); - } else if (memLink->isReachable(ev->getDst())) { + } else if (downLink->isReachable(ev->getDst())) { memMsgQueue.insert(std::make_pair(ts, MemMsg(ev, dirAccess))); } else { out.fatal(CALL_INFO, -1, "%s, Error: Destination %s appears unreachable on both links. Event: %s\n", diff --git a/src/sst/elements/memHierarchy/directoryController.h b/src/sst/elements/memHierarchy/directoryController.h index 2bcd2fd365..a0737294fc 100644 --- a/src/sst/elements/memHierarchy/directoryController.h +++ b/src/sst/elements/memHierarchy/directoryController.h @@ -16,7 +16,6 @@ /* * File: directoryController.h * Author: Branden Moore / Caesar De la Paz III - * Email: bjmoor@sandia.gov / caesar.sst@gmail.com */ #ifndef _MEMHIERARCHY_DIRCONTROLLER_H_ @@ -69,18 +68,22 @@ class DirectoryController : public Component { {"interleave_step", "Distance between interleaved chunks. E.g., to interleave 8B chunks among 3 directories, set size=8B, step=24B", "0B"}, {"node", "Node number in multinode environment"}, /* Old parameters - deprecated or moved */ - {"network_num_vc", "DEPRECATED. Number of virtual channels (VCs) on the on-chip network. memHierarchy only uses one VC.", "1"}, // Remove SST 9.0 - {"network_address", "DEPRECATD - Now auto-detected by link control", ""}, // Remove SST 9.0 - {"network_bw", "MOVED. Now a member of the MemNIC/MemLink subcomponent.", "80GiB/s"}, // Remove SST 9.0 - {"network_input_buffer_size", "MOVED. Now a member of the MemNIC/MemLink subcomponent.", "1KiB"}, // Remove SST 9.0 - {"network_output_buffer_size", "MOVED. Now a member of the MemNIC/MemLink subcomponent.", "1KiB"}) // Remove SST 9.0 + {"network_bw", "MOVED. Now a member of the MemNIC subcomponent.", "80GiB/s"}, // Remove SST 9.0 + {"network_input_buffer_size", "MOVED. Now a member of the MemNIC subcomponent.", "1KiB"}, // Remove SST 9.0 + {"network_output_buffer_size", "MOVED. Now a member of the MemNIC subcomponent.", "1KiB"}) // Remove SST 9.0 SST_ELI_DOCUMENT_PORTS( - {"memory", "Link to memory controller", { "memHierarchy.MemEventBase" } }, - {"network", "Link to network; doubles as request network for split networks", { "memHierarchy.MemRtrEvent" } }, - {"network_ack", "For split networks, link to response/ack network", { "memHierarchy.MemRtrEvent" } }, - {"network_fwd", "For split networks, link to forward request network", { "memHierarchy.MemRtrEvent" } }, - {"network_data","For split networks, link to data network", { "memHierarchy.MemRtrEvent" } }) + {"highlink", "Non-network upper/CPU-side link (i.e., link towards the core/accelerator/etc.). This port loads the 'memHierarchy.MemLink' manager. " + "To connect to a network component or to use non-default parameters on the MemLink subcomponent, fill the 'highlink' subcomponent slot instead of connecting this port.", {"memHierarchy.MemEventBase"} }, + {"lowlink", "Non-network lower/memory-side link (i.e., link towards memory). This port loads the 'memHierarchy.MemLink' manager. " + "To connect to a network component or use non-default parameters on the MemLink subcomponent, fill the 'lowlink' subcomponent slot instead of connecting this port.", {"memHierarchy.MemEventBase"} }, + {"network", "DEPRECATED. Fill 'lowlink' subcomponent slot with 'memHierarchy.MemNIC' or 'memHierarchy.MemNICFour' instead and connect that subcomponent's ports. Network CPU-side link (i.e., link towards the core/accelerator/etc.). This port loads the 'memHierarchy.MemNIC' manager. If the 'lowlink' or deprecated 'memory' port is not filled, traffic to memory will also route through this port. Doubles as request network for split networks.", { "memHierarchy.MemRtrEvent" } }, + {"memory", "DEPRECATED. Use 'lowlink' port or fill 'lowlink' subcomponent slot instead. Link to memory controller", { "memHierarchy.MemEventBase" } }, + {"network_ack", "DEPRECATED. Fill 'highlink' subcomponent slot with 'memHierarchy.MemNICFour' instead. For split networks, link to response/ack network", { "memHierarchy.MemRtrEvent" } }, + {"network_fwd", "DEPRECATED. Fill 'highlink' subcomponent slot with 'memHierarchy.MemNICFour' instead. For split networks, link to forward request network", { "memHierarchy.MemRtrEvent" } }, + {"network_data","DEPRECATED. Fill 'highlink' subcomponent slot with 'memHierarchy.MemNICFour' instead. For split networks, link to data network", { "memHierarchy.MemRtrEvent" } }, + ) + SST_ELI_DOCUMENT_STATISTICS( {"replacement_request_latency", "Total latency in ns of all replacement (put*) requests handled", "nanoseconds", 1}, @@ -104,8 +107,10 @@ class DirectoryController : public Component { {"FetchResp_recv", "Event received: FetchResp (response to FetchInv/Fetch)", "count", 2}, {"FetchXResp_recv", "Event received: FetchXResp (response to FetchInvX)", "count", 2}, {"AckInv_recv", "Event received: AckInv (response to Inv/FetchInv/ForceInv)", "count", 2}, + {"AckFlush_recv", "Event received: AckFlush (response to ForwardFlush)", "count", 2}, {"FlushLine_recv", "Event received: FlushLine (flush, don't invalidate)", "count", 2}, {"FlushLineInv_recv", "Event received: FlushLineInv (flush and invalidate)", "count", 2}, + {"FlushAll_recv", "Event received: FlushAll (full cache flush)", "count", 2}, {"FlushLineResp_recv", "Event received: FlushLineResp (response to FlushLine/Inv)", "count", 2}, {"NACK_recv", "Event received: NACK", "count", 2}, {"GetS_uncache_recv", "Noncacheable Event: GetS received", "count", 4}, @@ -128,22 +133,27 @@ class DirectoryController : public Component { {"eventSent_FetchInv", "Event sent: FetchInv", "count", 2}, {"eventSent_FetchInvX", "Event sent: FetchInvX","count", 2}, {"eventSent_ForceInv", "Event sent: ForceInv", "count", 2}, + {"eventSent_ForwardFlush", "Event sent: ForwardFlush", "count", 2}, {"eventSent_NACK", "Event sent: NACK", "count", 2}, {"eventSent_GetSResp", "Event sent: GetSResp (shared data response)", "count", 1}, {"eventSent_GetXResp", "Event sent: GetXResp (exclusive data response)", "count", 1}, - {"eventSent_WriteResp", "Event sent: WriteResp (write ack)", "count", 1}, + {"eventSent_WriteResp", "Event sent: WriteResp (write ack)", "count", 1}, {"eventSent_FetchResp", "Event sent: FetchResp", "count", 2}, {"eventSent_AckInv", "Event sent: AckInv", "count", 2}, {"eventSent_AckPut", "Event sent: AckPut", "count", 2}, {"eventSent_FlushLine", "Event sent: FlushLine", "count", 2}, {"eventSent_FlushLineInv", "Event sent: FlushLineInv", "count", 2}, {"eventSent_FlushLineResp", "Event sent: FlushLineResp", "count", 2}, + {"eventSent_FlushAllResp", "Event sent: FlushAllResp", "count", 2}, + {"eventSent_UnblockFlush", "Event sent: UnblockFlush", "count", 2}, {"MSHR_occupancy", "Number of events in MSHR each cycle", "events", 1}, {"default_stat", "Default statistic. If not 0 then a statistic is missing", "", 1}) SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS( - {"cpulink", "CPU-side link manager, for single-link directories, use this one only", "SST::MemHierarchy::MemLinkBase"}, - {"memlink", "Memory-side link manager", "SST::MemHierarchy::MemLinkBase"} ) + {"highlink", "Port manager on the upper/processor-side (i.e., where requests typically come from). If you use this subcomponent slot, you do not need to connect the directory's highlink port. Do connect this subcomponent's ports instead. For directories with a single link, use this subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"lowlink", "Port manager on the lower/memory side. If you use this subcomponent slot, you do not need to connect the directory's lowlink port. Do connect the subcomponent's ports instead. For directories with a single link, use the 'highlink' subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"cpulink", "DEPRECATED. Renamed to 'highlink'. CPU-side port manager, for single-link directories, use this one only", "SST::MemHierarchy::MemLinkBase"}, + {"memlink", "DEPRECATD. Renamed to 'lowlink'. Memory-side port manager", "SST::MemHierarchy::MemLinkBase"} ) /* Begin class definition */ private: @@ -192,11 +202,11 @@ class DirectoryController : public Component { std::set addrsThisCycle; /* Network connections */ - MemLinkBase* memLink; - MemLinkBase* cpuLink; - string memoryName; // if connected to mem via network, this should be the name of the memory we own - param is memory_name - bool clockMemLink; - bool clockCpuLink; + MemLinkBase* downLink; + MemLinkBase* upLink; + + bool clockUpLink; + bool clockDownLink; bool isRequestAddressValid(Addr addr); @@ -245,12 +255,14 @@ class DirectoryController : public Component { bool handlePutX(MemEvent* event, bool inMSHR); bool handleFlushLine(MemEvent* event, bool inMSHR); bool handleFlushLineInv(MemEvent* event, bool inMSHR); + bool handleFlushAll(MemEvent* event, bool inMSHR); bool handleFetchInv(MemEvent* event, bool inMSHR); bool handleForceInv(MemEvent* event, bool inMSHR); bool handleGetSResp(MemEvent* event, bool inMSHR); bool handleGetXResp(MemEvent* event, bool inMSHR); bool handleWriteResp(MemEvent* event, bool inMSHR); bool handleFlushLineResp(MemEvent* event, bool inMSHR); + bool handleAckFlush(MemEvent* event, bool inMSHR); bool handleAckPut(MemEvent* event, bool inMSHR); bool handleAckInv(MemEvent* event, bool inMSHR); bool handleFetchResp(MemEvent* event, bool inMSHR); @@ -292,11 +304,11 @@ class DirectoryController : public Component { } eventDI, evictDI; struct DirEntry { - bool cached; // whether block is cached or not + bool cached; // whether block is cached or not Addr addr; // block address State state; // state std::list::iterator cacheIter; - std::set sharers; // set of sharers for block + std::set sharers; // set of sharers for block std::string owner; // Owner of block DirEntry(Addr a) { @@ -420,6 +432,8 @@ class DirectoryController : public Component { uint64_t accessLatency; uint64_t mshrLatency; + FlushState flush_state_; + std::map > responses; std::map dirMemAccesses; diff --git a/src/sst/elements/memHierarchy/lineTypes.h b/src/sst/elements/memHierarchy/lineTypes.h index a37d2a59c4..d555496a47 100644 --- a/src/sst/elements/memHierarchy/lineTypes.h +++ b/src/sst/elements/memHierarchy/lineTypes.h @@ -35,6 +35,7 @@ namespace SST { namespace MemHierarchy { * - getString() for debug * - getAddr() for identifiying a line * - getReplacementInfo() for returning the information that a replacement policy might need + * - allocated() to determine whether the line is currently allocated/valid */ @@ -52,17 +53,20 @@ class DirectoryLine { bool wasPrefetch_; public: - DirectoryLine(uint32_t size, unsigned int index) : index_(index), addr_(0), state_(I), lastSendTimestamp_(0), wasPrefetch_(false) { + DirectoryLine(uint32_t size, unsigned int index) : index_(index) { info_ = new CoherenceReplacementInfo(index, I, false, false); + reset(); } virtual ~DirectoryLine() { } void reset() { + addr_ = NO_ADDR; state_ = I; sharers_.clear(); owner_ = ""; lastSendTimestamp_ = 0; wasPrefetch_ = false; + info_->reset(); } // Index @@ -115,6 +119,9 @@ class DirectoryLine { // Replacement ReplacementInfo* getReplacementInfo() { return info_; } + // Validity + bool allocated() { return state_ != I; } + // String-ify for debugging std::string getString() { std::ostringstream str; @@ -138,14 +145,17 @@ class DataLine { DirectoryLine* tag_; CoherenceReplacementInfo* info_; public: - DataLine(uint8_t size, unsigned int index) : index_(index), addr_(0), tag_(nullptr) { + DataLine(uint8_t size, unsigned int index) : index_(index) { data_.resize(size); info_ = new CoherenceReplacementInfo(index, I, false, false); + reset(); } virtual ~DataLine() { } void reset() { + addr_ = NO_ADDR; tag_ = nullptr; + info_->reset(); } // Index @@ -169,7 +179,10 @@ class DataLine { } // Replacement - ReplacementInfo* getReplacementInfo() { return tag_ ? tag_->getReplacementInfo() : info_; } + ReplacementInfo* getReplacementInfo() { return (tag_ != nullptr ? tag_->getReplacementInfo() : info_); } + + // Validity + bool allocated() { return tag_ != nullptr; } // String-ify for debugging std::string getString() { @@ -193,12 +206,14 @@ class CacheLine { virtual void updateReplacement() = 0; public: - CacheLine(uint32_t size, unsigned int index) : index_(index), addr_(0), state_(I), lastSendTimestamp_(0), wasPrefetch_(false) { + CacheLine(uint32_t size, unsigned int index) : index_(index) { + reset(); data_.resize(size); } virtual ~CacheLine() { } void reset() { + addr_ = NO_ADDR; state_ = I; lastSendTimestamp_ = 0; wasPrefetch_ = false; @@ -231,6 +246,9 @@ class CacheLine { virtual ReplacementInfo* getReplacementInfo() = 0; + // Validity + bool allocated() { return state_ != I; } + // String-ify for debugging std::string getString() { std::ostringstream str; @@ -243,22 +261,22 @@ class CacheLine { /* With atomic/lock flags for L1 caches */ class L1CacheLine : public CacheLine { private: - bool LLSC_; /* True if LL has been issued and no intervening accesses have occured */ + bool LLSC_; /* True if LL has been issued and no intervening accesses have occurred */ Cycle_t LLSCTime_; /* For caches that guarantee forward progress on LLSC, LLSC temporarily locks the line. This is the time that the LLSC lock will be released */ std::set LLSCTidBuf_; /* Track hardware thread IDs that have LL'd this line*/ /* This is stored in the line rather than in a separate cache-side map to make lookup & maintenance faster (esp. on non-atomic accesses) */ /* TODO add ability to limit outstanding LLSCs per thread and/or overall (requires a cache-side structure to track global cache state) */ unsigned int userLock_; /* Count number of lock operations to the line */ bool eventsWaitingForLock_; /* Number of events in the queue waiting for the lock */ - ReplacementInfo * info; /* Replacement info - depends on replacement algorithm */ + ReplacementInfo * info_; /* Replacement info - depends on replacement algorithm */ protected: - void updateReplacement() { info->setState(state_); } + void updateReplacement() { info_->setState(state_); } public: - L1CacheLine(uint32_t size, unsigned int index) : LLSC_(false), LLSCTime_(0), userLock_(0), eventsWaitingForLock_(false), CacheLine(size, index) { - info = new ReplacementInfo(index, I); + L1CacheLine(uint32_t size, unsigned int index) : CacheLine(size, index), LLSC_(false), LLSCTime_(0), userLock_(0), eventsWaitingForLock_(false) { + info_ = new ReplacementInfo(index, I); } virtual ~L1CacheLine() { - delete info; + delete info_; } void reset() { @@ -268,6 +286,7 @@ class L1CacheLine : public CacheLine { LLSCTidBuf_.clear(); userLock_ = 0; eventsWaitingForLock_ = false; + info_->setState(getState()); } // LLSC @@ -300,7 +319,7 @@ class L1CacheLine : public CacheLine { bool getEventsWaitingForLock() { return eventsWaitingForLock_; } void setEventsWaitingForLock(bool eventsWaiting) { eventsWaitingForLock_ = eventsWaiting; } - ReplacementInfo * getReplacementInfo() { return info; } + ReplacementInfo * getReplacementInfo() { return info_; } // String-ify for debugging std::string getString() { @@ -322,22 +341,23 @@ class SharedCacheLine : public CacheLine { private: std::set sharers_; std::string owner_; - CoherenceReplacementInfo * info; + CoherenceReplacementInfo * info_; protected: - virtual void updateReplacement() { info->setState(state_); } + virtual void updateReplacement() { info_->setState(state_); } public: - SharedCacheLine(uint32_t size, unsigned int index) : owner_(""), CacheLine(size, index) { - info = new CoherenceReplacementInfo(index, I, false, false); + SharedCacheLine(uint32_t size, unsigned int index) : CacheLine(size, index), owner_("") { + info_ = new CoherenceReplacementInfo(index, I, false, false); } virtual ~SharedCacheLine() { - delete info; + delete info_; } void reset() { CacheLine::reset(); sharers_.clear(); owner_ = ""; + info_->reset(); } // Sharers @@ -348,11 +368,11 @@ class SharedCacheLine : public CacheLine { bool hasOtherSharers(std::string shr) { return !(sharers_.empty() || (sharers_.size() == 1 && sharers_.find(shr) != sharers_.end())); } void addSharer(std::string s) { sharers_.insert(s); - info->setShared(true); + info_->setShared(true); } void removeSharer(std::string s) { sharers_.erase(s); - info->setShared(!sharers_.empty()); + info_->setShared(!sharers_.empty()); } // Owner @@ -360,15 +380,15 @@ class SharedCacheLine : public CacheLine { bool hasOwner() { return !owner_.empty(); } void setOwner(std::string owner) { owner_ = owner; - info->setOwned(true); + info_->setOwned(true); } void removeOwner() { owner_.clear(); - info->setOwned(false); + info_->setOwned(false); } // Replacement - ReplacementInfo * getReplacementInfo() { return info; } + ReplacementInfo * getReplacementInfo() { return info_; } // String-ify for debugging std::string getString() { @@ -387,41 +407,42 @@ class SharedCacheLine : public CacheLine { /* With flags indicating whether block is cached abov efor private caches */ class PrivateCacheLine : public CacheLine { private: - bool shared; - bool owned; - CoherenceReplacementInfo * info; + bool shared_; + bool owned_; + CoherenceReplacementInfo * info_; protected: - virtual void updateReplacement() { info->setState(state_); } + virtual void updateReplacement() { info_->setState(state_); } public: - PrivateCacheLine(uint32_t size, unsigned int index) : shared(false), owned(false), CacheLine(size, index) { - info = new CoherenceReplacementInfo(index, I, false, false); + PrivateCacheLine(uint32_t size, unsigned int index) : CacheLine(size, index), shared_(false), owned_(false) { + info_ = new CoherenceReplacementInfo(index, I, false, false); } virtual ~PrivateCacheLine() { } void reset() { CacheLine::reset(); - shared = false; - owned = false; + shared_ = false; + owned_ = false; + info_->reset(); } // Shared - bool getShared() { return shared; } - void setShared(bool s) { shared = s; info->setShared(s);} + bool getShared() { return shared_; } + void setShared(bool s) { shared_ = s; info_->setShared(s);} // Owned - bool getOwned() { return owned; } - void setOwned(bool o) { owned = o; info->setOwned(o); } + bool getOwned() { return owned_; } + void setOwned(bool o) { owned_ = o; info_->setOwned(o); } // Replacement - ReplacementInfo * getReplacementInfo() { return info; } + ReplacementInfo * getReplacementInfo() { return info_; } // String-ify for debugging std::string getString() { std::string str = "O: "; - str += owned ? "Yes" : "No"; + str += owned_ ? "Yes" : "No"; str += " S: "; - str += shared ? "Yes" : "No"; + str += shared_ ? "Yes" : "No"; return str; } }; diff --git a/src/sst/elements/memHierarchy/memEvent.h b/src/sst/elements/memHierarchy/memEvent.h index c8ef184dbe..2eb7e1d26d 100644 --- a/src/sst/elements/memHierarchy/memEvent.h +++ b/src/sst/elements/memHierarchy/memEvent.h @@ -40,51 +40,33 @@ using namespace std; */ class MemEvent : public MemEventBase { public: - - /****** Old calls will now throw deprecated warnings since parent pointer is not available *************/ - /** Creates a new MemEvent - Generic */ - MemEvent(const Component *src, Addr addr, Addr baseAddr, Command cmd) : MemEventBase(src->getName(), cmd) { - initialize(); - addr_ = addr; - baseAddr_ = baseAddr; - } - - /** MemEvent constructor - Reads */ - MemEvent(const Component *src, Addr addr, Addr baseAddr, Command cmd, uint32_t size) : MemEventBase(src->getName(), cmd) { - initialize(); - addr_ = addr; - baseAddr_ = baseAddr; - size_ = size; - } - - /** MemEvent constructor - Writes */ - MemEvent(const Component *src, Addr addr, Addr baseAddr, Command cmd, std::vector& data) : MemEventBase(src->getName(), cmd) { - initialize(); - addr_ = addr; - baseAddr_ = baseAddr; - setPayload(data); // Also sets size_ field - } - - /************ New calls - use these! *****************/ + + /* Constructor - Coherence control */ MemEvent(std::string src, Addr addr, Addr baseAddr, Command cmd) : MemEventBase(src, cmd) { initialize(); addr_ = addr; baseAddr_ = baseAddr; } + /* Constructor - Events that request data */ MemEvent(std::string src, Addr addr, Addr baseAddr, Command cmd, uint32_t size) : MemEventBase(src, cmd) { initialize(); addr_ = addr; baseAddr_ = baseAddr; size_ = size; } + /* Constructor - Events that carry data */ MemEvent(std::string src, Addr addr, Addr baseAddr, Command cmd, std::vector& data) : MemEventBase(src, cmd) { initialize(); addr_ = addr; baseAddr_ = baseAddr; setPayload(data); } - - + /* Constructor - Events that are not routed by address */ + MemEvent(std::string src, Command cmd) : MemEventBase(src, cmd) { + initialize(); + addr_ = 0; + baseAddr_ = 0; + } /** Create a new MemEvent instance, pre-configured to act as a NACK response */ MemEvent* makeNACKResponse(MemEvent* NACKedEvent) { diff --git a/src/sst/elements/memHierarchy/memEventBase.h b/src/sst/elements/memHierarchy/memEventBase.h index 895ea29025..0193522149 100644 --- a/src/sst/elements/memHierarchy/memEventBase.h +++ b/src/sst/elements/memHierarchy/memEventBase.h @@ -444,24 +444,32 @@ class MemEventInitEndpoint : public MemEventInit { class MemEventInitRegion : public MemEventInit { public: - MemEventInitRegion(std::string src, MemRegion region, bool setRegion) : - MemEventInit(src, InitCommand::Region), region_(region), setRegion_(setRegion) { } + + enum class ReachableGroup { Source, Dest, Peer, Unknown }; - MemRegion getRegion() { return region_; } + MemEventInitRegion(std::string src, MemRegion region, ReachableGroup group = ReachableGroup::Unknown) : + MemEventInit(src, InitCommand::Region), region_(region), group_(group) { } - bool getSetRegion() { return setRegion_; } + MemRegion getRegion() { return region_; } + + ReachableGroup getGroup() { return group_; } + void setGroup(ReachableGroup group) { group_ = group; } virtual MemEventInitRegion* clone(void) override { return new MemEventInitRegion(*this); } virtual std::string getVerboseString(int level = 1) override { - return MemEventInit::getVerboseString(level) + region_.toString() + " SetRegion: " + (setRegion_ ? "T" : "F"); + std::string groupstr = "Unknown"; + if (group_ == ReachableGroup::Source) groupstr = "Source"; + else if (group_ == ReachableGroup::Dest) groupstr = "Dest"; + else if (group_ == ReachableGroup::Peer) groupstr = "Peer"; + return MemEventInit::getVerboseString(level) + region_.toString() + " Group: " + groupstr.c_str(); } private: MemRegion region_; // MemRegion for source - bool setRegion_; // Whether this is a push to set the destination's region or not + ReachableGroup group_; // Whether sent from a source/dest/peer or something else (unknown) MemEventInitRegion() {} // For serialization only @@ -472,7 +480,7 @@ class MemEventInitRegion : public MemEventInit { ser & region_.end; ser & region_.interleaveStep; ser & region_.interleaveSize; - ser & setRegion_; + ser & group_; } ImplementSerializable(SST::MemHierarchy::MemEventInitRegion); diff --git a/src/sst/elements/memHierarchy/memLink.cc b/src/sst/elements/memHierarchy/memLink.cc index 0c3599679b..3e0ea0868f 100644 --- a/src/sst/elements/memHierarchy/memLink.cc +++ b/src/sst/elements/memHierarchy/memLink.cc @@ -28,12 +28,12 @@ MemLink::MemLink(ComponentId_t id, Params ¶ms, TimeConverter* tc) : MemLinkB std::string port = params.find("port", "port"); if (found) { - link = configureLink(port, latency, new Event::Handler(this, &MemLink::recvNotify)); + link_ = configureLink(port, latency, new Event::Handler(this, &MemLink::recvNotify)); } else { - link = configureLink(port, new Event::Handler(this, &MemLink::recvNotify)); + link_ = configureLink(port, new Event::Handler(this, &MemLink::recvNotify)); } - if (!link) + if (!link_) dbg.fatal(CALL_INFO, -1, "%s, Error: unable to configure link on port '%s'\n", getName().c_str(), port.c_str()); dbg.debug(_L10_, "%s memLink info is: Name: %s, addr: %" PRIu64 ", id: %" PRIu32 "\n", @@ -43,26 +43,43 @@ MemLink::MemLink(ComponentId_t id, Params ¶ms, TimeConverter* tc) : MemLinkB /* init function */ void MemLink::init(unsigned int phase) { if (!phase) { - MemEventInitRegion * ev = new MemEventInitRegion(info.name, info.region, false); + // It's not easy to discern if we're on a lowlink or highlink and set the group to Dest or Source accordingly. + // Anonymous subcomponents don't have the slot name in their name. For now, we don't strictly have to differentiate + // Dest & Source, so just always put Dest. If there's a bus between this component and the component on the other side, + // the bus will update the group to the correct one since it has a notion of "high" (source) vs "low" (dest) ports. + // Otherwise, the group will be incorrect if this MemLink is loaded into a 'highlink' subcomponent slot. + // Not a problem unless we start treating source & dest differently. + MemEventInitRegion * ev = new MemEventInitRegion(info.name, info.region, MemEventInitRegion::ReachableGroup::Dest); dbg.debug(_L10_, "%s sending region init message: %s\n", getName().c_str(), ev->getVerboseString().c_str()); - link->sendUntimedData(ev); + link_->sendUntimedData(ev); } SST::Event * ev; - while ((ev = link->recvUntimedData())) { + while ((ev = link_->recvUntimedData())) { MemEventInit * mEv = static_cast(ev); if (mEv) { if (mEv->getInitCmd() == MemEventInit::InitCommand::Region) { MemEventInitRegion * mEvRegion = static_cast(mEv); - dbg.debug(_L10_, "%s received init message: %s\n", getName().c_str(), mEvRegion->getVerboseString().c_str()); - - EndpointInfo epInfo; - epInfo.name = mEvRegion->getSrc(); - epInfo.addr = 0; - epInfo.id = 0; - epInfo.region = mEvRegion->getRegion(); - addRemote(epInfo); + if (mEvRegion->getGroup() != MemEventInitRegion::ReachableGroup::Peer) { + dbg.debug(_L10_, "%s received init message: %s\n", getName().c_str(), mEvRegion->getVerboseString().c_str()); + + EndpointInfo ep_info; + ep_info.name = mEvRegion->getSrc(); + ep_info.addr = 0; + ep_info.id = 0; + ep_info.region = mEvRegion->getRegion(); + addRemote(ep_info); + } else { + EndpointInfo ep_info; + ep_info.name = mEvRegion->getSrc(); + ep_info.addr = 0; + ep_info.id = 0; + ep_info.region = mEvRegion->getRegion(); + peers_.insert(ep_info); + reachable_names_.insert(ep_info.name); + peer_names_.insert(ep_info.name); + } delete ev; } else if (mEv->getInitCmd() == MemEventInit::InitCommand::Endpoint) { // Intercept and record so that we know how to find this endpoint. @@ -72,12 +89,12 @@ void MemLink::init(unsigned int phase) { dbg.debug(_L10_, "%s received init message: %s\n", getName().c_str(), mEvEndPt->getVerboseString().c_str()); std::vector> regions = mEvEndPt->getRegions(); for (auto it = regions.begin(); it != regions.end(); it++) { - EndpointInfo epInfo; - epInfo.name = mEvEndPt->getSrc(); - epInfo.addr = 0; // Not on a network so don't need it - epInfo.id = 0; // Not on a network so don't need it - epInfo.region = it->first; - addEndpoint(epInfo); + EndpointInfo ep_info; + ep_info.name = mEvEndPt->getSrc(); + ep_info.addr = 0; // Not on a network so don't need it + ep_info.id = 0; // Not on a network so don't need it + ep_info.region = it->first; + addEndpoint(ep_info); } initReceiveQ.push(mEv); // Our component will forward on all its other ports } else { @@ -88,13 +105,13 @@ void MemLink::init(unsigned int phase) { } // Attempt to drain send Q - for (auto it = initSendQ.begin(); it != initSendQ.end(); ) { + for (auto it = init_send_queue_.begin(); it != init_send_queue_.end(); ) { std::string dst = findTargetDestination((*it)->getRoutingAddress()); if (dst != "") { dbg.debug(_L10_, "%s sending init message: %s\n", getName().c_str(), (*it)->getVerboseString().c_str()); (*it)->setDst(dst); - link->sendUntimedData(*it); - it = initSendQ.erase(it); + link_->sendUntimedData(*it); + it = init_send_queue_.erase(it); } else { it++; } @@ -105,16 +122,29 @@ void MemLink::init(unsigned int phase) { void MemLink::setup() { dbg.debug(_L10_, "Routing information for %s\n", getName().c_str()); - for (auto it = remotes.begin(); it != remotes.end(); it++) { + for (auto it = remotes_.begin(); it != remotes_.end(); it++) { dbg.debug(_L10_, " Remote: %s\n", it->toString().c_str()); } - for (auto it = endpoints.begin(); it != endpoints.end(); it++) { + for (auto it = endpoints_.begin(); it != endpoints_.end(); it++) { dbg.debug(_L10_, " Endpoint: %s\n", it->toString().c_str()); } - - if (!initSendQ.empty()) { + auto sources = getSources(); + if (sources->empty()) dbg.debug(_L10_, " Source: NONE\n"); + for (auto it = sources->begin(); it != sources->end(); it++) { + dbg.debug(_L10_, " Source: %s\n", it->toString().c_str()); + } + auto dests = getDests(); + if (dests->empty()) dbg.debug(_L10_, " Destination: NONE\n"); + for (auto it = dests->begin(); it != dests->end(); it++) { + dbg.debug(_L10_, " Destination: %s\n", it->toString().c_str()); + } + if (peers_.empty()) dbg.debug(_L10_, " Peer: NONE\n"); + for (auto it = peers_.begin(); it != peers_.end(); it++) { + dbg.debug(_L10_, " Peer: %s\n", it->toString().c_str()); + } + if (!init_send_queue_.empty()) { dbg.fatal(CALL_INFO, -1, "%s, Error: Unable to find destination for init event %s\n", - getName().c_str(), (*initSendQ.begin())->getVerboseString().c_str()); + getName().c_str(), (*init_send_queue_.begin())->getVerboseString().c_str()); } } @@ -127,13 +157,13 @@ void MemLink::sendInitData(MemEventInit * event, bool broadcast) { std::string dst = findTargetDestination(event->getRoutingAddress()); if (dst == "") { /* Stall this until address is known */ - initSendQ.insert(event); + init_send_queue_.insert(event); return; } event->setDst(dst); } dbg.debug(_L10_, "%s sending init message: %s\n", getName().c_str(), event->getVerboseString().c_str()); - link->sendUntimedData(event); + link_->sendUntimedData(event); } /** @@ -149,12 +179,12 @@ MemEventInit * MemLink::recvInitData() { } void MemLink::addRemote(EndpointInfo info) { - remotes.insert(info); - remoteNames.insert(info.name); + remotes_.insert(info); + reachable_names_.insert(info.name); } void MemLink::addEndpoint(EndpointInfo info) { - endpoints.insert(info); + endpoints_.insert(info); } bool MemLink::isDest(std::string UNUSED(str)) { @@ -165,26 +195,34 @@ bool MemLink::isSource(std::string UNUSED(str)) { return true; } +bool MemLink::isPeer(std::string str) { + return peer_names_.find(str) != peer_names_.end(); +} + std::set* MemLink::getSources() { - return &remotes; + return &remotes_; } std::set* MemLink::getDests() { - return &remotes; + return &remotes_; +} + +std::set* MemLink::getPeers() { + return &peers_; } /** * send event on link */ void MemLink::send(MemEventBase *ev) { - link->send(ev); + link_->send(ev); } /** * Polled receive */ MemEventBase * MemLink::recv() { - SST::Event * ev = link->recv(); + SST::Event * ev = link_->recv(); MemEventBase * mEv = static_cast(ev); if (mEv) return mEv; @@ -201,7 +239,7 @@ std::string MemLink::getTargetDestination(Addr addr) { stringstream error; error << getName() + " (MemLink) cannot find a destination for address " << std::hex << addr << std::dec << endl; error << "Known destinations: " << endl; - for (std::set::const_iterator it = remotes.begin(); it != remotes.end(); it++) { + for (std::set::const_iterator it = remotes_.begin(); it != remotes_.end(); it++) { error << it->name << " " << it->region.toString() << endl; } dbg.fatal(CALL_INFO, -1, "%s", error.str().c_str()); @@ -209,19 +247,19 @@ std::string MemLink::getTargetDestination(Addr addr) { } std::string MemLink::findTargetDestination(Addr addr) { - for (std::set::const_iterator it = remotes.begin(); it != remotes.end(); it++) { + for (std::set::const_iterator it = remotes_.begin(); it != remotes_.end(); it++) { if (it->region.contains(addr)) return it->name; } return ""; } bool MemLink::isReachable(std::string dst) { - return remoteNames.find(dst) != remoteNames.end(); + return reachable_names_.find(dst) != reachable_names_.end(); } std::string MemLink::getAvailableDestinationsAsString() { std::stringstream str; - for (std::set::const_iterator it = endpoints.begin(); it != endpoints.end(); it++) { + for (std::set::const_iterator it = endpoints_.begin(); it != endpoints_.end(); it++) { str << it->toString() << std::endl; } return str.str(); diff --git a/src/sst/elements/memHierarchy/memLink.h b/src/sst/elements/memHierarchy/memLink.h index a7d80749fa..30acb78d97 100644 --- a/src/sst/elements/memHierarchy/memLink.h +++ b/src/sst/elements/memHierarchy/memLink.h @@ -99,8 +99,10 @@ class MemLink : public MemLinkBase { /* Remote endpoint info management */ virtual std::set* getSources(); virtual std::set* getDests(); + virtual std::set* getPeers(); virtual bool isDest(std::string UNUSED(str)); virtual bool isSource(std::string UNUSED(str)); + virtual bool isPeer(std::string str); virtual std::string findTargetDestination(Addr addr); virtual std::string getTargetDestination(Addr addr); virtual bool isReachable(std::string dst); @@ -122,15 +124,17 @@ class MemLink : public MemLinkBase { void addEndpoint(EndpointInfo info); // Link - SST::Link* link; + SST::Link* link_; // Data structures - std::set remotes; // Tracks remotes immediately accessible on the other side of our link - std::set endpoints; // Tracks endpoints in the system with info on how to get there - std::set remoteNames; // Tracks remote names for faster lookup than iteratinv via remotes + std::set remotes_; // Tracks remotes (source or dest) immediately accessible on the other side of our link + std::set peers_; // Tracks peers immediately accessible on the other side of our link + std::set endpoints_; // Tracks endpoints in the system with info on how to get there + std::set reachable_names_; // Tracks reachable names for faster lookup than iterating via remotes/peers + std::set peer_names_; // Tracks peer names for faster lookup than iterating via peers // For events that require destination names during init - std::set initSendQ; + std::set init_send_queue_; private: diff --git a/src/sst/elements/memHierarchy/memLinkBase.h b/src/sst/elements/memHierarchy/memLinkBase.h index 6417569428..393f3a14d7 100644 --- a/src/sst/elements/memHierarchy/memLinkBase.h +++ b/src/sst/elements/memHierarchy/memLinkBase.h @@ -72,6 +72,9 @@ class MemLinkBase : public SST::SubComponent { return str.str(); } }; + + // Identifiers that can be attached to init messages to detect memory system topology + enum class ReachableGroup{Source, Dest, Peer, Unknown}; /* Constructor */ MemLinkBase(ComponentId_t id, Params ¶ms, TimeConverter* tc) : SubComponent(id) { @@ -100,8 +103,7 @@ class MemLinkBase : public SST::SubComponent { string ilStep = params.find("interleave_step", "0B", found); foundany |= found; if (foundany) { - dbg.output("%s, Warning: Region parameters given to link managers (addr_range_start/end, interleave_size/step) will be overwritten if the component sets them; specify region via component to eliminate this message\n", - getName().c_str()); + dbg.output("%s, Warning: The region parameters (addr_range_start, addr_range_end, interleave_size, interleave_step) are deprecated in MemLink and MemNIC. Give these parameters to the component instead to eliminate this message\n", getName().c_str()); } // Ensure SI units are power-2 not power-10 - for backward compability @@ -184,9 +186,11 @@ class MemLinkBase : public SST::SubComponent { /* Functions for managing source/destination information */ virtual std::set* getSources() =0; virtual std::set* getDests() =0; + virtual std::set* getPeers() =0; // If peers are reachable via this link, may be empty if no peers or not reachable virtual bool isDest(std::string UNUSED(str)) =0; /* Check whether a component is a destination on this link. May be slow (for init() only) */ - virtual bool isSource(std::string UNUSED(str)) =0; /* Check whether a component is a soruce on this link. May be slow (for init() only) */ + virtual bool isSource(std::string UNUSED(str)) =0; /* Check whether a component is a source on this link. May be slow (for init() only) */ + virtual bool isPeer(std::string UNUSED(str)) =0; /* Check whether a component is a peer on this link. May be slow (for init() only) */ virtual bool isReachable(std::string dst) =0; /* Check whether a component is reachable on this link. Should be fast - used during simulation */ MemRegion getRegion() { return info.region; } diff --git a/src/sst/elements/memHierarchy/memNICBase.h b/src/sst/elements/memHierarchy/memNICBase.h index b1d54ed53d..f5a64219a6 100644 --- a/src/sst/elements/memHierarchy/memNICBase.h +++ b/src/sst/elements/memHierarchy/memNICBase.h @@ -198,11 +198,19 @@ class MemNICBase : public MemLinkBase { return false; } + virtual bool isPeer(std::string str) { + for (std::set::iterator it = peerEndpointInfo.begin(); it != peerEndpointInfo.end(); it++) { + if (it->name == str) return true; + } + return false; + } + virtual bool isClocked() { return true; } // Tell parent to trigger our clock virtual std::set* getSources() { return &sourceEndpointInfo; } virtual std::set* getDests() { return &destEndpointInfo; } - + virtual std::set* getPeers() { return &peerEndpointInfo; } + virtual std::string findTargetDestination(Addr addr) { for (std::set::const_iterator it = destEndpointInfo.begin(); it != destEndpointInfo.end(); it++) { if (it->region.contains(addr)) return it->name; @@ -249,6 +257,10 @@ class MemNICBase : public MemLinkBase { reachableNames.insert(info.name); } + virtual void addPeer(EndpointInfo info) { + peerEndpointInfo.insert(info); + } + virtual void addEndpoint(EndpointInfo info) { endpointInfo.insert(info); } virtual InitMemRtrEvent* createInitMemRtrEvent() { @@ -268,6 +280,10 @@ class MemNICBase : public MemLinkBase { dbg.debug(_L10_, "%s (memNICBase) received dest imre. Name: %s, Addr: %" PRIu64 ", ID: %" PRIu32 ", start: %" PRIu64 ", end: %" PRIu64 ", size: %" PRIu64 ", step: %" PRIu64 "\n", getName().c_str(), imre->info.name.c_str(), imre->info.addr, imre->info.id, imre->info.region.start, imre->info.region.end, imre->info.region.interleaveSize, imre->info.region.interleaveStep); } + + if (imre->info.id == info.id) { + addPeer(imre->info); + } } /* NIC initialization so that subclasses don't have to do this. Subclasses should call this during init() */ @@ -364,10 +380,7 @@ class MemNICBase : public MemLinkBase { dbg.debug(_L10_, "\tInserting in initQueue\n"); mre->putEvent(ev); // If we did not delete the Event, give it back to the MemRtrEvent initQueue.push(mre); - } else { - delete mre; - delete ev; - } + } } delete req; } @@ -440,9 +453,15 @@ class MemNICBase : public MemLinkBase { for (auto it = sourceEndpointInfo.begin(); it != sourceEndpointInfo.end(); it++) { dbg.debug(_L10_, " Source: %s\n", it->toString().c_str()); } + if (sourceEndpointInfo.empty()) dbg.debug(_L10_, " Source: NONE\n"); for (std::set::const_iterator it = destEndpointInfo.begin(); it != destEndpointInfo.end(); it++) { dbg.debug(_L10_, " Dest: %s\n", it->toString().c_str()); } + if (destEndpointInfo.empty()) dbg.debug(_L10_, " Dest: NONE\n"); + for (auto it = peerEndpointInfo.begin(); it != peerEndpointInfo.end(); it++) { + dbg.debug(_L10_, " Peer: %s\n", it->toString().c_str()); + } + if (peerEndpointInfo.empty()) dbg.debug(_L10_, " Peer: NONE\n"); for (auto it = endpointInfo.begin(); it != endpointInfo.end(); it++) { dbg.debug(_L10_, " Endpoint: %s\n", it->toString().c_str()); } @@ -490,7 +509,7 @@ class MemNICBase : public MemLinkBase { #ifdef __SST_DEBUG_OUTPUT__ if (!debugEvStr.empty() && doDebug) { dbg.debug(_L4_, "E: %-20" PRIu64 " %-20" PRIu64 " %-20s Event:Send (%s), Dst: %" PRIu64 "\n", - getCurrentSimCycle(), 0, getName().c_str(), debugEvStr.c_str(), dst); + getCurrentSimCycle(), 0ULL, getName().c_str(), debugEvStr.c_str(), dst); } #endif queue->pop(); @@ -520,6 +539,9 @@ class MemNICBase : public MemLinkBase { if (destIDs.find(imre->info.id) != destIDs.end()) { addDest(imre->info); } + if (imre->info.id == info.id) { + addPeer(imre->info); + } delete imre; } } @@ -533,6 +555,7 @@ class MemNICBase : public MemLinkBase { std::unordered_map networkAddressMap; // Map of name -> address for each network endpoint std::set sourceEndpointInfo; std::set destEndpointInfo; + std::set peerEndpointInfo; std::set endpointInfo; std::set reachableNames; diff --git a/src/sst/elements/memHierarchy/memTypes.h b/src/sst/elements/memHierarchy/memTypes.h index da30f15f32..9653b5d6fa 100644 --- a/src/sst/elements/memHierarchy/memTypes.h +++ b/src/sst/elements/memHierarchy/memTypes.h @@ -76,6 +76,10 @@ enum class MemEventType { Cache, Move, Custom }; // For parsi X(FetchInvX, FetchXResp, Request, ForwardRequest, 0, 0, Cache) /* Other read request to owner: Downgrade cache line to O/S (Remove exclusivity) */\ X(FetchResp, NULLCMD, Response, Data, 1, 0, Cache) /* response to a Fetch, FetchInv or FetchInvX request */\ X(FetchXResp, NULLCMD, Response, Data, 1, 0, Cache) /* response to a FetchInvX request - indicates a shared copy of the line was kept */\ + /* Flush orchestration */\ + X(ForwardFlush, AckFlush, Request, ForwardRequest, 0, 0, Cache) /* Forwarded request to flush an entire cache */\ + X(AckFlush, NULLCMD, Response, Ack, 0, 0, Cache) /* Acknowledge that cache is flushed */\ + X(UnblockFlush, NULLCMD, Response, Ack, 0, 0, Cache) /* Confirm that flush is complete and it is safe to unblock cache */\ /* Others */\ X(NACK, NULLCMD, Response, Ack, 1, 0, Cache) /* NACK response to a message */\ X(AckInv, NULLCMD, Response, Ack, 1, 0, Cache) /* Acknowledgement response to an invalidation request */\ @@ -228,6 +232,9 @@ static const std::string NONE = "None"; // Define status types used internally to classify event handling resutls enum class MemEventStatus { OK, Stall, Reject }; +// Define global cache state used to manage cache flushes +enum class FlushState { Ready, Drain, Forward, Invalidate }; + /* Define an address region by start/end & interleaving */ class MemRegion : public SST::Core::Serialization::serializable { public: diff --git a/src/sst/elements/memHierarchy/memoryCacheController.cc b/src/sst/elements/memHierarchy/memoryCacheController.cc index 25d1deccb5..f998fbf4f4 100644 --- a/src/sst/elements/memHierarchy/memoryCacheController.cc +++ b/src/sst/elements/memHierarchy/memoryCacheController.cc @@ -126,10 +126,17 @@ MemCacheController::MemCacheController(ComponentId_t id, Params ¶ms) : Compo bool found; - link_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, clockTimeBase_); + link_ = loadUserSubComponent("highlink", ComponentInfo::SHARE_NONE, clockTimeBase_); if (!link_) { - out.fatal(CALL_INFO,-1,"%s, Error: No link handler loaded into 'cpulink' subcomponent slot.\n", getName().c_str()); + link_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, clockTimeBase_); + if (link_) { + out.output("%s, DEPRECATION WARNING: The 'cpulink' subcomponent slot has been renamed to 'highlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + } + + if (!link_) { + out.fatal(CALL_INFO,-1,"%s, Error: No link handler loaded into 'highlink' subcomponent slot.\n", getName().c_str()); } clockLink_ = link_->isClocked(); diff --git a/src/sst/elements/memHierarchy/memoryCacheController.h b/src/sst/elements/memHierarchy/memoryCacheController.h index efbf6a0831..f048bde5ec 100644 --- a/src/sst/elements/memHierarchy/memoryCacheController.h +++ b/src/sst/elements/memHierarchy/memoryCacheController.h @@ -62,7 +62,8 @@ class MemCacheController : public SST::Component { #define MEMCACHE_ELI_SUBCOMPONENTSLOTS {"backend", "Memory controller and/or memory timing model.", "SST::MemHierarchy::MemBackend"},\ {"backendConvertor", "Convertor to translate incoming memory events for the backend. Loaded automatically based on backend type.", "SST::MemHierarchy::MemBackendConvertor"},\ {"listener", "Optional listeners to gather statistics, create traces, etc. Multiple listeners supported.", "SST::MemHierarchy::CacheListener"}, \ - {"cpulink", "CPU-side link manager (e.g., to caches/cpu)", "SST::MemHierarchy::MemLinkBase"} + {"highlink", "CPU-side port manager (e.g., link to caches/cpu). If used, do not connect the 'highlink' port and connect the highlink subcomponent's port(s) instead.", "SST::MemHierarchy.MemLinkBase"},\ + {"cpulink", "DEPRECATED: Renamed to 'highlink' for naming consistency. CPU-side link manager (e.g., to caches/cpu). Defaults to MemLink.", "SST::MemHierarchy::MemLinkBase"} SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS( MEMCACHE_ELI_SUBCOMPONENTSLOTS ) diff --git a/src/sst/elements/memHierarchy/memoryController.cc b/src/sst/elements/memHierarchy/memoryController.cc index 6e73fd2453..7b7eada858 100644 --- a/src/sst/elements/memHierarchy/memoryController.cc +++ b/src/sst/elements/memHierarchy/memoryController.cc @@ -97,20 +97,6 @@ MemController::MemController(ComponentId_t id, Params ¶ms) : Component(id), // Check for deprecated parameters and warn/fatal // Currently deprecated - network_num_vc, statistic, direct_link bool found; - params.find("statistics", 0, found); - if (found) { - out.output("%s, **WARNING** ** Found deprecated parameter: statistics ** memHierarchy statistics have been moved to the Statistics API. Please see sst-info to view available statistics and update your input deck accordingly.\nNO statistics will be printed otherwise! Remove this parameter from your deck to eliminate this message.\n", getName().c_str()); - } - - params.find("network_num_vc", 0, found); - if (found) { - out.output("%s, ** Found deprecated parameter: network_num_vc ** MemHierarchy does not use multiple virtual channels. Remove this parameter from your input deck to eliminate this message.\n", getName().c_str()); - } - - params.find("direct_link", 0, found); - if (found) { - out.output("%s, ** Found deprecated parameter: direct_link ** The value of this parameter is now auto-detected by the link configuration in your input deck. Remove this parameter from your input deck to eliminate this message.\n", getName().c_str()); - } /* Clock Handler */ std::string clockfreq = params.find("clock"); @@ -234,19 +220,33 @@ MemController::MemController(ComponentId_t id, Params ¶ms) : Component(id), region_.interleaveSize = UnitAlgebra(ilSize).getRoundedValue(); region_.interleaveStep = UnitAlgebra(ilStep).getRoundedValue(); - link_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, clockTimeBase_); + link_ = loadUserSubComponent("highlink", ComponentInfo::SHARE_NONE, clockTimeBase_); + if (!link_) { + link_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, clockTimeBase_); + if (link_) { + out.output("%s, DEPRECATION WARNING: The 'cpulink' subcomponent slot has been renamed to 'highlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + } if (!link_ && isPortConnected("direct_link")) { Params linkParams = params.get_scoped_params("cpulink"); linkParams.insert("port", "direct_link"); linkParams.insert("latency", link_lat, false); - link_ = loadAnonymousSubComponent("memHierarchy.MemLink", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, linkParams, clockTimeBase_); + link_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, linkParams, clockTimeBase_); + out.output("%s, WARNING: To standardize port names across memHierarchy elements, the MemController's port 'direct_link' has been renamed to 'highlink'. The 'direct_link' port will be removed in SST 16.\n", getName().c_str()); + } else if (!link_ && isPortConnected("highlink")) { + Params linkParams = params.get_scoped_params("highlink"); + linkParams.insert("port", "highlink"); + linkParams.insert("latency", link_lat, false); + link_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, linkParams, clockTimeBase_); } else if (!link_) { if (!isPortConnected("network")) { - out.fatal(CALL_INFO,-1,"%s, Error: No connected port detected. Connect 'direct_link' or 'network' port.\n", getName().c_str()); + out.fatal(CALL_INFO,-1,"%s, Error: No connected port detected. Connect 'highlink' port, or if this memory is on a network, fill the 'highlink' subcomponent slot with memHierarchy.MemNIC or memHierarchy.MemNICFour.\n", getName().c_str()); } + out.output("%s, WARNING: Use of the network* ports in MemController is deprecated. Instead, fill this component's 'highlink' subcomponent slot with memHierarchy.MemNIC or memHierarchy.MemNICFour\n", getName().c_str()); + Params nicParams = params.get_scoped_params("memNIC"); nicParams.insert("group", "4", false); @@ -255,10 +255,10 @@ MemController::MemController(ComponentId_t id, Params ¶ms) : Component(id), nicParams.insert("ack.port", "network_ack"); nicParams.insert("fwd.port", "network_fwd"); nicParams.insert("data.port", "network_data"); - link_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, clockTimeBase_); + link_ = loadAnonymousSubComponent("memHierarchy.MemNICFour", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, clockTimeBase_); } else { nicParams.insert("port", "network"); - link_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, clockTimeBase_); + link_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, clockTimeBase_); } } @@ -458,6 +458,18 @@ void MemController::handleEvent(SST::Event* event) { } break; + case Command::FlushAll: + { + MemEvent * resp = ev->makeResponse(); + + if (is_debug_event(resp)) { + Debug(_L4_, "E: %-20" PRIu64 " %-20" PRIu64 " %-20s Event:Send (%s)\n", + getCurrentSimCycle(), getNextClockCycle(clockTimeBase_) - 1, getName().c_str(), resp->getVerboseString(dlevel).c_str()); + } + link_->send( resp ); + delete ev; + } + break; case Command::PutS: case Command::PutE: diff --git a/src/sst/elements/memHierarchy/memoryController.h b/src/sst/elements/memHierarchy/memoryController.h index e79b861420..49d3c3ab75 100644 --- a/src/sst/elements/memHierarchy/memoryController.h +++ b/src/sst/elements/memHierarchy/memoryController.h @@ -61,11 +61,12 @@ class MemController : public SST::Component { SST_ELI_DOCUMENT_PARAMS( MEMCONTROLLER_ELI_PARAMS ) -#define MEMCONTROLLER_ELI_PORTS {"direct_link", "Direct connection to a cache/directory controller", {"memHierarchy.MemEventBase"} },\ - {"network", "Network connection to a cache/directory controller; also request network for split networks", {"memHierarchy.MemRtrEvent"} },\ - {"network_ack", "For split networks, ack/response network connection to a cache/directory controller", {"memHierarchy.MemRtrEvent"} },\ - {"network_fwd", "For split networks, forward request network connection to a cache/directory controller", {"memHierarchy.MemRtrEvent"} },\ - {"network_data","For split networks, data network connection to a cache/directory controller", {"memHierarchy.MemRtrEvent"} },\ +#define MEMCONTROLLER_ELI_PORTS {"highlink", "Direct connection to another memHierarchy component or subcomponent. If a network port is needed, fill the 'highlink' subcomponent slot instead.", {"memHierarchy.MemEventBase"} },\ + {"direct_link", "DEPRECATED: Use 'highlink' subcomponent or port instead. Direct connection to a cache/directory controller", {"memHierarchy.MemEventBase"} },\ + {"network", "DEPRECATED: Set 'highlink' subcomponent slot to memHierarchy.MemNIC or memHierarchy.MemNICFour instead. Network connection to a cache/directory controller; also request network for split networks", {"memHierarchy.MemRtrEvent"} },\ + {"network_ack", "DEPRECATED: Set 'highlink' subcomponent slot to memHierarchy.MemNICFour instead. For split networks, ack/response network connection to a cache/directory controller", {"memHierarchy.MemRtrEvent"} },\ + {"network_fwd", "DEPRECATED: Set 'highlink' subcomponent slot to memHierarchy.MemNICFour instead. For split networks, forward request network connection to a cache/directory controller", {"memHierarchy.MemRtrEvent"} },\ + {"network_data","DEPRECATED: Set 'highlink' subcomponent slot to memHierarchy.MemNICFour instead. For split networks, data network connection to a cache/directory controller", {"memHierarchy.MemRtrEvent"} },\ {"cube_link", "DEPRECATED. Use named subcomponents and their links instead.", {"sst.Event"} } SST_ELI_DOCUMENT_PORTS( MEMCONTROLLER_ELI_PORTS ) @@ -74,7 +75,8 @@ class MemController : public SST::Component { #define MEMCONTROLLER_ELI_SUBCOMPONENTSLOTS {"backend", "Backend memory model to use for timing. Defaults to simpleMem", "SST::MemHierarchy::MemBackend"},\ {"customCmdHandler", "Optional handler for custom command types", "SST::MemHierarchy::CustomCmdMemHandler"}, \ {"listener", "Optional listeners to gather statistics, create traces, etc. Multiple listeners supported.", "SST::MemHierarchy::CacheListener"}, \ - {"cpulink", "CPU-side link manager (e.g., to caches/cpu). Defaults to MemLink.", "SST::MemHierarchy::MemLinkBase"} + {"highlink", "CPU-side port manager (e.g., link to caches/cpu). If used, do not connect the 'highlink' port and connect the subcomponent's port(s) instead. Defaults to 'memHierarchy.MemLink' if the 'highlink' port is used instead.", "SST::MemHierarchy.MemLinkBase"},\ + {"cpulink", "DEPRECATED: Renamed to 'highlink' for naming consistency. CPU-side link manager (e.g., to caches/cpu). Defaults to MemLink.", "SST::MemHierarchy::MemLinkBase"} SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS( MEMCONTROLLER_ELI_SUBCOMPONENTSLOTS ) diff --git a/src/sst/elements/memHierarchy/mshr.cc b/src/sst/elements/memHierarchy/mshr.cc index 74ec1770c5..a5db643576 100644 --- a/src/sst/elements/memHierarchy/mshr.cc +++ b/src/sst/elements/memHierarchy/mshr.cc @@ -24,20 +24,20 @@ using namespace SST::MemHierarchy; MSHR::MSHR(ComponentId_t cid, Output* debug, int maxSize, string cacheName, std::set debugAddr) : ComponentExtension(cid) { - d_ = debug; - maxSize_ = maxSize; + dbg_ = debug; + max_size_ = maxSize; size_ = 0; - prefetchCount_ = 0; - ownerName_ = cacheName; - - d2_ = new Output(); - d2_->init("", 10, 0, (Output::output_location_t)1); + prefetch_count_ = 0; + owner_name_ = cacheName; DEBUG_ADDR = debugAddr; + + flush_acks_needed_ = 0; + flush_all_in_mshr_count_ = 0; } int MSHR::getMaxSize() { - return maxSize_; + return max_size_; } int MSHR::getSize() { @@ -48,7 +48,11 @@ unsigned int MSHR::getSize(Addr addr) { if (mshr_.find(addr) == mshr_.end()) return 0; else - return mshr_.find(addr)->second.entries.size(); + return mshr_.find(addr)->second.entries_.size(); +} + +int MSHR::getFlushSize() { + return (int) flushes_.size(); } bool MSHR::exists(Addr addr) { @@ -57,37 +61,37 @@ bool MSHR::exists(Addr addr) { MSHREntry MSHR::getEntry(Addr addr, size_t index) { if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntry(0x%" PRIx64 ", %zu). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr, index); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntry(0x%" PRIx64 ", %zu). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr, index); } - if (mshr_.find(addr)->second.entries.size() <= index) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntry(0x%" PRIx64 ", %zu). Entry list size is %zu.\n", ownerName_.c_str(), addr, index, mshr_.find(addr)->second.entries.size()); + if (mshr_.find(addr)->second.entries_.size() <= index) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntry(0x%" PRIx64 ", %zu). Entry list size is %zu.\n", owner_name_.c_str(), addr, index, mshr_.find(addr)->second.entries_.size()); } - std::list::iterator it = mshr_.find(addr)->second.entries.begin(); + std::list::iterator it = mshr_.find(addr)->second.entries_.begin(); std::advance(it, index); return *it; } MSHREntry MSHR::getFront(Addr addr) { if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFront(0x%" PRIx64 "). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFront(0x%" PRIx64 "). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFront(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFront(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } - return mshr_.find(addr)->second.entries.front(); + return mshr_.find(addr)->second.entries_.front(); } void MSHR::removeEntry(Addr addr, size_t index) { if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEntry(0x%" PRIx64 ", %zu). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr, index); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEntry(0x%" PRIx64 ", %zu). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr, index); } MSHRRegister * reg = &(mshr_.find(addr)->second); - if (reg->entries.size() <= index) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEntry(0x%" PRIx64 ", %zu). Entry list is shorter than requested index.\n", ownerName_.c_str(), addr, index); + if (reg->entries_.size() <= index) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEntry(0x%" PRIx64 ", %zu). Entry list is shorter than requested index.\n", owner_name_.c_str(), addr, index); } - std::list::iterator entry = reg->entries.begin(); + std::list::iterator entry = reg->entries_.begin(); std::advance(entry, index); if (entry->getType() == MSHREntryType::Event) @@ -96,78 +100,78 @@ void MSHR::removeEntry(Addr addr, size_t index) { if (is_debug_addr(addr)) printDebug(10, "Remove", addr, (*entry).getString().c_str()); - reg->entries.erase(entry); - if (reg->entries.empty()) { + reg->entries_.erase(entry); + if (reg->entries_.empty()) { if (is_debug_addr(addr)) printDebug(10, "Erase", addr, ""); - //d_->debug(_L10_, "M: %-41" PRIu64 " %-20s Erase 0x%-16" PRIx64 " %-10d\n", - // getCurrentSimCycle(), ownerName_.c_str(), addr, size_); - //d_->debug(_L10_, " MSHR: erasing 0x%" PRIx64 " from MSHR\n", addr); + //dbg_->debug(_L10_, "M: %-41" PRIu64 " %-20s Erase 0x%-16" PRIx64 " %-10d\n", + // getCurrentSimCycle(), owner_name_.c_str(), addr, size_); + //dbg_->debug(_L10_, " MSHR: erasing 0x%" PRIx64 " from MSHR\n", addr); mshr_.erase(addr); } } void MSHR::removeFront(Addr addr) { if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeFront(0x%" PRIx64 "). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeFront(0x%" PRIx64 "). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr); } MSHRRegister * reg = &(mshr_.find(addr)->second); - if (reg->entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeFront(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (reg->entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeFront(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } // if (is_debug_addr(addr)) - // d_->debug(_L10_, " MSHR::removeFront(0x%" PRIx64 ", %s)\n", addr, reg->entries.front().getString().c_str()); + // dbg_->debug(_L10_, " MSHR::removeFront(0x%" PRIx64 ", %s)\n", addr, reg->entries_.front().getString().c_str()); if (getFrontType(addr) == MSHREntryType::Event) size_--; if (is_debug_addr(addr)) - printDebug(10, "RemFr", addr, (reg->entries.front()).getString().c_str()); + printDebug(10, "RemFr", addr, (reg->entries_.front()).getString().c_str()); - reg->entries.pop_front(); - if (reg->entries.empty()) { + reg->entries_.pop_front(); + if (reg->entries_.empty()) { if (is_debug_addr(addr)) printDebug(10, "Erase", addr, ""); - //d_->debug(_L10_, " MSHR: erasing 0x%" PRIx64 " from MSHR\n", addr); + //dbg_->debug(_L10_, " MSHR: erasing 0x%" PRIx64 " from MSHR\n", addr); mshr_.erase(addr); } } MSHREntryType MSHR::getEntryType(Addr addr, size_t index) { //if (is_debug_addr(addr)) - // d_->debug(_L20_, " MSHR::getEntryType(0x%" PRIx64 ", %zu)\n", addr, index); + // dbg_->debug(_L20_, " MSHR::getEntryType(0x%" PRIx64 ", %zu)\n", addr, index); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntryType(0x%" PRIx64 ", %zu). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr, index); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntryType(0x%" PRIx64 ", %zu). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr, index); } - if (mshr_.find(addr)->second.entries.size() <= index) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntryType(0x%" PRIx64 ", %zu). Entry list is shoerter than index.\n", ownerName_.c_str(), addr, index); + if (mshr_.find(addr)->second.entries_.size() <= index) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEntryType(0x%" PRIx64 ", %zu). Entry list is shoerter than index.\n", owner_name_.c_str(), addr, index); } - std::list::iterator it = mshr_.find(addr)->second.entries.begin(); + std::list::iterator it = mshr_.find(addr)->second.entries_.begin(); std::advance(it, index); return it->getType(); } MSHREntryType MSHR::getFrontType(Addr addr) { //if (is_debug_addr(addr)) - // d_->debug(_L20_, " MSHR::getFrontType(0x%" PRIx64 ")\n", addr); + // dbg_->debug(_L20_, " MSHR::getFrontType(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFrontType(0x%" PRIx64 "). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFrontType(0x%" PRIx64 "). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFrontType(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getFrontType(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } - return mshr_.find(addr)->second.entries.front().getType(); + return mshr_.find(addr)->second.entries_.front().getType(); } MemEventBase* MSHR::getEntryEvent(Addr addr, size_t index) { //if (is_debug_addr(addr)) - // d_->debug(_L20_, " MSHR::getEntryEvent(0x%" PRIx64 ", %zu)\n", addr, index); + // dbg_->debug(_L20_, " MSHR::getEntryEvent(0x%" PRIx64 ", %zu)\n", addr, index); - if (mshr_.find(addr) == mshr_.end() || mshr_.find(addr)->second.entries.size() <= index) + if (mshr_.find(addr) == mshr_.end() || mshr_.find(addr)->second.entries_.size() <= index) return nullptr; - std::list::iterator it = mshr_.find(addr)->second.entries.begin(); + std::list::iterator it = mshr_.find(addr)->second.entries_.begin(); std::advance(it, index); if (it->getType() != MSHREntryType::Event) return nullptr; @@ -177,38 +181,54 @@ MemEventBase* MSHR::getEntryEvent(Addr addr, size_t index) { MemEventBase* MSHR::getFrontEvent(Addr addr) { //if (is_debug_addr(addr)) - // d_->debug(_L20_, " MSHR::getFrontEvent(0x%" PRIx64 ")\n", addr); + // dbg_->debug(_L20_, " MSHR::getFrontEvent(0x%" PRIx64 ")\n", addr); if (getFrontType(addr) != MSHREntryType::Event) { return nullptr; } - return mshr_.find(addr)->second.entries.front().getEvent(); + return mshr_.find(addr)->second.entries_.front().getEvent(); } MemEventBase* MSHR::getFirstEventEntry(Addr addr, Command cmd) { // if (is_debug_addr(addr)) -// d_->debug(_L20_, " MSHR::getFirstEventEntry(0x%" PRIx64 ", %s)\n", addr, CommandString[(int)cmd]); +// dbg_->debug(_L20_, " MSHR::getFirstEventEntry(0x%" PRIx64 ", %s)\n", addr, CommandString[(int)cmd]); if (mshr_.find(addr) == mshr_.end()) return nullptr; - for (std::list::iterator it = mshr_.find(addr)->second.entries.begin(); it != mshr_.find(addr)->second.entries.end(); it++) { + for (std::list::iterator it = mshr_.find(addr)->second.entries_.begin(); it != mshr_.find(addr)->second.entries_.end(); it++) { if (it->getType() == MSHREntryType::Event && it->getEvent()->getCmd() == cmd) return it->getEvent(); } return nullptr; } +MemEventBase* MSHR::getFlush() { + if (flushes_.empty()) return nullptr; + return flushes_.front(); +} + +void MSHR::removeFlush() { + if (flushes_.empty()) + dbg_->fatal(CALL_INFO, -1, "%s, Error: removeFlush. Flush queue is empty.\n", owner_name_.c_str()); + size_--; + if (flushes_.front()->getCmd() == Command::FlushAll) + flush_all_in_mshr_count_--; + printDebug(10, "RemFlush", 0, flushes_.front()->toString().c_str()); + + flushes_.pop_front(); +} + std::list* MSHR::getEvictPointers(Addr addr) { if (getFrontType(addr) != MSHREntryType::Evict) - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEvictPointers(0x%" PRIx64 "). Entry type is not Evict.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getEvictPointers(0x%" PRIx64 "). Entry type is not Evict.\n", owner_name_.c_str(), addr); - return mshr_.find(addr)->second.entries.front().getPointers(); + return mshr_.find(addr)->second.entries_.front().getPointers(); } // Return whether we should retry a new event or not bool MSHR::removeEvictPointer(Addr addr, Addr addrPtr) { if (getFrontType(addr) == MSHREntryType::Event) - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEvictPointer(0x%" PRIx64 ", 0x%" PRIx64 "). Front entry type is not Evict or Writeback.\n", ownerName_.c_str(), addr, addrPtr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEvictPointer(0x%" PRIx64 ", 0x%" PRIx64 "). Front entry type is not Evict or Writeback.\n", owner_name_.c_str(), addr, addrPtr); if (is_debug_addr(addr) || is_debug_addr(addrPtr)) { stringstream reason; @@ -218,17 +238,17 @@ bool MSHR::removeEvictPointer(Addr addr, Addr addrPtr) { // Sometimes we insert a WB before the Evict & then remove the Evict pointer, othertimes the Evict is front if (getFrontType(addr) == MSHREntryType::Evict) { - MSHREntry * entry = &(mshr_.find(addr)->second.entries.front()); + MSHREntry * entry = &(mshr_.find(addr)->second.entries_.front()); entry->getPointers()->remove(addrPtr); if (entry->getPointers()->empty()) { removeFront(addr); return true; } } else { - std::list::iterator it = mshr_.find(addr)->second.entries.begin(); + std::list::iterator it = mshr_.find(addr)->second.entries_.begin(); it++; if (it->getType() != MSHREntryType::Evict) - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEvictPointer(0x%" PRIx64 ", 0x%" PRIx64 "). Entry type is not Evict.\n", ownerName_.c_str(), addr, addrPtr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removeEvictPointer(0x%" PRIx64 ", 0x%" PRIx64 "). Entry type is not Evict.\n", owner_name_.c_str(), addr, addrPtr); it->getPointers()->remove(addrPtr); if (it->getPointers()->empty()) { removeEntry(addr, 1); @@ -243,15 +263,15 @@ bool MSHR::pendingWriteback(Addr addr) { bool MSHR::pendingWritebackIsDowngrade(Addr addr) { if (pendingWriteback(addr)) - return mshr_.find(addr)->second.entries.front().getDowngrade(); + return mshr_.find(addr)->second.entries_.front().getDowngrade(); return false; } int MSHR::insertEvent(Addr addr, MemEventBase* event, int pos, bool fwdRequest, bool stallEvict) { - if ((size_ == maxSize_) || (!fwdRequest && (size_ == maxSize_-1))) { + if ((size_ == max_size_) || (!fwdRequest && (size_ == max_size_-1))) { if (is_debug_addr(addr)) { stringstream reason; - reason << "<" << event->getID().first << "," << event->getID().second << "> FAILED " << (fwdRequest ? "fwd, " : "") << "maxsz: " << maxSize_; + reason << "<" << event->getID().first << "," << event->getID().second << "> FAILED " << (fwdRequest ? "fwd, " : "") << "maxsz: " << max_size_; printDebug(10, "InsEv", addr, reason.str()); } return -1; @@ -262,7 +282,7 @@ int MSHR::insertEvent(Addr addr, MemEventBase* event, int pos, bool fwdRequest, if (mshr_.find(addr) == mshr_.end()) { MSHRRegister reg; - reg.entries.push_back(MSHREntry(event, stallEvict, getCurrentSimCycle())); + reg.entries_.push_back(MSHREntry(event, stallEvict, getCurrentSimCycle())); mshr_.insert(std::make_pair(addr, reg)); if (is_debug_addr(addr)) { @@ -274,18 +294,18 @@ int MSHR::insertEvent(Addr addr, MemEventBase* event, int pos, bool fwdRequest, return 0; } else { - if (pos == -1 || pos > mshr_.find(addr)->second.entries.size()) { - mshr_.find(addr)->second.entries.push_back(MSHREntry(event, stallEvict, getCurrentSimCycle())); + if (pos == -1 || pos > mshr_.find(addr)->second.entries_.size()) { + mshr_.find(addr)->second.entries_.push_back(MSHREntry(event, stallEvict, getCurrentSimCycle())); if (is_debug_addr(addr)) { stringstream reason; - reason << "<" << event->getID().first << "," << event->getID().second << ">, pos=" << (mshr_.find(addr)->second.entries.size() - 1); + reason << "<" << event->getID().first << "," << event->getID().second << ">, pos=" << (mshr_.find(addr)->second.entries_.size() - 1); printDebug(10, "InsEv", addr, reason.str()); } - return (mshr_.find(addr)->second.entries.size() - 1); + return (mshr_.find(addr)->second.entries_.size() - 1); } else { - std::list::iterator it = mshr_.find(addr)->second.entries.begin(); + std::list::iterator it = mshr_.find(addr)->second.entries_.begin(); std::advance(it, pos); - mshr_.find(addr)->second.entries.insert(it, MSHREntry(event, stallEvict, getCurrentSimCycle())); + mshr_.find(addr)->second.entries_.insert(it, MSHREntry(event, stallEvict, getCurrentSimCycle())); if (is_debug_addr(addr)) { stringstream reason; reason << "<" << event->getID().first << "," << event->getID().second << ">, pos=" << pos; @@ -307,57 +327,57 @@ int MSHR::insertEventIfConflict(Addr addr, MemEventBase* event) { if (mshr_.find(addr) == mshr_.end()) return 0; - if (size_ == maxSize_-1) { /* Assuming fwdEvent == false */ + if (size_ == max_size_-1) { /* Assuming fwdEvent == false */ if (is_debug_addr(addr)) { stringstream reason; - reason << "<" << event->getID().first << "," << event->getID().second << "> FAILED " << "maxsz: " << maxSize_; + reason << "<" << event->getID().first << "," << event->getID().second << "> FAILED " << "maxsz: " << max_size_; printDebug(10, "InsEv", addr, reason.str()); } return -1; } size_++; - mshr_.find(addr)->second.entries.push_back(MSHREntry(event, false, getCurrentSimCycle())); + mshr_.find(addr)->second.entries_.push_back(MSHREntry(event, false, getCurrentSimCycle())); if (is_debug_addr(addr)) { stringstream reason; - reason << "<" << event->getID().first << "," << event->getID().second << ">, pos=" << (mshr_.find(addr)->second.entries.size() - 1); + reason << "<" << event->getID().first << "," << event->getID().second << ">, pos=" << (mshr_.find(addr)->second.entries_.size() - 1); printDebug(10, "InsEv", addr, reason.str()); } - return (mshr_.find(addr)->second.entries.size() - 1); + return (mshr_.find(addr)->second.entries_.size() - 1); } MemEventBase* MSHR::swapFrontEvent(Addr addr, MemEventBase* event) { if (is_debug_addr(addr)) printDebug(10, "SwpEv", addr, ""); - if (mshr_.find(addr)->second.entries.empty()) + if (mshr_.find(addr)->second.entries_.empty()) return nullptr; - return mshr_.find(addr)->second.entries.front().swapEvent(event, getCurrentSimCycle()); + return mshr_.find(addr)->second.entries_.front().swapEvent(event, getCurrentSimCycle()); } void MSHR::moveEntryToFront(Addr addr, unsigned int index) { if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::moveEntryToFront(0x%" PRIx64 ", %u). Address doesn't exist in MSHR.\n", ownerName_.c_str(), addr, index); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::moveEntryToFront(0x%" PRIx64 ", %u). Address doesn't exist in MSHR.\n", owner_name_.c_str(), addr, index); } MSHRRegister * reg = &(mshr_.find(addr)->second); - if (reg->entries.size() <= index) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::moveEntryToFront(0x%" PRIx64 ", %u). Entry list is shorter than requested index.\n", ownerName_.c_str(), addr, index); + if (reg->entries_.size() <= index) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::moveEntryToFront(0x%" PRIx64 ", %u). Entry list is shorter than requested index.\n", owner_name_.c_str(), addr, index); } - std::list::iterator entry = reg->entries.begin(); + std::list::iterator entry = reg->entries_.begin(); std::advance(entry, index); MSHREntry tmpEntry = *entry; if (is_debug_addr(addr)) printDebug(10, "MvEnt", addr, entry->getString()); - reg->entries.erase(entry); - reg->entries.push_front(tmpEntry); + reg->entries_.erase(entry); + reg->entries_.push_front(tmpEntry); } bool MSHR::insertWriteback(Addr addr, bool downgrade) { // if (is_debug_addr(addr)) -// d_->debug(_L10_, " MSHR::insertWriteback(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L10_, " MSHR::insertWriteback(0x%" PRIx64 ")\n", addr); if (is_debug_addr(addr)) { stringstream reason; @@ -367,10 +387,10 @@ bool MSHR::insertWriteback(Addr addr, bool downgrade) { if (mshr_.find(addr) == mshr_.end()) { MSHRRegister reg; - reg.entries.push_back(MSHREntry(downgrade, getCurrentSimCycle())); + reg.entries_.push_back(MSHREntry(downgrade, getCurrentSimCycle())); mshr_.insert(std::make_pair(addr, reg)); } else { - mshr_.find(addr)->second.entries.push_front(MSHREntry(downgrade, getCurrentSimCycle())); + mshr_.find(addr)->second.entries_.push_front(MSHREntry(downgrade, getCurrentSimCycle())); } return true; @@ -379,7 +399,7 @@ bool MSHR::insertWriteback(Addr addr, bool downgrade) { bool MSHR::insertEviction(Addr oldAddr, Addr newAddr) { // if (is_debug_addr(oldAddr) || is_debug_addr(newAddr)) -// d_->debug(_L10_, " MSHR::insertEviction(0x%" PRIx64 ", 0x%" PRIx64 ")\n", oldAddr, newAddr); +// dbg_->debug(_L10_, " MSHR::insertEviction(0x%" PRIx64 ", 0x%" PRIx64 ")\n", oldAddr, newAddr); if (is_debug_addr(oldAddr) || is_debug_addr(newAddr)) { stringstream reason; @@ -389,10 +409,10 @@ bool MSHR::insertEviction(Addr oldAddr, Addr newAddr) { if (mshr_.find(oldAddr) == mshr_.end()) { // No MSHR entry for oldAddr MSHRRegister reg; - reg.entries.push_back(MSHREntry(newAddr, getCurrentSimCycle())); + reg.entries_.push_back(MSHREntry(newAddr, getCurrentSimCycle())); mshr_.insert(std::make_pair(oldAddr, reg)); } else { - list* entries = &(mshr_.find(oldAddr)->second.entries); + list* entries = &(mshr_.find(oldAddr)->second.entries_); if (!entries->empty() && entries->back().getType() == MSHREntryType::Evict) { // MSHR entry for oldAddr is an Evict entries->back().getPointers()->push_back(newAddr); } else { // MSHR entry for oldAddr is not an Evict (or no entry exists) @@ -402,12 +422,52 @@ bool MSHR::insertEviction(Addr oldAddr, Addr newAddr) { return true; } + +MemEventStatus MSHR::insertFlush(MemEventBase* event, bool forward_flush, bool check_ok_to_forward) { + if (size_ == max_size_-1 || (forward_flush && size_ == max_size_)) { + return MemEventStatus::Reject; // MSHR is full, cannot enqueue flush + } + size_++; + + stringstream reason; + reason << "<" << event->getID().first << "," << event->getID().second << ">, size=" << flushes_.size(); + + printDebug(10, "InsFlush", 0, reason.str()); + MemEventStatus status; + if (forward_flush) { + flushes_.push_front(event); + status = flushes_.front() == event ? MemEventStatus::OK : MemEventStatus::Stall; + } else { + flushes_.push_back(event); + flush_all_in_mshr_count_++; + if (check_ok_to_forward) { + status = flush_all_in_mshr_count_ == 1 ? MemEventStatus::OK : MemEventStatus::Stall; + } else { + status = flushes_.front() == event ? MemEventStatus::OK : MemEventStatus::Stall; + } + } + + return status; +} + +void MSHR::incrementFlushCount(int count) { + flush_acks_needed_ += count; +} + +void MSHR::decrementFlushCount() { + flush_acks_needed_--; +} + +int MSHR::getFlushCount() { + return flush_acks_needed_; +} + void MSHR::addPendingRetry(Addr addr) { if (is_debug_addr(addr)) printDebug(20, "IncRetry", addr, ""); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::addPendingRetry(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::addPendingRetry(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } mshr_.find(addr)->second.addPendingRetry(); } @@ -417,7 +477,7 @@ void MSHR::removePendingRetry(Addr addr) { printDebug(20, "DecRetry", addr, ""); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removePendingRetry(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::removePendingRetry(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } mshr_.find(addr)->second.removePendingRetry(); } @@ -432,27 +492,27 @@ uint32_t MSHR::getPendingRetries(Addr addr) { void MSHR::setInProgress(Addr addr, bool value) { // if (is_debug_addr(addr)) -// d_->debug(_L10_, " MSHR::setInProgress(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L10_, " MSHR::setInProgress(0x%" PRIx64 ")\n", addr); if (is_debug_addr(addr)) printDebug(20, "InProg", addr, ""); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setInProgress(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setInProgress(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setInProgress(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setInProgress(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } - mshr_.find(addr)->second.entries.front().setInProgress(value); + mshr_.find(addr)->second.entries_.front().setInProgress(value); } bool MSHR::getInProgress(Addr addr) { if (mshr_.find(addr) == mshr_.end()) { return false; } - if (mshr_.find(addr)->second.entries.empty()) { + if (mshr_.find(addr)->second.entries_.empty()) { return false; } - return mshr_.find(addr)->second.entries.front().getInProgress(); + return mshr_.find(addr)->second.entries_.front().getInProgress(); } void MSHR::setStalledForEvict(Addr addr, bool set) { @@ -464,22 +524,22 @@ void MSHR::setStalledForEvict(Addr addr, bool set) { } if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setStalledForEvict(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setStalledForEvict(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setStalledForEvict(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setStalledForEvict(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } - mshr_.find(addr)->second.entries.front().setStalledForEvict(set); + mshr_.find(addr)->second.entries_.front().setStalledForEvict(set); } bool MSHR::getStalledForEvict(Addr addr) { if (mshr_.find(addr) == mshr_.end()) { return false; } - if (mshr_.find(addr)->second.entries.empty()) { + if (mshr_.find(addr)->second.entries_.empty()) { return false; } - return mshr_.find(addr)->second.entries.front().getStalledForEvict(); + return mshr_.find(addr)->second.entries_.front().getStalledForEvict(); } void MSHR::setProfiled(Addr addr) { @@ -487,32 +547,32 @@ void MSHR::setProfiled(Addr addr) { printDebug(20, "Profile", addr, ""); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setProfiled(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setProfiled(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s Error: MSHR::setProfiled(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s Error: MSHR::setProfiled(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } - mshr_.find(addr)->second.entries.front().setProfiled(); + mshr_.find(addr)->second.entries_.front().setProfiled(); } bool MSHR::getProfiled(Addr addr) { // if (is_debug_addr(addr)) -// d_->debug(_L20_, " MSHR::getProfiled(0x%" PRIx64 "\n", addr); +// dbg_->debug(_L20_, " MSHR::getProfiled(0x%" PRIx64 "\n", addr); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 "). Entry list is empty.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 "). Entry list is empty.\n", owner_name_.c_str(), addr); } - return mshr_.find(addr)->second.entries.front().getProfiled(); + return mshr_.find(addr)->second.entries_.front().getProfiled(); } bool MSHR::getProfiled(Addr addr, SST::Event::id_type id) { if (mshr_.find(addr) == mshr_.end()) - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Address does not exist in MSHR.\n", ownerName_.c_str(), addr, id.first, id.second); - if (mshr_.find(addr)->second.entries.empty()) - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Entry list is empty.\n", ownerName_.c_str(), addr, id.first, id.second); - for (list::iterator jt = mshr_.find(addr)->second.entries.begin(); jt != mshr_.find(addr)->second.entries.end(); jt++) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Address does not exist in MSHR.\n", owner_name_.c_str(), addr, id.first, id.second); + if (mshr_.find(addr)->second.entries_.empty()) + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Entry list is empty.\n", owner_name_.c_str(), addr, id.first, id.second); + for (list::iterator jt = mshr_.find(addr)->second.entries_.begin(); jt != mshr_.find(addr)->second.entries_.end(); jt++) { if (jt->getType() == MSHREntryType::Event && jt->getEvent()->getID() == id) { return jt->getProfiled(); } @@ -525,12 +585,12 @@ void MSHR::setProfiled(Addr addr, SST::Event::id_type id) { printDebug(20, "Profile", addr, ""); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Address does not exist in MSHR.\n", ownerName_.c_str(), addr, id.first, id.second); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Address does not exist in MSHR.\n", owner_name_.c_str(), addr, id.first, id.second); } - if (mshr_.find(addr)->second.entries.empty()) { - d_->fatal(CALL_INFO, -1, "%s Error: MSHR::setProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Entry list is empty.\n", ownerName_.c_str(), addr, id.first, id.second); + if (mshr_.find(addr)->second.entries_.empty()) { + dbg_->fatal(CALL_INFO, -1, "%s Error: MSHR::setProfiled(0x%" PRIx64 ", (%" PRIu64 ", %" PRId32 ")). Entry list is empty.\n", owner_name_.c_str(), addr, id.first, id.second); } - for (list::iterator jt = mshr_.find(addr)->second.entries.begin(); jt != mshr_.find(addr)->second.entries.end(); jt++) { + for (list::iterator jt = mshr_.find(addr)->second.entries_.begin(); jt != mshr_.find(addr)->second.entries_.end(); jt++) { if (jt->getType() == MSHREntryType::Event && jt->getEvent()->getID() == id) { jt->setProfiled(); return; @@ -544,7 +604,7 @@ MSHREntry* MSHR::getOldestEntry() { uint64_t time; for (MSHRBlock::iterator it = mshr_.begin(); it != mshr_.end(); it++) { - for (list::iterator jt = it->second.entries.begin(); jt != it->second.entries.end(); jt++) { + for (list::iterator jt = it->second.entries_.begin(); jt != it->second.entries_.end(); jt++) { if (jt->getType() == MSHREntryType::Event) { if (!first) { entry = &(*jt); @@ -561,109 +621,109 @@ MSHREntry* MSHR::getOldestEntry() { void MSHR::incrementAcksNeeded(Addr addr) { // if (is_debug_addr(addr)) - // d_->debug(_L10_, " MSHR::incrementAcksNeeded(0x%" PRIx64 ")\n", addr); + // dbg_->debug(_L10_, " MSHR::incrementAcksNeeded(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { MSHRRegister reg; mshr_.insert(std::make_pair(addr, reg)); } - mshr_.find(addr)->second.acksNeeded++; + mshr_.find(addr)->second.acks_needed_++; if (is_debug_addr(addr)) { std::stringstream reason; - reason << mshr_.find(addr)->second.acksNeeded << " acks"; + reason << mshr_.find(addr)->second.acks_needed_ << " acks"; printDebug(10, "IncAck", addr, reason.str()); } } -/* Decrement acks needed and return if we're done waiting (acksNeeded == 0) */ +/* Decrement acks needed and return if we're done waiting (acks_needed_ == 0) */ bool MSHR::decrementAcksNeeded(Addr addr) { // if (is_debug_addr(addr)) - // d_->debug(_L10_, " MSHR::decrementAcksNeeded(0x%" PRIx64 ")\n", addr); + // dbg_->debug(_L10_, " MSHR::decrementAcksNeeded(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::decrementAcksNeeded(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::decrementAcksNeeded(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - if (mshr_.find(addr)->second.acksNeeded == 0) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::decrementAcksNeeded(0x%" PRIx64 "). AcksNeeded is already 0.\n", ownerName_.c_str(), addr); + if (mshr_.find(addr)->second.acks_needed_ == 0) { + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::decrementAcksNeeded(0x%" PRIx64 "). AcksNeeded is already 0.\n", owner_name_.c_str(), addr); } - mshr_.find(addr)->second.acksNeeded--; + mshr_.find(addr)->second.acks_needed_--; if (is_debug_addr(addr)) { std::stringstream reason; - reason << mshr_.find(addr)->second.acksNeeded << " acks"; + reason << mshr_.find(addr)->second.acks_needed_ << " acks"; printDebug(10, "DecAck", addr, reason.str()); } - return (mshr_.find(addr)->second.acksNeeded == 0); + return (mshr_.find(addr)->second.acks_needed_ == 0); } uint32_t MSHR::getAcksNeeded(Addr addr) { // if (is_debug_addr(addr)) -// d_->debug(_L20_, " MSHR::getAcksNeeded(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L20_, " MSHR::getAcksNeeded(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { return 0; } - return (mshr_.find(addr)->second.acksNeeded); + return (mshr_.find(addr)->second.acks_needed_); } void MSHR::setData(Addr addr, vector& data, bool dirty) { // if (is_debug_addr(addr)) -// d_->debug(_L10_, " MSHR::setData(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L10_, " MSHR::setData(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setData(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setData(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } if (is_debug_addr(addr)) printDebug(10, "SetData", addr, (dirty ? "Dirty" : "Clean")); - mshr_.find(addr)->second.dataBuffer = data; - mshr_.find(addr)->second.dataDirty = dirty; + mshr_.find(addr)->second.data_buffer_ = data; + mshr_.find(addr)->second.data_dirty_ = dirty; } void MSHR::clearData(Addr addr) { // if (is_debug_addr(addr)) -// d_->debug(_L10_, " MSHR::clearData(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L10_, " MSHR::clearData(0x%" PRIx64 ")\n", addr); if (is_debug_addr(addr)) printDebug(10, "ClrData", addr, ""); - mshr_.find(addr)->second.dataBuffer.clear(); - mshr_.find(addr)->second.dataDirty = false; + mshr_.find(addr)->second.data_buffer_.clear(); + mshr_.find(addr)->second.data_dirty_ = false; } vector& MSHR::getData(Addr addr) { // if (is_debug_addr(addr)) -// d_->debug(_L20_, " MSHR::getData(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L20_, " MSHR::getData(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getData(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getData(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - return mshr_.find(addr)->second.dataBuffer; + return mshr_.find(addr)->second.data_buffer_; } bool MSHR::hasData(Addr addr) { if (mshr_.find(addr) == mshr_.end()) return false; - return !(mshr_.find(addr)->second.dataBuffer.empty()); + return !(mshr_.find(addr)->second.data_buffer_.empty()); } bool MSHR::getDataDirty(Addr addr) { // if (is_debug_addr(addr)) -// d_->debug(_L20_, " MSHR::getDataDirty(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L20_, " MSHR::getDataDirty(0x%" PRIx64 ")\n", addr); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getDataDirty(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::getDataDirty(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - return mshr_.find(addr)->second.dataDirty; + return mshr_.find(addr)->second.data_dirty_; } void MSHR::setDataDirty(Addr addr, bool dirty) { // if (is_debug_addr(addr)) -// d_->debug(_L10_, " MSHR::setDataDirty(0x%" PRIx64 ")\n", addr); +// dbg_->debug(_L10_, " MSHR::setDataDirty(0x%" PRIx64 ")\n", addr); if (is_debug_addr(addr)) printDebug(20, "SetDirt", addr, (dirty ? "Dirty" : "Clean")); if (mshr_.find(addr) == mshr_.end()) { - d_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setDataDirty(0x%" PRIx64 "). Address does not exist in MSHR.\n", ownerName_.c_str(), addr); + dbg_->fatal(CALL_INFO, -1, "%s, Error: MSHR::setDataDirty(0x%" PRIx64 "). Address does not exist in MSHR.\n", owner_name_.c_str(), addr); } - mshr_.find(addr)->second.dataDirty = dirty; + mshr_.find(addr)->second.data_dirty_ = dirty; } @@ -671,30 +731,30 @@ void MSHR::setDataDirty(Addr addr, bool dirty) { void MSHR::printDebug(uint32_t lev, std::string action, Addr addr, std::string reason) { if (lev == 10) { if (reason.empty()) - d_->debug(_L10_, "M: %-20" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n", - getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_); + dbg_->debug(_L10_, "M: %-20" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n", + getCurrentSimCycle(), owner_name_.c_str(), action.c_str(), addr, size_); else - d_->debug(_L10_, "M: %-20" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n", - getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_, reason.c_str()); + dbg_->debug(_L10_, "M: %-20" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n", + getCurrentSimCycle(), owner_name_.c_str(), action.c_str(), addr, size_, reason.c_str()); } else { if (reason.empty()) - d_->debug(_L20_, "M: %-41" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n", - getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_); + dbg_->debug(_L20_, "M: %-41" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d\n", + getCurrentSimCycle(), owner_name_.c_str(), action.c_str(), addr, size_); else - d_->debug(_L20_, "M: %-41" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n", - getCurrentSimCycle(), ownerName_.c_str(), action.c_str(), addr, size_, reason.c_str()); + dbg_->debug(_L20_, "M: %-41" PRIu64 " - %-25s MSHR:%-8s 0x%-16" PRIx64 " Sz: %-6d (%s)\n", + getCurrentSimCycle(), owner_name_.c_str(), action.c_str(), addr, size_, reason.c_str()); } } // Print status. Called by cache controller on EmergencyShutdown and printStatus() void MSHR::printStatus(Output &out) { - out.output(" MSHR Status for %s. Size: %u. Prefetches: %u\b", ownerName_.c_str(), size_, prefetchCount_); + out.output(" MSHR Status for %s. Size: %u. Prefetches: %u\b", owner_name_.c_str(), size_, prefetch_count_); for (std::map::iterator it = mshr_.begin(); it != mshr_.end(); it++) { // Iterate over addresses out.output(" Entry: Addr = 0x%" PRIx64 "\n", (it->first)); - for (std::list::iterator it2 = it->second.entries.begin(); it2 != it->second.entries.end(); it2++) { // Iterate over entries for each address + for (std::list::iterator it2 = it->second.entries_.begin(); it2 != it->second.entries_.end(); it2++) { // Iterate over entries for each address out.output(" %s\n", it2->getString().c_str()); } } - out.output(" End MSHR Status for %s\n", ownerName_.c_str()); + out.output(" End MSHR Status for %s\n", owner_name_.c_str()); } diff --git a/src/sst/elements/memHierarchy/mshr.h b/src/sst/elements/memHierarchy/mshr.h index 02345c727a..76254e82f6 100644 --- a/src/sst/elements/memHierarchy/mshr.h +++ b/src/sst/elements/memHierarchy/mshr.h @@ -27,6 +27,7 @@ #include #include "sst/elements/memHierarchy/memEvent.h" +#include "sst/elements/memHierarchy/memTypes.h" #include "sst/elements/memHierarchy/util.h" namespace SST { namespace MemHierarchy { @@ -47,102 +48,102 @@ class MSHREntry { public: // Event entry MSHREntry(MemEventBase* ev, bool stallEvict, SimTime_t curr_time) { - type = MSHREntryType::Event; - evictPtrs = nullptr; - event = ev; - time = curr_time; - inProgress = false; - needEvict = stallEvict; - profiled = false; - downgrade = false; + entry_type_ = MSHREntryType::Event; + evict_ptrs_ = nullptr; + event_ = ev; + time_ = curr_time; + in_progress_ = false; + need_evict_ = stallEvict; + profiled_ = false; + downgrade_ = false; } // Writeback entry MSHREntry(bool downgr, SimTime_t curr_time) { - type = MSHREntryType::Writeback; - evictPtrs = nullptr; - event = nullptr; - time = curr_time; - inProgress = false; - needEvict = false; - profiled = false; - event = nullptr; - downgrade = downgr; + entry_type_ = MSHREntryType::Writeback; + evict_ptrs_ = nullptr; + event_ = nullptr; + time_ = curr_time; + in_progress_ = false; + need_evict_ = false; + profiled_ = false; + event_ = nullptr; + downgrade_ = downgr; } // Evict entry MSHREntry(Addr addr, SimTime_t curr_time) { - type = MSHREntryType::Evict; - event = nullptr; - evictPtrs = new std::list; - evictPtrs->push_back(addr); - time = curr_time; - inProgress = false; - needEvict = false; - profiled = false; - event = nullptr; - downgrade = false; + entry_type_ = MSHREntryType::Evict; + event_ = nullptr; + evict_ptrs_ = new std::list; + evict_ptrs_->push_back(addr); + time_ = curr_time; + in_progress_ = false; + need_evict_ = false; + profiled_ = false; + event_ = nullptr; + downgrade_ = false; } - MSHREntry(const MSHREntry& entry) { - type = entry.type; - evictPtrs = entry.evictPtrs; - event = entry.event; - time = entry.time; - inProgress = entry.inProgress; - needEvict = entry.needEvict; - profiled = entry.profiled; - downgrade = entry.downgrade; - } + MSHREntry(const MSHREntry& entry) { + entry_type_ = entry.entry_type_; + evict_ptrs_ = entry.evict_ptrs_; + event_ = entry.event_; + time_ = entry.time_; + in_progress_ = entry.in_progress_; + need_evict_ = entry.need_evict_; + profiled_ = entry.profiled_; + downgrade_ = entry.downgrade_; + } - MSHREntryType getType() { return type; } + MSHREntryType getType() { return entry_type_; } - bool getInProgress() { return inProgress; } - void setInProgress(bool value) { inProgress = value; } + bool getInProgress() { return in_progress_; } + void setInProgress(bool value) { in_progress_ = value; } - bool getStalledForEvict() { return needEvict; } - void setStalledForEvict(bool set) { needEvict = set; } + bool getStalledForEvict() { return need_evict_; } + void setStalledForEvict(bool set) { need_evict_ = set; } - void setProfiled() { profiled = true; } - bool getProfiled() { return profiled; } + void setProfiled() { profiled_ = true; } + bool getProfiled() { return profiled_; } - SimTime_t getStartTime() { return time; } + SimTime_t getStartTime() { return time_; } std::list* getPointers() { - return evictPtrs; + return evict_ptrs_; } MemEventBase * getEvent() { - return event; + return event_; } bool getDowngrade() { - return downgrade; + return downgrade_; } /* Remove event at head of queue and swap with a new one (leaving entry in place) */ MemEventBase * swapEvent(MemEventBase* newEvent, SimTime_t curr_time) { - if (type != MSHREntryType::Event) return nullptr; - time = curr_time; - MemEventBase* oldEvent = event; - event = newEvent; + if (entry_type_ != MSHREntryType::Event) return nullptr; + time_ = curr_time; + MemEventBase* oldEvent = event_; + event_ = newEvent; return oldEvent; } std::string getString() { std::ostringstream str; - str << "Time: " << std::to_string(time); + str << "Time: " << std::to_string(time_); str << " Iss: "; - inProgress ? str << "T" : str << "F"; + in_progress_ ? str << "T" : str << "F"; str << " Evi: "; - needEvict ? str << "T" : str << "F"; + need_evict_ ? str << "T" : str << "F"; str << " Stat: "; - profiled ? str << "T" : str << "F"; - if (type == MSHREntryType::Event) { - str << " Type: Event" << " (" << event->getBriefString() << ")"; - } else if (type == MSHREntryType::Evict) { + profiled_ ? str << "T" : str << "F"; + if (entry_type_ == MSHREntryType::Event) { + str << " Type: Event" << " (" << event_->getBriefString() << ")"; + } else if (entry_type_ == MSHREntryType::Evict) { str << " Type: Evict ("; - for (std::list::iterator it = evictPtrs->begin(); it != evictPtrs->end(); it++) { + for (std::list::iterator it = evict_ptrs_->begin(); it != evict_ptrs_->end(); it++) { str << " 0x" << std::hex << *it; } str << ")"; @@ -153,27 +154,27 @@ class MSHREntry { } private: - MSHREntryType type; - std::list *evictPtrs; // Specific to Evict type - MemEventBase* event; // Specific to Event type - SimTime_t time; - bool needEvict; - bool inProgress; // Whether event is currently being handled; prevents early retries - bool profiled; - bool downgrade; // Specific to Writeback type + MSHREntryType entry_type_; // Type of entry + std::list *evict_ptrs_; // Specific to Evict type - address(es) waiting for this address to be evicted from cache + MemEventBase* event_; // Specific to Event type + SimTime_t time_; // Time event was enqueued in the MSHR - used for latency stats and detecting timeout + bool need_evict_; // Whether event is stalled for an eviction + bool in_progress_; // Whether event is currently being handled; prevents early retries + bool profiled_; // Whether event has been profiled/added to stats already + bool downgrade_; // Specific to Writeback type }; struct MSHRRegister { - MSHRRegister() : acksNeeded(0), dataDirty(false), pendingRetries(0) { } - list entries; - uint32_t acksNeeded; - vector dataBuffer; - bool dataDirty; - uint32_t pendingRetries; - - uint32_t getPendingRetries() { return pendingRetries; } - void addPendingRetry() { pendingRetries++; } - void removePendingRetry() { pendingRetries--; } + MSHRRegister() : acks_needed_(0), data_dirty_(false), pending_retries_(0) { } + list entries_; + uint32_t acks_needed_; + vector data_buffer_; + bool data_dirty_; + uint32_t pending_retries_; + + uint32_t getPendingRetries() { return pending_retries_; } + void addPendingRetry() { pending_retries_++; } + void removePendingRetry() { pending_retries_--; } }; typedef map MSHRBlock; @@ -184,43 +185,83 @@ typedef map MSHRBlock; class MSHR : public ComponentExtension { public: - // used externally + /* Construct a new MSHR */ MSHR(ComponentId_t cid, Output* dbg, int maxSize, string cacheName, std::set debugAddr); - + + /* Return maxSize_ */ int getMaxSize(); + + /* Return size_ */ int getSize(); + + /* Return size of MSHR list for a particular address */ unsigned int getSize(Addr addr); + + /* Return the size of the flush queue */ + int getFlushSize(); + + /* Return whether an address exists in the MSHR (i.e., current outstanding events for that address) */ bool exists(Addr addr); - // Accessors for first event since that's most common +// Functions to manage the head entry in an address's list. + /* Accessor for first entry in the list for a particular address since that's most common */ MSHREntry getFront(Addr addr); + + /* Remove first entry in the list for a particular address */ void removeFront(Addr addr); + /* Return what type the first entry in the list for a particular address is */ MSHREntryType getFrontType(Addr addr); + /* Return the event at the front of the list for an address IF it is an event */ MemEventBase* getFrontEvent(Addr addr); + + /* Return the list of addresses which have events waiting for 'addr' to be evicted */ std::list* getEvictPointers(Addr addr); + + /* Remove the eviction pointer from ptrAddr to addr */ bool removeEvictPointer(Addr addr, Addr ptrAddr); - // Special move accessor +// Functions to manage entries other than the head of the list for an address + /* Sometimes need to rearrange MSHR entries to handle races. + * Move the entry at index 'index' for 'addr' to the front of the list. + */ void moveEntryToFront(Addr addr, unsigned int index); - // Generic accessors + /* Get the entry at index 'index' in 'addr's list. */ MSHREntry getEntry(Addr addr, size_t index); + + /* Remove the entry at index 'index' in 'addr's list. */ void removeEntry(Addr addr, size_t index); + /* Return the type of the entry at index 'index' in address 'addr's list */ MSHREntryType getEntryType(Addr addr, size_t index); + + /* Return the event mapping to entry at index 'index' in address 'addr's list IF it is an event */ MemEventBase* getEntryEvent(Addr addr, size_t index); + /* Swap the event at the head of 'addr's list for 'event' and return the original one */ MemEventBase* swapFrontEvent(Addr addr, MemEventBase* event); + /* Return whether the entry at the head of 'addr's list is a writeback (including downgrade) */ bool pendingWriteback(Addr addr); + + /* Return whether the entry at the head of 'addr's list is a downgrade */ bool pendingWritebackIsDowngrade(Addr addr); +// Functions to manage Flush list + MemEventBase* getFlush(); + void removeFlush(); + void incrementFlushCount(int count = 1); + void decrementFlushCount(); + int getFlushCount(); + +// Functions to manage events and retries int insertEvent(Addr addr, MemEventBase* event, int position, bool fwdRequest, bool stallEvict); int insertEventIfConflict(Addr addr, MemEventBase* event); bool insertWriteback(Addr addr, bool downgrade); bool insertEviction(Addr evictAddr, Addr newAddr); + MemEventStatus insertFlush(MemEventBase* event, bool forward, bool check_ok_to_forward = false); void setInProgress(Addr addr, bool value = true); bool getInProgress(Addr addr); @@ -245,27 +286,31 @@ class MSHR : public ComponentExtension { bool decrementAcksNeeded(Addr addr); uint32_t getAcksNeeded(Addr addr); +// Functions to manage temporary data storage for an address void setData(Addr addr, vector& data, bool dirty = false); void clearData(Addr addr); vector& getData(Addr addr); bool hasData(Addr addr); bool getDataDirty(Addr addr); void setDataDirty(Addr addr, bool dirty); - + + /* Print contents of MSHR to out*/ void printStatus(Output &out); private: void printDebug(uint32_t level, std::string action, Addr addr, std::string reason); - MSHRBlock mshr_; - Output* d_; - Output* d2_; - int size_; - int maxSize_; - int prefetchCount_; - string ownerName_; - std::set DEBUG_ADDR; + MSHRBlock mshr_; // MSHR maps each address to a list of events/evictions/etc + std::list flushes_; // Flushes are not linked to a particular address so are stored outside the mshr_ structure + int flush_all_in_mshr_count_; // Number of FlushAll (vs ForwardFlush) in the flushes_ list + int flush_acks_needed_; // Number of things that need to complete before flush can retry + Output* dbg_; // Debug output acquired from owning component + int size_; // Current entries in mshr_ + flushes_ + int max_size_; // Size limit for mshr_ + flushes_ + int prefetch_count_; // Number of prefetches in mshr_ + string owner_name_; // Name of owning component + std::set DEBUG_ADDR; // Which addresses to print debug info for (empty = all) }; }} #endif diff --git a/src/sst/elements/memHierarchy/replacementManager.h b/src/sst/elements/memHierarchy/replacementManager.h index 7e2f16e9de..02ff73a7da 100644 --- a/src/sst/elements/memHierarchy/replacementManager.h +++ b/src/sst/elements/memHierarchy/replacementManager.h @@ -42,6 +42,7 @@ class ReplacementInfo { State getState() { return state; } void setState(State s) { state = s; } + virtual void reset() { state = I; } protected: unsigned int index; State state; @@ -56,6 +57,11 @@ class CoherenceReplacementInfo : public ReplacementInfo { bool getShared() { return shared; } void setOwned(bool o) { owned = o; } void setShared(bool s) { shared = s; } + void reset() override { + ReplacementInfo::reset(); + owned = false; + shared = false; + } protected: bool owned; bool shared; diff --git a/src/sst/elements/memHierarchy/scratchpad.cc b/src/sst/elements/memHierarchy/scratchpad.cc index 493a2a617e..f343d433e9 100644 --- a/src/sst/elements/memHierarchy/scratchpad.cc +++ b/src/sst/elements/memHierarchy/scratchpad.cc @@ -201,11 +201,33 @@ Scratchpad::Scratchpad(ComponentId_t id, Params ¶ms) : Component(id) { // Options: cpu and network; or cpu and memory; // cpu is a MoveEvent interface, memory & network are MemEvent interfaces (memory is a direct connect while network uses SimpleNetwork) - linkUp_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, tc); + linkUp_ = loadUserSubComponent("highlink", ComponentInfo::SHARE_NONE, tc); + if (!linkUp_) { + linkUp_ = loadUserSubComponent("cpulink", ComponentInfo::SHARE_NONE, tc); + if (linkUp_) { + out.output("%s, DEPRECATION WARNING: The 'cpulink' subcomponent slot has been renamed to 'highlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + if (!linkUp_ && isPortConnected("highlink")) { + Params p; + p.insert("port", "highlink"); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, p, tc); + } + } if (linkUp_) linkUp_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingCPUEvent)); - linkDown_ = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, tc); + linkDown_ = loadUserSubComponent("lowlink", ComponentInfo::SHARE_NONE, tc); + if (!linkDown_) { + linkDown_ = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, tc); + if (linkDown_) { + out.output("%s, DEPRECATION WARNING: The 'memlink' subcomponent slot has been renamed to 'lowlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + if (!linkDown_ && isPortConnected("lowlink")) { + Params p; + p.insert("port", "lowlink"); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, p, tc); + } + } if (linkDown_) linkDown_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingRemoteEvent)); @@ -218,32 +240,37 @@ Scratchpad::Scratchpad(ComponentId_t id, Params ¶ms) : Component(id) { } if (!linkUp_) { + bool highlink = isPortConnected("highlink"); + bool lowlink = isPortConnected("lowlink"); bool memoryDirect = isPortConnected("memory"); bool scratchNetwork = isPortConnected("network"); bool cpuDirect = isPortConnected("cpu"); - if (!cpuDirect && !scratchNetwork) { - out.fatal(CALL_INFO, -1, "Invalid port configuration (%s): Did not detect port for cpu-side events. Connect either 'cpu' or 'network'\n", getName().c_str()); - } else if (!memoryDirect && !scratchNetwork) { - out.fatal(CALL_INFO, -1, "Invalid port configuration (%s): Did not detect port for memory-side events. Connect either 'memory' or 'network'\n", getName().c_str()); - } else if (cpuDirect && scratchNetwork && memoryDirect) { - out.fatal(CALL_INFO, -1, "Invalid port configuration (%s): Too many connected ports. Connect either 'cpu' or 'network' for cpu-side events and either 'memory' or 'network' for memory-side events\n", + if (!cpuDirect && !scratchNetwork && !highlink) { + out.fatal(CALL_INFO, -1, "Invalid port configuration (%s): Did not detect port for cpu-side events. Connect either the highlink port or fill the highlink subcomponent slot\n", getName().c_str()); + } else if (!memoryDirect && !scratchNetwork && !lowlink) { + out.fatal(CALL_INFO, -1, "Invalid port configuration (%s): Did not detect port for memory-side events. Connect either the lowlink port or fill the lowlink subcomponent slot\n", getName().c_str()); + } else if ((cpuDirect || highlink) && scratchNetwork && (memoryDirect || lowlink) ) { + out.fatal(CALL_INFO, -1, "Invalid port configuration (%s): Too many connected ports. Connect either the lowlink/highlink ports or fill the lowlink/highlink subcomponent slots\n", getName().c_str()); } if (cpuDirect) { Params cpulink = params.get_scoped_params("cpulink"); cpulink.insert("port", "cpu"); - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, cpulink, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemLink", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, cpulink, tc); linkUp_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingCPUEvent)); + out.output("%s, DEPRECATION WARNING: The scratchpad's 'cpu' port has been renamed to 'highlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); } if (memoryDirect) { Params memlink = params.get_scoped_params("memlink"); memlink.insert("port", "memory"); - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "memlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, memlink, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, memlink, tc); linkDown_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingRemoteEvent)); + out.output("%s, DEPRECATION WARNING: The scratchpad's 'memory' port has been renamed to 'lowlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); } if (scratchNetwork) { + out.output("%s, DEPRECATION WARNING: Use of the scratchpad's 'network' port is deprecated. Instead, fill the 'highlink' and/or 'lowlink' subcomponent slots with 'memHierarchy.MemNIC' and connect the MemNIC's port to the network.\n", getName().c_str()); // Fix up parameters for nic params & warn that we're doing it if (fixupParam(params, "network_bw", "memNIC.network_bw")) out.output(CALL_INFO, "Note (%s): Changed 'network_bw' to 'memNIC.network_bw' in params. Change your input file to remove this notice.\n", getName().c_str()); @@ -264,14 +291,14 @@ Scratchpad::Scratchpad(ComponentId_t id, Params ¶ms) : Component(id) { nicParams.insert("group", "3", false); // 3 is the default for anything that talks to memory but this can be set by user too so don't overwrite if (!memoryDirect) { /* Connect mem side to network */ - linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "memlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, tc); + linkDown_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, tc); linkDown_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingRemoteEvent)); if (!cpuDirect) { linkUp_ = linkDown_; /* Connect cpu side to same network */ linkDown_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingNetworkEvent)); } } else { - linkUp_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "cpulink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, tc); + linkUp_ = loadAnonymousSubComponent("memHierarchy.MemNIC", "highlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, nicParams, tc); linkUp_->setRecvHandler(new Event::Handler(this, &Scratchpad::processIncomingCPUEvent)); } } diff --git a/src/sst/elements/memHierarchy/scratchpad.h b/src/sst/elements/memHierarchy/scratchpad.h index 472f49591a..85967e9d84 100644 --- a/src/sst/elements/memHierarchy/scratchpad.h +++ b/src/sst/elements/memHierarchy/scratchpad.h @@ -55,9 +55,11 @@ class Scratchpad : public SST::Component { {"debug_level", "(uint) Debug verbosity level. Between 0 and 10", "0"} ) SST_ELI_DOCUMENT_PORTS( - {"cpu", "Link to cpu/cache on the cpu side", {"memHierarchy.MemEventBase"}}, - {"memory", "Direct link to a memory or bus", {"memHierarchy.MemEventBase"}}, - {"network", "Network link to memory", {"memHierarchy.MemRtrEvent"}} ) + {"highlink", "Link to a processor/cache/etc. on the upper/towards-processor side", {"memHierarchy.MemEventBase"}}, + {"lowlink", "Link to a cache/memoryetc. on the lower/towards-memory side", {"memHierarchy.MemEventBase"}}, + {"cpu", "DEPRECATED: Use 'highlink' instead. Link to cpu/cache on the cpu side", {"memHierarchy.MemEventBase"}}, + {"memory", "DEPRECATED: Use 'lowlink' instead. Direct link to a memory or bus", {"memHierarchy.MemEventBase"}}, + {"network", "DEPRECATED: Fill the 'lowlink' subcomponent slot with memHierarchy.MemNIC or memHierarchy.MemNICFour instead. Network link to memory", {"memHierarchy.MemRtrEvent"}} ) SST_ELI_DOCUMENT_STATISTICS( {"request_received_scratch_read", "Number of scratchpad reads received from CPU", "count", 1}, @@ -71,8 +73,10 @@ class Scratchpad : public SST::Component { SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS( {"backendConvertor", "Convertor to interface to memory timing model (backend)", "SST::MemHierarchy::ScratchBackendConvertor" }, - {"cpulink", "CPU-side link manager", "SST::MemHierarchy::MemLinkBase"}, - {"memlink", "Memory-side link manager", "SST::MemHierarchy::MemLinkBase"} ) + {"highlink", "Port manager on the upper/processor-side (i.e., where requests typically come from). If you use this subcomponent slot, you do not need to connect the scratchpad's highlink port. Do connect this subcomponent's ports instead. For scratchpads with a single link, use this subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"lowlink", "Port manager on the lower/memory side (i.e., where requests should be sent to). If you use this subcomponent slot, you do not need to connect the scratchpad's lowlink port. Do connect this subcomponent's ports instead. For scratchpads with a single link, use the 'highlink' subcomponent slot only.", "SST::MemHierarchy::MemLinkBase"}, + {"cpulink", "DEPRECATED: Renamed to 'highlink'. CPU-side link manager", "SST::MemHierarchy::MemLinkBase"}, + {"memlink", "DEPRECATED: Renamed to 'lowlink'. Memory-side link manager", "SST::MemHierarchy::MemLinkBase"} ) /* Begin class defintion */ Scratchpad(ComponentId_t id, Params ¶ms); diff --git a/src/sst/elements/memHierarchy/standardInterface.cc b/src/sst/elements/memHierarchy/standardInterface.cc index 7384cf19dd..87bd85bf40 100644 --- a/src/sst/elements/memHierarchy/standardInterface.cc +++ b/src/sst/elements/memHierarchy/standardInterface.cc @@ -50,16 +50,34 @@ StandardInterface::StandardInterface(SST::ComponentId_t id, Params ¶ms, Time // Handler - if nullptr then polling will be assumed recvHandler_ = handler; - link_ = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, getDefaultTimeBase()); + link_ = loadUserSubComponent("lowlink", ComponentInfo::SHARE_NONE, getDefaultTimeBase()); + if (!link_) { + link_ = loadUserSubComponent("memlink", ComponentInfo::SHARE_NONE, getDefaultTimeBase()); + if (link_) { + output.output("%s, DEPRECATION WARNING: The StandardInterface's 'memlink' subcomponent slot has been renamed to 'lowlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + } if (!link_) { // Default is a regular non-network link on port 'port' + std::string port = ""; + if (isPortConnected("lowlink")) port = "lowlink"; + else if (isPortConnected("port")) { + port = "port"; + output.output("%s, DEPRECATION WARNING: The StandardInterface's port named 'port' has been renamed to 'lowlink' to improve name standardization. Please change this in your input file.\n", getName().c_str()); + } + else port = params.find("port", ""); + + if (port == "") { + output.fatal(CALL_INFO, -1, "%s, Error: Unable to configure link. Three options: (1) Fill the 'lowlink' subcomponent slot and connect the subcomponent's port(s). (2) Connect this interface's 'lowlink' port. (3) Connect this interface's parent component's port and pass its name as a parameter to this interface.\n", getName().c_str()); + } + Params lparams; - lparams.insert("port", params.find("port", "port")); - link_ = loadAnonymousSubComponent("memHierarchy.MemLink", "link", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, lparams, getDefaultTimeBase()); + lparams.insert("port", port); + link_ = loadAnonymousSubComponent("memHierarchy.MemLink", "lowlink", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS, lparams, getDefaultTimeBase()); } if (!link_) - output.fatal(CALL_INFO, -1, "%s, Error: unable to configure link on port 'port'\n", getName().c_str()); + output.fatal(CALL_INFO, -1, "%s, Error: unable to configure link. Three options: (1) Fill the 'lowlink' subcomponent slot and connect the subcomponent's port(s). (2) Connect this interface's 'lowlink' port. (3) Connect this interface's parent component's port and pass its name as a parameter to this interface.\n", getName().c_str()); link_->setRecvHandler( new SST::Event::Handler(this, &StandardInterface::receive)); link_->setName(getName()); @@ -104,7 +122,7 @@ void StandardInterface::init(unsigned int phase) { /* Broadcast our name, type, and coherence configuration parameters on link */ MemEventInitCoherence * event = new MemEventInitCoherence(getName(), epType, false, false, 0, false); link_->sendUntimedData(event); - + /* * If we are addressable (MMIO), broadcast that info across the system * For now, treat all MMIO regions as noncacheable @@ -250,6 +268,9 @@ void StandardInterface::receive(SST::Event* ev) { case Command::FlushLineResp: deliverReq = convertResponseFlushResp(origReq, me); break; + case Command::FlushAllResp: + deliverReq = convertResponseFlushAllResp(origReq, me); + break; case Command::AckMove: deliverReq = convertResponseAckMove(origReq, me); break; @@ -424,6 +445,17 @@ SST::Event* StandardInterface::MemEventConverter::convert(StandardMem::FlushAddr return flush; } +SST::Event* StandardInterface::MemEventConverter::convert(StandardMem::FlushCache* req) { + MemEvent* flush = new MemEvent(iface->getName(), Command::FlushAll); + flush->setRqstr(iface->getName()); + flush->setThreadID(req->tid); + std::string dst = iface->link_->getDests()->begin()->name; + flush->setDst(dst); + flush->setVirtualAddress(0); /* Not routed by address, will be 0 */ + flush->setInstructionPointer(req->iPtr); + return flush; +} + Event* StandardInterface::MemEventConverter::convert(StandardMem::ReadLock* req) { Addr bAddr = (iface->lineSize_ == 0 || req->getNoncacheable()) ? req->pAddr : req->pAddr & iface->baseAddrMask_; MemEvent* read = new MemEvent(iface->getName(), req->pAddr, bAddr, Command::GetSX, req->size); @@ -611,6 +643,16 @@ StandardMem::Request* StandardInterface::convertResponseFlushResp(StandardMem::R return resp; } +StandardMem::Request* StandardInterface::convertResponseFlushAllResp(StandardMem::Request* req, MemEventBase* meb) { + MemEvent* me = static_cast(meb); + StandardMem::Request* resp = req->makeResponse(); + if (!me->success()) { + resp->setFail(); + resp->unsetSuccess(); + } + return resp; +} + StandardMem::Request* StandardInterface::convertResponseAckMove(StandardMem::Request* req, UNUSED(MemEventBase* meb)) { StandardMem::Request* resp = req->needsResponse()? req->makeResponse() : nullptr; return resp; diff --git a/src/sst/elements/memHierarchy/standardInterface.h b/src/sst/elements/memHierarchy/standardInterface.h index 8c79598cc9..94cd22471a 100644 --- a/src/sst/elements/memHierarchy/standardInterface.h +++ b/src/sst/elements/memHierarchy/standardInterface.h @@ -47,18 +47,18 @@ class MemEvent; * This subcomponent translates a standard event type (StandardMem::Request) into an internal MemHierarchy event type. * It can be loaded by components to provide an interface into the memory system. * - * - If this subcomponent is loaded anonymously, the component loading it must connect a port and pass that port name via the "port" parameter. + * - If this subcomponent is loaded anonymously, the component loading it must connect a port and pass that port name to this subcomponent via the "port" parameter. * The loading component must share that port with the subcomponent (via SHARE_PORTS flag). Anonymous loading does not support a SimpleNetwork connection. * - If this subcomponent is not loaded anonymously, the subcomponent can connect either directly to a memHierarchy component (default) or to a SimpleNetwork interface such as Merlin or Kingsley * - Ways to connect * - Options to connect directly to another memHierarchy component (pick ONE): * a. Load this subcomponent anonymously with the SHARE_PORTS flag and set the "port" parameter to a connected port owned by the parent component * b. Load this subcomponent explicitly in the input file and connect the 'port' port to either a memHierarchy component's port, - * or to a MemLink subcomponent belonging to a memHierarchy component. Do not use the "port" parameter or fill the "memlink" subcomponent slot. - * c. Load this subcomponent explicitly in the input file and fill the memlink subcomponent slot with "memHierarchy.MemLink". - * Connect the memlink subcomponent's port. Do not connect this subcomponent's port or use the "port" parameter. + * or to a MemLink subcomponent belonging to a memHierarchy component. Do not use the "port" parameter or fill the "lowlink" subcomponent slot. + * c. Load this subcomponent explicitly in the input file and fill the lowlink subcomponent slot with "memHierarchy.MemLink". + * Connect the lowlink subcomponent's port. Do not connect this subcomponent's port or use the "port" parameter. * - To connect over a network - * - Load a MemNIC (e.g., MemNIC, MemNICFour) into the "memlink" subcomponent and parameterize appropriately. Do not connect the "port" port or use the "port" parameter. + * - Load a MemNIC (e.g., MemNIC, MemNICFour) into the "lowlink" subcomponent and parameterize appropriately. Do not connect the "port" port or use the "port" parameter. * * Notes on using this interface * - The parent component MUST call init(), setup(), and finish() on this subcomponent during each of SST's respective phases. In particular, failing to call init() will lead to errors. @@ -78,14 +78,18 @@ class StandardInterface : public Interfaces::StandardMem { {"verbose", "(uint) Output verbosity for warnings/errors. 0[fatal error only], 1[warnings], 2[full state dump on fatal error]", "1"}, {"debug", "(uint) Where to send debug output. Options: 0[none], 1[stdout], 2[stderr], 3[file]", "0"}, {"debug_level", "(uint) Debugging level: 0 to 10. Must configure sst-core with '--enable-debug'. 1=info, 2-10=debug output", "0"}, - {"port", "(string) port name to use for interfacing to the memory system. This must be provided if this subcomponent is being loaded anonymously. Otherwise this should not be specified and either the 'port' port should be connected or the 'memlink' subcomponent slot should be filled"}, + {"port", "(string) port name to use for interfacing to the memory system. This must be provided if this subcomponent is being loaded anonymously. Otherwise this should not be specified and either the 'lowlink' port should be connected or the 'lowlink' subcomponent slot should be filled"}, {"noncacheable_regions", "(string) vector of (start, end) address pairs for noncacheable address ranges. Vector format should be [start0, end0, start1, end1, ...].", "[]"} ) - SST_ELI_DOCUMENT_PORTS( {"port", "Port to memory hierarchy (caches/memory/etc.). Required if subcomponent slot not filled or if 'port' parameter not provided.", {}} ) + SST_ELI_DOCUMENT_PORTS( + {"lowlink", "Port to memory hierarchy (caches/memory/etc.). Required if 'lowlink' subcomponent slot not filled or if 'lowlink' parameter not provided to this interface.", {}}, + {"port", "DEPRECATED: Renamed to 'lowlink'. Port to memory hierarchy (caches/memory/etc.). Required if subcomponent slot not filled or if 'port' parameter not provided.", {}} + ) SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS( - {"memlink", "Link manager, optional - if not filled this subcompoonent's port should be connected", "SST::MemHierarchy::MemLinkBase"}) + {"lowlink", "Port manager for link to memory system. This slot must be used if the StandardInterface links to a network (do not connect the StandardInterface's 'port' in this case). Otherwise, either this slot or the StandardInterface's 'port' port may be used to connect to the memory system.", "SST::MemHierarchy::MemLinkBase"}, + {"memlink", "DEPRECATED: Renamed to 'lowlink'. Port manager, optional - if not filled this subcomponent's port should be connected", "SST::MemHierarchy::MemLinkBase"}) /* Begin class definition */ StandardInterface(SST::ComponentId_t id, Params ¶ms, TimeConverter* time, HandlerBase* handler = NULL); @@ -139,6 +143,7 @@ class StandardInterface : public Interfaces::StandardMem { virtual SST::Event* convert(StandardMem::Write* req) override; virtual SST::Event* convert(StandardMem::WriteResp* req) override; virtual SST::Event* convert(StandardMem::FlushAddr* req) override; + virtual SST::Event* convert(StandardMem::FlushCache* req) override; virtual SST::Event* convert(StandardMem::FlushResp* req) override; virtual SST::Event* convert(StandardMem::ReadLock* req) override; virtual SST::Event* convert(StandardMem::WriteUnlock* req) override; @@ -171,6 +176,7 @@ class StandardInterface : public Interfaces::StandardMem { StandardMem::Request* convertResponseGetSResp(StandardMem::Request* req, MemEventBase* meb); StandardMem::Request* convertResponseWriteResp(StandardMem::Request* req, MemEventBase* meb); StandardMem::Request* convertResponseFlushResp(StandardMem::Request* req, MemEventBase* meb); + StandardMem::Request* convertResponseFlushAllResp(StandardMem::Request* req, MemEventBase* meb); StandardMem::Request* convertResponseAckMove(StandardMem::Request* req, MemEventBase* meb); StandardMem::Request* convertResponseCustomResp(StandardMem::Request* req, MemEventBase* meb); StandardMem::Request* convertRequestInv(MemEventBase* req); diff --git a/src/sst/elements/memHierarchy/testcpu/standardCPU.cc b/src/sst/elements/memHierarchy/testcpu/standardCPU.cc index 952af82433..52c821d55f 100644 --- a/src/sst/elements/memHierarchy/testcpu/standardCPU.cc +++ b/src/sst/elements/memHierarchy/testcpu/standardCPU.cc @@ -75,6 +75,7 @@ standardCPU::standardCPU(ComponentId_t id, Params& params) : unsigned writef = params.find("write_freq", 75); unsigned flushf = params.find("flush_freq", 0); unsigned flushinvf = params.find("flushinv_freq", 0); + unsigned flushcachef = params.find("flushcache_freq", 0); unsigned customf = params.find("custom_freq", 0); unsigned llscf = params.find("llsc_freq", 0); unsigned mmiof = params.find("mmio_freq", 0); @@ -83,17 +84,18 @@ standardCPU::standardCPU(ComponentId_t id, Params& params) : out.fatal(CALL_INFO, -1, "%s, Error: mmio_freq is > 0 but no mmio device has been specified via mmio_addr\n", getName().c_str()); } - high_mark = readf + writef + flushf + flushinvf + customf + llscf + mmiof; /* Numbers less than this and above other marks indicate read */ + high_mark = readf + writef + flushf + flushinvf + flushcachef + customf + llscf + mmiof; /* Numbers less than this and above other marks indicate read */ if (high_mark == 0) { out.fatal(CALL_INFO, -1, "%s, Error: The input doesn't indicate a frequency for any command type.\n", getName().c_str()); } write_mark = writef; /* Numbers less than this indicate write */ flush_mark = write_mark + flushf; /* Numbers less than this indicate flush */ flushinv_mark = flush_mark + flushinvf; /* Numbers less than this indicate flush-inv */ - custom_mark = flushinv_mark + customf; /* Numbers less than this indicate flush */ + flushcache_mark = flushinv_mark + flushcachef; /* Numbers less than this indicate flush-cache */ + custom_mark = flushcache_mark + customf; /* Numbers less than this indicate flush */ llsc_mark = custom_mark + llscf; /* Numbers less than this indicate LL-SC */ mmio_mark = llsc_mark + mmiof; /* Numbers less than this indicate MMIO read or write */ - + noncacheableRangeStart = params.find("noncacheableRangeStart", 0); noncacheableRangeEnd = params.find("noncacheableRangeEnd", 0); noncacheableSize = noncacheableRangeEnd - noncacheableRangeStart; @@ -133,6 +135,9 @@ standardCPU::standardCPU(ComponentId_t id, Params& params) : if (flushinvf != 0) { num_flushinvs_issued = registerStatistic("flushinvs"); } + if (flushcachef != 0) { + num_flushcache_issued = registerStatistic("flushcaches"); + } if (customf != 0) { num_custom_issued = registerStatistic("customReqs"); } @@ -161,7 +166,10 @@ void standardCPU::handleEvent(StandardMem::Request *req) { std::map>::iterator i = requests.find(req->getID()); if ( requests.end() == i ) { - out.fatal(CALL_INFO, -1, "Event (%" PRIx64 ") not found!\n", req->getID()); + out.output("%s, Error, Event (%" PRIu64 ") for request (%s) not found\n", getName().c_str(), req->getID(), req->getString().c_str()); + for (const auto& [key, value] : requests) + out.output("\t%" PRIu64 " %s, %" PRIu64 "\n", key, value.second.c_str(), value.first); + out.fatal(CALL_INFO, -1, "%s, Error: Event (%" PRIu64 ") not found!\n", getName().c_str(), req->getID()); } else { SimTime_t et = getCurrentSimTime() - i->second.first; if (i->second.second == "StoreConditional" && req->getSuccess()) @@ -210,7 +218,7 @@ bool standardCPU::clockTic( Cycle_t ) if (ll_issued) { req = createSC(); cmdString = "StoreConditional"; - }else if (instNum < write_mark) { + } else if (instNum < write_mark) { req = createWrite(addr); cmdString = "Write"; } else if (instNum < flush_mark) { @@ -219,6 +227,9 @@ bool standardCPU::clockTic( Cycle_t ) } else if (instNum < flushinv_mark) { req = createFlushInv(addr); cmdString = "FlushInv"; + } else if (instNum < flushcache_mark) { + req = createFlushCache(); + cmdString = "FlushCache"; } else if (instNum < custom_mark) { } else if (instNum < llsc_mark) { req = createLL(addr); @@ -313,6 +324,13 @@ StandardMem::Request* standardCPU::createFlushInv(Addr addr) { return req; } +StandardMem::Request* standardCPU::createFlushCache() { + StandardMem::Request* req = new Interfaces::StandardMem::FlushCache(); + num_flushcache_issued->addData(1); + out.verbose(CALL_INFO, 2, 0, "%s: %" PRIu64 " Issued FlushCache\n", getName().c_str(), ops); + return req; +} + StandardMem::Request* standardCPU::createLL(Addr addr) { // Addr needs to be a cacheable range Addr cacheableSize = maxAddr + 1 - noncacheableRangeEnd + noncacheableRangeStart; diff --git a/src/sst/elements/memHierarchy/testcpu/standardCPU.h b/src/sst/elements/memHierarchy/testcpu/standardCPU.h index 745f06465f..ed2cde88f5 100644 --- a/src/sst/elements/memHierarchy/testcpu/standardCPU.h +++ b/src/sst/elements/memHierarchy/testcpu/standardCPU.h @@ -57,6 +57,7 @@ class standardCPU : public SST::Component { {"read_freq", "(uint) Relative read frequency", "75"}, {"flush_freq", "(uint) Relative flush frequency", "0"}, {"flushinv_freq", "(uint) Relative flush-inv frequency", "0"}, + {"flushcache_freq", "(uint) Relative frequency to flush the entire cache", "0"}, {"custom_freq", "(uint) Relative custom op frequency", "0"}, {"llsc_freq", "(uint) Relative LLSC frequency", "0"}, {"mmio_addr", "(uint) Base address of the test MMIO component. 0 means not present.", "0"}, @@ -68,8 +69,9 @@ class standardCPU : public SST::Component { {"pendCycle", "Number of pending requests per cycle", "count", 1}, {"reads", "Number of reads issued (including noncacheable)", "count", 1}, {"writes", "Number of writes issued (including noncacheable)", "count", 1}, - {"flushes", "Number of flushes issued", "count", 1}, - {"flushinvs", "Number of flush-invs issued", "count", 1}, + {"flushes", "Number of line flushes issued", "count", 1}, + {"flushinvs", "Number of line flush-invs issued", "count", 1}, + {"flushcaches", "Number of cache flushes issued", "count", 1}, {"customReqs", "Number of custom requests issued", "count", 1}, {"llsc", "Number of LL-SC pairs issued", "count", 1}, {"llsc_success", "Number of successful LLSC pairs issued", "count", 1}, @@ -102,6 +104,7 @@ class standardCPU : public SST::Component { unsigned write_mark; unsigned flush_mark; unsigned flushinv_mark; + unsigned flushcache_mark; unsigned custom_mark; unsigned llsc_mark; unsigned mmio_mark; @@ -112,6 +115,7 @@ class standardCPU : public SST::Component { Statistic* num_reads_issued; Statistic* num_writes_issued; Statistic* num_flushes_issued; + Statistic* num_flushcache_issued; Statistic* num_flushinvs_issued; Statistic* num_custom_issued; Statistic* num_llsc_issued; @@ -136,6 +140,7 @@ class standardCPU : public SST::Component { Interfaces::StandardMem::Request* createRead(Addr addr); Interfaces::StandardMem::Request* createFlush(Addr addr); Interfaces::StandardMem::Request* createFlushInv(Addr addr); + Interfaces::StandardMem::Request* createFlushCache(); Interfaces::StandardMem::Request* createLL(Addr addr); Interfaces::StandardMem::Request* createSC(); Interfaces::StandardMem::Request* createMMIOWrite(); diff --git a/src/sst/elements/memHierarchy/tests/goblinCustomCmd-2.py b/src/sst/elements/memHierarchy/tests/goblinCustomCmd-2.py index 50b6436a70..95e6484f05 100644 --- a/src/sst/elements/memHierarchy/tests/goblinCustomCmd-2.py +++ b/src/sst/elements/memHierarchy/tests/goblinCustomCmd-2.py @@ -58,8 +58,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/hbm-2-trace.py b/src/sst/elements/memHierarchy/tests/hbm-2-trace.py index 381b568bb7..499391eb24 100644 --- a/src/sst/elements/memHierarchy/tests/hbm-2-trace.py +++ b/src/sst/elements/memHierarchy/tests/hbm-2-trace.py @@ -44,6 +44,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/hbm-2.py b/src/sst/elements/memHierarchy/tests/hbm-2.py index abc07f2618..f90adb7780 100644 --- a/src/sst/elements/memHierarchy/tests/hbm-2.py +++ b/src/sst/elements/memHierarchy/tests/hbm-2.py @@ -43,6 +43,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/mhlib.py b/src/sst/elements/memHierarchy/tests/mhlib.py index 37ecc27873..6304ae0764 100644 --- a/src/sst/elements/memHierarchy/tests/mhlib.py +++ b/src/sst/elements/memHierarchy/tests/mhlib.py @@ -1,3 +1,17 @@ +import sst + +### Note: This module is being used to prototype a set of python utilities +### for more easily generating and configuring simulations using memHierarchy. +### Feel free to use the utilities available here but be aware that this file +### may change without warning in the SST-Elements repository. +### +### Eventually, a python module with convenience functions for memHierarchy will be released +### and that module will be fully supported by the project (provide backwards compatibility, +### deprecation notices, stability testing). +### + + +# List of components in memH, convenient for enabling stats by component componentlist = ( "memHierarchy.BroadcastShim", "memHierarchy.Bus", @@ -55,3 +69,41 @@ "memHierarchy.timingDRAM", "memHierarchy.vaultsim" ) + +class Bus: + """ MemHierarchy Bus instance with convenience functions for connecting links """ + + def __init__(self, name, params, latency, highcomps=[], lowcomps=[]): + """name = name of bus component + params = parameters for bus component + latency = default link latency for links to the bus + highcomps = components to connect on the upper/cpu-side of the bus + lowcomps = components to connect on the lower/memory-side of the bus + """ + self.bus = sst.Component(name, "memHierarchy.Bus") + self.bus.addParams(params) + self.name = name + self.highlinks = 0 + self.lowlinks = 0 + self.latency = latency + + self.connect(highcomps, lowcomps) + + def connect(self, highcomps=[], lowcomps=[], latency=None): + if latency is None: + latency = self.latency + + for x in highcomps: + link = sst.Link("link_" + self.name + "_" + x.getFullName() + "_highlink" + str(self.highlinks)) # port_busname_compname_portnum + link.connect( (x, "lowlink", latency), (self.bus, "highlink" + str(self.highlinks), latency) ) + self.highlinks = self.highlinks + 1 + + for x in lowcomps: + link = sst.Link("link_" + self.name + "_" + x.getFullName() + "_lowlink" + str(self.lowlinks)) # port_busname_compname_portnum + link.connect( (x, "highlink", latency), (self.bus, "lowlink" + str(self.lowlinks), latency) ) + self.lowlinks = self.lowlinks + 1 + + + + + diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_hybridsim.out b/src/sst/elements/memHierarchy/tests/refFiles/test_hybridsim.out index ccd1681a8f..66356f7904 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_hybridsim.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_hybridsim.out @@ -2,4 +2,4 @@ l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to got to save state in nvdimm save file was state/nvdimm_restore.txt NVDIMM is saving the used table, dirty table and address map -Simulation is complete, simulated time: 11.8955 us +Simulation is complete, simulated time: 12.2825 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out index bb2adaaa34..e2c2ff0bc8 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendChaining.out @@ -71,13 +71,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3002; SumSQ.u64 = 3002; Count.u64 = 3002; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4876; SumSQ.u64 = 4876; Count.u64 = 4876; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4907727; SumSQ.u64 = 77843067; Count.u64 = 313669; Min.u64 = 0; Max.u64 = 16; @@ -232,13 +240,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3030; SumSQ.u64 = 3030; Count.u64 = 3030; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1970; SumSQ.u64 = 1970; Count.u64 = 1970; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 1970; SumSQ.u64 = 1970; Count.u64 = 1970; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4858; SumSQ.u64 = 4858; Count.u64 = 4858; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 828; SumSQ.u64 = 828; Count.u64 = 828; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4917461; SumSQ.u64 = 78078019; Count.u64 = 313669; Min.u64 = 0; Max.u64 = 16; @@ -432,8 +448,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6901; SumSQ.u64 = 6901; Count.u64 = 6901; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; @@ -442,6 +461,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9734; SumSQ.u64 = 9734; Count.u64 = 9734; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1677; SumSQ.u64 = 1677; Count.u64 = 1677; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9573; SumSQ.u64 = 9573; Count.u64 = 9573; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3232; SumSQ.u64 = 3232; Count.u64 = 3232; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4669; SumSQ.u64 = 4669; Count.u64 = 4669; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1675; SumSQ.u64 = 1675; Count.u64 = 1675; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 817; SumSQ.u64 = 817; Count.u64 = 817; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3090; SumSQ.u64 = 3090; Count.u64 = 3090; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1910; SumSQ.u64 = 1910; Count.u64 = 1910; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -659,6 +690,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 1910; SumSQ.u64 = 1910; Count.u64 = 1910; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4878; SumSQ.u64 = 4878; Count.u64 = 4878; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 817; SumSQ.u64 = 817; Count.u64 = 817; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4877730; SumSQ.u64 = 77428278; Count.u64 = 313669; Min.u64 = 0; Max.u64 = 16; @@ -787,13 +823,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2979; SumSQ.u64 = 2979; Count.u64 = 2979; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -801,7 +840,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.mesi.evict_I : Accumulator : Sum.u64 = 4958; SumSQ.u64 = 4958; Count.u64 = 4958; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.evict_I : Accumulator : Sum.u64 = 4960; SumSQ.u64 = 4960; Count.u64 = 4960; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.evict_S : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.evict_M : Accumulator : Sum.u64 = 1622; SumSQ.u64 = 1622; Count.u64 = 1622; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.evict_IS : Accumulator : Sum.u64 = 2410; SumSQ.u64 = 2410; Count.u64 = 2410; Min.u64 = 1; Max.u64 = 1; @@ -820,6 +859,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4887; SumSQ.u64 = 4887; Count.u64 = 4887; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4977973; SumSQ.u64 = 79095359; Count.u64 = 313669; Min.u64 = 0; Max.u64 = 16; @@ -987,8 +1031,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6828; SumSQ.u64 = 6828; Count.u64 = 6828; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; @@ -997,6 +1044,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9765; SumSQ.u64 = 9765; Count.u64 = 9765; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1682; SumSQ.u64 = 1682; Count.u64 = 1682; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9597; SumSQ.u64 = 9597; Count.u64 = 9597; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3175; SumSQ.u64 = 3175; Count.u64 = 3175; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4734; SumSQ.u64 = 4734; Count.u64 = 4734; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1680; SumSQ.u64 = 1680; Count.u64 = 1680; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 5774291; SumSQ.u64 = 108672793; Count.u64 = 313669; Min.u64 = 0; Max.u64 = 32; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 68925; SumSQ.u64 = 150223; Count.u64 = 36558; Min.u64 = 0; Max.u64 = 3; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6058368; SumSQ.u64 = 2529681408; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 24676450; SumSQ.u64 = 76656537500; Count.u64 = 12436; Min.u64 = 50; Max.u64 = 19700; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 68925; SumSQ.u64 = 150223; Count.u64 = 36558; Min.u64 = 0; Max.u64 = 3; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6058368; SumSQ.u64 = 2529681408; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 24676450; SumSQ.u64 = 76656537500; Count.u64 = 12436; Min.u64 = 50; Max.u64 = 19700; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 14869; SumSQ.u64 = 14869; Count.u64 = 14869; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; @@ -1224,8 +1280,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7263; SumSQ.u64 = 7263; Count.u64 = 7263; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19170; SumSQ.u64 = 19170; Count.u64 = 19170; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 13741; SumSQ.u64 = 13741; Count.u64 = 13741; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18791; SumSQ.u64 = 18791; Count.u64 = 18791; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 1799; SumSQ.u64 = 1799; Count.u64 = 1799; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 2539; SumSQ.u64 = 2539; Count.u64 = 2539; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 13729; SumSQ.u64 = 13729; Count.u64 = 13729; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17767; SumSQ.u64 = 17767; Count.u64 = 17767; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 11150805; SumSQ.u64 = 404009975; Count.u64 = 313669; Min.u64 = 0; Max.u64 = 64; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 71230; SumSQ.u64 = 155462; Count.u64 = 36558; Min.u64 = 0; Max.u64 = 3; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15679360; SumSQ.u64 = 8687116288; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 67197868; SumSQ.u64 = 555188876828; Count.u64 = 15869; Min.u64 = 1; Max.u64 = 43623; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 71230; SumSQ.u64 = 155462; Count.u64 = 36558; Min.u64 = 0; Max.u64 = 3; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 15679360; SumSQ.u64 = 8687116288; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 67197868; SumSQ.u64 = 555188876828; Count.u64 = 15869; Min.u64 = 1; Max.u64 = 43623; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35534; SumSQ.u64 = 71068; Count.u64 = 17767; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 7406072; SumSQ.u64 = 3653141798; Count.u64 = 18791; Min.u64 = 60; Max.u64 = 1285; @@ -1374,8 +1442,10 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18791; SumSQ.u64 = 18791; Count.u64 = 18791; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 7368490; SumSQ.u64 = 236320262; Count.u64 = 235119; Min.u64 = 0; Max.u64 = 62; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out index 671e58df05..c1faf44e1f 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDelayBuffer.out @@ -71,13 +71,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 840; SumSQ.u64 = 840; Count.u64 = 840; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2986; SumSQ.u64 = 2986; Count.u64 = 2986; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 2014; Count.u64 = 2014; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 2014; Count.u64 = 2014; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4864; SumSQ.u64 = 4864; Count.u64 = 4864; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 841; SumSQ.u64 = 841; Count.u64 = 841; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 84260385; SumSQ.u64 = 1346910969; Count.u64 = 5273042; Min.u64 = 0; Max.u64 = 16; @@ -232,13 +240,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 835; SumSQ.u64 = 835; Count.u64 = 835; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3036; SumSQ.u64 = 3036; Count.u64 = 3036; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1964; SumSQ.u64 = 1964; Count.u64 = 1964; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 1964; SumSQ.u64 = 1964; Count.u64 = 1964; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4885; SumSQ.u64 = 4885; Count.u64 = 4885; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 835; SumSQ.u64 = 835; Count.u64 = 835; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83984992; SumSQ.u64 = 1341894442; Count.u64 = 5273042; Min.u64 = 0; Max.u64 = 16; @@ -432,8 +448,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6856; SumSQ.u64 = 6856; Count.u64 = 6856; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; @@ -442,6 +461,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9749; SumSQ.u64 = 9749; Count.u64 = 9749; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1676; SumSQ.u64 = 1676; Count.u64 = 1676; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9578; SumSQ.u64 = 9578; Count.u64 = 9578; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3238; SumSQ.u64 = 3238; Count.u64 = 3238; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4670; SumSQ.u64 = 4670; Count.u64 = 4670; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1675; SumSQ.u64 = 1675; Count.u64 = 1675; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 818; SumSQ.u64 = 818; Count.u64 = 818; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3052; SumSQ.u64 = 3052; Count.u64 = 3052; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -659,6 +690,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4892; SumSQ.u64 = 4892; Count.u64 = 4892; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 818; SumSQ.u64 = 818; Count.u64 = 818; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83668498; SumSQ.u64 = 1330328906; Count.u64 = 5273042; Min.u64 = 0; Max.u64 = 16; @@ -787,13 +823,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -820,6 +859,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4878; SumSQ.u64 = 4878; Count.u64 = 4878; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83410423; SumSQ.u64 = 1332473027; Count.u64 = 5273042; Min.u64 = 0; Max.u64 = 16; @@ -987,8 +1031,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6974; SumSQ.u64 = 6974; Count.u64 = 6974; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; @@ -997,6 +1044,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9770; SumSQ.u64 = 9770; Count.u64 = 9770; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1675; SumSQ.u64 = 1675; Count.u64 = 1675; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9592; SumSQ.u64 = 9592; Count.u64 = 9592; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3220; SumSQ.u64 = 3220; Count.u64 = 3220; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4699; SumSQ.u64 = 4699; Count.u64 = 4699; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1675; SumSQ.u64 = 1675; Count.u64 = 1675; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 106323008; SumSQ.u64 = 2176100390; Count.u64 = 5273042; Min.u64 = 0; Max.u64 = 32; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 4026592; SumSQ.u64 = 442926464; Count.u64 = 36608; Min.u64 = 22; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6093824; SumSQ.u64 = 2550530048; Count.u64 = 36608; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 147500; SumSQ.u64 = 17718750000; Count.u64 = 3; Min.u64 = 2500; Max.u64 = 132500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 4026592; SumSQ.u64 = 442926464; Count.u64 = 36608; Min.u64 = 22; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6093824; SumSQ.u64 = 2550530048; Count.u64 = 36608; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 147500; SumSQ.u64 = 17718750000; Count.u64 = 3; Min.u64 = 2500; Max.u64 = 132500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 14971; SumSQ.u64 = 14971; Count.u64 = 14971; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; @@ -1224,8 +1280,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7326; SumSQ.u64 = 7326; Count.u64 = 7326; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19170; SumSQ.u64 = 19170; Count.u64 = 19170; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 13831; SumSQ.u64 = 13831; Count.u64 = 13831; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18816; SumSQ.u64 = 18816; Count.u64 = 18816; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 2502; SumSQ.u64 = 2502; Count.u64 = 2502; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 13830; SumSQ.u64 = 13830; Count.u64 = 13830; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17792; SumSQ.u64 = 17792; Count.u64 = 17792; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 211424582; SumSQ.u64 = 8550149730; Count.u64 = 5273042; Min.u64 = 0; Max.u64 = 64; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 3111620; SumSQ.u64 = 264483200; Count.u64 = 36608; Min.u64 = 75; Max.u64 = 85; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15727616; SumSQ.u64 = 8716156928; Count.u64 = 36608; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 397000; SumSQ.u64 = 64089000000; Count.u64 = 3; Min.u64 = 70000; Max.u64 = 217000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 3111620; SumSQ.u64 = 264483200; Count.u64 = 36608; Min.u64 = 75; Max.u64 = 85; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 15727616; SumSQ.u64 = 8716156928; Count.u64 = 36608; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 397000; SumSQ.u64 = 64089000000; Count.u64 = 3; Min.u64 = 70000; Max.u64 = 217000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35584; SumSQ.u64 = 71168; Count.u64 = 17792; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 3649120; SumSQ.u64 = 707726976; Count.u64 = 18816; Min.u64 = 170; Max.u64 = 194; @@ -1374,8 +1442,10 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18816; SumSQ.u64 = 18816; Count.u64 = 18816; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 3611488; SumSQ.u64 = 5647136; Count.u64 = 2636475; Min.u64 = 0; Max.u64 = 3; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDramsim3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDramsim3.out index 90b2344c10..11a8cc43b7 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDramsim3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendDramsim3.out @@ -1,7 +1,7 @@ - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 9817036; SumSQ.u64 = 1304744332; Count.u64 = 73900; Min.u64 = 79; Max.u64 = 133; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 12429056; SumSQ.u64 = 5230346240; Count.u64 = 73900; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 146000; SumSQ.u64 = 11858500000; Count.u64 = 2; Min.u64 = 48500; Max.u64 = 97500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 9817036; SumSQ.u64 = 1304744332; Count.u64 = 73900; Min.u64 = 79; Max.u64 = 133; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 12429056; SumSQ.u64 = 5230346240; Count.u64 = 73900; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 146000; SumSQ.u64 = 11858500000; Count.u64 = 2; Min.u64 = 48500; Max.u64 = 97500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 76857; SumSQ.u64 = 76857; Count.u64 = 76857; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 40287; SumSQ.u64 = 40287; Count.u64 = 40287; Min.u64 = 1; Max.u64 = 1; @@ -111,8 +111,11 @@ l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 15038; SumSQ.u64 = 15038; Count.u64 = 15038; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -121,6 +124,9 @@ l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 21611; SumSQ.u64 = 21611; Count.u64 = 21611; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 20227; SumSQ.u64 = 20227; Count.u64 = 20227; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -145,6 +151,7 @@ l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1069; SumSQ.u64 = 1069; Count.u64 = 1069; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 890; SumSQ.u64 = 890; Count.u64 = 890; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -215,10 +222,12 @@ l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 37462; SumSQ.u64 = 37462; Count.u64 = 37462; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; @@ -230,6 +239,9 @@ l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 20227; SumSQ.u64 = 20227; Count.u64 = 20227; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 17584; SumSQ.u64 = 17584; Count.u64 = 17584; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 36438; SumSQ.u64 = 36438; Count.u64 = 36438; Min.u64 = 1; Max.u64 = 1; @@ -305,13 +317,16 @@ l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1418; SumSQ.u64 = 1418; Count.u64 = 1418; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2092; SumSQ.u64 = 2092; Count.u64 = 2092; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3016; SumSQ.u64 = 3016; Count.u64 = 3016; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1984; SumSQ.u64 = 1984; Count.u64 = 1984; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -338,6 +353,7 @@ l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -384,14 +400,18 @@ l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 1984; SumSQ.u64 = 1984; Count.u64 = 1984; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2310; SumSQ.u64 = 2310; Count.u64 = 2310; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2678; SumSQ.u64 = 2678; Count.u64 = 2678; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 2093; Count.u64 = 2093; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1418; SumSQ.u64 = 1418; Count.u64 = 1418; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 169491610; SumSQ.u64 = 2709638136; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; @@ -505,8 +525,11 @@ l2cache0.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2512; SumSQ.u64 = 2512; Count.u64 = 2512; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2243; SumSQ.u64 = 2243; Count.u64 = 2243; Min.u64 = 1; Max.u64 = 1; @@ -515,6 +538,9 @@ l2cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2678; SumSQ.u64 = 2678; Count.u64 = 2678; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1418; SumSQ.u64 = 1418; Count.u64 = 1418; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -539,6 +565,7 @@ l2cache0.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -609,10 +636,12 @@ l2cache0.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2295; SumSQ.u64 = 2295; Count.u64 = 2295; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2665; SumSQ.u64 = 2665; Count.u64 = 2665; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.PutS_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.PutM_recv : Accumulator : Sum.u64 = 580; SumSQ.u64 = 580; Count.u64 = 580; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.PutE_recv : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; @@ -624,6 +653,9 @@ l2cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1418; SumSQ.u64 = 1418; Count.u64 = 1418; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.AckInv_recv : Accumulator : Sum.u64 = 2092; SumSQ.u64 = 2092; Count.u64 = 2092; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -699,13 +731,16 @@ l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2061; SumSQ.u64 = 2061; Count.u64 = 2061; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3035; SumSQ.u64 = 3035; Count.u64 = 3035; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -732,6 +767,7 @@ l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,14 +814,18 @@ l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 2291; Count.u64 = 2291; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2696; SumSQ.u64 = 2696; Count.u64 = 2696; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 2061; SumSQ.u64 = 2061; Count.u64 = 2061; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 168569235; SumSQ.u64 = 2694673919; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; @@ -899,8 +939,11 @@ l2cache1.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2209; SumSQ.u64 = 2209; Count.u64 = 2209; Min.u64 = 1; Max.u64 = 1; @@ -909,6 +952,9 @@ l2cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2696; SumSQ.u64 = 2696; Count.u64 = 2696; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -933,6 +979,7 @@ l2cache1.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1003,10 +1050,12 @@ l2cache1.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2269; SumSQ.u64 = 2269; Count.u64 = 2269; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2681; SumSQ.u64 = 2681; Count.u64 = 2681; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.PutS_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.PutM_recv : Accumulator : Sum.u64 = 569; SumSQ.u64 = 569; Count.u64 = 569; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.PutE_recv : Accumulator : Sum.u64 = 675; SumSQ.u64 = 675; Count.u64 = 675; Min.u64 = 1; Max.u64 = 1; @@ -1018,6 +1067,9 @@ l2cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.AckInv_recv : Accumulator : Sum.u64 = 2061; SumSQ.u64 = 2061; Count.u64 = 2061; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1093,13 +1145,16 @@ l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2024; SumSQ.u64 = 2024; Count.u64 = 2024; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2965; SumSQ.u64 = 2965; Count.u64 = 2965; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2035; SumSQ.u64 = 2035; Count.u64 = 2035; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1126,6 +1181,7 @@ l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1172,14 +1228,18 @@ l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2035; SumSQ.u64 = 2035; Count.u64 = 2035; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2253; SumSQ.u64 = 2253; Count.u64 = 2253; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2730; SumSQ.u64 = 2730; Count.u64 = 2730; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 2024; SumSQ.u64 = 2024; Count.u64 = 2024; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 168582036; SumSQ.u64 = 2693352794; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; @@ -1293,8 +1353,11 @@ l2cache2.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_PutS : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2561; SumSQ.u64 = 2561; Count.u64 = 2561; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2179; SumSQ.u64 = 2179; Count.u64 = 2179; Min.u64 = 1; Max.u64 = 1; @@ -1303,6 +1366,9 @@ l2cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2730; SumSQ.u64 = 2730; Count.u64 = 2730; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1327,6 +1393,7 @@ l2cache2.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1397,10 +1464,12 @@ l2cache2.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2238; SumSQ.u64 = 2238; Count.u64 = 2238; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2709; SumSQ.u64 = 2709; Count.u64 = 2709; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.PutS_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.PutM_recv : Accumulator : Sum.u64 = 581; SumSQ.u64 = 581; Count.u64 = 581; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.PutE_recv : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; @@ -1412,6 +1481,9 @@ l2cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.AckInv_recv : Accumulator : Sum.u64 = 2024; SumSQ.u64 = 2024; Count.u64 = 2024; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1487,13 +1559,16 @@ l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 2014; Count.u64 = 2014; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3002; SumSQ.u64 = 3002; Count.u64 = 3002; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1520,6 +1595,7 @@ l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1566,20 +1642,24 @@ l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2242; SumSQ.u64 = 2242; Count.u64 = 2242; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2744; SumSQ.u64 = 2744; Count.u64 = 2744; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 168339238; SumSQ.u64 = 2690557118; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; l1cache3.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.mesi.evict_I : Accumulator : Sum.u64 = 4853; SumSQ.u64 = 4853; Count.u64 = 4853; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.evict_I : Accumulator : Sum.u64 = 4854; SumSQ.u64 = 4854; Count.u64 = 4854; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.evict_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; @@ -1687,8 +1767,11 @@ l2cache3.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_PutS : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2549; SumSQ.u64 = 2549; Count.u64 = 2549; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2165; SumSQ.u64 = 2165; Count.u64 = 2165; Min.u64 = 1; Max.u64 = 1; @@ -1697,6 +1780,9 @@ l2cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2744; SumSQ.u64 = 2744; Count.u64 = 2744; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1721,6 +1807,7 @@ l2cache3.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1791,10 +1878,12 @@ l2cache3.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2214; SumSQ.u64 = 2214; Count.u64 = 2214; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2723; SumSQ.u64 = 2723; Count.u64 = 2723; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.PutS_recv : Accumulator : Sum.u64 = 271; SumSQ.u64 = 271; Count.u64 = 271; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.PutM_recv : Accumulator : Sum.u64 = 571; SumSQ.u64 = 571; Count.u64 = 571; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.PutE_recv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; @@ -1806,6 +1895,9 @@ l2cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.AckInv_recv : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 2014; Count.u64 = 2014; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1881,13 +1973,16 @@ l1cache4.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3006; SumSQ.u64 = 3006; Count.u64 = 3006; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1914,6 +2009,7 @@ l1cache4.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,20 +2056,24 @@ l1cache4.mesi.Write_recv : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2267; SumSQ.u64 = 2267; Count.u64 = 2267; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2718; SumSQ.u64 = 2718; Count.u64 = 2718; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Inv_recv : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 170014809; SumSQ.u64 = 2718876809; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; l1cache4.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.mesi.evict_I : Accumulator : Sum.u64 = 4866; SumSQ.u64 = 4866; Count.u64 = 4866; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.evict_I : Accumulator : Sum.u64 = 4868; SumSQ.u64 = 4868; Count.u64 = 4868; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.evict_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -2081,8 +2181,11 @@ l2cache4.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2494; SumSQ.u64 = 2494; Count.u64 = 2494; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2191; SumSQ.u64 = 2191; Count.u64 = 2191; Min.u64 = 1; Max.u64 = 1; @@ -2091,6 +2194,9 @@ l2cache4.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2718; SumSQ.u64 = 2718; Count.u64 = 2718; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2115,6 +2221,7 @@ l2cache4.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2185,10 +2292,12 @@ l2cache4.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2247; SumSQ.u64 = 2247; Count.u64 = 2247; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2706; SumSQ.u64 = 2706; Count.u64 = 2706; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.PutS_recv : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.PutM_recv : Accumulator : Sum.u64 = 555; SumSQ.u64 = 555; Count.u64 = 555; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.PutE_recv : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; @@ -2200,6 +2309,9 @@ l2cache4.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.AckInv_recv : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2275,13 +2387,16 @@ l1cache5.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1429; SumSQ.u64 = 1429; Count.u64 = 1429; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2034; SumSQ.u64 = 2034; Count.u64 = 2034; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3024; SumSQ.u64 = 3024; Count.u64 = 3024; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2308,6 +2423,7 @@ l1cache5.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2354,14 +2470,18 @@ l1cache5.mesi.Write_recv : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2254; SumSQ.u64 = 2254; Count.u64 = 2254; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2738; SumSQ.u64 = 2738; Count.u64 = 2738; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Inv_recv : Accumulator : Sum.u64 = 2034; SumSQ.u64 = 2034; Count.u64 = 2034; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1429; SumSQ.u64 = 1429; Count.u64 = 1429; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 170212836; SumSQ.u64 = 2722498794; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; @@ -2475,8 +2595,11 @@ l2cache5.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_PutS : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2479; SumSQ.u64 = 2479; Count.u64 = 2479; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2200; SumSQ.u64 = 2200; Count.u64 = 2200; Min.u64 = 1; Max.u64 = 1; @@ -2485,6 +2608,9 @@ l2cache5.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2738; SumSQ.u64 = 2738; Count.u64 = 2738; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1429; SumSQ.u64 = 1429; Count.u64 = 1429; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2509,6 +2635,7 @@ l2cache5.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2579,10 +2706,12 @@ l2cache5.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2244; SumSQ.u64 = 2244; Count.u64 = 2244; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2716; SumSQ.u64 = 2716; Count.u64 = 2716; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.PutS_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.PutM_recv : Accumulator : Sum.u64 = 561; SumSQ.u64 = 561; Count.u64 = 561; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.PutE_recv : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; @@ -2594,6 +2723,9 @@ l2cache5.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1429; SumSQ.u64 = 1429; Count.u64 = 1429; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.AckInv_recv : Accumulator : Sum.u64 = 2034; SumSQ.u64 = 2034; Count.u64 = 2034; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2669,13 +2801,16 @@ l1cache6.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2092; SumSQ.u64 = 2092; Count.u64 = 2092; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2983; SumSQ.u64 = 2983; Count.u64 = 2983; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2017; SumSQ.u64 = 2017; Count.u64 = 2017; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2702,6 +2837,7 @@ l1cache6.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2748,14 +2884,18 @@ l1cache6.mesi.Write_recv : Accumulator : Sum.u64 = 2017; SumSQ.u64 = 2017; Count.u64 = 2017; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2288; SumSQ.u64 = 2288; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2697; SumSQ.u64 = 2697; Count.u64 = 2697; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Inv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 169192888; SumSQ.u64 = 2704204160; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; @@ -2869,8 +3009,11 @@ l2cache6.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2532; SumSQ.u64 = 2532; Count.u64 = 2532; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2224; SumSQ.u64 = 2224; Count.u64 = 2224; Min.u64 = 1; Max.u64 = 1; @@ -2879,6 +3022,9 @@ l2cache6.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2697; SumSQ.u64 = 2697; Count.u64 = 2697; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2903,6 +3049,7 @@ l2cache6.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2973,10 +3120,12 @@ l2cache6.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2275; SumSQ.u64 = 2275; Count.u64 = 2275; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.PutS_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.PutM_recv : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.PutE_recv : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; @@ -2988,6 +3137,9 @@ l2cache6.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache6.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.AckInv_recv : Accumulator : Sum.u64 = 2092; SumSQ.u64 = 2092; Count.u64 = 2092; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3063,13 +3215,16 @@ l1cache7.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2993; SumSQ.u64 = 2993; Count.u64 = 2993; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2007; SumSQ.u64 = 2007; Count.u64 = 2007; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3096,6 +3251,7 @@ l1cache7.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3142,14 +3298,18 @@ l1cache7.mesi.Write_recv : Accumulator : Sum.u64 = 2007; SumSQ.u64 = 2007; Count.u64 = 2007; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2248; SumSQ.u64 = 2248; Count.u64 = 2248; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2738; SumSQ.u64 = 2738; Count.u64 = 2738; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Inv_recv : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 169410388; SumSQ.u64 = 2708968110; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 16; @@ -3263,8 +3423,11 @@ l2cache7.mesi.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_PutS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 2562; SumSQ.u64 = 2562; Count.u64 = 2562; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2173; SumSQ.u64 = 2173; Count.u64 = 2173; Min.u64 = 1; Max.u64 = 1; @@ -3273,6 +3436,9 @@ l2cache7.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 2738; SumSQ.u64 = 2738; Count.u64 = 2738; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3297,6 +3463,7 @@ l2cache7.mesi.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3367,10 +3534,12 @@ l2cache7.mesi.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2231; SumSQ.u64 = 2231; Count.u64 = 2231; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2729; SumSQ.u64 = 2729; Count.u64 = 2729; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.PutS_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.PutM_recv : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.PutE_recv : Accumulator : Sum.u64 = 654; SumSQ.u64 = 654; Count.u64 = 654; Min.u64 = 1; Max.u64 = 1; @@ -3382,15 +3551,18 @@ l2cache7.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.FetchResp_recv : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.FetchXResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.AckInv_recv : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 166281465; SumSQ.u64 = 2615196715; Count.u64 = 10643349; Min.u64 = 0; Max.u64 = 17; l2cache7.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 8941900; SumSQ.u64 = 1081969900; Count.u64 = 73900; Min.u64 = 121; Max.u64 = 121; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 31609600; SumSQ.u64 = 17505894400; Count.u64 = 73900; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 416665; SumSQ.u64 = 59868212225; Count.u64 = 5; Min.u64 = 7000; Max.u64 = 218000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 8941900; SumSQ.u64 = 1081969900; Count.u64 = 73900; Min.u64 = 121; Max.u64 = 121; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 31609600; SumSQ.u64 = 17505894400; Count.u64 = 73900; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 416665; SumSQ.u64 = 59868212225; Count.u64 = 5; Min.u64 = 7000; Max.u64 = 218000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 72876; SumSQ.u64 = 145752; Count.u64 = 36438; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 3381107; SumSQ.u64 = 471678835; Count.u64 = 37462; Min.u64 = 46; Max.u64 = 666; @@ -3413,8 +3585,10 @@ directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3433,6 +3607,7 @@ directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 37462; SumSQ.u64 = 37462; Count.u64 = 37462; Min.u64 = 1; Max.u64 = 1; @@ -3443,6 +3618,8 @@ directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 3306183; SumSQ.u64 = 4137289; Count.u64 = 5321029; Min.u64 = 0; Max.u64 = 8; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out index 715358d56d..151a0dd0bb 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendGoblinHMC.out @@ -68,13 +68,16 @@ l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3013; SumSQ.u64 = 3013; Count.u64 = 3013; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1987; SumSQ.u64 = 1987; Count.u64 = 1987; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -101,6 +104,7 @@ l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -138,14 +142,18 @@ l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 1987; SumSQ.u64 = 1987; Count.u64 = 1987; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 3002; SumSQ.u64 = 3002; Count.u64 = 3002; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 1985; SumSQ.u64 = 1985; Count.u64 = 1985; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 10241; SumSQ.u64 = 10241; Count.u64 = 10241; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 84441644; SumSQ.u64 = 1344909936; Count.u64 = 5309816; Min.u64 = 0; Max.u64 = 16; @@ -220,13 +228,16 @@ l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3065; SumSQ.u64 = 3065; Count.u64 = 3065; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1935; SumSQ.u64 = 1935; Count.u64 = 1935; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -253,6 +264,7 @@ l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -290,14 +302,18 @@ l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 1935; SumSQ.u64 = 1935; Count.u64 = 1935; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 3055; SumSQ.u64 = 3055; Count.u64 = 3055; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 1934; SumSQ.u64 = 1934; Count.u64 = 1934; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 10566; SumSQ.u64 = 10566; Count.u64 = 10566; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 84524670; SumSQ.u64 = 1346294216; Count.u64 = 5309816; Min.u64 = 0; Max.u64 = 16; @@ -411,8 +427,11 @@ l2cache0.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 5509; SumSQ.u64 = 5509; Count.u64 = 5509; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3570; SumSQ.u64 = 3570; Count.u64 = 3570; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; @@ -421,6 +440,9 @@ l2cache0.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3919; SumSQ.u64 = 3919; Count.u64 = 3919; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -445,6 +467,7 @@ l2cache0.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -480,10 +503,12 @@ l2cache0.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 5907; SumSQ.u64 = 5907; Count.u64 = 5907; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3877; SumSQ.u64 = 3877; Count.u64 = 3877; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5980; SumSQ.u64 = 5980; Count.u64 = 5980; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3814; SumSQ.u64 = 3814; Count.u64 = 3814; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -495,6 +520,9 @@ l2cache0.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -570,13 +598,16 @@ l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3080; SumSQ.u64 = 3080; Count.u64 = 3080; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -603,6 +634,7 @@ l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -640,14 +672,18 @@ l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 1920; SumSQ.u64 = 1920; Count.u64 = 1920; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 3069; SumSQ.u64 = 3069; Count.u64 = 3069; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 1918; SumSQ.u64 = 1918; Count.u64 = 1918; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 10372; SumSQ.u64 = 10372; Count.u64 = 10372; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 84406714; SumSQ.u64 = 1344185024; Count.u64 = 5309816; Min.u64 = 0; Max.u64 = 16; @@ -722,13 +758,16 @@ l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3052; SumSQ.u64 = 3052; Count.u64 = 3052; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -755,6 +794,7 @@ l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -792,14 +832,18 @@ l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 3039; SumSQ.u64 = 3039; Count.u64 = 3039; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 1945; SumSQ.u64 = 1945; Count.u64 = 1945; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 11009; SumSQ.u64 = 11009; Count.u64 = 11009; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 84202179; SumSQ.u64 = 1340886285; Count.u64 = 5309816; Min.u64 = 0; Max.u64 = 16; @@ -913,8 +957,11 @@ l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 5570; SumSQ.u64 = 5570; Count.u64 = 5570; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3509; SumSQ.u64 = 3509; Count.u64 = 3509; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; @@ -923,6 +970,9 @@ l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3863; SumSQ.u64 = 3863; Count.u64 = 3863; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -947,6 +997,7 @@ l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -982,10 +1033,12 @@ l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 5948; SumSQ.u64 = 5948; Count.u64 = 5948; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3815; SumSQ.u64 = 3815; Count.u64 = 3815; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 6007; SumSQ.u64 = 6007; Count.u64 = 6007; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3772; SumSQ.u64 = 3772; Count.u64 = 3772; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -997,15 +1050,18 @@ l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 163016477; SumSQ.u64 = 5017536373; Count.u64 = 5309816; Min.u64 = 0; Max.u64 = 32; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 3281163; SumSQ.u64 = 292023507; Count.u64 = 36867; Min.u64 = 89; Max.u64 = 89; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6041280; SumSQ.u64 = 2507354112; Count.u64 = 36867; Min.u64 = 64; Max.u64 = 576; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 39782500000; Count.u64 = 2; Min.u64 = 19500; Max.u64 = 198500; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 3281163; SumSQ.u64 = 292023507; Count.u64 = 36867; Min.u64 = 89; Max.u64 = 89; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6041280; SumSQ.u64 = 2507354112; Count.u64 = 36867; Min.u64 = 64; Max.u64 = 576; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 39782500000; Count.u64 = 2; Min.u64 = 19500; Max.u64 = 198500; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1115,8 +1171,11 @@ l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 10592; SumSQ.u64 = 10592; Count.u64 = 10592; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7191; SumSQ.u64 = 7191; Count.u64 = 7191; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1125,6 +1184,9 @@ l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 7692; SumSQ.u64 = 7692; Count.u64 = 7692; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1149,6 +1211,7 @@ l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1184,10 +1247,12 @@ l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 11486; SumSQ.u64 = 11486; Count.u64 = 11486; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 7598; SumSQ.u64 = 7598; Count.u64 = 7598; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 11079; SumSQ.u64 = 11079; Count.u64 = 11079; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 7079; SumSQ.u64 = 7079; Count.u64 = 7079; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1199,15 +1264,18 @@ l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17783; SumSQ.u64 = 17783; Count.u64 = 17783; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 323950925; SumSQ.u64 = 19791409211; Count.u64 = 5309816; Min.u64 = 0; Max.u64 = 62; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 3391764; SumSQ.u64 = 312042288; Count.u64 = 36867; Min.u64 = 92; Max.u64 = 92; - directory.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15670464; SumSQ.u64 = 8670031872; Count.u64 = 36867; Min.u64 = 64; Max.u64 = 576; - directory.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.idle_time : Accumulator : Sum.u64 = 357101; SumSQ.u64 = 88602544201; Count.u64 = 2; Min.u64 = 67101; Max.u64 = 290000; + directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 3391764; SumSQ.u64 = 312042288; Count.u64 = 36867; Min.u64 = 92; Max.u64 = 92; + directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 15670464; SumSQ.u64 = 8670031872; Count.u64 = 36867; Min.u64 = 64; Max.u64 = 576; + directory.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi:highlink.idle_time : Accumulator : Sum.u64 = 357101; SumSQ.u64 = 88602544201; Count.u64 = 2; Min.u64 = 67101; Max.u64 = 290000; directory.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.replacement_request_latency : Accumulator : Sum.u64 = 35566; SumSQ.u64 = 71132; Count.u64 = 17783; Min.u64 = 2; Max.u64 = 2; directory.msi.get_request_latency : Accumulator : Sum.u64 = 1034939; SumSQ.u64 = 56892283; Count.u64 = 19084; Min.u64 = 2; Max.u64 = 55; @@ -1230,8 +1298,10 @@ directory.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1250,6 +1320,7 @@ directory.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 11486; SumSQ.u64 = 11486; Count.u64 = 11486; Min.u64 = 1; Max.u64 = 1; directory.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 7598; SumSQ.u64 = 7598; Count.u64 = 7598; Min.u64 = 1; Max.u64 = 1; @@ -1260,6 +1331,8 @@ directory.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.MSHR_occupancy : Accumulator : Sum.u64 = 996771; SumSQ.u64 = 996771; Count.u64 = 2654697; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out index 607733d87a..045e45efd9 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMDramsim.out @@ -92,13 +92,16 @@ Channel 7 statistics l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3031; SumSQ.u64 = 3031; Count.u64 = 3031; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1969; SumSQ.u64 = 1969; Count.u64 = 1969; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -106,7 +109,7 @@ Channel 7 statistics l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 1422; SumSQ.u64 = 1422; Count.u64 = 1422; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 2876; SumSQ.u64 = 2876; Count.u64 = 2876; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 1820; SumSQ.u64 = 1820; Count.u64 = 1820; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 724; SumSQ.u64 = 724; Count.u64 = 724; Min.u64 = 1; Max.u64 = 1; @@ -125,6 +128,7 @@ Channel 7 statistics l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -162,14 +166,18 @@ Channel 7 statistics l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 1969; SumSQ.u64 = 1969; Count.u64 = 1969; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 2929; SumSQ.u64 = 2929; Count.u64 = 2929; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 1952; SumSQ.u64 = 1952; Count.u64 = 1952; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 237458; SumSQ.u64 = 2039730; Count.u64 = 42791; Min.u64 = 0; Max.u64 = 16; @@ -244,13 +252,16 @@ Channel 7 statistics l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3000; SumSQ.u64 = 3000; Count.u64 = 3000; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -277,6 +288,7 @@ Channel 7 statistics l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -314,20 +326,24 @@ Channel 7 statistics l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 2905; SumSQ.u64 = 2905; Count.u64 = 2905; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 1967; SumSQ.u64 = 1967; Count.u64 = 1967; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 235174; SumSQ.u64 = 2021536; Count.u64 = 42791; Min.u64 = 0; Max.u64 = 16; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.evict_I : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_I : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_S : Accumulator : Sum.u64 = 4939; SumSQ.u64 = 4939; Count.u64 = 4939; Min.u64 = 1; Max.u64 = 1; @@ -435,8 +451,11 @@ Channel 7 statistics l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 4939; SumSQ.u64 = 4939; Count.u64 = 4939; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 3246; SumSQ.u64 = 3246; Count.u64 = 3246; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 265; SumSQ.u64 = 265; Count.u64 = 265; Min.u64 = 1; Max.u64 = 1; @@ -445,6 +464,9 @@ Channel 7 statistics l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 3919; SumSQ.u64 = 3919; Count.u64 = 3919; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -469,6 +491,7 @@ Channel 7 statistics l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -504,10 +527,12 @@ Channel 7 statistics l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 5262; SumSQ.u64 = 5262; Count.u64 = 5262; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 3745; SumSQ.u64 = 3745; Count.u64 = 3745; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 5735; SumSQ.u64 = 5735; Count.u64 = 5735; Min.u64 = 1; Max.u64 = 1; l2cache0.PutM_recv : Accumulator : Sum.u64 = 3645; SumSQ.u64 = 3645; Count.u64 = 3645; Min.u64 = 1; Max.u64 = 1; l2cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -519,6 +544,9 @@ Channel 7 statistics l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -594,13 +622,16 @@ Channel 7 statistics l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2994; SumSQ.u64 = 2994; Count.u64 = 2994; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2006; SumSQ.u64 = 2006; Count.u64 = 2006; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -608,7 +639,7 @@ Channel 7 statistics l1cache2.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.msi.evict_I : Accumulator : Sum.u64 = 1374; SumSQ.u64 = 1374; Count.u64 = 1374; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.evict_I : Accumulator : Sum.u64 = 1375; SumSQ.u64 = 1375; Count.u64 = 1375; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.evict_S : Accumulator : Sum.u64 = 2881; SumSQ.u64 = 2881; Count.u64 = 2881; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.evict_M : Accumulator : Sum.u64 = 1817; SumSQ.u64 = 1817; Count.u64 = 1817; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.evict_IS : Accumulator : Sum.u64 = 691; SumSQ.u64 = 691; Count.u64 = 691; Min.u64 = 1; Max.u64 = 1; @@ -627,6 +658,7 @@ Channel 7 statistics l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -664,14 +696,18 @@ Channel 7 statistics l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 2006; SumSQ.u64 = 2006; Count.u64 = 2006; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 2906; SumSQ.u64 = 2906; Count.u64 = 2906; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 1979; SumSQ.u64 = 1979; Count.u64 = 1979; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 235772; SumSQ.u64 = 2040852; Count.u64 = 42791; Min.u64 = 0; Max.u64 = 16; @@ -746,13 +782,16 @@ Channel 7 statistics l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2987; SumSQ.u64 = 2987; Count.u64 = 2987; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2013; SumSQ.u64 = 2013; Count.u64 = 2013; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -779,6 +818,7 @@ Channel 7 statistics l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -816,14 +856,18 @@ Channel 7 statistics l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 2013; SumSQ.u64 = 2013; Count.u64 = 2013; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 2902; SumSQ.u64 = 2902; Count.u64 = 2902; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 1989; SumSQ.u64 = 1989; Count.u64 = 1989; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 235343; SumSQ.u64 = 2019431; Count.u64 = 42791; Min.u64 = 0; Max.u64 = 16; @@ -937,8 +981,11 @@ Channel 7 statistics l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 4940; SumSQ.u64 = 4940; Count.u64 = 4940; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3287; SumSQ.u64 = 3287; Count.u64 = 3287; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 272; SumSQ.u64 = 272; Count.u64 = 272; Min.u64 = 1; Max.u64 = 1; @@ -947,6 +994,9 @@ Channel 7 statistics l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3968; SumSQ.u64 = 3968; Count.u64 = 3968; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -971,6 +1021,7 @@ Channel 7 statistics l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1006,10 +1057,12 @@ Channel 7 statistics l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 5233; SumSQ.u64 = 5233; Count.u64 = 5233; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3825; SumSQ.u64 = 3825; Count.u64 = 3825; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5739; SumSQ.u64 = 5739; Count.u64 = 5739; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3653; SumSQ.u64 = 3653; Count.u64 = 3653; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,17 +1074,20 @@ Channel 7 statistics l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 332; SumSQ.u64 = 332; Count.u64 = 332; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 285807; SumSQ.u64 = 2687683; Count.u64 = 42791; Min.u64 = 0; Max.u64 = 24; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 829; Min.u64 = 0; Max.u64 = 1; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 53056; SumSQ.u64 = 3395584; Count.u64 = 829; Min.u64 = 64; Max.u64 = 64; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 1728580; SumSQ.u64 = 8689758000; Count.u64 = 938; Min.u64 = 20; Max.u64 = 38320; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 829; Min.u64 = 0; Max.u64 = 1; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 53056; SumSQ.u64 = 3395584; Count.u64 = 829; Min.u64 = 64; Max.u64 = 64; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 1728580; SumSQ.u64 = 8689758000; Count.u64 = 938; Min.u64 = 20; Max.u64 = 38320; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1139,8 +1195,11 @@ Channel 7 statistics l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1149,6 +1208,9 @@ Channel 7 statistics l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 7570; SumSQ.u64 = 7570; Count.u64 = 7570; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1173,6 +1235,7 @@ Channel 7 statistics l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 10169; SumSQ.u64 = 10169; Count.u64 = 10169; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7051; SumSQ.u64 = 7051; Count.u64 = 7051; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1208,10 +1271,12 @@ Channel 7 statistics l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 9879; SumSQ.u64 = 9879; Count.u64 = 9879; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 6533; SumSQ.u64 = 6533; Count.u64 = 6533; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1223,15 +1288,18 @@ Channel 7 statistics l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 537; SumSQ.u64 = 537; Count.u64 = 537; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 124337; SumSQ.u64 = 1893071; Count.u64 = 42791; Min.u64 = 0; Max.u64 = 39; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 420; Min.u64 = 0; Max.u64 = 1; - directory0.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 157952; SumSQ.u64 = 85606400; Count.u64 = 420; Min.u64 = 64; Max.u64 = 576; - directory0.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.msi:cpulink.idle_time : Accumulator : Sum.u64 = 20266860; SumSQ.u64 = 163477253808400; Count.u64 = 419; Min.u64 = 120; Max.u64 = 12637260; + directory0.msi:highlink.packet_latency : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 420; Min.u64 = 0; Max.u64 = 1; + directory0.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 157952; SumSQ.u64 = 85606400; Count.u64 = 420; Min.u64 = 64; Max.u64 = 576; + directory0.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.msi:highlink.idle_time : Accumulator : Sum.u64 = 20266860; SumSQ.u64 = 163477253808400; Count.u64 = 419; Min.u64 = 120; Max.u64 = 12637260; directory0.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.get_request_latency : Accumulator : Sum.u64 = 9189; SumSQ.u64 = 422319; Count.u64 = 420; Min.u64 = 2; Max.u64 = 138; @@ -1254,8 +1322,10 @@ Channel 7 statistics directory0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1274,6 +1344,7 @@ Channel 7 statistics directory0.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; directory0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; @@ -1284,13 +1355,15 @@ Channel 7 statistics directory0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 8349; SumSQ.u64 = 51699; Count.u64 = 8758; Min.u64 = 0; Max.u64 = 13; - directory1.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 409; Min.u64 = 0; Max.u64 = 1; - directory1.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 157248; SumSQ.u64 = 85561344; Count.u64 = 409; Min.u64 = 64; Max.u64 = 576; - directory1.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.msi:cpulink.idle_time : Accumulator : Sum.u64 = 20065140; SumSQ.u64 = 217108753211600; Count.u64 = 430; Min.u64 = 40; Max.u64 = 14699260; + directory1.msi:highlink.packet_latency : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 409; Min.u64 = 0; Max.u64 = 1; + directory1.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 157248; SumSQ.u64 = 85561344; Count.u64 = 409; Min.u64 = 64; Max.u64 = 576; + directory1.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.msi:highlink.idle_time : Accumulator : Sum.u64 = 20065140; SumSQ.u64 = 217108753211600; Count.u64 = 430; Min.u64 = 40; Max.u64 = 14699260; directory1.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.get_request_latency : Accumulator : Sum.u64 = 22690; SumSQ.u64 = 2430942; Count.u64 = 409; Min.u64 = 2; Max.u64 = 156; @@ -1313,8 +1386,10 @@ Channel 7 statistics directory1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1333,6 +1408,7 @@ Channel 7 statistics directory1.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; directory1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; @@ -1343,6 +1419,8 @@ Channel 7 statistics directory1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 21872; SumSQ.u64 = 348474; Count.u64 = 6696; Min.u64 = 0; Max.u64 = 25; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out index cf8c117c67..c8bd7ff14f 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendHBMPagedMulti.out @@ -96,13 +96,16 @@ Channel 7 statistics l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 858; SumSQ.u64 = 858; Count.u64 = 858; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3014; SumSQ.u64 = 3014; Count.u64 = 3014; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -129,6 +132,7 @@ Channel 7 statistics l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -175,14 +179,18 @@ Channel 7 statistics l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4879; SumSQ.u64 = 4879; Count.u64 = 4879; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 858; SumSQ.u64 = 858; Count.u64 = 858; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 84197930; SumSQ.u64 = 1345105532; Count.u64 = 5273015; Min.u64 = 0; Max.u64 = 16; @@ -257,13 +265,16 @@ Channel 7 statistics l1cache.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 869; SumSQ.u64 = 869; Count.u64 = 869; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3045; SumSQ.u64 = 3045; Count.u64 = 3045; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1955; SumSQ.u64 = 1955; Count.u64 = 1955; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -290,6 +301,7 @@ Channel 7 statistics l1cache.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -336,14 +348,18 @@ Channel 7 statistics l1cache.mesi.Write_recv : Accumulator : Sum.u64 = 1955; SumSQ.u64 = 1955; Count.u64 = 1955; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.GetSResp_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4882; SumSQ.u64 = 4882; Count.u64 = 4882; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.Inv_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.FetchInv_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83024034; SumSQ.u64 = 1325608100; Count.u64 = 5273015; Min.u64 = 0; Max.u64 = 16; @@ -457,8 +473,11 @@ Channel 7 statistics l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 859; SumSQ.u64 = 859; Count.u64 = 859; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6941; SumSQ.u64 = 6941; Count.u64 = 6941; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; @@ -467,6 +486,9 @@ Channel 7 statistics l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9761; SumSQ.u64 = 9761; Count.u64 = 9761; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1728; SumSQ.u64 = 1728; Count.u64 = 1728; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -491,6 +513,7 @@ Channel 7 statistics l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -561,10 +584,12 @@ Channel 7 statistics l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9580; SumSQ.u64 = 9580; Count.u64 = 9580; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4681; SumSQ.u64 = 4681; Count.u64 = 4681; Min.u64 = 1; Max.u64 = 1; @@ -576,6 +601,9 @@ Channel 7 statistics l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1727; SumSQ.u64 = 1727; Count.u64 = 1727; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -651,13 +679,16 @@ Channel 7 statistics l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 824; SumSQ.u64 = 824; Count.u64 = 824; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3042; SumSQ.u64 = 3042; Count.u64 = 3042; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1958; SumSQ.u64 = 1958; Count.u64 = 1958; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -684,6 +715,7 @@ Channel 7 statistics l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -730,14 +762,18 @@ Channel 7 statistics l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 1958; SumSQ.u64 = 1958; Count.u64 = 1958; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4877; SumSQ.u64 = 4877; Count.u64 = 4877; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 824; SumSQ.u64 = 824; Count.u64 = 824; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 84142078; SumSQ.u64 = 1343966444; Count.u64 = 5273015; Min.u64 = 0; Max.u64 = 16; @@ -812,13 +848,16 @@ Channel 7 statistics l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 840; SumSQ.u64 = 840; Count.u64 = 840; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2980; SumSQ.u64 = 2980; Count.u64 = 2980; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2020; SumSQ.u64 = 2020; Count.u64 = 2020; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -845,6 +884,7 @@ Channel 7 statistics l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -891,20 +931,24 @@ Channel 7 statistics l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2020; SumSQ.u64 = 2020; Count.u64 = 2020; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4888; SumSQ.u64 = 4888; Count.u64 = 4888; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 841; SumSQ.u64 = 841; Count.u64 = 841; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83754177; SumSQ.u64 = 1337453831; Count.u64 = 5273015; Min.u64 = 0; Max.u64 = 16; l1cache3.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.mesi.inclus.evict_I : Accumulator : Sum.u64 = 7479; SumSQ.u64 = 7479; Count.u64 = 7479; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.evict_I : Accumulator : Sum.u64 = 7480; SumSQ.u64 = 7480; Count.u64 = 7480; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.evict_S : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; @@ -1012,8 +1056,11 @@ Channel 7 statistics l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6882; SumSQ.u64 = 6882; Count.u64 = 6882; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; @@ -1022,6 +1069,9 @@ Channel 7 statistics l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9765; SumSQ.u64 = 9765; Count.u64 = 9765; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1665; SumSQ.u64 = 1665; Count.u64 = 1665; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1046,6 +1096,7 @@ Channel 7 statistics l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1116,10 +1167,12 @@ Channel 7 statistics l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9583; SumSQ.u64 = 9583; Count.u64 = 9583; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3227; SumSQ.u64 = 3227; Count.u64 = 3227; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4710; SumSQ.u64 = 4710; Count.u64 = 4710; Min.u64 = 1; Max.u64 = 1; @@ -1131,15 +1184,18 @@ Channel 7 statistics l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1664; SumSQ.u64 = 1664; Count.u64 = 1664; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 105413868; SumSQ.u64 = 2134315836; Count.u64 = 5273015; Min.u64 = 0; Max.u64 = 32; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 4538392; SumSQ.u64 = 562635808; Count.u64 = 36610; Min.u64 = 100; Max.u64 = 124; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6097024; SumSQ.u64 = 2552504320; Count.u64 = 36610; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 166000; SumSQ.u64 = 11921500000; Count.u64 = 3; Min.u64 = 21000; Max.u64 = 94500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 4538392; SumSQ.u64 = 562635808; Count.u64 = 36610; Min.u64 = 100; Max.u64 = 124; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6097024; SumSQ.u64 = 2552504320; Count.u64 = 36610; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 166000; SumSQ.u64 = 11921500000; Count.u64 = 3; Min.u64 = 21000; Max.u64 = 94500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 14959; SumSQ.u64 = 14959; Count.u64 = 14959; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; @@ -1249,8 +1305,11 @@ Channel 7 statistics l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7332; SumSQ.u64 = 7332; Count.u64 = 7332; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1259,6 +1318,9 @@ Channel 7 statistics l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19163; SumSQ.u64 = 19163; Count.u64 = 19163; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 13824; SumSQ.u64 = 13824; Count.u64 = 13824; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1283,6 +1345,7 @@ Channel 7 statistics l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1353,10 +1416,12 @@ Channel 7 statistics l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18817; SumSQ.u64 = 18817; Count.u64 = 18817; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 1752; SumSQ.u64 = 1752; Count.u64 = 1752; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 2498; SumSQ.u64 = 2498; Count.u64 = 2498; Min.u64 = 1; Max.u64 = 1; @@ -1368,15 +1433,18 @@ Channel 7 statistics l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 13823; SumSQ.u64 = 13823; Count.u64 = 13823; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17793; SumSQ.u64 = 17793; Count.u64 = 17793; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 211089549; SumSQ.u64 = 8524536547; Count.u64 = 5273015; Min.u64 = 0; Max.u64 = 64; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 4502970; SumSQ.u64 = 553859730; Count.u64 = 36610; Min.u64 = 93; Max.u64 = 123; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15731328; SumSQ.u64 = 8718458880; Count.u64 = 36610; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 307500; SumSQ.u64 = 51779250000; Count.u64 = 3; Min.u64 = 28000; Max.u64 = 217000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 4502970; SumSQ.u64 = 553859730; Count.u64 = 36610; Min.u64 = 93; Max.u64 = 123; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 15731328; SumSQ.u64 = 8718458880; Count.u64 = 36610; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 307500; SumSQ.u64 = 51779250000; Count.u64 = 3; Min.u64 = 28000; Max.u64 = 217000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35586; SumSQ.u64 = 71172; Count.u64 = 17793; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 1000084; SumSQ.u64 = 82094208; Count.u64 = 18817; Min.u64 = 38; Max.u64 = 296; @@ -1399,8 +1467,10 @@ Channel 7 statistics directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1419,6 +1489,7 @@ Channel 7 statistics directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18817; SumSQ.u64 = 18817; Count.u64 = 18817; Min.u64 = 1; Max.u64 = 1; @@ -1429,6 +1500,8 @@ Channel 7 statistics directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 962450; SumSQ.u64 = 1099806; Count.u64 = 2636253; Min.u64 = 0; Max.u64 = 5; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out index 82d6f93d3a..57081caf6e 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendPagedMulti.out @@ -72,13 +72,16 @@ fast_t_pages: 1024 l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1732; SumSQ.u64 = 1732; Count.u64 = 1732; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 5965; SumSQ.u64 = 5965; Count.u64 = 5965; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 4035; SumSQ.u64 = 4035; Count.u64 = 4035; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -86,7 +89,7 @@ fast_t_pages: 1024 l1cache0.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.mesi.evict_I : Accumulator : Sum.u64 = 10137; SumSQ.u64 = 10137; Count.u64 = 10137; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.evict_I : Accumulator : Sum.u64 = 10138; SumSQ.u64 = 10138; Count.u64 = 10138; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.evict_S : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.evict_M : Accumulator : Sum.u64 = 3264; SumSQ.u64 = 3264; Count.u64 = 3264; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.evict_IS : Accumulator : Sum.u64 = 4926; SumSQ.u64 = 4926; Count.u64 = 4926; Min.u64 = 1; Max.u64 = 1; @@ -105,6 +108,7 @@ fast_t_pages: 1024 l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -151,14 +155,18 @@ fast_t_pages: 1024 l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 4035; SumSQ.u64 = 4035; Count.u64 = 4035; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 9769; SumSQ.u64 = 9769; Count.u64 = 9769; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1733; SumSQ.u64 = 1733; Count.u64 = 1733; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 170628543; SumSQ.u64 = 2726213557; Count.u64 = 10682663; Min.u64 = 0; Max.u64 = 16; @@ -233,13 +241,16 @@ fast_t_pages: 1024 l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1759; SumSQ.u64 = 1759; Count.u64 = 1759; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 5999; SumSQ.u64 = 5999; Count.u64 = 5999; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 4001; SumSQ.u64 = 4001; Count.u64 = 4001; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -266,6 +277,7 @@ fast_t_pages: 1024 l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -312,14 +324,18 @@ fast_t_pages: 1024 l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 4001; SumSQ.u64 = 4001; Count.u64 = 4001; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 9723; SumSQ.u64 = 9723; Count.u64 = 9723; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1760; SumSQ.u64 = 1760; Count.u64 = 1760; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 170273459; SumSQ.u64 = 2720004823; Count.u64 = 10682663; Min.u64 = 0; Max.u64 = 16; @@ -433,8 +449,11 @@ fast_t_pages: 1024 l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1791; SumSQ.u64 = 1791; Count.u64 = 1791; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 14144; SumSQ.u64 = 14144; Count.u64 = 14144; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; @@ -443,6 +462,9 @@ fast_t_pages: 1024 l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19492; SumSQ.u64 = 19492; Count.u64 = 19492; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 3493; SumSQ.u64 = 3493; Count.u64 = 3493; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -467,6 +489,7 @@ fast_t_pages: 1024 l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -537,10 +560,12 @@ fast_t_pages: 1024 l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 19147; SumSQ.u64 = 19147; Count.u64 = 19147; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 352; SumSQ.u64 = 352; Count.u64 = 352; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 6528; SumSQ.u64 = 6528; Count.u64 = 6528; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 9254; SumSQ.u64 = 9254; Count.u64 = 9254; Min.u64 = 1; Max.u64 = 1; @@ -552,6 +577,9 @@ fast_t_pages: 1024 l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 3491; SumSQ.u64 = 3491; Count.u64 = 3491; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -627,13 +655,16 @@ fast_t_pages: 1024 l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1763; SumSQ.u64 = 1763; Count.u64 = 1763; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 6035; SumSQ.u64 = 6035; Count.u64 = 6035; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 3965; SumSQ.u64 = 3965; Count.u64 = 3965; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -660,6 +691,7 @@ fast_t_pages: 1024 l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -706,14 +738,18 @@ fast_t_pages: 1024 l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 3965; SumSQ.u64 = 3965; Count.u64 = 3965; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 9765; SumSQ.u64 = 9765; Count.u64 = 9765; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 169052250; SumSQ.u64 = 2699759778; Count.u64 = 10682663; Min.u64 = 0; Max.u64 = 16; @@ -788,13 +824,16 @@ fast_t_pages: 1024 l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 5989; SumSQ.u64 = 5989; Count.u64 = 5989; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 4011; SumSQ.u64 = 4011; Count.u64 = 4011; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -821,6 +860,7 @@ fast_t_pages: 1024 l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -867,14 +907,18 @@ fast_t_pages: 1024 l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 4011; SumSQ.u64 = 4011; Count.u64 = 4011; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 9756; SumSQ.u64 = 9756; Count.u64 = 9756; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1724; SumSQ.u64 = 1724; Count.u64 = 1724; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 169360368; SumSQ.u64 = 2705246220; Count.u64 = 10682663; Min.u64 = 0; Max.u64 = 16; @@ -988,8 +1032,11 @@ fast_t_pages: 1024 l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1775; SumSQ.u64 = 1775; Count.u64 = 1775; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 14183; SumSQ.u64 = 14183; Count.u64 = 14183; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; @@ -998,6 +1045,9 @@ fast_t_pages: 1024 l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19521; SumSQ.u64 = 19521; Count.u64 = 19521; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 3489; SumSQ.u64 = 3489; Count.u64 = 3489; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1022,6 +1072,7 @@ fast_t_pages: 1024 l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1092,10 +1143,12 @@ fast_t_pages: 1024 l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 19167; SumSQ.u64 = 19167; Count.u64 = 19167; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 6439; SumSQ.u64 = 6439; Count.u64 = 6439; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 9396; SumSQ.u64 = 9396; Count.u64 = 9396; Min.u64 = 1; Max.u64 = 1; @@ -1107,15 +1160,18 @@ fast_t_pages: 1024 l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 3486; SumSQ.u64 = 3486; Count.u64 = 3486; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 215662460; SumSQ.u64 = 4431535216; Count.u64 = 10682663; Min.u64 = 0; Max.u64 = 32; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 8312066; SumSQ.u64 = 931696892; Count.u64 = 74168; Min.u64 = 112; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 12534272; SumSQ.u64 = 5287804928; Count.u64 = 74168; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 529500; SumSQ.u64 = 79553250000; Count.u64 = 5; Min.u64 = 20500; Max.u64 = 208500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 8312066; SumSQ.u64 = 931696892; Count.u64 = 74168; Min.u64 = 112; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 12534272; SumSQ.u64 = 5287804928; Count.u64 = 74168; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 529500; SumSQ.u64 = 79553250000; Count.u64 = 5; Min.u64 = 20500; Max.u64 = 208500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 29580; SumSQ.u64 = 29580; Count.u64 = 29580; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; @@ -1225,8 +1281,11 @@ fast_t_pages: 1024 l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 15210; SumSQ.u64 = 15210; Count.u64 = 15210; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1235,6 +1294,9 @@ fast_t_pages: 1024 l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 38314; SumSQ.u64 = 38314; Count.u64 = 38314; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 28330; SumSQ.u64 = 28330; Count.u64 = 28330; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1259,6 +1321,7 @@ fast_t_pages: 1024 l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1329,10 +1392,12 @@ fast_t_pages: 1024 l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 37596; SumSQ.u64 = 37596; Count.u64 = 37596; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 340; SumSQ.u64 = 340; Count.u64 = 340; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3566; SumSQ.u64 = 3566; Count.u64 = 3566; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 5101; SumSQ.u64 = 5101; Count.u64 = 5101; Min.u64 = 1; Max.u64 = 1; @@ -1344,15 +1409,18 @@ fast_t_pages: 1024 l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 28327; SumSQ.u64 = 28327; Count.u64 = 28327; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 562; SumSQ.u64 = 562; Count.u64 = 562; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 36572; SumSQ.u64 = 36572; Count.u64 = 36572; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 428014049; SumSQ.u64 = 17302356347; Count.u64 = 10682663; Min.u64 = 0; Max.u64 = 64; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 9122554; SumSQ.u64 = 1122065846; Count.u64 = 74168; Min.u64 = 84; Max.u64 = 137; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 31783424; SumSQ.u64 = 17607262208; Count.u64 = 74168; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 837500; SumSQ.u64 = 174121250000; Count.u64 = 5; Min.u64 = 70000; Max.u64 = 286000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 9122554; SumSQ.u64 = 1122065846; Count.u64 = 74168; Min.u64 = 84; Max.u64 = 137; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 31783424; SumSQ.u64 = 17607262208; Count.u64 = 74168; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 837500; SumSQ.u64 = 174121250000; Count.u64 = 5; Min.u64 = 70000; Max.u64 = 286000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 73144; SumSQ.u64 = 146288; Count.u64 = 36572; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 2778004; SumSQ.u64 = 219209016; Count.u64 = 37596; Min.u64 = 38; Max.u64 = 360; @@ -1375,8 +1443,10 @@ fast_t_pages: 1024 directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1395,6 +1465,7 @@ fast_t_pages: 1024 directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 37596; SumSQ.u64 = 37596; Count.u64 = 37596; Min.u64 = 1; Max.u64 = 1; @@ -1405,6 +1476,8 @@ fast_t_pages: 1024 directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 2702812; SumSQ.u64 = 2783432; Count.u64 = 5341171; Min.u64 = 0; Max.u64 = 4; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_1.out similarity index 94% rename from src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out rename to src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_1.out index 3c3321ab39..4f9cf32406 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2_ramulator.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_1.out @@ -69,13 +69,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2282; SumSQ.u64 = 2282; Count.u64 = 2282; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -102,6 +105,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -139,14 +143,18 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 2180; SumSQ.u64 = 2180; Count.u64 = 2180; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 710; SumSQ.u64 = 710; Count.u64 = 710; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2953199; SumSQ.u64 = 186261689; Count.u64 = 47439; Min.u64 = 0; Max.u64 = 64; @@ -221,13 +229,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2262; SumSQ.u64 = 2262; Count.u64 = 2262; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -254,6 +265,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -291,14 +303,18 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2950624; SumSQ.u64 = 185920066; Count.u64 = 47439; Min.u64 = 0; Max.u64 = 64; @@ -412,8 +428,11 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 2534; SumSQ.u64 = 2534; Count.u64 = 2534; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1140; SumSQ.u64 = 1140; Count.u64 = 1140; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -422,6 +441,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -446,6 +468,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1094; SumSQ.u64 = 1094; Count.u64 = 1094; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -481,10 +504,12 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 4186; SumSQ.u64 = 4186; Count.u64 = 4186; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 4171; SumSQ.u64 = 4171; Count.u64 = 4171; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 1371; SumSQ.u64 = 1371; Count.u64 = 1371; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -496,6 +521,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_2.out similarity index 94% rename from src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out rename to src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_2.out index 3892101cca..2f57a3a995 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1_ramulator.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendRamulator_2.out @@ -71,13 +71,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + c0.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1813; SumSQ.u64 = 1813; Count.u64 = 1813; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 1187; SumSQ.u64 = 1187; Count.u64 = 1187; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -85,7 +88,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - c0.l1cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + c0.l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; c0.l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; c0.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; c0.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -141,14 +145,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.Write_recv : Accumulator : Sum.u64 = 1187; SumSQ.u64 = 1187; Count.u64 = 1187; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; c0.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.Inv_recv : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; c0.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; + c0.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1002815; SumSQ.u64 = 15530789; Count.u64 = 66681; Min.u64 = 0; Max.u64 = 16; @@ -223,13 +231,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; c1.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; c1.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; + c1.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1803; SumSQ.u64 = 1803; Count.u64 = 1803; Min.u64 = 1; Max.u64 = 1; c1.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 1197; SumSQ.u64 = 1197; Count.u64 = 1197; Min.u64 = 1; Max.u64 = 1; c1.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -237,7 +248,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - c1.l1cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + c1.l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; c1.l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -256,6 +267,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; c1.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; c1.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -293,20 +305,24 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.Write_recv : Accumulator : Sum.u64 = 1197; SumSQ.u64 = 1197; Count.u64 = 1197; Min.u64 = 1; Max.u64 = 1; c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; c1.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; c1.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.Inv_recv : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; c1.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; c1.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + c1.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1010948; SumSQ.u64 = 15668524; Count.u64 = 66681; Min.u64 = 0; Max.u64 = 16; c1.l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - n0.l2cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + n0.l2cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; n0.l2cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -414,8 +430,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 537; SumSQ.u64 = 537; Count.u64 = 537; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; @@ -424,6 +443,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1427; SumSQ.u64 = 1427; Count.u64 = 1427; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 771; SumSQ.u64 = 771; Count.u64 = 771; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -448,6 +470,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; n0.l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; n0.l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -483,10 +506,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetSResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; n0.l2cache.GetXResp_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; n0.l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -498,6 +523,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 771; SumSQ.u64 = 771; Count.u64 = 771; Min.u64 = 1; Max.u64 = 1; n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + n0.l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.AckInv_recv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; n0.l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -573,13 +601,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; c2.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; c2.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + c2.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1846; SumSQ.u64 = 1846; Count.u64 = 1846; Min.u64 = 1; Max.u64 = 1; c2.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; c2.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -587,7 +618,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - c2.l1cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + c2.l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; c2.l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -606,6 +637,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; c2.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; c2.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -643,14 +675,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.Write_recv : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; c2.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 687; SumSQ.u64 = 687; Count.u64 = 687; Min.u64 = 1; Max.u64 = 1; c2.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.Inv_recv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; c2.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; c2.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + c2.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 989313; SumSQ.u64 = 15319255; Count.u64 = 66681; Min.u64 = 0; Max.u64 = 16; @@ -725,13 +761,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + c3.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1834; SumSQ.u64 = 1834; Count.u64 = 1834; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 1166; SumSQ.u64 = 1166; Count.u64 = 1166; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -739,7 +778,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - c3.l1cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + c3.l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; c3.l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -758,6 +797,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; c3.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; c3.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -795,20 +835,24 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.Write_recv : Accumulator : Sum.u64 = 1166; SumSQ.u64 = 1166; Count.u64 = 1166; Min.u64 = 1; Max.u64 = 1; c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; c3.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 696; SumSQ.u64 = 696; Count.u64 = 696; Min.u64 = 1; Max.u64 = 1; c3.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.Inv_recv : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; c3.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; c3.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + c3.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1018026; SumSQ.u64 = 15765176; Count.u64 = 66681; Min.u64 = 0; Max.u64 = 16; c3.l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - n1.l2cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + n1.l2cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; n1.l2cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -916,8 +960,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; @@ -926,6 +973,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1383; SumSQ.u64 = 1383; Count.u64 = 1383; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 720; SumSQ.u64 = 720; Count.u64 = 720; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -950,6 +1000,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; n1.l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; n1.l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -985,10 +1036,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.GetSResp_recv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; n1.l2cache.GetXResp_recv : Accumulator : Sum.u64 = 894; SumSQ.u64 = 894; Count.u64 = 894; Min.u64 = 1; Max.u64 = 1; n1.l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1000,13 +1053,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 720; SumSQ.u64 = 720; Count.u64 = 720; Min.u64 = 1; Max.u64 = 1; n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; + n1.l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.AckInv_recv : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1356; Count.u64 = 1356; Min.u64 = 1; Max.u64 = 1; n1.l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 1007462; SumSQ.u64 = 15881696; Count.u64 = 66681; Min.u64 = 0; Max.u64 = 25; n1.l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.default_stat : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l3cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1114,8 +1170,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1124,6 +1183,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1781; SumSQ.u64 = 1781; Count.u64 = 1781; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1148,6 +1210,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 701; SumSQ.u64 = 701; Count.u64 = 701; Min.u64 = 1; Max.u64 = 1; l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1183,10 +1246,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1198,6 +1263,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FetchResp_recv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.AckInv_recv : Accumulator : Sum.u64 = 707; SumSQ.u64 = 707; Count.u64 = 707; Min.u64 = 1; Max.u64 = 1; l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out index 21db085cae..87260ddede 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderRow.out @@ -71,13 +71,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2966; SumSQ.u64 = 2966; Count.u64 = 2966; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2034; SumSQ.u64 = 2034; Count.u64 = 2034; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2034; SumSQ.u64 = 2034; Count.u64 = 2034; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4873; SumSQ.u64 = 4873; Count.u64 = 4873; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 852; SumSQ.u64 = 852; Count.u64 = 852; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4936467; SumSQ.u64 = 78367055; Count.u64 = 312116; Min.u64 = 0; Max.u64 = 16; @@ -232,13 +240,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 845; SumSQ.u64 = 845; Count.u64 = 845; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2934; SumSQ.u64 = 2934; Count.u64 = 2934; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2066; SumSQ.u64 = 2066; Count.u64 = 2066; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 2066; SumSQ.u64 = 2066; Count.u64 = 2066; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4875; SumSQ.u64 = 4875; Count.u64 = 4875; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 846; SumSQ.u64 = 846; Count.u64 = 846; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4923503; SumSQ.u64 = 78208901; Count.u64 = 312116; Min.u64 = 0; Max.u64 = 16; @@ -432,8 +448,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 889; SumSQ.u64 = 889; Count.u64 = 889; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6843; SumSQ.u64 = 6843; Count.u64 = 6843; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; @@ -442,6 +461,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9748; SumSQ.u64 = 9748; Count.u64 = 9748; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1698; SumSQ.u64 = 1698; Count.u64 = 1698; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9563; SumSQ.u64 = 9563; Count.u64 = 9563; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3325; SumSQ.u64 = 3325; Count.u64 = 3325; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4552; SumSQ.u64 = 4552; Count.u64 = 4552; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1696; SumSQ.u64 = 1696; Count.u64 = 1696; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3096; SumSQ.u64 = 3096; Count.u64 = 3096; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1904; SumSQ.u64 = 1904; Count.u64 = 1904; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -640,7 +671,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4849; SumSQ.u64 = 4849; Count.u64 = 4849; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4850; SumSQ.u64 = 4850; Count.u64 = 4850; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_S : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_M : Accumulator : Sum.u64 = 1533; SumSQ.u64 = 1533; Count.u64 = 1533; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_IS : Accumulator : Sum.u64 = 2387; SumSQ.u64 = 2387; Count.u64 = 2387; Min.u64 = 1; Max.u64 = 1; @@ -659,6 +690,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 1904; SumSQ.u64 = 1904; Count.u64 = 1904; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4878; SumSQ.u64 = 4878; Count.u64 = 4878; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4770240; SumSQ.u64 = 75702618; Count.u64 = 312116; Min.u64 = 0; Max.u64 = 16; @@ -787,13 +823,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 827; SumSQ.u64 = 827; Count.u64 = 827; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2969; SumSQ.u64 = 2969; Count.u64 = 2969; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2031; SumSQ.u64 = 2031; Count.u64 = 2031; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -820,6 +859,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2031; SumSQ.u64 = 2031; Count.u64 = 2031; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4864; SumSQ.u64 = 4864; Count.u64 = 4864; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 4945952; SumSQ.u64 = 78550360; Count.u64 = 312116; Min.u64 = 0; Max.u64 = 16; @@ -987,8 +1031,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6947; SumSQ.u64 = 6947; Count.u64 = 6947; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; @@ -997,6 +1044,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9742; SumSQ.u64 = 9742; Count.u64 = 9742; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1706; SumSQ.u64 = 1706; Count.u64 = 1706; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9548; SumSQ.u64 = 9548; Count.u64 = 9548; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3164; SumSQ.u64 = 3164; Count.u64 = 3164; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4726; SumSQ.u64 = 4726; Count.u64 = 4726; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1702; SumSQ.u64 = 1702; Count.u64 = 1702; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 5644396; SumSQ.u64 = 105238056; Count.u64 = 312116; Min.u64 = 0; Max.u64 = 32; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 69391; SumSQ.u64 = 152327; Count.u64 = 36526; Min.u64 = 0; Max.u64 = 3; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6123392; SumSQ.u64 = 2572476416; Count.u64 = 36526; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 24938750; SumSQ.u64 = 79464507500; Count.u64 = 12415; Min.u64 = 50; Max.u64 = 20400; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 69391; SumSQ.u64 = 152327; Count.u64 = 36526; Min.u64 = 0; Max.u64 = 3; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6123392; SumSQ.u64 = 2572476416; Count.u64 = 36526; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 24938750; SumSQ.u64 = 79464507500; Count.u64 = 12415; Min.u64 = 50; Max.u64 = 20400; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 14948; SumSQ.u64 = 14948; Count.u64 = 14948; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; @@ -1224,8 +1280,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7394; SumSQ.u64 = 7394; Count.u64 = 7394; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19111; SumSQ.u64 = 19111; Count.u64 = 19111; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 13792; SumSQ.u64 = 13792; Count.u64 = 13792; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18775; SumSQ.u64 = 18775; Count.u64 = 18775; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 1784; SumSQ.u64 = 1784; Count.u64 = 1784; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 2450; SumSQ.u64 = 2450; Count.u64 = 2450; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 13790; SumSQ.u64 = 13790; Count.u64 = 13790; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17751; SumSQ.u64 = 17751; Count.u64 = 17751; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 10931705; SumSQ.u64 = 390118349; Count.u64 = 312116; Min.u64 = 0; Max.u64 = 64; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 70997; SumSQ.u64 = 154919; Count.u64 = 36526; Min.u64 = 0; Max.u64 = 3; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15736192; SumSQ.u64 = 8724668416; Count.u64 = 36526; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 66429166; SumSQ.u64 = 553396526358; Count.u64 = 15751; Min.u64 = 1; Max.u64 = 46824; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 70997; SumSQ.u64 = 154919; Count.u64 = 36526; Min.u64 = 0; Max.u64 = 3; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 15736192; SumSQ.u64 = 8724668416; Count.u64 = 36526; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 66429166; SumSQ.u64 = 553396526358; Count.u64 = 15751; Min.u64 = 1; Max.u64 = 46824; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35502; SumSQ.u64 = 71004; Count.u64 = 17751; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 7235485; SumSQ.u64 = 3607265943; Count.u64 = 18775; Min.u64 = 27; Max.u64 = 1354; @@ -1374,8 +1442,10 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18775; SumSQ.u64 = 18775; Count.u64 = 18775; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 7197935; SumSQ.u64 = 226555645; Count.u64 = 233955; Min.u64 = 0; Max.u64 = 60; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out index e2cc57c232..c0b67aefe5 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendReorderSimple.out @@ -71,13 +71,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3040; SumSQ.u64 = 3040; Count.u64 = 3040; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1960; SumSQ.u64 = 1960; Count.u64 = 1960; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 1960; SumSQ.u64 = 1960; Count.u64 = 1960; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4872; SumSQ.u64 = 4872; Count.u64 = 4872; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 854; SumSQ.u64 = 854; Count.u64 = 854; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 84018299; SumSQ.u64 = 1343234385; Count.u64 = 5257599; Min.u64 = 0; Max.u64 = 16; @@ -232,13 +240,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 845; SumSQ.u64 = 845; Count.u64 = 845; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3029; SumSQ.u64 = 3029; Count.u64 = 3029; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 1971; SumSQ.u64 = 1971; Count.u64 = 1971; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4847; SumSQ.u64 = 4847; Count.u64 = 4847; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 846; SumSQ.u64 = 846; Count.u64 = 846; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83406898; SumSQ.u64 = 1333074966; Count.u64 = 5257599; Min.u64 = 0; Max.u64 = 16; @@ -432,8 +448,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6887; SumSQ.u64 = 6887; Count.u64 = 6887; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; @@ -442,6 +461,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9719; SumSQ.u64 = 9719; Count.u64 = 9719; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1700; SumSQ.u64 = 1700; Count.u64 = 1700; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9543; SumSQ.u64 = 9543; Count.u64 = 9543; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3157; SumSQ.u64 = 3157; Count.u64 = 3157; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4694; SumSQ.u64 = 4694; Count.u64 = 4694; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1698; SumSQ.u64 = 1698; Count.u64 = 1698; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 837; SumSQ.u64 = 837; Count.u64 = 837; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2999; SumSQ.u64 = 2999; Count.u64 = 2999; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2001; SumSQ.u64 = 2001; Count.u64 = 2001; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -659,6 +690,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2001; SumSQ.u64 = 2001; Count.u64 = 2001; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4871; SumSQ.u64 = 4871; Count.u64 = 4871; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 837; SumSQ.u64 = 837; Count.u64 = 837; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 83863620; SumSQ.u64 = 1340540324; Count.u64 = 5257599; Min.u64 = 0; Max.u64 = 16; @@ -787,13 +823,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3083; SumSQ.u64 = 3083; Count.u64 = 3083; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1917; SumSQ.u64 = 1917; Count.u64 = 1917; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -820,6 +859,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 1917; SumSQ.u64 = 1917; Count.u64 = 1917; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4873; SumSQ.u64 = 4873; Count.u64 = 4873; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 828; SumSQ.u64 = 828; Count.u64 = 828; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 82937193; SumSQ.u64 = 1325093231; Count.u64 = 5257599; Min.u64 = 0; Max.u64 = 16; @@ -987,8 +1031,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 920; SumSQ.u64 = 920; Count.u64 = 920; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 6833; SumSQ.u64 = 6833; Count.u64 = 6833; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 259; SumSQ.u64 = 259; Count.u64 = 259; Min.u64 = 1; Max.u64 = 1; @@ -997,6 +1044,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9744; SumSQ.u64 = 9744; Count.u64 = 9744; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1665; SumSQ.u64 = 1665; Count.u64 = 1665; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9588; SumSQ.u64 = 9588; Count.u64 = 9588; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 4721; SumSQ.u64 = 4721; Count.u64 = 4721; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1663; SumSQ.u64 = 1663; Count.u64 = 1663; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 105566592; SumSQ.u64 = 2151192936; Count.u64 = 5257599; Min.u64 = 0; Max.u64 = 31; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 3978698; SumSQ.u64 = 433706198; Count.u64 = 36500; Min.u64 = 109; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6039296; SumSQ.u64 = 2519613440; Count.u64 = 36500; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 375100; SumSQ.u64 = 49901370000; Count.u64 = 4; Min.u64 = 36700; Max.u64 = 194200; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 3978698; SumSQ.u64 = 433706198; Count.u64 = 36500; Min.u64 = 109; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6039296; SumSQ.u64 = 2519613440; Count.u64 = 36500; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 375100; SumSQ.u64 = 49901370000; Count.u64 = 4; Min.u64 = 36700; Max.u64 = 194200; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 14897; SumSQ.u64 = 14897; Count.u64 = 14897; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; @@ -1224,8 +1280,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7233; SumSQ.u64 = 7233; Count.u64 = 7233; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19131; SumSQ.u64 = 19131; Count.u64 = 19131; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 13722; SumSQ.u64 = 13722; Count.u64 = 13722; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 464; SumSQ.u64 = 464; Count.u64 = 464; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 289; SumSQ.u64 = 289; Count.u64 = 289; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18762; SumSQ.u64 = 18762; Count.u64 = 18762; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 1752; SumSQ.u64 = 1752; Count.u64 = 1752; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 2544; SumSQ.u64 = 2544; Count.u64 = 2544; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 13720; SumSQ.u64 = 13720; Count.u64 = 13720; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 495; SumSQ.u64 = 495; Count.u64 = 495; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17738; SumSQ.u64 = 17738; Count.u64 = 17738; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 210445321; SumSQ.u64 = 8502173419; Count.u64 = 5257599; Min.u64 = 0; Max.u64 = 63; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 4708406; SumSQ.u64 = 607373946; Count.u64 = 36500; Min.u64 = 109; Max.u64 = 129; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15645440; SumSQ.u64 = 8667545600; Count.u64 = 36500; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 545100; SumSQ.u64 = 84894170000; Count.u64 = 4; Min.u64 = 77500; Max.u64 = 216200; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 4708406; SumSQ.u64 = 607373946; Count.u64 = 36500; Min.u64 = 109; Max.u64 = 129; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 15645440; SumSQ.u64 = 8667545600; Count.u64 = 36500; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 545100; SumSQ.u64 = 84894170000; Count.u64 = 4; Min.u64 = 77500; Max.u64 = 216200; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35476; SumSQ.u64 = 70952; Count.u64 = 17738; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 934440; SumSQ.u64 = 46647000; Count.u64 = 18762; Min.u64 = 20; Max.u64 = 50; @@ -1374,8 +1442,10 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18762; SumSQ.u64 = 18762; Count.u64 = 18762; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 896916; SumSQ.u64 = 896916; Count.u64 = 2628626; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out index 383021d555..9ba9b526ff 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_1.out @@ -71,13 +71,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3059; SumSQ.u64 = 3059; Count.u64 = 3059; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4863; SumSQ.u64 = 4863; Count.u64 = 4863; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 167761890; SumSQ.u64 = 5360745496; Count.u64 = 5265331; Min.u64 = 0; Max.u64 = 32; @@ -232,13 +240,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3021; SumSQ.u64 = 3021; Count.u64 = 3021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1979; SumSQ.u64 = 1979; Count.u64 = 1979; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 1979; SumSQ.u64 = 1979; Count.u64 = 1979; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4883; SumSQ.u64 = 4883; Count.u64 = 4883; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 168174176; SumSQ.u64 = 5375269672; Count.u64 = 5265331; Min.u64 = 0; Max.u64 = 32; @@ -432,8 +448,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3546; SumSQ.u64 = 3546; Count.u64 = 3546; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -442,6 +461,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9746; SumSQ.u64 = 9746; Count.u64 = 9746; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9515; SumSQ.u64 = 9515; Count.u64 = 9515; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3812; SumSQ.u64 = 3812; Count.u64 = 3812; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 5722; SumSQ.u64 = 5722; Count.u64 = 5722; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3044; SumSQ.u64 = 3044; Count.u64 = 3044; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1956; SumSQ.u64 = 1956; Count.u64 = 1956; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -659,6 +690,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 1956; SumSQ.u64 = 1956; Count.u64 = 1956; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4865; SumSQ.u64 = 4865; Count.u64 = 4865; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 167740282; SumSQ.u64 = 5360024730; Count.u64 = 5265331; Min.u64 = 0; Max.u64 = 32; @@ -787,13 +823,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3008; SumSQ.u64 = 3008; Count.u64 = 3008; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -820,6 +859,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4857; SumSQ.u64 = 4857; Count.u64 = 4857; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 167416615; SumSQ.u64 = 5346169263; Count.u64 = 5265331; Min.u64 = 0; Max.u64 = 32; @@ -987,8 +1031,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3564; SumSQ.u64 = 3564; Count.u64 = 3564; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; @@ -997,6 +1044,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9722; SumSQ.u64 = 9722; Count.u64 = 9722; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9505; SumSQ.u64 = 9505; Count.u64 = 9505; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3842; SumSQ.u64 = 3842; Count.u64 = 3842; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 5689; SumSQ.u64 = 5689; Count.u64 = 5689; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 319185024; SumSQ.u64 = 19440547598; Count.u64 = 5265331; Min.u64 = 0; Max.u64 = 65; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 3253662; SumSQ.u64 = 289575918; Count.u64 = 36558; Min.u64 = 89; Max.u64 = 89; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6044544; SumSQ.u64 = 2520834048; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 23780000000; Count.u64 = 3; Min.u64 = 10000; Max.u64 = 136000; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 3253662; SumSQ.u64 = 289575918; Count.u64 = 36558; Min.u64 = 89; Max.u64 = 89; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6044544; SumSQ.u64 = 2520834048; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 23780000000; Count.u64 = 3; Min.u64 = 10000; Max.u64 = 136000; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1224,8 +1280,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7236; SumSQ.u64 = 7236; Count.u64 = 7236; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 19020; SumSQ.u64 = 19020; Count.u64 = 19020; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18791; SumSQ.u64 = 18791; Count.u64 = 18791; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 664; SumSQ.u64 = 664; Count.u64 = 664; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 7110; SumSQ.u64 = 7110; Count.u64 = 7110; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 10361; SumSQ.u64 = 10361; Count.u64 = 10361; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17767; SumSQ.u64 = 17767; Count.u64 = 17767; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 636295190; SumSQ.u64 = 77120905816; Count.u64 = 5265331; Min.u64 = 0; Max.u64 = 128; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 5629932; SumSQ.u64 = 867009528; Count.u64 = 36558; Min.u64 = 154; Max.u64 = 154; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15665536; SumSQ.u64 = 8678268928; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 362500; SumSQ.u64 = 89356250000; Count.u64 = 2; Min.u64 = 72500; Max.u64 = 290000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 5629932; SumSQ.u64 = 867009528; Count.u64 = 36558; Min.u64 = 154; Max.u64 = 154; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 15665536; SumSQ.u64 = 8678268928; Count.u64 = 36558; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 362500; SumSQ.u64 = 89356250000; Count.u64 = 2; Min.u64 = 72500; Max.u64 = 290000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35534; SumSQ.u64 = 71068; Count.u64 = 17767; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 1311980; SumSQ.u64 = 91701200; Count.u64 = 18791; Min.u64 = 40; Max.u64 = 70; @@ -1374,8 +1442,10 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18791; SumSQ.u64 = 18791; Count.u64 = 18791; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 1274398; SumSQ.u64 = 1274398; Count.u64 = 2632464; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out index 7d5f1db719..5463e92877 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendSimpleDRAM_2.out @@ -71,13 +71,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4865; SumSQ.u64 = 4865; Count.u64 = 4865; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 287804732; SumSQ.u64 = 9197922184; Count.u64 = 9047220; Min.u64 = 0; Max.u64 = 32; @@ -232,13 +240,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2952; SumSQ.u64 = 2952; Count.u64 = 2952; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2048; SumSQ.u64 = 2048; Count.u64 = 2048; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 2048; SumSQ.u64 = 2048; Count.u64 = 2048; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4862; SumSQ.u64 = 4862; Count.u64 = 4862; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 288378350; SumSQ.u64 = 9217608472; Count.u64 = 9047220; Min.u64 = 0; Max.u64 = 32; @@ -432,8 +448,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3697; SumSQ.u64 = 3697; Count.u64 = 3697; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; @@ -442,6 +461,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9727; SumSQ.u64 = 9727; Count.u64 = 9727; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9486; SumSQ.u64 = 9486; Count.u64 = 9486; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3980; SumSQ.u64 = 3980; Count.u64 = 3980; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 5550; SumSQ.u64 = 5550; Count.u64 = 5550; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3000; SumSQ.u64 = 3000; Count.u64 = 3000; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -659,6 +690,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4853; SumSQ.u64 = 4853; Count.u64 = 4853; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 289195982; SumSQ.u64 = 9248167908; Count.u64 = 9047220; Min.u64 = 0; Max.u64 = 32; @@ -787,13 +823,16 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3006; SumSQ.u64 = 3006; Count.u64 = 3006; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -820,6 +859,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 4876; SumSQ.u64 = 4876; Count.u64 = 4876; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 289163131; SumSQ.u64 = 9247077309; Count.u64 = 9047220; Min.u64 = 0; Max.u64 = 32; @@ -987,8 +1031,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 340; SumSQ.u64 = 340; Count.u64 = 340; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3619; SumSQ.u64 = 3619; Count.u64 = 3619; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; @@ -997,6 +1044,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 9729; SumSQ.u64 = 9729; Count.u64 = 9729; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 9507; SumSQ.u64 = 9507; Count.u64 = 9507; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 276; SumSQ.u64 = 276; Count.u64 = 276; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 3892; SumSQ.u64 = 3892; Count.u64 = 3892; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 5635; SumSQ.u64 = 5635; Count.u64 = 5635; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 552592484; SumSQ.u64 = 33799726944; Count.u64 = 9047220; Min.u64 = 0; Max.u64 = 65; l2cache1.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 4081908; SumSQ.u64 = 501858696; Count.u64 = 36570; Min.u64 = 70; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6157440; SumSQ.u64 = 2592645120; Count.u64 = 36570; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 47128500; SumSQ.u64 = 3391976250000; Count.u64 = 655; Min.u64 = 40500; Max.u64 = 72000; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 1048937500; SumSQ.u64 = 122826721750000; Count.u64 = 11441; Min.u64 = 7500; Max.u64 = 288000; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 4081908; SumSQ.u64 = 501858696; Count.u64 = 36570; Min.u64 = 70; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6157440; SumSQ.u64 = 2592645120; Count.u64 = 36570; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 47128500; SumSQ.u64 = 3391976250000; Count.u64 = 655; Min.u64 = 40500; Max.u64 = 72000; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 1048937500; SumSQ.u64 = 122826721750000; Count.u64 = 11441; Min.u64 = 7500; Max.u64 = 288000; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1224,8 +1280,11 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7455; SumSQ.u64 = 7455; Count.u64 = 7455; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 18993; SumSQ.u64 = 18993; Count.u64 = 18993; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 18797; SumSQ.u64 = 18797; Count.u64 = 18797; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 7316; SumSQ.u64 = 7316; Count.u64 = 7316; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 10156; SumSQ.u64 = 10156; Count.u64 = 10156; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17773; SumSQ.u64 = 17773; Count.u64 = 17773; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 1101215040; SumSQ.u64 = 134294132092; Count.u64 = 9047220; Min.u64 = 0; Max.u64 = 128; l3cache.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 19707183; SumSQ.u64 = 28955725261; Count.u64 = 55367; Min.u64 = 21; Max.u64 = 4104; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 21278592; SumSQ.u64 = 11302428672; Count.u64 = 62822; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 352000; SumSQ.u64 = 87944000000; Count.u64 = 2; Min.u64 = 62000; Max.u64 = 290000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 19707183; SumSQ.u64 = 28955725261; Count.u64 = 55367; Min.u64 = 21; Max.u64 = 4104; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 21278592; SumSQ.u64 = 11302428672; Count.u64 = 62822; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 352000; SumSQ.u64 = 87944000000; Count.u64 = 2; Min.u64 = 62000; Max.u64 = 290000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 35546; SumSQ.u64 = 71092; Count.u64 = 17773; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 261257338; SumSQ.u64 = 3836245157300; Count.u64 = 18797; Min.u64 = 434; Max.u64 = 16922; @@ -1374,8 +1442,10 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 18797; SumSQ.u64 = 18797; Count.u64 = 18797; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 261219744; SumSQ.u64 = 15654015936; Count.u64 = 4523188; Min.u64 = 0; Max.u64 = 72; @@ -1424,8 +1497,8 @@ l3cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int memory.cycles_with_issue : Accumulator : Sum.u64 = 26252; SumSQ.u64 = 26252; Count.u64 = 26252; Min.u64 = 1; Max.u64 = 1; memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.total_cycles : Accumulator : Sum.u64 = 4523610; SumSQ.u64 = 20463047432100; Count.u64 = 1; Min.u64 = 4523610; Max.u64 = 4523610; - memory:cpulink.packet_latency : Accumulator : Sum.u64 = 3163160; SumSQ.u64 = 409645040; Count.u64 = 26252; Min.u64 = 70; Max.u64 = 142; - memory:cpulink.send_bit_count : Accumulator : Sum.u64 = 10827072; SumSQ.u64 = 6236393472; Count.u64 = 18797; Min.u64 = 576; Max.u64 = 576; - memory:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory:cpulink.idle_time : Accumulator : Sum.u64 = 1411849000; SumSQ.u64 = 144204353000000; Count.u64 = 18065; Min.u64 = 41000; Max.u64 = 1337000; + memory:highlink.packet_latency : Accumulator : Sum.u64 = 3163160; SumSQ.u64 = 409645040; Count.u64 = 26252; Min.u64 = 70; Max.u64 = 142; + memory:highlink.send_bit_count : Accumulator : Sum.u64 = 10827072; SumSQ.u64 = 6236393472; Count.u64 = 18797; Min.u64 = 576; Max.u64 = 576; + memory:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory:highlink.idle_time : Accumulator : Sum.u64 = 1411849000; SumSQ.u64 = 144204353000000; Count.u64 = 18065; Min.u64 = 41000; Max.u64 = 1337000; Simulation is complete, simulated time: 4.52361 ms diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out index 5c6636969b..931b119e6b 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_1.out @@ -1,7 +1,7 @@ - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 6987248; SumSQ.u64 = 663815256; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 6987248; SumSQ.u64 = 663815256; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 119638; SumSQ.u64 = 119638; Count.u64 = 119638; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 68913; SumSQ.u64 = 68913; Count.u64 = 68913; Min.u64 = 1; Max.u64 = 1; @@ -111,8 +111,11 @@ l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 15039; SumSQ.u64 = 15039; Count.u64 = 15039; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -121,6 +124,9 @@ l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 18898; SumSQ.u64 = 18898; Count.u64 = 18898; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 17480; SumSQ.u64 = 17480; Count.u64 = 17480; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -145,6 +151,7 @@ l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -215,10 +222,12 @@ l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -230,6 +239,9 @@ l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 17479; SumSQ.u64 = 17479; Count.u64 = 17479; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 20268; SumSQ.u64 = 20268; Count.u64 = 20268; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 36262; SumSQ.u64 = 36262; Count.u64 = 36262; Min.u64 = 1; Max.u64 = 1; @@ -305,13 +317,16 @@ l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -338,6 +353,7 @@ l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -384,20 +400,24 @@ l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337477647; SumSQ.u64 = 10785094549; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; l1cache0.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4884; SumSQ.u64 = 4884; Count.u64 = 4884; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4886; SumSQ.u64 = 4886; Count.u64 = 4886; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; @@ -505,8 +525,11 @@ l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2197; SumSQ.u64 = 2197; Count.u64 = 2197; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2540; SumSQ.u64 = 2540; Count.u64 = 2540; Min.u64 = 1; Max.u64 = 1; @@ -515,6 +538,9 @@ l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -539,6 +565,7 @@ l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -609,10 +636,12 @@ l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2596; SumSQ.u64 = 2596; Count.u64 = 2596; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2365; SumSQ.u64 = 2365; Count.u64 = 2365; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; @@ -624,6 +653,9 @@ l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -699,13 +731,16 @@ l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2979; SumSQ.u64 = 2979; Count.u64 = 2979; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -732,6 +767,7 @@ l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,14 +814,18 @@ l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2614; SumSQ.u64 = 2614; Count.u64 = 2614; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 2101; SumSQ.u64 = 2101; Count.u64 = 2101; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338409616; SumSQ.u64 = 10823556192; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -899,8 +939,11 @@ l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2168; SumSQ.u64 = 2168; Count.u64 = 2168; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2553; SumSQ.u64 = 2553; Count.u64 = 2553; Min.u64 = 1; Max.u64 = 1; @@ -909,6 +952,9 @@ l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -933,6 +979,7 @@ l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1003,10 +1050,12 @@ l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2357; SumSQ.u64 = 2357; Count.u64 = 2357; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; @@ -1018,6 +1067,9 @@ l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1093,13 +1145,16 @@ l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2955; SumSQ.u64 = 2955; Count.u64 = 2955; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1107,7 +1162,7 @@ l1cache2.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4600; SumSQ.u64 = 4600; Count.u64 = 4600; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4601; SumSQ.u64 = 4601; Count.u64 = 4601; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_S : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_M : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_IS : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; @@ -1126,6 +1181,7 @@ l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1172,14 +1228,18 @@ l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2574; SumSQ.u64 = 2574; Count.u64 = 2574; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 2065; SumSQ.u64 = 2065; Count.u64 = 2065; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337719688; SumSQ.u64 = 10795953034; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1293,8 +1353,11 @@ l2cache2.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 2492; Count.u64 = 2492; Min.u64 = 1; Max.u64 = 1; @@ -1303,6 +1366,9 @@ l2cache2.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1327,6 +1393,7 @@ l2cache2.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1397,10 +1464,12 @@ l2cache2.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2551; SumSQ.u64 = 2551; Count.u64 = 2551; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; @@ -1412,6 +1481,9 @@ l2cache2.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache2.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1487,13 +1559,16 @@ l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2981; SumSQ.u64 = 2981; Count.u64 = 2981; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1520,6 +1595,7 @@ l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1566,14 +1642,18 @@ l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2598; SumSQ.u64 = 2598; Count.u64 = 2598; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 2142; SumSQ.u64 = 2142; Count.u64 = 2142; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 334138095; SumSQ.u64 = 10675247815; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1687,8 +1767,11 @@ l2cache3.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; @@ -1697,6 +1780,9 @@ l2cache3.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1721,6 +1807,7 @@ l2cache3.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1791,10 +1878,12 @@ l2cache3.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2589; SumSQ.u64 = 2589; Count.u64 = 2589; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 2374; Count.u64 = 2374; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; @@ -1806,6 +1895,9 @@ l2cache3.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1881,13 +1973,16 @@ l1cache4.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1914,6 +2009,7 @@ l1cache4.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,14 +2056,18 @@ l1cache4.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2612; SumSQ.u64 = 2612; Count.u64 = 2612; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Inv_recv : Accumulator : Sum.u64 = 2149; SumSQ.u64 = 2149; Count.u64 = 2149; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337232970; SumSQ.u64 = 10777117428; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2081,8 +2181,11 @@ l2cache4.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; @@ -2091,6 +2194,9 @@ l2cache4.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2115,6 +2221,7 @@ l2cache4.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2185,10 +2292,12 @@ l2cache4.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2595; SumSQ.u64 = 2595; Count.u64 = 2595; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2367; SumSQ.u64 = 2367; Count.u64 = 2367; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; @@ -2200,6 +2309,9 @@ l2cache4.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2275,13 +2387,16 @@ l1cache5.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3014; SumSQ.u64 = 3014; Count.u64 = 3014; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2289,7 +2404,7 @@ l1cache5.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4631; SumSQ.u64 = 4631; Count.u64 = 4631; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4632; SumSQ.u64 = 4632; Count.u64 = 4632; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_S : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_M : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_IS : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; @@ -2308,6 +2423,7 @@ l1cache5.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2354,14 +2470,18 @@ l1cache5.mesi.Write_recv : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Inv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337334754; SumSQ.u64 = 10782425724; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2475,8 +2595,11 @@ l2cache5.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2189; SumSQ.u64 = 2189; Count.u64 = 2189; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2546; SumSQ.u64 = 2546; Count.u64 = 2546; Min.u64 = 1; Max.u64 = 1; @@ -2485,6 +2608,9 @@ l2cache5.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2509,6 +2635,7 @@ l2cache5.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2579,10 +2706,12 @@ l2cache5.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2591; SumSQ.u64 = 2591; Count.u64 = 2591; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2360; SumSQ.u64 = 2360; Count.u64 = 2360; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; @@ -2594,6 +2723,9 @@ l2cache5.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2669,13 +2801,16 @@ l1cache6.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 3020; Count.u64 = 3020; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2702,6 +2837,7 @@ l1cache6.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2748,14 +2884,18 @@ l1cache6.mesi.Write_recv : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2636; SumSQ.u64 = 2636; Count.u64 = 2636; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Inv_recv : Accumulator : Sum.u64 = 2128; SumSQ.u64 = 2128; Count.u64 = 2128; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338577163; SumSQ.u64 = 10829397351; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2869,8 +3009,11 @@ l2cache6.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2539; SumSQ.u64 = 2539; Count.u64 = 2539; Min.u64 = 1; Max.u64 = 1; @@ -2879,6 +3022,9 @@ l2cache6.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2903,6 +3049,7 @@ l2cache6.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2973,10 +3120,12 @@ l2cache6.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2620; SumSQ.u64 = 2620; Count.u64 = 2620; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2338; SumSQ.u64 = 2338; Count.u64 = 2338; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 523; SumSQ.u64 = 523; Count.u64 = 523; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; @@ -2988,6 +3137,9 @@ l2cache6.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache6.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3063,13 +3215,16 @@ l1cache7.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2989; SumSQ.u64 = 2989; Count.u64 = 2989; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3077,7 +3232,7 @@ l1cache7.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4516; SumSQ.u64 = 4516; Count.u64 = 4516; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_S : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_M : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_IS : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; @@ -3096,6 +3251,7 @@ l1cache7.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3142,14 +3298,18 @@ l1cache7.mesi.Write_recv : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 2619; Count.u64 = 2619; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Inv_recv : Accumulator : Sum.u64 = 2106; SumSQ.u64 = 2106; Count.u64 = 2106; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 330513517; SumSQ.u64 = 10547396239; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -3263,8 +3423,11 @@ l2cache7.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2215; SumSQ.u64 = 2215; Count.u64 = 2215; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2524; SumSQ.u64 = 2524; Count.u64 = 2524; Min.u64 = 1; Max.u64 = 1; @@ -3273,6 +3436,9 @@ l2cache7.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3297,6 +3463,7 @@ l2cache7.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3367,10 +3534,12 @@ l2cache7.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2604; SumSQ.u64 = 2604; Count.u64 = 2604; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2351; SumSQ.u64 = 2351; Count.u64 = 2351; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; @@ -3382,15 +3551,18 @@ l2cache7.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 301625591; SumSQ.u64 = 8812329585; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 33; l2cache7.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 391656; SumSQ.u64 = 62735766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 391656; SumSQ.u64 = 62735766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 72524; SumSQ.u64 = 145048; Count.u64 = 36262; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 2222459; SumSQ.u64 = 133290561; Count.u64 = 37286; Min.u64 = 37; Max.u64 = 61; @@ -3413,8 +3585,10 @@ directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3433,6 +3607,7 @@ directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; @@ -3443,6 +3618,8 @@ directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 2147887; SumSQ.u64 = 2147887; Count.u64 = 5295879; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out index 0a48c2837c..a124247257 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_2.out @@ -1,7 +1,7 @@ - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 7428512; SumSQ.u64 = 750303000; Count.u64 = 73548; Min.u64 = 101; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 7428512; SumSQ.u64 = 750303000; Count.u64 = 73548; Min.u64 = 101; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 119638; SumSQ.u64 = 119638; Count.u64 = 119638; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 68913; SumSQ.u64 = 68913; Count.u64 = 68913; Min.u64 = 1; Max.u64 = 1; @@ -111,8 +111,11 @@ l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 15039; SumSQ.u64 = 15039; Count.u64 = 15039; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -121,6 +124,9 @@ l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 18898; SumSQ.u64 = 18898; Count.u64 = 18898; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 17480; SumSQ.u64 = 17480; Count.u64 = 17480; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -145,6 +151,7 @@ l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -215,10 +222,12 @@ l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -230,6 +239,9 @@ l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 17479; SumSQ.u64 = 17479; Count.u64 = 17479; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 20268; SumSQ.u64 = 20268; Count.u64 = 20268; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 36262; SumSQ.u64 = 36262; Count.u64 = 36262; Min.u64 = 1; Max.u64 = 1; @@ -305,13 +317,16 @@ l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -338,6 +353,7 @@ l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -384,20 +400,24 @@ l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337477647; SumSQ.u64 = 10785094549; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; l1cache0.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4884; SumSQ.u64 = 4884; Count.u64 = 4884; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4886; SumSQ.u64 = 4886; Count.u64 = 4886; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; @@ -505,8 +525,11 @@ l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2197; SumSQ.u64 = 2197; Count.u64 = 2197; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2540; SumSQ.u64 = 2540; Count.u64 = 2540; Min.u64 = 1; Max.u64 = 1; @@ -515,6 +538,9 @@ l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -539,6 +565,7 @@ l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -609,10 +636,12 @@ l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2596; SumSQ.u64 = 2596; Count.u64 = 2596; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2365; SumSQ.u64 = 2365; Count.u64 = 2365; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; @@ -624,6 +653,9 @@ l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -699,13 +731,16 @@ l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2979; SumSQ.u64 = 2979; Count.u64 = 2979; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -732,6 +767,7 @@ l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,14 +814,18 @@ l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2614; SumSQ.u64 = 2614; Count.u64 = 2614; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 2101; SumSQ.u64 = 2101; Count.u64 = 2101; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338409616; SumSQ.u64 = 10823556192; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -899,8 +939,11 @@ l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2168; SumSQ.u64 = 2168; Count.u64 = 2168; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2553; SumSQ.u64 = 2553; Count.u64 = 2553; Min.u64 = 1; Max.u64 = 1; @@ -909,6 +952,9 @@ l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -933,6 +979,7 @@ l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1003,10 +1050,12 @@ l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2357; SumSQ.u64 = 2357; Count.u64 = 2357; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; @@ -1018,6 +1067,9 @@ l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1093,13 +1145,16 @@ l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2955; SumSQ.u64 = 2955; Count.u64 = 2955; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1107,7 +1162,7 @@ l1cache2.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4600; SumSQ.u64 = 4600; Count.u64 = 4600; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4601; SumSQ.u64 = 4601; Count.u64 = 4601; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_S : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_M : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_IS : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; @@ -1126,6 +1181,7 @@ l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1172,14 +1228,18 @@ l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2574; SumSQ.u64 = 2574; Count.u64 = 2574; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 2065; SumSQ.u64 = 2065; Count.u64 = 2065; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337719688; SumSQ.u64 = 10795953034; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1293,8 +1353,11 @@ l2cache2.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 2492; Count.u64 = 2492; Min.u64 = 1; Max.u64 = 1; @@ -1303,6 +1366,9 @@ l2cache2.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1327,6 +1393,7 @@ l2cache2.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1397,10 +1464,12 @@ l2cache2.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2551; SumSQ.u64 = 2551; Count.u64 = 2551; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; @@ -1412,6 +1481,9 @@ l2cache2.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache2.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1487,13 +1559,16 @@ l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2981; SumSQ.u64 = 2981; Count.u64 = 2981; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1520,6 +1595,7 @@ l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1566,14 +1642,18 @@ l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2598; SumSQ.u64 = 2598; Count.u64 = 2598; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 2142; SumSQ.u64 = 2142; Count.u64 = 2142; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 334138095; SumSQ.u64 = 10675247815; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1687,8 +1767,11 @@ l2cache3.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; @@ -1697,6 +1780,9 @@ l2cache3.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1721,6 +1807,7 @@ l2cache3.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1791,10 +1878,12 @@ l2cache3.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2589; SumSQ.u64 = 2589; Count.u64 = 2589; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 2374; Count.u64 = 2374; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; @@ -1806,6 +1895,9 @@ l2cache3.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1881,13 +1973,16 @@ l1cache4.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1914,6 +2009,7 @@ l1cache4.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,14 +2056,18 @@ l1cache4.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2612; SumSQ.u64 = 2612; Count.u64 = 2612; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Inv_recv : Accumulator : Sum.u64 = 2149; SumSQ.u64 = 2149; Count.u64 = 2149; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337232970; SumSQ.u64 = 10777117428; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2081,8 +2181,11 @@ l2cache4.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; @@ -2091,6 +2194,9 @@ l2cache4.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2115,6 +2221,7 @@ l2cache4.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2185,10 +2292,12 @@ l2cache4.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2595; SumSQ.u64 = 2595; Count.u64 = 2595; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2367; SumSQ.u64 = 2367; Count.u64 = 2367; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; @@ -2200,6 +2309,9 @@ l2cache4.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2275,13 +2387,16 @@ l1cache5.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3014; SumSQ.u64 = 3014; Count.u64 = 3014; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2289,7 +2404,7 @@ l1cache5.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4631; SumSQ.u64 = 4631; Count.u64 = 4631; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4632; SumSQ.u64 = 4632; Count.u64 = 4632; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_S : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_M : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_IS : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; @@ -2308,6 +2423,7 @@ l1cache5.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2354,14 +2470,18 @@ l1cache5.mesi.Write_recv : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Inv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337334754; SumSQ.u64 = 10782425724; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2475,8 +2595,11 @@ l2cache5.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2189; SumSQ.u64 = 2189; Count.u64 = 2189; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2546; SumSQ.u64 = 2546; Count.u64 = 2546; Min.u64 = 1; Max.u64 = 1; @@ -2485,6 +2608,9 @@ l2cache5.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2509,6 +2635,7 @@ l2cache5.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2579,10 +2706,12 @@ l2cache5.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2591; SumSQ.u64 = 2591; Count.u64 = 2591; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2360; SumSQ.u64 = 2360; Count.u64 = 2360; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; @@ -2594,6 +2723,9 @@ l2cache5.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2669,13 +2801,16 @@ l1cache6.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 3020; Count.u64 = 3020; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2702,6 +2837,7 @@ l1cache6.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2748,14 +2884,18 @@ l1cache6.mesi.Write_recv : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2636; SumSQ.u64 = 2636; Count.u64 = 2636; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Inv_recv : Accumulator : Sum.u64 = 2128; SumSQ.u64 = 2128; Count.u64 = 2128; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338577163; SumSQ.u64 = 10829397351; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2869,8 +3009,11 @@ l2cache6.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2539; SumSQ.u64 = 2539; Count.u64 = 2539; Min.u64 = 1; Max.u64 = 1; @@ -2879,6 +3022,9 @@ l2cache6.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2903,6 +3049,7 @@ l2cache6.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2973,10 +3120,12 @@ l2cache6.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2620; SumSQ.u64 = 2620; Count.u64 = 2620; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2338; SumSQ.u64 = 2338; Count.u64 = 2338; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 523; SumSQ.u64 = 523; Count.u64 = 523; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; @@ -2988,6 +3137,9 @@ l2cache6.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache6.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3063,13 +3215,16 @@ l1cache7.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2989; SumSQ.u64 = 2989; Count.u64 = 2989; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3077,7 +3232,7 @@ l1cache7.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4516; SumSQ.u64 = 4516; Count.u64 = 4516; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_S : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_M : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_IS : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; @@ -3096,6 +3251,7 @@ l1cache7.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3142,14 +3298,18 @@ l1cache7.mesi.Write_recv : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 2619; Count.u64 = 2619; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Inv_recv : Accumulator : Sum.u64 = 2106; SumSQ.u64 = 2106; Count.u64 = 2106; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 330513517; SumSQ.u64 = 10547396239; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -3263,8 +3423,11 @@ l2cache7.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2215; SumSQ.u64 = 2215; Count.u64 = 2215; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2524; SumSQ.u64 = 2524; Count.u64 = 2524; Min.u64 = 1; Max.u64 = 1; @@ -3273,6 +3436,9 @@ l2cache7.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3297,6 +3463,7 @@ l2cache7.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3367,10 +3534,12 @@ l2cache7.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2604; SumSQ.u64 = 2604; Count.u64 = 2604; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2351; SumSQ.u64 = 2351; Count.u64 = 2351; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; @@ -3382,15 +3551,18 @@ l2cache7.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 301625591; SumSQ.u64 = 8812329585; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 33; l2cache7.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 397656; SumSQ.u64 = 63911766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 397656; SumSQ.u64 = 63911766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 72524; SumSQ.u64 = 145048; Count.u64 = 36262; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 1573170; SumSQ.u64 = 66380934; Count.u64 = 37286; Min.u64 = 42; Max.u64 = 43; @@ -3413,8 +3585,10 @@ directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3433,6 +3607,7 @@ directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; @@ -3443,6 +3618,8 @@ directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 1498598; SumSQ.u64 = 1498598; Count.u64 = 5295861; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out index 9c8d7f5308..20d1218610 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_3.out @@ -1,7 +1,7 @@ - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 6987248; SumSQ.u64 = 663815256; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 6987248; SumSQ.u64 = 663815256; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 119638; SumSQ.u64 = 119638; Count.u64 = 119638; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 68913; SumSQ.u64 = 68913; Count.u64 = 68913; Min.u64 = 1; Max.u64 = 1; @@ -111,8 +111,11 @@ l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 15039; SumSQ.u64 = 15039; Count.u64 = 15039; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -121,6 +124,9 @@ l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 18898; SumSQ.u64 = 18898; Count.u64 = 18898; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 17480; SumSQ.u64 = 17480; Count.u64 = 17480; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -145,6 +151,7 @@ l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -215,10 +222,12 @@ l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -230,6 +239,9 @@ l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 17479; SumSQ.u64 = 17479; Count.u64 = 17479; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 20268; SumSQ.u64 = 20268; Count.u64 = 20268; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 36262; SumSQ.u64 = 36262; Count.u64 = 36262; Min.u64 = 1; Max.u64 = 1; @@ -305,13 +317,16 @@ l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -338,6 +353,7 @@ l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -384,20 +400,24 @@ l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337477647; SumSQ.u64 = 10785094549; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; l1cache0.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4884; SumSQ.u64 = 4884; Count.u64 = 4884; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4886; SumSQ.u64 = 4886; Count.u64 = 4886; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; @@ -505,8 +525,11 @@ l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2197; SumSQ.u64 = 2197; Count.u64 = 2197; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2540; SumSQ.u64 = 2540; Count.u64 = 2540; Min.u64 = 1; Max.u64 = 1; @@ -515,6 +538,9 @@ l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -539,6 +565,7 @@ l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -609,10 +636,12 @@ l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2596; SumSQ.u64 = 2596; Count.u64 = 2596; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2365; SumSQ.u64 = 2365; Count.u64 = 2365; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; @@ -624,6 +653,9 @@ l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -699,13 +731,16 @@ l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2979; SumSQ.u64 = 2979; Count.u64 = 2979; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -732,6 +767,7 @@ l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,14 +814,18 @@ l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2614; SumSQ.u64 = 2614; Count.u64 = 2614; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 2101; SumSQ.u64 = 2101; Count.u64 = 2101; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338409616; SumSQ.u64 = 10823556192; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -899,8 +939,11 @@ l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2168; SumSQ.u64 = 2168; Count.u64 = 2168; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2553; SumSQ.u64 = 2553; Count.u64 = 2553; Min.u64 = 1; Max.u64 = 1; @@ -909,6 +952,9 @@ l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -933,6 +979,7 @@ l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1003,10 +1050,12 @@ l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2357; SumSQ.u64 = 2357; Count.u64 = 2357; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; @@ -1018,6 +1067,9 @@ l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1093,13 +1145,16 @@ l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2955; SumSQ.u64 = 2955; Count.u64 = 2955; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1107,7 +1162,7 @@ l1cache2.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4600; SumSQ.u64 = 4600; Count.u64 = 4600; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4601; SumSQ.u64 = 4601; Count.u64 = 4601; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_S : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_M : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_IS : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; @@ -1126,6 +1181,7 @@ l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1172,14 +1228,18 @@ l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2574; SumSQ.u64 = 2574; Count.u64 = 2574; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 2065; SumSQ.u64 = 2065; Count.u64 = 2065; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337719688; SumSQ.u64 = 10795953034; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1293,8 +1353,11 @@ l2cache2.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 2492; Count.u64 = 2492; Min.u64 = 1; Max.u64 = 1; @@ -1303,6 +1366,9 @@ l2cache2.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1327,6 +1393,7 @@ l2cache2.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1397,10 +1464,12 @@ l2cache2.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2551; SumSQ.u64 = 2551; Count.u64 = 2551; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; @@ -1412,6 +1481,9 @@ l2cache2.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache2.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1487,13 +1559,16 @@ l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2981; SumSQ.u64 = 2981; Count.u64 = 2981; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1520,6 +1595,7 @@ l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1566,14 +1642,18 @@ l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2598; SumSQ.u64 = 2598; Count.u64 = 2598; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 2142; SumSQ.u64 = 2142; Count.u64 = 2142; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 334138095; SumSQ.u64 = 10675247815; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1687,8 +1767,11 @@ l2cache3.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; @@ -1697,6 +1780,9 @@ l2cache3.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1721,6 +1807,7 @@ l2cache3.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1791,10 +1878,12 @@ l2cache3.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2589; SumSQ.u64 = 2589; Count.u64 = 2589; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 2374; Count.u64 = 2374; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; @@ -1806,6 +1895,9 @@ l2cache3.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1881,13 +1973,16 @@ l1cache4.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1914,6 +2009,7 @@ l1cache4.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,14 +2056,18 @@ l1cache4.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2612; SumSQ.u64 = 2612; Count.u64 = 2612; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Inv_recv : Accumulator : Sum.u64 = 2149; SumSQ.u64 = 2149; Count.u64 = 2149; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337232970; SumSQ.u64 = 10777117428; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2081,8 +2181,11 @@ l2cache4.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; @@ -2091,6 +2194,9 @@ l2cache4.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2115,6 +2221,7 @@ l2cache4.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2185,10 +2292,12 @@ l2cache4.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2595; SumSQ.u64 = 2595; Count.u64 = 2595; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2367; SumSQ.u64 = 2367; Count.u64 = 2367; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; @@ -2200,6 +2309,9 @@ l2cache4.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2275,13 +2387,16 @@ l1cache5.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3014; SumSQ.u64 = 3014; Count.u64 = 3014; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2289,7 +2404,7 @@ l1cache5.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4631; SumSQ.u64 = 4631; Count.u64 = 4631; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4632; SumSQ.u64 = 4632; Count.u64 = 4632; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_S : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_M : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_IS : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; @@ -2308,6 +2423,7 @@ l1cache5.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2354,14 +2470,18 @@ l1cache5.mesi.Write_recv : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Inv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337334754; SumSQ.u64 = 10782425724; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2475,8 +2595,11 @@ l2cache5.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2189; SumSQ.u64 = 2189; Count.u64 = 2189; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2546; SumSQ.u64 = 2546; Count.u64 = 2546; Min.u64 = 1; Max.u64 = 1; @@ -2485,6 +2608,9 @@ l2cache5.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2509,6 +2635,7 @@ l2cache5.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2579,10 +2706,12 @@ l2cache5.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2591; SumSQ.u64 = 2591; Count.u64 = 2591; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2360; SumSQ.u64 = 2360; Count.u64 = 2360; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; @@ -2594,6 +2723,9 @@ l2cache5.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2669,13 +2801,16 @@ l1cache6.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 3020; Count.u64 = 3020; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2702,6 +2837,7 @@ l1cache6.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2748,14 +2884,18 @@ l1cache6.mesi.Write_recv : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2636; SumSQ.u64 = 2636; Count.u64 = 2636; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Inv_recv : Accumulator : Sum.u64 = 2128; SumSQ.u64 = 2128; Count.u64 = 2128; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338577163; SumSQ.u64 = 10829397351; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2869,8 +3009,11 @@ l2cache6.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2539; SumSQ.u64 = 2539; Count.u64 = 2539; Min.u64 = 1; Max.u64 = 1; @@ -2879,6 +3022,9 @@ l2cache6.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2903,6 +3049,7 @@ l2cache6.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2973,10 +3120,12 @@ l2cache6.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2620; SumSQ.u64 = 2620; Count.u64 = 2620; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2338; SumSQ.u64 = 2338; Count.u64 = 2338; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 523; SumSQ.u64 = 523; Count.u64 = 523; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; @@ -2988,6 +3137,9 @@ l2cache6.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache6.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3063,13 +3215,16 @@ l1cache7.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2989; SumSQ.u64 = 2989; Count.u64 = 2989; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3077,7 +3232,7 @@ l1cache7.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4516; SumSQ.u64 = 4516; Count.u64 = 4516; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_S : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_M : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_IS : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; @@ -3096,6 +3251,7 @@ l1cache7.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3142,14 +3298,18 @@ l1cache7.mesi.Write_recv : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 2619; Count.u64 = 2619; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Inv_recv : Accumulator : Sum.u64 = 2106; SumSQ.u64 = 2106; Count.u64 = 2106; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 330513517; SumSQ.u64 = 10547396239; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -3263,8 +3423,11 @@ l2cache7.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2215; SumSQ.u64 = 2215; Count.u64 = 2215; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2524; SumSQ.u64 = 2524; Count.u64 = 2524; Min.u64 = 1; Max.u64 = 1; @@ -3273,6 +3436,9 @@ l2cache7.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3297,6 +3463,7 @@ l2cache7.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3367,10 +3534,12 @@ l2cache7.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2604; SumSQ.u64 = 2604; Count.u64 = 2604; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2351; SumSQ.u64 = 2351; Count.u64 = 2351; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; @@ -3382,15 +3551,18 @@ l2cache7.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 301625591; SumSQ.u64 = 8812329585; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 33; l2cache7.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 391656; SumSQ.u64 = 62735766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 391656; SumSQ.u64 = 62735766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 72524; SumSQ.u64 = 145048; Count.u64 = 36262; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 1830455; SumSQ.u64 = 89878083; Count.u64 = 37286; Min.u64 = 48; Max.u64 = 59; @@ -3413,8 +3585,10 @@ directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3433,6 +3607,7 @@ directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; @@ -3443,6 +3618,8 @@ directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 1755883; SumSQ.u64 = 1755883; Count.u64 = 5295867; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out index 27ea86a4fa..2e7bdbb236 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendTimingDRAM_4.out @@ -1,7 +1,7 @@ - l3cache.mesi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 6987248; SumSQ.u64 = 663815256; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 142; - l3cache.mesi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - l3cache.mesi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.mesi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; + l3cache.mesi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 6987248; SumSQ.u64 = 663815256; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 142; + l3cache.mesi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 12407040; SumSQ.u64 = 5229232128; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + l3cache.mesi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 168500; SumSQ.u64 = 12364750000; Count.u64 = 3; Min.u64 = 22500; Max.u64 = 97500; l3cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 119638; SumSQ.u64 = 119638; Count.u64 = 119638; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 68913; SumSQ.u64 = 68913; Count.u64 = 68913; Min.u64 = 1; Max.u64 = 1; @@ -111,8 +111,11 @@ l3cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 15039; SumSQ.u64 = 15039; Count.u64 = 15039; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -121,6 +124,9 @@ l3cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 18898; SumSQ.u64 = 18898; Count.u64 = 18898; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 17480; SumSQ.u64 = 17480; Count.u64 = 17480; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -145,6 +151,7 @@ l3cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -215,10 +222,12 @@ l3cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -230,6 +239,9 @@ l3cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 17479; SumSQ.u64 = 17479; Count.u64 = 17479; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l3cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 20268; SumSQ.u64 = 20268; Count.u64 = 20268; Min.u64 = 1; Max.u64 = 1; l3cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 36262; SumSQ.u64 = 36262; Count.u64 = 36262; Min.u64 = 1; Max.u64 = 1; @@ -305,13 +317,16 @@ l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -338,6 +353,7 @@ l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -384,20 +400,24 @@ l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337477647; SumSQ.u64 = 10785094549; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; l1cache0.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4884; SumSQ.u64 = 4884; Count.u64 = 4884; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.evict_I : Accumulator : Sum.u64 = 4886; SumSQ.u64 = 4886; Count.u64 = 4886; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.evict_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; @@ -505,8 +525,11 @@ l2cache0.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2197; SumSQ.u64 = 2197; Count.u64 = 2197; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2540; SumSQ.u64 = 2540; Count.u64 = 2540; Min.u64 = 1; Max.u64 = 1; @@ -515,6 +538,9 @@ l2cache0.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -539,6 +565,7 @@ l2cache0.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -609,10 +636,12 @@ l2cache0.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2596; SumSQ.u64 = 2596; Count.u64 = 2596; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2365; SumSQ.u64 = 2365; Count.u64 = 2365; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; @@ -624,6 +653,9 @@ l2cache0.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2138; SumSQ.u64 = 2138; Count.u64 = 2138; Min.u64 = 1; Max.u64 = 1; l2cache0.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -699,13 +731,16 @@ l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2979; SumSQ.u64 = 2979; Count.u64 = 2979; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -732,6 +767,7 @@ l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,14 +814,18 @@ l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2614; SumSQ.u64 = 2614; Count.u64 = 2614; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 2101; SumSQ.u64 = 2101; Count.u64 = 2101; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338409616; SumSQ.u64 = 10823556192; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -899,8 +939,11 @@ l2cache1.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2168; SumSQ.u64 = 2168; Count.u64 = 2168; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2553; SumSQ.u64 = 2553; Count.u64 = 2553; Min.u64 = 1; Max.u64 = 1; @@ -909,6 +952,9 @@ l2cache1.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 1409; Count.u64 = 1409; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -933,6 +979,7 @@ l2cache1.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1003,10 +1050,12 @@ l2cache1.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2357; SumSQ.u64 = 2357; Count.u64 = 2357; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; @@ -1018,6 +1067,9 @@ l2cache1.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2098; SumSQ.u64 = 2098; Count.u64 = 2098; Min.u64 = 1; Max.u64 = 1; l2cache1.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1093,13 +1145,16 @@ l1cache2.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2955; SumSQ.u64 = 2955; Count.u64 = 2955; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1107,7 +1162,7 @@ l1cache2.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4600; SumSQ.u64 = 4600; Count.u64 = 4600; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.evict_I : Accumulator : Sum.u64 = 4601; SumSQ.u64 = 4601; Count.u64 = 4601; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_S : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_M : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.evict_IS : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; @@ -1126,6 +1181,7 @@ l1cache2.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1172,14 +1228,18 @@ l1cache2.mesi.Write_recv : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2574; SumSQ.u64 = 2574; Count.u64 = 2574; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Inv_recv : Accumulator : Sum.u64 = 2065; SumSQ.u64 = 2065; Count.u64 = 2065; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l1cache2.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache2.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337719688; SumSQ.u64 = 10795953034; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1293,8 +1353,11 @@ l2cache2.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 2492; Count.u64 = 2492; Min.u64 = 1; Max.u64 = 1; @@ -1303,6 +1366,9 @@ l2cache2.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1327,6 +1393,7 @@ l2cache2.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1397,10 +1464,12 @@ l2cache2.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2551; SumSQ.u64 = 2551; Count.u64 = 2551; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2386; SumSQ.u64 = 2386; Count.u64 = 2386; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; @@ -1412,6 +1481,9 @@ l2cache2.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache2.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2058; SumSQ.u64 = 2058; Count.u64 = 2058; Min.u64 = 1; Max.u64 = 1; l2cache2.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1487,13 +1559,16 @@ l1cache3.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2981; SumSQ.u64 = 2981; Count.u64 = 2981; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1520,6 +1595,7 @@ l1cache3.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1566,14 +1642,18 @@ l1cache3.mesi.Write_recv : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2598; SumSQ.u64 = 2598; Count.u64 = 2598; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Inv_recv : Accumulator : Sum.u64 = 2142; SumSQ.u64 = 2142; Count.u64 = 2142; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l1cache3.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache3.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 334138095; SumSQ.u64 = 10675247815; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -1687,8 +1767,11 @@ l2cache3.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; @@ -1697,6 +1780,9 @@ l2cache3.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2392; SumSQ.u64 = 2392; Count.u64 = 2392; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1721,6 +1807,7 @@ l2cache3.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1791,10 +1878,12 @@ l2cache3.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2589; SumSQ.u64 = 2589; Count.u64 = 2589; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 2374; Count.u64 = 2374; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; @@ -1806,6 +1895,9 @@ l2cache3.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache3.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; l2cache3.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1881,13 +1973,16 @@ l1cache4.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2982; SumSQ.u64 = 2982; Count.u64 = 2982; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1914,6 +2009,7 @@ l1cache4.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,14 +2056,18 @@ l1cache4.mesi.Write_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2612; SumSQ.u64 = 2612; Count.u64 = 2612; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Inv_recv : Accumulator : Sum.u64 = 2149; SumSQ.u64 = 2149; Count.u64 = 2149; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache4.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache4.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337232970; SumSQ.u64 = 10777117428; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2081,8 +2181,11 @@ l2cache4.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2181; SumSQ.u64 = 2181; Count.u64 = 2181; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; @@ -2091,6 +2194,9 @@ l2cache4.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2376; SumSQ.u64 = 2376; Count.u64 = 2376; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2115,6 +2221,7 @@ l2cache4.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2185,10 +2292,12 @@ l2cache4.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2595; SumSQ.u64 = 2595; Count.u64 = 2595; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2367; SumSQ.u64 = 2367; Count.u64 = 2367; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; @@ -2200,6 +2309,9 @@ l2cache4.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache4.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2145; SumSQ.u64 = 2145; Count.u64 = 2145; Min.u64 = 1; Max.u64 = 1; l2cache4.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2275,13 +2387,16 @@ l1cache5.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3014; SumSQ.u64 = 3014; Count.u64 = 3014; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2289,7 +2404,7 @@ l1cache5.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4631; SumSQ.u64 = 4631; Count.u64 = 4631; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.evict_I : Accumulator : Sum.u64 = 4632; SumSQ.u64 = 4632; Count.u64 = 4632; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_S : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_M : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.evict_IS : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; @@ -2308,6 +2423,7 @@ l1cache5.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2354,14 +2470,18 @@ l1cache5.mesi.Write_recv : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2610; SumSQ.u64 = 2610; Count.u64 = 2610; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Inv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l1cache5.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache5.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 337334754; SumSQ.u64 = 10782425724; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2475,8 +2595,11 @@ l2cache5.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2189; SumSQ.u64 = 2189; Count.u64 = 2189; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2546; SumSQ.u64 = 2546; Count.u64 = 2546; Min.u64 = 1; Max.u64 = 1; @@ -2485,6 +2608,9 @@ l2cache5.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2509,6 +2635,7 @@ l2cache5.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2579,10 +2706,12 @@ l2cache5.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2591; SumSQ.u64 = 2591; Count.u64 = 2591; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2360; SumSQ.u64 = 2360; Count.u64 = 2360; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 529; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; @@ -2594,6 +2723,9 @@ l2cache5.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache5.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 2094; Count.u64 = 2094; Min.u64 = 1; Max.u64 = 1; l2cache5.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2669,13 +2801,16 @@ l1cache6.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 3020; Count.u64 = 3020; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2702,6 +2837,7 @@ l1cache6.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2748,14 +2884,18 @@ l1cache6.mesi.Write_recv : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2636; SumSQ.u64 = 2636; Count.u64 = 2636; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Inv_recv : Accumulator : Sum.u64 = 2128; SumSQ.u64 = 2128; Count.u64 = 2128; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l1cache6.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache6.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 338577163; SumSQ.u64 = 10829397351; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -2869,8 +3009,11 @@ l2cache6.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2143; SumSQ.u64 = 2143; Count.u64 = 2143; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2539; SumSQ.u64 = 2539; Count.u64 = 2539; Min.u64 = 1; Max.u64 = 1; @@ -2879,6 +3022,9 @@ l2cache6.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2903,6 +3049,7 @@ l2cache6.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2973,10 +3120,12 @@ l2cache6.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2620; SumSQ.u64 = 2620; Count.u64 = 2620; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2338; SumSQ.u64 = 2338; Count.u64 = 2338; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 523; SumSQ.u64 = 523; Count.u64 = 523; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; @@ -2988,6 +3137,9 @@ l2cache6.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache6.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2127; SumSQ.u64 = 2127; Count.u64 = 2127; Min.u64 = 1; Max.u64 = 1; l2cache6.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3063,13 +3215,16 @@ l1cache7.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2989; SumSQ.u64 = 2989; Count.u64 = 2989; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3077,7 +3232,7 @@ l1cache7.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4515; SumSQ.u64 = 4515; Count.u64 = 4515; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.evict_I : Accumulator : Sum.u64 = 4516; SumSQ.u64 = 4516; Count.u64 = 4516; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_S : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_M : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.evict_IS : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; @@ -3096,6 +3251,7 @@ l1cache7.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3142,14 +3298,18 @@ l1cache7.mesi.Write_recv : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.GetSResp_recv : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 2619; Count.u64 = 2619; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.GetXResp_recv : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Inv_recv : Accumulator : Sum.u64 = 2106; SumSQ.u64 = 2106; Count.u64 = 2106; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.FetchInv_recv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l1cache7.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache7.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 330513517; SumSQ.u64 = 10547396239; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 32; @@ -3263,8 +3423,11 @@ l2cache7.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2215; SumSQ.u64 = 2215; Count.u64 = 2215; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2524; SumSQ.u64 = 2524; Count.u64 = 2524; Min.u64 = 1; Max.u64 = 1; @@ -3273,6 +3436,9 @@ l2cache7.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2371; SumSQ.u64 = 2371; Count.u64 = 2371; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3297,6 +3463,7 @@ l2cache7.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3367,10 +3534,12 @@ l2cache7.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2604; SumSQ.u64 = 2604; Count.u64 = 2604; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2351; SumSQ.u64 = 2351; Count.u64 = 2351; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; @@ -3382,15 +3551,18 @@ l2cache7.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache7.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; l2cache7.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.mesi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 301625591; SumSQ.u64 = 8812329585; Count.u64 = 10592085; Min.u64 = 0; Max.u64 = 33; l2cache7.mesi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; - directory.mesi:cpulink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; - directory.mesi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.mesi:cpulink.idle_time : Accumulator : Sum.u64 = 391656; SumSQ.u64 = 62735766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; + directory.mesi:highlink.packet_latency : Accumulator : Sum.u64 = 8899204; SumSQ.u64 = 1076793804; Count.u64 = 73548; Min.u64 = 95; Max.u64 = 121; + directory.mesi:highlink.send_bit_count : Accumulator : Sum.u64 = 31497472; SumSQ.u64 = 17447108608; Count.u64 = 73548; Min.u64 = 64; Max.u64 = 576; + directory.mesi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi:highlink.idle_time : Accumulator : Sum.u64 = 391656; SumSQ.u64 = 62735766336; Count.u64 = 3; Min.u64 = 78656; Max.u64 = 218000; directory.mesi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.replacement_request_latency : Accumulator : Sum.u64 = 72524; SumSQ.u64 = 145048; Count.u64 = 36262; Min.u64 = 2; Max.u64 = 2; directory.mesi.get_request_latency : Accumulator : Sum.u64 = 1826610; SumSQ.u64 = 89484498; Count.u64 = 37286; Min.u64 = 48; Max.u64 = 49; @@ -3413,8 +3585,10 @@ directory.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3433,6 +3607,7 @@ directory.mesi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 37286; SumSQ.u64 = 37286; Count.u64 = 37286; Min.u64 = 1; Max.u64 = 1; @@ -3443,6 +3618,8 @@ directory.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.mesi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 1752038; SumSQ.u64 = 1752038; Count.u64 = 5295867; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out index 8ad3ecc44e..97629e002b 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_BackendVaultSim.out @@ -72,13 +72,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3023; SumSQ.u64 = 3023; Count.u64 = 3023; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1977; SumSQ.u64 = 1977; Count.u64 = 1977; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -142,14 +146,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 1977; SumSQ.u64 = 1977; Count.u64 = 1977; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 3010; SumSQ.u64 = 3010; Count.u64 = 3010; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 167840767; SumSQ.u64 = 5363409691; Count.u64 = 5288964; Min.u64 = 0; Max.u64 = 32; @@ -224,13 +232,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3001; SumSQ.u64 = 3001; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1999; SumSQ.u64 = 1999; Count.u64 = 1999; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -257,6 +268,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -294,14 +306,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 1999; SumSQ.u64 = 1999; Count.u64 = 1999; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 2988; SumSQ.u64 = 2988; Count.u64 = 2988; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 168508784; SumSQ.u64 = 5385179050; Count.u64 = 5288964; Min.u64 = 0; Max.u64 = 32; @@ -415,8 +431,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 5468; SumSQ.u64 = 5468; Count.u64 = 5468; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3596; SumSQ.u64 = 3596; Count.u64 = 3596; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; @@ -425,6 +444,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3972; SumSQ.u64 = 3972; Count.u64 = 3972; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -449,6 +471,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -484,10 +507,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 5831; SumSQ.u64 = 5831; Count.u64 = 5831; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3924; SumSQ.u64 = 3924; Count.u64 = 3924; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5907; SumSQ.u64 = 5907; Count.u64 = 5907; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3889; SumSQ.u64 = 3889; Count.u64 = 3889; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -499,6 +524,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -574,13 +602,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 3010; SumSQ.u64 = 3010; Count.u64 = 3010; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1990; SumSQ.u64 = 1990; Count.u64 = 1990; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -607,6 +638,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -644,14 +676,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 1990; SumSQ.u64 = 1990; Count.u64 = 1990; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 3004; SumSQ.u64 = 3004; Count.u64 = 3004; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 1987; SumSQ.u64 = 1987; Count.u64 = 1987; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 168405398; SumSQ.u64 = 5380586918; Count.u64 = 5288964; Min.u64 = 0; Max.u64 = 32; @@ -726,13 +762,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2969; SumSQ.u64 = 2969; Count.u64 = 2969; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2031; SumSQ.u64 = 2031; Count.u64 = 2031; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -759,6 +798,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -796,14 +836,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 2031; SumSQ.u64 = 2031; Count.u64 = 2031; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 2959; SumSQ.u64 = 2959; Count.u64 = 2959; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 2029; SumSQ.u64 = 2029; Count.u64 = 2029; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 169025603; SumSQ.u64 = 5404968919; Count.u64 = 5288964; Min.u64 = 0; Max.u64 = 32; @@ -917,8 +961,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 5440; SumSQ.u64 = 5440; Count.u64 = 5440; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3633; SumSQ.u64 = 3633; Count.u64 = 3633; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; @@ -927,6 +974,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 4016; SumSQ.u64 = 4016; Count.u64 = 4016; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -951,6 +1001,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -986,10 +1037,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 5809; SumSQ.u64 = 5809; Count.u64 = 5809; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3972; SumSQ.u64 = 3972; Count.u64 = 3972; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5870; SumSQ.u64 = 5870; Count.u64 = 5870; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3919; SumSQ.u64 = 3919; Count.u64 = 3919; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1001,15 +1054,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 320447547; SumSQ.u64 = 19464670783; Count.u64 = 5288964; Min.u64 = 0; Max.u64 = 65; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 5324545; SumSQ.u64 = 772059025; Count.u64 = 36721; Min.u64 = 145; Max.u64 = 145; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 6123584; SumSQ.u64 = 2565410816; Count.u64 = 36721; Min.u64 = 64; Max.u64 = 576; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 33146500000; Count.u64 = 2; Min.u64 = 40500; Max.u64 = 177500; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 5324545; SumSQ.u64 = 772059025; Count.u64 = 36721; Min.u64 = 145; Max.u64 = 145; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 6123584; SumSQ.u64 = 2565410816; Count.u64 = 36721; Min.u64 = 64; Max.u64 = 576; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 33146500000; Count.u64 = 2; Min.u64 = 40500; Max.u64 = 177500; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1119,8 +1175,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 10347; SumSQ.u64 = 10347; Count.u64 = 10347; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 7370; SumSQ.u64 = 7370; Count.u64 = 7370; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1129,6 +1188,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 7896; SumSQ.u64 = 7896; Count.u64 = 7896; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1153,6 +1215,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 352; SumSQ.u64 = 352; Count.u64 = 352; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1188,10 +1251,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 11221; SumSQ.u64 = 11221; Count.u64 = 11221; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 7783; SumSQ.u64 = 7783; Count.u64 = 7783; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 10908; SumSQ.u64 = 10908; Count.u64 = 10908; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 7229; SumSQ.u64 = 7229; Count.u64 = 7229; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1203,15 +1268,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 17717; SumSQ.u64 = 17717; Count.u64 = 17717; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 637293650; SumSQ.u64 = 77043155098; Count.u64 = 5288964; Min.u64 = 0; Max.u64 = 128; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 4149473; SumSQ.u64 = 468890449; Count.u64 = 36721; Min.u64 = 113; Max.u64 = 113; - directory.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 15718976; SumSQ.u64 = 8706461696; Count.u64 = 36721; Min.u64 = 64; Max.u64 = 576; - directory.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.idle_time : Accumulator : Sum.u64 = 427000; SumSQ.u64 = 102869000000; Count.u64 = 2; Min.u64 = 137000; Max.u64 = 290000; + directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 4149473; SumSQ.u64 = 468890449; Count.u64 = 36721; Min.u64 = 113; Max.u64 = 113; + directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 15718976; SumSQ.u64 = 8706461696; Count.u64 = 36721; Min.u64 = 64; Max.u64 = 576; + directory.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi:highlink.idle_time : Accumulator : Sum.u64 = 427000; SumSQ.u64 = 102869000000; Count.u64 = 2; Min.u64 = 137000; Max.u64 = 290000; directory.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.replacement_request_latency : Accumulator : Sum.u64 = 35434; SumSQ.u64 = 70868; Count.u64 = 17717; Min.u64 = 2; Max.u64 = 2; directory.msi.get_request_latency : Accumulator : Sum.u64 = 1331137; SumSQ.u64 = 94474433; Count.u64 = 19004; Min.u64 = 2; Max.u64 = 71; @@ -1234,8 +1302,10 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1254,6 +1324,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 11221; SumSQ.u64 = 11221; Count.u64 = 11221; Min.u64 = 1; Max.u64 = 1; directory.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 7783; SumSQ.u64 = 7783; Count.u64 = 7783; Min.u64 = 1; Max.u64 = 1; @@ -1264,6 +1335,8 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1293129; SumSQ.u64 = 1293129; Count.u64 = 2644201; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CoherenceDomains.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CoherenceDomains.out index 67b8d8ce19..54b49de064 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CoherenceDomains.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CoherenceDomains.out @@ -1,10 +1,10 @@ n0.core0.pendCycle : Accumulator : Sum.u64 = 24996862; SumSQ.u64 = 399580550; Count.u64 = 1566589; Min.u64 = 0; Max.u64 = 16; n0.core0.reads : Accumulator : Sum.u64 = 2953; SumSQ.u64 = 2953; Count.u64 = 2953; Min.u64 = 1; Max.u64 = 1; n0.core0.writes : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; - n0.l1cache0:memlink.packet_latency : Accumulator : Sum.u64 = 5316594; SumSQ.u64 = 5754085908; Count.u64 = 7132; Min.u64 = 37; Max.u64 = 2232; - n0.l1cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 977792; SumSQ.u64 = 347408384; Count.u64 = 7119; Min.u64 = 64; Max.u64 = 576; - n0.l1cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 43357000; SumSQ.u64 = 4514557000000; Count.u64 = 480; Min.u64 = 63500; Max.u64 = 216000; - n0.l1cache0:memlink.idle_time : Accumulator : Sum.u64 = 137849500; SumSQ.u64 = 22026008750000; Count.u64 = 1290; Min.u64 = 51000; Max.u64 = 641500; + n0.l1cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 5316594; SumSQ.u64 = 5754085908; Count.u64 = 7132; Min.u64 = 37; Max.u64 = 2232; + n0.l1cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 977792; SumSQ.u64 = 347408384; Count.u64 = 7119; Min.u64 = 64; Max.u64 = 576; + n0.l1cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 43357000; SumSQ.u64 = 4514557000000; Count.u64 = 480; Min.u64 = 63500; Max.u64 = 216000; + n0.l1cache0:lowlink.idle_time : Accumulator : Sum.u64 = 137849500; SumSQ.u64 = 22026008750000; Count.u64 = 1290; Min.u64 = 51000; Max.u64 = 641500; n0.l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; @@ -72,13 +72,16 @@ n0.l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + n0.l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 2953; SumSQ.u64 = 2953; Count.u64 = 2953; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ n0.l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -142,14 +146,18 @@ n0.l1cache0.Write_recv : Accumulator : Sum.u64 = 1009; SumSQ.u64 = 1009; Count.u64 = 1009; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.Inv_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + n0.l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache0.AckPut_recv : Accumulator : Sum.u64 = 2179; SumSQ.u64 = 2179; Count.u64 = 2179; Min.u64 = 1; Max.u64 = 1; n0.l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 12649164; SumSQ.u64 = 111679102; Count.u64 = 1582573; Min.u64 = 0; Max.u64 = 15; @@ -157,10 +165,10 @@ n0.core1.pendCycle : Accumulator : Sum.u64 = 24945573; SumSQ.u64 = 398668213; Count.u64 = 1567741; Min.u64 = 0; Max.u64 = 16; n0.core1.reads : Accumulator : Sum.u64 = 3009; SumSQ.u64 = 3009; Count.u64 = 3009; Min.u64 = 1; Max.u64 = 1; n0.core1.writes : Accumulator : Sum.u64 = 1991; SumSQ.u64 = 1991; Count.u64 = 1991; Min.u64 = 1; Max.u64 = 1; - n0.l1cache1:memlink.packet_latency : Accumulator : Sum.u64 = 5430588; SumSQ.u64 = 5908606242; Count.u64 = 7169; Min.u64 = 37; Max.u64 = 2232; - n0.l1cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 971456; SumSQ.u64 = 342480896; Count.u64 = 7156; Min.u64 = 64; Max.u64 = 576; - n0.l1cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 37821500; SumSQ.u64 = 3941512750000; Count.u64 = 423; Min.u64 = 60000; Max.u64 = 216000; - n0.l1cache1:memlink.idle_time : Accumulator : Sum.u64 = 140901000; SumSQ.u64 = 22719988000000; Count.u64 = 1329; Min.u64 = 58000; Max.u64 = 648000; + n0.l1cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 5430588; SumSQ.u64 = 5908606242; Count.u64 = 7169; Min.u64 = 37; Max.u64 = 2232; + n0.l1cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 971456; SumSQ.u64 = 342480896; Count.u64 = 7156; Min.u64 = 64; Max.u64 = 576; + n0.l1cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 37821500; SumSQ.u64 = 3941512750000; Count.u64 = 423; Min.u64 = 60000; Max.u64 = 216000; + n0.l1cache1:lowlink.idle_time : Accumulator : Sum.u64 = 140901000; SumSQ.u64 = 22719988000000; Count.u64 = 1329; Min.u64 = 58000; Max.u64 = 648000; n0.l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1388; SumSQ.u64 = 1388; Count.u64 = 1388; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; @@ -228,13 +236,16 @@ n0.l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + n0.l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3009; SumSQ.u64 = 3009; Count.u64 = 3009; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1991; SumSQ.u64 = 1991; Count.u64 = 1991; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -261,6 +272,7 @@ n0.l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -298,14 +310,18 @@ n0.l1cache1.Write_recv : Accumulator : Sum.u64 = 985; SumSQ.u64 = 985; Count.u64 = 985; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 1388; SumSQ.u64 = 1388; Count.u64 = 1388; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.Inv_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + n0.l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l1cache1.AckPut_recv : Accumulator : Sum.u64 = 2178; SumSQ.u64 = 2178; Count.u64 = 2178; Min.u64 = 1; Max.u64 = 1; n0.l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 12509221; SumSQ.u64 = 110051433; Count.u64 = 1582573; Min.u64 = 0; Max.u64 = 15; @@ -313,10 +329,10 @@ n1.core0.pendCycle : Accumulator : Sum.u64 = 25273037; SumSQ.u64 = 404130293; Count.u64 = 1582573; Min.u64 = 0; Max.u64 = 16; n1.core0.reads : Accumulator : Sum.u64 = 3051; SumSQ.u64 = 3051; Count.u64 = 3051; Min.u64 = 1; Max.u64 = 1; n1.core0.writes : Accumulator : Sum.u64 = 1949; SumSQ.u64 = 1949; Count.u64 = 1949; Min.u64 = 1; Max.u64 = 1; - n1.l1cache0:memlink.packet_latency : Accumulator : Sum.u64 = 5523584; SumSQ.u64 = 6067968188; Count.u64 = 7194; Min.u64 = 37; Max.u64 = 2304; - n1.l1cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 964224; SumSQ.u64 = 337747968; Count.u64 = 7178; Min.u64 = 64; Max.u64 = 576; - n1.l1cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 44445500; SumSQ.u64 = 4572059750000; Count.u64 = 499; Min.u64 = 52500; Max.u64 = 216000; - n1.l1cache0:memlink.idle_time : Accumulator : Sum.u64 = 139755000; SumSQ.u64 = 22503901500000; Count.u64 = 1291; Min.u64 = 60000; Max.u64 = 648000; + n1.l1cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 5523584; SumSQ.u64 = 6067968188; Count.u64 = 7194; Min.u64 = 37; Max.u64 = 2304; + n1.l1cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 964224; SumSQ.u64 = 337747968; Count.u64 = 7178; Min.u64 = 64; Max.u64 = 576; + n1.l1cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 44445500; SumSQ.u64 = 4572059750000; Count.u64 = 499; Min.u64 = 52500; Max.u64 = 216000; + n1.l1cache0:lowlink.idle_time : Accumulator : Sum.u64 = 139755000; SumSQ.u64 = 22503901500000; Count.u64 = 1291; Min.u64 = 60000; Max.u64 = 648000; n1.l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; @@ -384,13 +400,16 @@ n1.l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + n1.l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3051; SumSQ.u64 = 3051; Count.u64 = 3051; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1949; SumSQ.u64 = 1949; Count.u64 = 1949; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -417,6 +436,7 @@ n1.l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -454,14 +474,18 @@ n1.l1cache0.Write_recv : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 953; SumSQ.u64 = 953; Count.u64 = 953; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.Inv_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + n1.l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache0.AckPut_recv : Accumulator : Sum.u64 = 2235; SumSQ.u64 = 2235; Count.u64 = 2235; Min.u64 = 1; Max.u64 = 1; n1.l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 13176755; SumSQ.u64 = 119385413; Count.u64 = 1582573; Min.u64 = 0; Max.u64 = 15; @@ -469,10 +493,10 @@ n1.core1.pendCycle : Accumulator : Sum.u64 = 25207524; SumSQ.u64 = 403032682; Count.u64 = 1577965; Min.u64 = 0; Max.u64 = 16; n1.core1.reads : Accumulator : Sum.u64 = 3037; SumSQ.u64 = 3037; Count.u64 = 3037; Min.u64 = 1; Max.u64 = 1; n1.core1.writes : Accumulator : Sum.u64 = 1963; SumSQ.u64 = 1963; Count.u64 = 1963; Min.u64 = 1; Max.u64 = 1; - n1.l1cache1:memlink.packet_latency : Accumulator : Sum.u64 = 5419791; SumSQ.u64 = 5913138573; Count.u64 = 7154; Min.u64 = 37; Max.u64 = 2160; - n1.l1cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 982720; SumSQ.u64 = 351262720; Count.u64 = 7140; Min.u64 = 64; Max.u64 = 576; - n1.l1cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 43796000; SumSQ.u64 = 4329004500000; Count.u64 = 504; Min.u64 = 58000; Max.u64 = 216000; - n1.l1cache1:memlink.idle_time : Accumulator : Sum.u64 = 142866500; SumSQ.u64 = 25637534750000; Count.u64 = 1307; Min.u64 = 58000; Max.u64 = 1581000; + n1.l1cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 5419791; SumSQ.u64 = 5913138573; Count.u64 = 7154; Min.u64 = 37; Max.u64 = 2160; + n1.l1cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 982720; SumSQ.u64 = 351262720; Count.u64 = 7140; Min.u64 = 64; Max.u64 = 576; + n1.l1cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 43796000; SumSQ.u64 = 4329004500000; Count.u64 = 504; Min.u64 = 58000; Max.u64 = 216000; + n1.l1cache1:lowlink.idle_time : Accumulator : Sum.u64 = 142866500; SumSQ.u64 = 25637534750000; Count.u64 = 1307; Min.u64 = 58000; Max.u64 = 1581000; n1.l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; @@ -540,13 +564,16 @@ n1.l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + n1.l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3037; SumSQ.u64 = 3037; Count.u64 = 3037; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1963; SumSQ.u64 = 1963; Count.u64 = 1963; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -573,6 +600,7 @@ n1.l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -610,22 +638,26 @@ n1.l1cache1.Write_recv : Accumulator : Sum.u64 = 1021; SumSQ.u64 = 1021; Count.u64 = 1021; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.Inv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + n1.l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l1cache1.AckPut_recv : Accumulator : Sum.u64 = 2184; SumSQ.u64 = 2184; Count.u64 = 2184; Min.u64 = 1; Max.u64 = 1; n1.l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 12802021; SumSQ.u64 = 113534479; Count.u64 = 1582573; Min.u64 = 0; Max.u64 = 15; n1.l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - n0.directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 8170140; SumSQ.u64 = 10750474238; Count.u64 = 7049; Min.u64 = 60; Max.u64 = 2520; - n0.directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 2173728; SumSQ.u64 = 1094292480; Count.u64 = 7060; Min.u64 = 64; Max.u64 = 576; - n0.directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 18119000; SumSQ.u64 = 1714595000000; Count.u64 = 218; Min.u64 = 37000; Max.u64 = 216000; - n0.directory0:cpulink.idle_time : Accumulator : Sum.u64 = 170142500; SumSQ.u64 = 35124081250000; Count.u64 = 1566; Min.u64 = 37000; Max.u64 = 1699500; + n0.directory0:highlink.packet_latency : Accumulator : Sum.u64 = 8170140; SumSQ.u64 = 10750474238; Count.u64 = 7049; Min.u64 = 60; Max.u64 = 2520; + n0.directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 2173728; SumSQ.u64 = 1094292480; Count.u64 = 7060; Min.u64 = 64; Max.u64 = 576; + n0.directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 18119000; SumSQ.u64 = 1714595000000; Count.u64 = 218; Min.u64 = 37000; Max.u64 = 216000; + n0.directory0:highlink.idle_time : Accumulator : Sum.u64 = 170142500; SumSQ.u64 = 35124081250000; Count.u64 = 1566; Min.u64 = 37000; Max.u64 = 1699500; n0.directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.replacement_request_latency : Accumulator : Sum.u64 = 4370; SumSQ.u64 = 8740; Count.u64 = 2185; Min.u64 = 2; Max.u64 = 2; n0.directory0.get_request_latency : Accumulator : Sum.u64 = 530365; SumSQ.u64 = 841139489; Count.u64 = 2360; Min.u64 = 2; Max.u64 = 6627; @@ -648,8 +680,10 @@ n0.directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.AckInv_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + n0.directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 1468; SumSQ.u64 = 1468; Count.u64 = 1468; Min.u64 = 1; Max.u64 = 1; n0.directory0.Write_uncache_recv : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; @@ -668,6 +702,7 @@ n0.directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; n0.directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; n0.directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 2839; SumSQ.u64 = 2839; Count.u64 = 2839; Min.u64 = 1; Max.u64 = 1; n0.directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; @@ -678,13 +713,15 @@ n0.directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory0.MSHR_occupancy : Accumulator : Sum.u64 = 525645; SumSQ.u64 = 831621; Count.u64 = 789443; Min.u64 = 0; Max.u64 = 5; - n0.directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 8253521; SumSQ.u64 = 10889542859; Count.u64 = 7120; Min.u64 = 62; Max.u64 = 2514; - n0.directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 2157152; SumSQ.u64 = 1078645760; Count.u64 = 7135; Min.u64 = 64; Max.u64 = 576; - n0.directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 27306000; SumSQ.u64 = 2556108000000; Count.u64 = 332; Min.u64 = 37000; Max.u64 = 216000; - n0.directory1:cpulink.idle_time : Accumulator : Sum.u64 = 153363500; SumSQ.u64 = 32265994250000; Count.u64 = 1409; Min.u64 = 37000; Max.u64 = 1267500; + n0.directory1:highlink.packet_latency : Accumulator : Sum.u64 = 8253521; SumSQ.u64 = 10889542859; Count.u64 = 7120; Min.u64 = 62; Max.u64 = 2514; + n0.directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 2157152; SumSQ.u64 = 1078645760; Count.u64 = 7135; Min.u64 = 64; Max.u64 = 576; + n0.directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 27306000; SumSQ.u64 = 2556108000000; Count.u64 = 332; Min.u64 = 37000; Max.u64 = 216000; + n0.directory1:highlink.idle_time : Accumulator : Sum.u64 = 153363500; SumSQ.u64 = 32265994250000; Count.u64 = 1409; Min.u64 = 37000; Max.u64 = 1267500; n0.directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.replacement_request_latency : Accumulator : Sum.u64 = 4344; SumSQ.u64 = 8688; Count.u64 = 2172; Min.u64 = 2; Max.u64 = 2; n0.directory1.get_request_latency : Accumulator : Sum.u64 = 471682; SumSQ.u64 = 680947334; Count.u64 = 2330; Min.u64 = 2; Max.u64 = 5763; @@ -707,8 +744,10 @@ n0.directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.AckInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + n0.directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 1548; SumSQ.u64 = 1548; Count.u64 = 1548; Min.u64 = 1; Max.u64 = 1; n0.directory1.Write_uncache_recv : Accumulator : Sum.u64 = 985; SumSQ.u64 = 985; Count.u64 = 985; Min.u64 = 1; Max.u64 = 1; @@ -727,6 +766,7 @@ n0.directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; n0.directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; n0.directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 2927; SumSQ.u64 = 2927; Count.u64 = 2927; Min.u64 = 1; Max.u64 = 1; n0.directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 951; SumSQ.u64 = 951; Count.u64 = 951; Min.u64 = 1; Max.u64 = 1; @@ -737,13 +777,15 @@ n0.directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.directory1.MSHR_occupancy : Accumulator : Sum.u64 = 467022; SumSQ.u64 = 724672; Count.u64 = 789875; Min.u64 = 0; Max.u64 = 5; - n1.directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 8431799; SumSQ.u64 = 11184229867; Count.u64 = 7242; Min.u64 = 64; Max.u64 = 2448; - n1.directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 2204064; SumSQ.u64 = 1104583680; Count.u64 = 7255; Min.u64 = 64; Max.u64 = 576; - n1.directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 34336000; SumSQ.u64 = 3115810000000; Count.u64 = 420; Min.u64 = 37000; Max.u64 = 216000; - n1.directory0:cpulink.idle_time : Accumulator : Sum.u64 = 138073500; SumSQ.u64 = 25877666250000; Count.u64 = 1317; Min.u64 = 37000; Max.u64 = 790000; + n1.directory0:highlink.packet_latency : Accumulator : Sum.u64 = 8431799; SumSQ.u64 = 11184229867; Count.u64 = 7242; Min.u64 = 64; Max.u64 = 2448; + n1.directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 2204064; SumSQ.u64 = 1104583680; Count.u64 = 7255; Min.u64 = 64; Max.u64 = 576; + n1.directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 34336000; SumSQ.u64 = 3115810000000; Count.u64 = 420; Min.u64 = 37000; Max.u64 = 216000; + n1.directory0:highlink.idle_time : Accumulator : Sum.u64 = 138073500; SumSQ.u64 = 25877666250000; Count.u64 = 1317; Min.u64 = 37000; Max.u64 = 790000; n1.directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.replacement_request_latency : Accumulator : Sum.u64 = 4452; SumSQ.u64 = 8904; Count.u64 = 2226; Min.u64 = 2; Max.u64 = 2; n1.directory0.get_request_latency : Accumulator : Sum.u64 = 542350; SumSQ.u64 = 921817394; Count.u64 = 2398; Min.u64 = 2; Max.u64 = 5115; @@ -766,8 +808,10 @@ n1.directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.AckInv_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + n1.directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 1543; SumSQ.u64 = 1543; Count.u64 = 1543; Min.u64 = 1; Max.u64 = 1; n1.directory0.Write_uncache_recv : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; @@ -786,6 +830,7 @@ n1.directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; n1.directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; n1.directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 2961; SumSQ.u64 = 2961; Count.u64 = 2961; Min.u64 = 1; Max.u64 = 1; n1.directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; @@ -796,13 +841,15 @@ n1.directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory0.MSHR_occupancy : Accumulator : Sum.u64 = 537554; SumSQ.u64 = 898380; Count.u64 = 791069; Min.u64 = 0; Max.u64 = 5; - n1.directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 8426785; SumSQ.u64 = 11278172469; Count.u64 = 7182; Min.u64 = 64; Max.u64 = 2448; - n1.directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 2168800; SumSQ.u64 = 1084048384; Count.u64 = 7199; Min.u64 = 64; Max.u64 = 576; - n1.directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 18326000; SumSQ.u64 = 1742894000000; Count.u64 = 219; Min.u64 = 37000; Max.u64 = 216000; - n1.directory1:cpulink.idle_time : Accumulator : Sum.u64 = 158369500; SumSQ.u64 = 28791851250000; Count.u64 = 1537; Min.u64 = 37000; Max.u64 = 1660500; + n1.directory1:highlink.packet_latency : Accumulator : Sum.u64 = 8426785; SumSQ.u64 = 11278172469; Count.u64 = 7182; Min.u64 = 64; Max.u64 = 2448; + n1.directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 2168800; SumSQ.u64 = 1084048384; Count.u64 = 7199; Min.u64 = 64; Max.u64 = 576; + n1.directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 18326000; SumSQ.u64 = 1742894000000; Count.u64 = 219; Min.u64 = 37000; Max.u64 = 216000; + n1.directory1:highlink.idle_time : Accumulator : Sum.u64 = 158369500; SumSQ.u64 = 28791851250000; Count.u64 = 1537; Min.u64 = 37000; Max.u64 = 1660500; n1.directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.replacement_request_latency : Accumulator : Sum.u64 = 4386; SumSQ.u64 = 8772; Count.u64 = 2193; Min.u64 = 2; Max.u64 = 2; n1.directory1.get_request_latency : Accumulator : Sum.u64 = 489930; SumSQ.u64 = 656666406; Count.u64 = 2369; Min.u64 = 2; Max.u64 = 5187; @@ -825,8 +872,10 @@ n1.directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.AckInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + n1.directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 1437; SumSQ.u64 = 1437; Count.u64 = 1437; Min.u64 = 1; Max.u64 = 1; n1.directory1.Write_uncache_recv : Accumulator : Sum.u64 = 1076; SumSQ.u64 = 1076; Count.u64 = 1076; Min.u64 = 1; Max.u64 = 1; @@ -845,6 +894,7 @@ n1.directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; n1.directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; n1.directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 2841; SumSQ.u64 = 2841; Count.u64 = 2841; Min.u64 = 1; Max.u64 = 1; n1.directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; @@ -855,6 +905,8 @@ n1.directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.directory1.MSHR_occupancy : Accumulator : Sum.u64 = 485192; SumSQ.u64 = 739450; Count.u64 = 789517; Min.u64 = 0; Max.u64 = 5; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out index 15af10cea8..919d170c87 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_1.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 13959; SumSQ.u64 = 13959; Count.u64 = 13959; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 2502; SumSQ.u64 = 2502; Count.u64 = 2502; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 59500; SumSQ.u64 = 257484; Count.u64 = 18813; Min.u64 = 0; Max.u64 = 16; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_2.out index bd7b7085cc..1b3d9d63d2 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_2.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 33787; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out index d79ce10d54..44e1c97da0 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_CustomCmdGoblin_3.out @@ -32,107 +32,107 @@ l2cache_12: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. l2cache_14: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. - router.send_bit_count.port0 : Accumulator : Sum.u64 = 223936; SumSQ.u64 = 110964736; Count.u64 = 635; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port0 : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port0 : Accumulator : Sum.u64 = 224576; SumSQ.u64 = 111300608; Count.u64 = 637; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port0 : Accumulator : Sum.u64 = 637; SumSQ.u64 = 637; Count.u64 = 637; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port0 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port0 : Accumulator : Sum.u64 = 4443423; SumSQ.u64 = 239027107893; Count.u64 = 549; Min.u64 = 166; Max.u64 = 142843; + router.idle_time.port0 : Accumulator : Sum.u64 = 4956087; SumSQ.u64 = 362740004367; Count.u64 = 528; Min.u64 = 126; Max.u64 = 178277; router.width_adj_count.port0 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port1 : Accumulator : Sum.u64 = 224192; SumSQ.u64 = 110981120; Count.u64 = 639; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port1 : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port1 : Accumulator : Sum.u64 = 224832; SumSQ.u64 = 111316992; Count.u64 = 641; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port1 : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port1 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port1 : Accumulator : Sum.u64 = 4443091; SumSQ.u64 = 327685848263; Count.u64 = 511; Min.u64 = 156; Max.u64 = 168905; + router.idle_time.port1 : Accumulator : Sum.u64 = 4955715; SumSQ.u64 = 440251351275; Count.u64 = 484; Min.u64 = 126; Max.u64 = 181922; router.width_adj_count.port1 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port2 : Accumulator : Sum.u64 = 226496; SumSQ.u64 = 112308224; Count.u64 = 643; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port2 : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port2 : Accumulator : Sum.u64 = 226560; SumSQ.u64 = 112312320; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port2 : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port2 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port2 : Accumulator : Sum.u64 = 4440103; SumSQ.u64 = 326408097791; Count.u64 = 503; Min.u64 = 156; Max.u64 = 163261; + router.idle_time.port2 : Accumulator : Sum.u64 = 4953204; SumSQ.u64 = 437038194836; Count.u64 = 501; Min.u64 = 126; Max.u64 = 172633; router.width_adj_count.port2 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port3 : Accumulator : Sum.u64 = 227328; SumSQ.u64 = 112656384; Count.u64 = 648; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port3 : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port3 : Accumulator : Sum.u64 = 227520; SumSQ.u64 = 112668672; Count.u64 = 651; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port3 : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port3 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port3 : Accumulator : Sum.u64 = 4439024; SumSQ.u64 = 347763969718; Count.u64 = 517; Min.u64 = 166; Max.u64 = 165502; + router.idle_time.port3 : Accumulator : Sum.u64 = 4951809; SumSQ.u64 = 433078776651; Count.u64 = 515; Min.u64 = 126; Max.u64 = 178277; router.width_adj_count.port3 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port4 : Accumulator : Sum.u64 = 225536; SumSQ.u64 = 111656960; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port4 : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port4 : Accumulator : Sum.u64 = 224960; SumSQ.u64 = 111325184; Count.u64 = 643; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port4 : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port4 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port4 : Accumulator : Sum.u64 = 4441348; SumSQ.u64 = 193486948542; Count.u64 = 540; Min.u64 = 166; Max.u64 = 119852; + router.idle_time.port4 : Accumulator : Sum.u64 = 4955529; SumSQ.u64 = 255867602815; Count.u64 = 540; Min.u64 = 119; Max.u64 = 146073; router.width_adj_count.port4 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port5 : Accumulator : Sum.u64 = 225856; SumSQ.u64 = 111972352; Count.u64 = 641; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port5 : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port5 : Accumulator : Sum.u64 = 226560; SumSQ.u64 = 112312320; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port5 : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port5 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port5 : Accumulator : Sum.u64 = 4440933; SumSQ.u64 = 381028173787; Count.u64 = 500; Min.u64 = 156; Max.u64 = 162099; + router.idle_time.port5 : Accumulator : Sum.u64 = 4953204; SumSQ.u64 = 397287699842; Count.u64 = 497; Min.u64 = 125; Max.u64 = 181016; router.width_adj_count.port5 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port6 : Accumulator : Sum.u64 = 228928; SumSQ.u64 = 113643520; Count.u64 = 649; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port6 : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port6 : Accumulator : Sum.u64 = 226688; SumSQ.u64 = 112320512; Count.u64 = 646; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port6 : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port6 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port6 : Accumulator : Sum.u64 = 4436949; SumSQ.u64 = 196370020199; Count.u64 = 558; Min.u64 = 166; Max.u64 = 113803; + router.idle_time.port6 : Accumulator : Sum.u64 = 4953018; SumSQ.u64 = 414581828338; Count.u64 = 522; Min.u64 = 126; Max.u64 = 180933; router.width_adj_count.port6 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port7 : Accumulator : Sum.u64 = 226816; SumSQ.u64 = 112328704; Count.u64 = 648; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port7 : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port7 : Accumulator : Sum.u64 = 227968; SumSQ.u64 = 112992256; Count.u64 = 650; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port7 : Accumulator : Sum.u64 = 650; SumSQ.u64 = 650; Count.u64 = 650; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port7 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port7 : Accumulator : Sum.u64 = 4439688; SumSQ.u64 = 332339824244; Count.u64 = 520; Min.u64 = 156; Max.u64 = 151807; + router.idle_time.port7 : Accumulator : Sum.u64 = 4951158; SumSQ.u64 = 504480691634; Count.u64 = 494; Min.u64 = 126; Max.u64 = 193770; router.width_adj_count.port7 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port8 : Accumulator : Sum.u64 = 223680; SumSQ.u64 = 110653440; Count.u64 = 639; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port8 : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port8 : Accumulator : Sum.u64 = 224896; SumSQ.u64 = 111321088; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port8 : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port8 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port8 : Accumulator : Sum.u64 = 4443755; SumSQ.u64 = 219137292533; Count.u64 = 540; Min.u64 = 166; Max.u64 = 122674; + router.idle_time.port8 : Accumulator : Sum.u64 = 4955622; SumSQ.u64 = 201529095192; Count.u64 = 551; Min.u64 = 126; Max.u64 = 120177; router.width_adj_count.port8 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port9 : Accumulator : Sum.u64 = 226432; SumSQ.u64 = 112304128; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port9 : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port9 : Accumulator : Sum.u64 = 225600; SumSQ.u64 = 111661056; Count.u64 = 645; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port9 : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port9 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port9 : Accumulator : Sum.u64 = 4440186; SumSQ.u64 = 362143332142; Count.u64 = 480; Min.u64 = 156; Max.u64 = 165834; + router.idle_time.port9 : Accumulator : Sum.u64 = 4954599; SumSQ.u64 = 435300459465; Count.u64 = 482; Min.u64 = 126; Max.u64 = 172019; router.width_adj_count.port9 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port10 : Accumulator : Sum.u64 = 224384; SumSQ.u64 = 110993408; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port10 : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port10 : Accumulator : Sum.u64 = 223680; SumSQ.u64 = 110653440; Count.u64 = 639; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port10 : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port10 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port10 : Accumulator : Sum.u64 = 4442842; SumSQ.u64 = 187280489618; Count.u64 = 534; Min.u64 = 166; Max.u64 = 123688; + router.idle_time.port10 : Accumulator : Sum.u64 = 4957389; SumSQ.u64 = 476318298789; Count.u64 = 514; Min.u64 = 146; Max.u64 = 177268; router.width_adj_count.port10 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port11 : Accumulator : Sum.u64 = 227648; SumSQ.u64 = 112971776; Count.u64 = 645; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port11 : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port11 : Accumulator : Sum.u64 = 227584; SumSQ.u64 = 112967680; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port11 : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port11 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port11 : Accumulator : Sum.u64 = 4438609; SumSQ.u64 = 266535417319; Count.u64 = 493; Min.u64 = 156; Max.u64 = 145997; + router.idle_time.port11 : Accumulator : Sum.u64 = 4951716; SumSQ.u64 = 495337384294; Count.u64 = 470; Min.u64 = 126; Max.u64 = 178692; router.width_adj_count.port11 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port12 : Accumulator : Sum.u64 = 225984; SumSQ.u64 = 111980544; Count.u64 = 643; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port12 : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port12 : Accumulator : Sum.u64 = 224256; SumSQ.u64 = 110985216; Count.u64 = 640; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port12 : Accumulator : Sum.u64 = 640; SumSQ.u64 = 640; Count.u64 = 640; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port12 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port12 : Accumulator : Sum.u64 = 4440767; SumSQ.u64 = 280461894031; Count.u64 = 547; Min.u64 = 166; Max.u64 = 151226; + router.idle_time.port12 : Accumulator : Sum.u64 = 4956552; SumSQ.u64 = 373307150776; Count.u64 = 511; Min.u64 = 126; Max.u64 = 185650; router.width_adj_count.port12 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port13 : Accumulator : Sum.u64 = 226688; SumSQ.u64 = 112320512; Count.u64 = 646; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port13 : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port13 : Accumulator : Sum.u64 = 225920; SumSQ.u64 = 111976448; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port13 : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port13 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port13 : Accumulator : Sum.u64 = 4439854; SumSQ.u64 = 363378316434; Count.u64 = 501; Min.u64 = 156; Max.u64 = 159775; + router.idle_time.port13 : Accumulator : Sum.u64 = 4954134; SumSQ.u64 = 344478468446; Count.u64 = 509; Min.u64 = 119; Max.u64 = 167155; router.width_adj_count.port13 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port14 : Accumulator : Sum.u64 = 227136; SumSQ.u64 = 112644096; Count.u64 = 645; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port14 : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port14 : Accumulator : Sum.u64 = 226048; SumSQ.u64 = 111984640; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port14 : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port14 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port14 : Accumulator : Sum.u64 = 4439273; SumSQ.u64 = 323471369913; Count.u64 = 536; Min.u64 = 156; Max.u64 = 142511; + router.idle_time.port14 : Accumulator : Sum.u64 = 4953948; SumSQ.u64 = 224153503416; Count.u64 = 531; Min.u64 = 126; Max.u64 = 112126; router.width_adj_count.port14 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port15 : Accumulator : Sum.u64 = 228480; SumSQ.u64 = 113319936; Count.u64 = 650; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port15 : Accumulator : Sum.u64 = 650; SumSQ.u64 = 650; Count.u64 = 650; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port15 : Accumulator : Sum.u64 = 227840; SumSQ.u64 = 112984064; Count.u64 = 648; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port15 : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port15 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port15 : Accumulator : Sum.u64 = 4437530; SumSQ.u64 = 258283405908; Count.u64 = 500; Min.u64 = 166; Max.u64 = 147076; + router.idle_time.port15 : Accumulator : Sum.u64 = 4951344; SumSQ.u64 = 355501944718; Count.u64 = 501; Min.u64 = 126; Max.u64 = 159187; router.width_adj_count.port15 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.send_bit_count.port16 : Accumulator : Sum.u64 = 1049792; SumSQ.u64 = 149073920; Count.u64 = 10299; Min.u64 = 64; Max.u64 = 576; - router.send_packet_count.port16 : Accumulator : Sum.u64 = 10299; SumSQ.u64 = 10299; Count.u64 = 10299; Min.u64 = 1; Max.u64 = 1; + router.send_bit_count.port16 : Accumulator : Sum.u64 = 1048960; SumSQ.u64 = 148430848; Count.u64 = 10302; Min.u64 = 64; Max.u64 = 576; + router.send_packet_count.port16 : Accumulator : Sum.u64 = 10302; SumSQ.u64 = 10302; Count.u64 = 10302; Min.u64 = 1; Max.u64 = 1; router.output_port_stalls.port16 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.idle_time.port16 : Accumulator : Sum.u64 = 3372391; SumSQ.u64 = 3870722549; Count.u64 = 6211; Min.u64 = 93; Max.u64 = 14543; + router.idle_time.port16 : Accumulator : Sum.u64 = 3758154; SumSQ.u64 = 4309616042; Count.u64 = 6606; Min.u64 = 96; Max.u64 = 8778; router.width_adj_count.port16 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - router.xbar_stalls.port0 : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port1 : Accumulator : Sum.u64 = 631; SumSQ.u64 = 631; Count.u64 = 631; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port2 : Accumulator : Sum.u64 = 538; SumSQ.u64 = 538; Count.u64 = 538; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port3 : Accumulator : Sum.u64 = 548; SumSQ.u64 = 548; Count.u64 = 548; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port4 : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port5 : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port6 : Accumulator : Sum.u64 = 548; SumSQ.u64 = 548; Count.u64 = 548; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port7 : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port8 : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port9 : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port10 : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port11 : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port12 : Accumulator : Sum.u64 = 575; SumSQ.u64 = 575; Count.u64 = 575; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port13 : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port14 : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; - router.xbar_stalls.port15 : Accumulator : Sum.u64 = 647; SumSQ.u64 = 647; Count.u64 = 647; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port0 : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port1 : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port2 : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port3 : Accumulator : Sum.u64 = 595; SumSQ.u64 = 595; Count.u64 = 595; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port4 : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port5 : Accumulator : Sum.u64 = 566; SumSQ.u64 = 566; Count.u64 = 566; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port6 : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port7 : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port8 : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port9 : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port10 : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port11 : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port12 : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port13 : Accumulator : Sum.u64 = 598; SumSQ.u64 = 598; Count.u64 = 598; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port14 : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; + router.xbar_stalls.port15 : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; router.xbar_stalls.port16 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu0.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu0.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -140,26 +140,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu0.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu0.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu0.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu0.cycles_with_issue : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; - cpu0.cycles_no_issue : Accumulator : Sum.u64 = 11475; SumSQ.u64 = 11475; Count.u64 = 11475; Min.u64 = 1; Max.u64 = 1; + cpu0.cycles_with_issue : Accumulator : Sum.u64 = 613; SumSQ.u64 = 613; Count.u64 = 613; Min.u64 = 1; Max.u64 = 1; + cpu0.cycles_no_issue : Accumulator : Sum.u64 = 12748; SumSQ.u64 = 12748; Count.u64 = 12748; Min.u64 = 1; Max.u64 = 1; cpu0.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu0.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu0.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu0.req_latency : Accumulator : Sum.u64 = 124587; SumSQ.u64 = 23885585; Count.u64 = 936; Min.u64 = 2; Max.u64 = 996; - cpu0.time : Accumulator : Sum.u64 = 4546; SumSQ.u64 = 20666116; Count.u64 = 1; Min.u64 = 4546; Max.u64 = 4546; + cpu0.req_latency : Accumulator : Sum.u64 = 139273; SumSQ.u64 = 29166693; Count.u64 = 936; Min.u64 = 2; Max.u64 = 624; + cpu0.time : Accumulator : Sum.u64 = 5024; SumSQ.u64 = 25240576; Count.u64 = 1; Min.u64 = 5024; Max.u64 = 5024; cpu0.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu0.cycles_max_issue : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - cpu0.cycles_max_reorder : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - cpu0.cycles : Accumulator : Sum.u64 = 12093; SumSQ.u64 = 12093; Count.u64 = 12093; Min.u64 = 1; Max.u64 = 1; + cpu0.cycles_max_issue : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + cpu0.cycles_max_reorder : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + cpu0.cycles : Accumulator : Sum.u64 = 13362; SumSQ.u64 = 13362; Count.u64 = 13362; Min.u64 = 1; Max.u64 = 1; l1cache_0.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l1cache_0.prefetches_issued : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l1cache_0.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_0.prefetches_canceled_by_history : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache_0.Prefetch_requests : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; - l1cache_0.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; - l1cache_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_0.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -167,8 +167,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache_0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -216,7 +216,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.eventSent_GetS : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l1cache_0.eventSent_GetS : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -224,13 +224,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -245,8 +248,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.latency_GetS_hit : Accumulator : Sum.u64 = 119032; SumSQ.u64 = 61794592; Count.u64 = 454; Min.u64 = 1; Max.u64 = 2263; - l1cache_0.latency_GetS_miss : Accumulator : Sum.u64 = 106068; SumSQ.u64 = 59945990; Count.u64 = 314; Min.u64 = 11; Max.u64 = 2646; + l1cache_0.latency_GetS_hit : Accumulator : Sum.u64 = 132934; SumSQ.u64 = 71304786; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1661; + l1cache_0.latency_GetS_miss : Accumulator : Sum.u64 = 119558; SumSQ.u64 = 74213214; Count.u64 = 314; Min.u64 = 13; Max.u64 = 1672; l1cache_0.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -257,10 +260,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l1cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.GetSHit_Blocked : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l1cache_0.GetSHit_Blocked : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSMiss_Arrival : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; @@ -269,27 +273,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.CacheHits : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache_0.CacheHits : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; l1cache_0.CacheMisses : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l1cache_0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.prefetch_useful : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache_0.prefetch_useful : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l1cache_0.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.prefetch_redundant : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; - l1cache_0.stateEvent_GetS_E : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache_0.prefetch_redundant : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache_0.stateEvent_GetS_E : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; l1cache_0.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_0.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.TotalEventsReceived : Accumulator : Sum.u64 = 1666; SumSQ.u64 = 1666; Count.u64 = 1666; Min.u64 = 1; Max.u64 = 1; - l1cache_0.TotalEventsReplayed : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l1cache_0.TotalEventsReceived : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; + l1cache_0.TotalEventsReplayed : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l1cache_0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -308,30 +312,34 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache_0.NACK_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; + l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.NACK_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; l1cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 221337; SumSQ.u64 = 4220463; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 248709; SumSQ.u64 = 4818997; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.packet_latency : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 635; Min.u64 = 0; Max.u64 = 1; - l2cache_0.send_bit_count : Accumulator : Sum.u64 = 62656; SumSQ.u64 = 7745536; Count.u64 = 635; Min.u64 = 64; Max.u64 = 576; - l2cache_0.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.idle_time : Accumulator : Sum.u64 = 3038858; SumSQ.u64 = 167895612606; Count.u64 = 647; Min.u64 = 4; Max.u64 = 116871; - l2cache_0.prefetch_opportunities : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; - l2cache_0.prefetches_issued : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; - l2cache_0.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache_0:lowlink.packet_latency : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 637; Min.u64 = 0; Max.u64 = 1; + l2cache_0:lowlink.send_bit_count : Accumulator : Sum.u64 = 63296; SumSQ.u64 = 8081408; Count.u64 = 637; Min.u64 = 64; Max.u64 = 576; + l2cache_0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.idle_time : Accumulator : Sum.u64 = 3504309; SumSQ.u64 = 264885907753; Count.u64 = 644; Min.u64 = 2; Max.u64 = 170821; + l2cache_0.prefetch_opportunities : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; + l2cache_0.prefetches_issued : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; + l2cache_0.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache_0.prefetches_canceled_by_history : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.Prefetch_requests : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; - l2cache_0.Prefetch_drops : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l2cache_0.Prefetch_requests : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; + l2cache_0.Prefetch_drops : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l2cache_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.evict_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_0.evict_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -344,8 +352,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; - l2cache_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; + l2cache_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -353,7 +361,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -433,26 +441,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.eventSent_GetS : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_0.eventSent_GetS : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.eventSent_NACK : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; - l2cache_0.eventSent_GetSResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache_0.eventSent_NACK : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; + l2cache_0.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.eventSent_FetchInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_0.eventSent_FetchInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -460,8 +474,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.latency_GetS_hit : Accumulator : Sum.u64 = 2869; SumSQ.u64 = 413571; Count.u64 = 140; Min.u64 = 1; Max.u64 = 305; - l2cache_0.latency_GetS_miss : Accumulator : Sum.u64 = 94423; SumSQ.u64 = 46619437; Count.u64 = 196; Min.u64 = 65; Max.u64 = 992; + l2cache_0.latency_GetS_hit : Accumulator : Sum.u64 = 3243; SumSQ.u64 = 694613; Count.u64 = 144; Min.u64 = 1; Max.u64 = 443; + l2cache_0.latency_GetS_miss : Accumulator : Sum.u64 = 102409; SumSQ.u64 = 56373221; Count.u64 = 190; Min.u64 = 65; Max.u64 = 890; l2cache_0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -473,30 +487,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.GetSHit_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache_0.GetSHit_Blocked : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.GetSMiss_Arrival : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_0.GetSMiss_Arrival : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.CacheHits : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l2cache_0.CacheMisses : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_0.CacheHits : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache_0.CacheMisses : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_0.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.prefetch_useful : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; + l2cache_0.prefetch_useful : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l2cache_0.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.prefetch_redundant : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_0.prefetch_redundant : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.stateEvent_GetS_E : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache_0.stateEvent_GetS_E : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -513,7 +528,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -523,13 +538,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.TotalEventsReceived : Accumulator : Sum.u64 = 1365; SumSQ.u64 = 1365; Count.u64 = 1365; Min.u64 = 1; Max.u64 = 1; - l2cache_0.TotalEventsReplayed : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache_0.TotalEventsReceived : Accumulator : Sum.u64 = 1479; SumSQ.u64 = 1479; Count.u64 = 1479; Min.u64 = 1; Max.u64 = 1; + l2cache_0.TotalEventsReplayed : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache_0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -542,16 +557,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.GetS_recv : Accumulator : Sum.u64 = 633; SumSQ.u64 = 633; Count.u64 = 633; Min.u64 = 1; Max.u64 = 1; + l2cache_0.GetS_recv : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -560,13 +577,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 156745; SumSQ.u64 = 2106403; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 177438; SumSQ.u64 = 2432276; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu1.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu1.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -574,22 +594,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu1.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu1.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu1.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu1.cycles_with_issue : Accumulator : Sum.u64 = 650; SumSQ.u64 = 650; Count.u64 = 650; Min.u64 = 1; Max.u64 = 1; - cpu1.cycles_no_issue : Accumulator : Sum.u64 = 11901; SumSQ.u64 = 11901; Count.u64 = 11901; Min.u64 = 1; Max.u64 = 1; + cpu1.cycles_with_issue : Accumulator : Sum.u64 = 659; SumSQ.u64 = 659; Count.u64 = 659; Min.u64 = 1; Max.u64 = 1; + cpu1.cycles_no_issue : Accumulator : Sum.u64 = 13382; SumSQ.u64 = 13382; Count.u64 = 13382; Min.u64 = 1; Max.u64 = 1; cpu1.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu1.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu1.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu1.req_latency : Accumulator : Sum.u64 = 126873; SumSQ.u64 = 21409919; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 412; - cpu1.time : Accumulator : Sum.u64 = 4719; SumSQ.u64 = 22268961; Count.u64 = 1; Min.u64 = 4719; Max.u64 = 4719; + cpu1.req_latency : Accumulator : Sum.u64 = 143155; SumSQ.u64 = 27109645; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 288; + cpu1.time : Accumulator : Sum.u64 = 5279; SumSQ.u64 = 27867841; Count.u64 = 1; Min.u64 = 5279; Max.u64 = 5279; cpu1.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu1.cycles_max_issue : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + cpu1.cycles_max_issue : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; cpu1.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu1.cycles : Accumulator : Sum.u64 = 12552; SumSQ.u64 = 12552; Count.u64 = 12552; Min.u64 = 1; Max.u64 = 1; + cpu1.cycles : Accumulator : Sum.u64 = 14042; SumSQ.u64 = 14042; Count.u64 = 14042; Min.u64 = 1; Max.u64 = 1; l1cache_1.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_1.prefetches_issued : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; - l1cache_1.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache_1.prefetches_canceled_by_history : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; - l1cache_1.Prefetch_requests : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l1cache_1.prefetches_issued : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; + l1cache_1.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_1.prefetches_canceled_by_history : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache_1.Prefetch_requests : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; l1cache_1.Prefetch_drops : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -650,7 +670,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.eventSent_GetS : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + l1cache_1.eventSent_GetS : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -658,13 +678,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -679,8 +702,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.latency_GetS_hit : Accumulator : Sum.u64 = 153038; SumSQ.u64 = 64993102; Count.u64 = 814; Min.u64 = 1; Max.u64 = 704; - l1cache_1.latency_GetS_miss : Accumulator : Sum.u64 = 85194; SumSQ.u64 = 40037830; Count.u64 = 316; Min.u64 = 13; Max.u64 = 1094; + l1cache_1.latency_GetS_hit : Accumulator : Sum.u64 = 173531; SumSQ.u64 = 82331015; Count.u64 = 812; Min.u64 = 1; Max.u64 = 595; + l1cache_1.latency_GetS_miss : Accumulator : Sum.u64 = 96500; SumSQ.u64 = 50817686; Count.u64 = 316; Min.u64 = 13; Max.u64 = 764; l1cache_1.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -691,10 +714,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; + l1cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.GetSHit_Blocked : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; + l1cache_1.GetSHit_Blocked : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -703,27 +727,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.CacheHits : Accumulator : Sum.u64 = 814; SumSQ.u64 = 814; Count.u64 = 814; Min.u64 = 1; Max.u64 = 1; + l1cache_1.CacheHits : Accumulator : Sum.u64 = 812; SumSQ.u64 = 812; Count.u64 = 812; Min.u64 = 1; Max.u64 = 1; l1cache_1.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.prefetch_useful : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache_1.prefetch_useful : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l1cache_1.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.prefetch_redundant : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; - l1cache_1.stateEvent_GetS_E : Accumulator : Sum.u64 = 814; SumSQ.u64 = 814; Count.u64 = 814; Min.u64 = 1; Max.u64 = 1; + l1cache_1.prefetch_redundant : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l1cache_1.stateEvent_GetS_E : Accumulator : Sum.u64 = 812; SumSQ.u64 = 812; Count.u64 = 812; Min.u64 = 1; Max.u64 = 1; l1cache_1.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_1.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.TotalEventsReceived : Accumulator : Sum.u64 = 1892; SumSQ.u64 = 1892; Count.u64 = 1892; Min.u64 = 1; Max.u64 = 1; - l1cache_1.TotalEventsReplayed : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; + l1cache_1.TotalEventsReceived : Accumulator : Sum.u64 = 1916; SumSQ.u64 = 1916; Count.u64 = 1916; Min.u64 = 1; Max.u64 = 1; + l1cache_1.TotalEventsReplayed : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; l1cache_1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -736,36 +760,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.GetS_recv : Accumulator : Sum.u64 = 1133; SumSQ.u64 = 1133; Count.u64 = 1133; Min.u64 = 1; Max.u64 = 1; + l1cache_1.GetS_recv : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache_1.NACK_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.NACK_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 232045; SumSQ.u64 = 4392657; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 263875; SumSQ.u64 = 5090343; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 23; l1cache_1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.packet_latency : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 639; Min.u64 = 0; Max.u64 = 1; - l2cache_1.send_bit_count : Accumulator : Sum.u64 = 64448; SumSQ.u64 = 8744960; Count.u64 = 639; Min.u64 = 64; Max.u64 = 576; - l2cache_1.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.idle_time : Accumulator : Sum.u64 = 3270687; SumSQ.u64 = 239975817837; Count.u64 = 641; Min.u64 = 5; Max.u64 = 161003; - l2cache_1.prefetch_opportunities : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; - l2cache_1.prefetches_issued : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; - l2cache_1.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; - l2cache_1.prefetches_canceled_by_history : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l2cache_1.Prefetch_requests : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; + l2cache_1:lowlink.packet_latency : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 641; Min.u64 = 0; Max.u64 = 1; + l2cache_1:lowlink.send_bit_count : Accumulator : Sum.u64 = 65088; SumSQ.u64 = 9080832; Count.u64 = 641; Min.u64 = 64; Max.u64 = 576; + l2cache_1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.idle_time : Accumulator : Sum.u64 = 3709723; SumSQ.u64 = 341569039063; Count.u64 = 632; Min.u64 = 5; Max.u64 = 170210; + l2cache_1.prefetch_opportunities : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + l2cache_1.prefetches_issued : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l2cache_1.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache_1.prefetches_canceled_by_history : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_1.Prefetch_requests : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; l2cache_1.Prefetch_drops : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.evict_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_1.evict_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,8 +806,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; - l2cache_1.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; + l2cache_1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -787,7 +815,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -867,26 +895,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.eventSent_GetS : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_1.eventSent_GetS : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.eventSent_NACK : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_1.eventSent_NACK : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.eventSent_FetchInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_1.eventSent_FetchInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -894,8 +928,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.latency_GetS_hit : Accumulator : Sum.u64 = 3223; SumSQ.u64 = 563561; Count.u64 = 162; Min.u64 = 1; Max.u64 = 409; - l2cache_1.latency_GetS_miss : Accumulator : Sum.u64 = 78696; SumSQ.u64 = 37092854; Count.u64 = 173; Min.u64 = 77; Max.u64 = 519; + l2cache_1.latency_GetS_hit : Accumulator : Sum.u64 = 3789; SumSQ.u64 = 1034437; Count.u64 = 162; Min.u64 = 1; Max.u64 = 507; + l2cache_1.latency_GetS_miss : Accumulator : Sum.u64 = 88804; SumSQ.u64 = 47412706; Count.u64 = 172; Min.u64 = 79; Max.u64 = 589; l2cache_1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -907,30 +941,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l2cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.GetSHit_Blocked : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache_1.GetSHit_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.GetSMiss_Arrival : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_1.GetSMiss_Arrival : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.CacheHits : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; - l2cache_1.CacheMisses : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_1.CacheMisses : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_1.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.prefetch_useful : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache_1.prefetch_useful : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l2cache_1.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.prefetch_redundant : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache_1.prefetch_redundant : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.stateEvent_GetS_E : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l2cache_1.stateEvent_GetS_E : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l2cache_1.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -947,7 +982,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache_1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -957,13 +992,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.TotalEventsReceived : Accumulator : Sum.u64 = 1283; SumSQ.u64 = 1283; Count.u64 = 1283; Min.u64 = 1; Max.u64 = 1; - l2cache_1.TotalEventsReplayed : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache_1.TotalEventsReceived : Accumulator : Sum.u64 = 1309; SumSQ.u64 = 1309; Count.u64 = 1309; Min.u64 = 1; Max.u64 = 1; + l2cache_1.TotalEventsReplayed : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache_1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -976,16 +1011,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.GetS_recv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; + l2cache_1.GetS_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -994,13 +1031,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 149469; SumSQ.u64 = 1877891; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 16; + l2cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 170230; SumSQ.u64 = 2156078; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 16; l2cache_1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu2.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu2.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1008,26 +1048,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu2.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu2.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu2.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu2.cycles_with_issue : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; - cpu2.cycles_no_issue : Accumulator : Sum.u64 = 11713; SumSQ.u64 = 11713; Count.u64 = 11713; Min.u64 = 1; Max.u64 = 1; + cpu2.cycles_with_issue : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; + cpu2.cycles_no_issue : Accumulator : Sum.u64 = 13115; SumSQ.u64 = 13115; Count.u64 = 13115; Min.u64 = 1; Max.u64 = 1; cpu2.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu2.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu2.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu2.req_latency : Accumulator : Sum.u64 = 124621; SumSQ.u64 = 26930175; Count.u64 = 936; Min.u64 = 2; Max.u64 = 995; - cpu2.time : Accumulator : Sum.u64 = 4628; SumSQ.u64 = 21418384; Count.u64 = 1; Min.u64 = 4628; Max.u64 = 4628; + cpu2.req_latency : Accumulator : Sum.u64 = 139707; SumSQ.u64 = 31081599; Count.u64 = 936; Min.u64 = 2; Max.u64 = 641; + cpu2.time : Accumulator : Sum.u64 = 5159; SumSQ.u64 = 26615281; Count.u64 = 1; Min.u64 = 5159; Max.u64 = 5159; cpu2.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu2.cycles_max_issue : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; - cpu2.cycles_max_reorder : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - cpu2.cycles : Accumulator : Sum.u64 = 12310; SumSQ.u64 = 12310; Count.u64 = 12310; Min.u64 = 1; Max.u64 = 1; + cpu2.cycles_max_issue : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + cpu2.cycles_max_reorder : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + cpu2.cycles : Accumulator : Sum.u64 = 13723; SumSQ.u64 = 13723; Count.u64 = 13723; Min.u64 = 1; Max.u64 = 1; l1cache_2.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache_2.prefetches_issued : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache_2.prefetches_issued : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; l1cache_2.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache_2.prefetches_canceled_by_history : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l1cache_2.Prefetch_requests : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache_2.prefetches_canceled_by_history : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache_2.Prefetch_requests : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; l1cache_2.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; - l1cache_2.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_2.stateEvent_GetS_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_2.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1035,8 +1075,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache_2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; l1cache_2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1084,7 +1124,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.eventSent_GetS : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; + l1cache_2.eventSent_GetS : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1092,13 +1132,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1113,8 +1156,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.latency_GetS_hit : Accumulator : Sum.u64 = 116245; SumSQ.u64 = 77206223; Count.u64 = 445; Min.u64 = 1; Max.u64 = 2638; - l1cache_2.latency_GetS_miss : Accumulator : Sum.u64 = 105320; SumSQ.u64 = 71545364; Count.u64 = 316; Min.u64 = 11; Max.u64 = 2645; + l1cache_2.latency_GetS_hit : Accumulator : Sum.u64 = 128690; SumSQ.u64 = 78577916; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1490; + l1cache_2.latency_GetS_miss : Accumulator : Sum.u64 = 120309; SumSQ.u64 = 83349381; Count.u64 = 316; Min.u64 = 13; Max.u64 = 1703; l1cache_2.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1125,10 +1168,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.GetSHit_Blocked : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l1cache_2.GetSHit_Blocked : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -1137,27 +1181,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.CacheHits : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l1cache_2.CacheHits : Accumulator : Sum.u64 = 444; SumSQ.u64 = 444; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1; l1cache_2.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.prefetch_useful : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l1cache_2.prefetch_useful : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; l1cache_2.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.prefetch_redundant : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; - l1cache_2.stateEvent_GetS_E : Accumulator : Sum.u64 = 444; SumSQ.u64 = 444; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1; + l1cache_2.prefetch_redundant : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache_2.stateEvent_GetS_E : Accumulator : Sum.u64 = 436; SumSQ.u64 = 436; Count.u64 = 436; Min.u64 = 1; Max.u64 = 1; l1cache_2.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache_2.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.TotalEventsReceived : Accumulator : Sum.u64 = 1730; SumSQ.u64 = 1730; Count.u64 = 1730; Min.u64 = 1; Max.u64 = 1; - l1cache_2.TotalEventsReplayed : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l1cache_2.TotalEventsReceived : Accumulator : Sum.u64 = 1800; SumSQ.u64 = 1800; Count.u64 = 1800; Min.u64 = 1; Max.u64 = 1; + l1cache_2.TotalEventsReplayed : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; l1cache_2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1170,34 +1214,38 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.GetS_recv : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; + l1cache_2.GetS_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; l1cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache_2.NACK_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.NACK_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; l1cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 217788; SumSQ.u64 = 4081988; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 245228; SumSQ.u64 = 4598886; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 21; l1cache_2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.packet_latency : Accumulator : Sum.u64 = 516; SumSQ.u64 = 516; Count.u64 = 643; Min.u64 = 0; Max.u64 = 1; - l2cache_2.send_bit_count : Accumulator : Sum.u64 = 64704; SumSQ.u64 = 8761344; Count.u64 = 643; Min.u64 = 64; Max.u64 = 576; - l2cache_2.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.idle_time : Accumulator : Sum.u64 = 3103666; SumSQ.u64 = 219940378762; Count.u64 = 656; Min.u64 = 4; Max.u64 = 156898; - l2cache_2.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l2cache_2.prefetches_issued : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; - l2cache_2.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache_2:lowlink.packet_latency : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 644; Min.u64 = 0; Max.u64 = 1; + l2cache_2:lowlink.send_bit_count : Accumulator : Sum.u64 = 65280; SumSQ.u64 = 9093120; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + l2cache_2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.idle_time : Accumulator : Sum.u64 = 3754270; SumSQ.u64 = 335436530126; Count.u64 = 668; Min.u64 = 2; Max.u64 = 168726; + l2cache_2.prefetch_opportunities : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; + l2cache_2.prefetches_issued : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; + l2cache_2.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache_2.prefetches_canceled_by_history : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache_2.Prefetch_requests : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; - l2cache_2.Prefetch_drops : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l2cache_2.Prefetch_requests : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; + l2cache_2.Prefetch_drops : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; l2cache_2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1213,7 +1261,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_GetS_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; - l2cache_2.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_2.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_2.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1307,20 +1355,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_2.eventSent_NACK : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; - l2cache_2.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache_2.eventSent_NACK : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l2cache_2.eventSent_GetSResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.eventSent_FetchInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_2.eventSent_FetchInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,8 +1382,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.latency_GetS_hit : Accumulator : Sum.u64 = 1962; SumSQ.u64 = 552384; Count.u64 = 159; Min.u64 = 1; Max.u64 = 714; - l2cache_2.latency_GetS_miss : Accumulator : Sum.u64 = 88462; SumSQ.u64 = 43572998; Count.u64 = 184; Min.u64 = 87; Max.u64 = 766; + l2cache_2.latency_GetS_hit : Accumulator : Sum.u64 = 3280; SumSQ.u64 = 935888; Count.u64 = 158; Min.u64 = 1; Max.u64 = 527; + l2cache_2.latency_GetS_miss : Accumulator : Sum.u64 = 99431; SumSQ.u64 = 54801479; Count.u64 = 185; Min.u64 = 90; Max.u64 = 942; l2cache_2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1341,10 +1395,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l2cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.GetSHit_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_2.GetSHit_Blocked : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSMiss_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; @@ -1353,18 +1408,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.CacheHits : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache_2.CacheHits : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l2cache_2.CacheMisses : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_2.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.prefetch_inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_2.prefetch_useful : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l2cache_2.prefetch_useful : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l2cache_2.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.prefetch_redundant : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache_2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.stateEvent_GetS_E : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l2cache_2.stateEvent_GetS_E : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l2cache_2.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1381,7 +1436,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache_2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache_2.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1391,13 +1446,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.TotalEventsReceived : Accumulator : Sum.u64 = 1437; SumSQ.u64 = 1437; Count.u64 = 1437; Min.u64 = 1; Max.u64 = 1; - l2cache_2.TotalEventsReplayed : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_2.TotalEventsReceived : Accumulator : Sum.u64 = 1508; SumSQ.u64 = 1508; Count.u64 = 1508; Min.u64 = 1; Max.u64 = 1; + l2cache_2.TotalEventsReplayed : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache_2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1410,16 +1465,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.GetS_recv : Accumulator : Sum.u64 = 707; SumSQ.u64 = 707; Count.u64 = 707; Min.u64 = 1; Max.u64 = 1; + l2cache_2.GetS_recv : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXResp_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l2cache_2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1428,13 +1485,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 160029; SumSQ.u64 = 2185717; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 181780; SumSQ.u64 = 2516830; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu3.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu3.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1442,25 +1502,25 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu3.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu3.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu3.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu3.cycles_with_issue : Accumulator : Sum.u64 = 656; SumSQ.u64 = 656; Count.u64 = 656; Min.u64 = 1; Max.u64 = 1; - cpu3.cycles_no_issue : Accumulator : Sum.u64 = 11798; SumSQ.u64 = 11798; Count.u64 = 11798; Min.u64 = 1; Max.u64 = 1; + cpu3.cycles_with_issue : Accumulator : Sum.u64 = 666; SumSQ.u64 = 666; Count.u64 = 666; Min.u64 = 1; Max.u64 = 1; + cpu3.cycles_no_issue : Accumulator : Sum.u64 = 13340; SumSQ.u64 = 13340; Count.u64 = 13340; Min.u64 = 1; Max.u64 = 1; cpu3.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu3.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu3.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu3.req_latency : Accumulator : Sum.u64 = 127151; SumSQ.u64 = 22050253; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 610; - cpu3.time : Accumulator : Sum.u64 = 4683; SumSQ.u64 = 21930489; Count.u64 = 1; Min.u64 = 4683; Max.u64 = 4683; + cpu3.req_latency : Accumulator : Sum.u64 = 142019; SumSQ.u64 = 27099767; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 441; + cpu3.time : Accumulator : Sum.u64 = 5266; SumSQ.u64 = 27730756; Count.u64 = 1; Min.u64 = 5266; Max.u64 = 5266; cpu3.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu3.cycles_max_issue : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + cpu3.cycles_max_issue : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; cpu3.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu3.cycles : Accumulator : Sum.u64 = 12455; SumSQ.u64 = 12455; Count.u64 = 12455; Min.u64 = 1; Max.u64 = 1; + cpu3.cycles : Accumulator : Sum.u64 = 14007; SumSQ.u64 = 14007; Count.u64 = 14007; Min.u64 = 1; Max.u64 = 1; l1cache_3.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_3.prefetches_issued : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; - l1cache_3.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache_3.prefetches_canceled_by_history : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; - l1cache_3.Prefetch_requests : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; - l1cache_3.Prefetch_drops : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache_3.prefetches_issued : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l1cache_3.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_3.prefetches_canceled_by_history : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache_3.Prefetch_requests : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l1cache_3.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.stateEvent_GetS_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_3.stateEvent_GetS_I : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l1cache_3.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1469,7 +1529,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l1cache_3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1518,7 +1578,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.eventSent_GetS : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l1cache_3.eventSent_GetS : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1526,13 +1586,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1540,15 +1603,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.evict_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_3.evict_I : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l1cache_3.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.latency_GetS_hit : Accumulator : Sum.u64 = 153931; SumSQ.u64 = 68154859; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1197; - l1cache_3.latency_GetS_miss : Accumulator : Sum.u64 = 85328; SumSQ.u64 = 42004516; Count.u64 = 318; Min.u64 = 13; Max.u64 = 1623; + l1cache_3.latency_GetS_hit : Accumulator : Sum.u64 = 170576; SumSQ.u64 = 81664946; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1168; + l1cache_3.latency_GetS_miss : Accumulator : Sum.u64 = 96586; SumSQ.u64 = 51325378; Count.u64 = 317; Min.u64 = 13; Max.u64 = 1171; l1cache_3.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1559,29 +1622,30 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 272; SumSQ.u64 = 272; Count.u64 = 272; Min.u64 = 1; Max.u64 = 1; + l1cache_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.GetSHit_Blocked : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l1cache_3.GetSHit_Blocked : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.GetSMiss_Arrival : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_3.GetSMiss_Arrival : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.CacheHits : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; - l1cache_3.CacheMisses : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_3.CacheHits : Accumulator : Sum.u64 = 815; SumSQ.u64 = 815; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1; + l1cache_3.CacheMisses : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l1cache_3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.prefetch_useful : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; + l1cache_3.prefetch_useful : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; l1cache_3.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.prefetch_redundant : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; - l1cache_3.stateEvent_GetS_E : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; + l1cache_3.prefetch_redundant : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache_3.stateEvent_GetS_E : Accumulator : Sum.u64 = 815; SumSQ.u64 = 815; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1; l1cache_3.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1590,8 +1654,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_3.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.TotalEventsReceived : Accumulator : Sum.u64 = 1906; SumSQ.u64 = 1906; Count.u64 = 1906; Min.u64 = 1; Max.u64 = 1; - l1cache_3.TotalEventsReplayed : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l1cache_3.TotalEventsReceived : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; + l1cache_3.TotalEventsReplayed : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; l1cache_3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1604,34 +1668,38 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.GetS_recv : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache_3.GetS_recv : Accumulator : Sum.u64 = 1133; SumSQ.u64 = 1133; Count.u64 = 1133; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l1cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache_3.NACK_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.NACK_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l1cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 233044; SumSQ.u64 = 4496726; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 23; + l1cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 261020; SumSQ.u64 = 4978082; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 23; l1cache_3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.packet_latency : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 648; Min.u64 = 0; Max.u64 = 1; - l2cache_3.send_bit_count : Accumulator : Sum.u64 = 66560; SumSQ.u64 = 9764864; Count.u64 = 648; Min.u64 = 64; Max.u64 = 576; - l2cache_3.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.idle_time : Accumulator : Sum.u64 = 3218815; SumSQ.u64 = 251586283159; Count.u64 = 641; Min.u64 = 6; Max.u64 = 152930; - l2cache_3.prefetch_opportunities : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; - l2cache_3.prefetches_issued : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; - l2cache_3.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_3:lowlink.packet_latency : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 651; Min.u64 = 0; Max.u64 = 1; + l2cache_3:lowlink.send_bit_count : Accumulator : Sum.u64 = 66752; SumSQ.u64 = 9777152; Count.u64 = 651; Min.u64 = 64; Max.u64 = 576; + l2cache_3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.idle_time : Accumulator : Sum.u64 = 3712463; SumSQ.u64 = 320304080371; Count.u64 = 641; Min.u64 = 3; Max.u64 = 164120; + l2cache_3.prefetch_opportunities : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l2cache_3.prefetches_issued : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l2cache_3.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache_3.prefetches_canceled_by_history : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l2cache_3.Prefetch_requests : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; - l2cache_3.Prefetch_drops : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache_3.Prefetch_requests : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l2cache_3.Prefetch_drops : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache_3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.evict_I : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1647,7 +1715,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.stateEvent_GetS_I : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; - l2cache_3.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache_3.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_3.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1741,16 +1809,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.eventSent_NACK : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - l2cache_3.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_3.eventSent_NACK : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache_3.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_GetXResp : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1762,8 +1836,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.latency_GetS_hit : Accumulator : Sum.u64 = 2735; SumSQ.u64 = 569297; Count.u64 = 157; Min.u64 = 1; Max.u64 = 416; - l2cache_3.latency_GetS_miss : Accumulator : Sum.u64 = 78589; SumSQ.u64 = 37540407; Count.u64 = 169; Min.u64 = 91; Max.u64 = 522; + l2cache_3.latency_GetS_hit : Accumulator : Sum.u64 = 4555; SumSQ.u64 = 1158749; Count.u64 = 157; Min.u64 = 1; Max.u64 = 472; + l2cache_3.latency_GetS_miss : Accumulator : Sum.u64 = 87555; SumSQ.u64 = 46804155; Count.u64 = 170; Min.u64 = 94; Max.u64 = 591; l2cache_3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1775,10 +1849,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l2cache_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.GetSHit_Blocked : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_3.GetSHit_Blocked : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSMiss_Arrival : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; @@ -1791,14 +1866,14 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.CacheMisses : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_3.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.prefetch_useful : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l2cache_3.prefetch_useful : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; l2cache_3.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.prefetch_redundant : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_3.prefetch_redundant : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.stateEvent_GetS_E : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache_3.stateEvent_GetS_E : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l2cache_3.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1830,8 +1905,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.TotalEventsReceived : Accumulator : Sum.u64 = 1306; SumSQ.u64 = 1306; Count.u64 = 1306; Min.u64 = 1; Max.u64 = 1; - l2cache_3.TotalEventsReplayed : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_3.TotalEventsReceived : Accumulator : Sum.u64 = 1317; SumSQ.u64 = 1317; Count.u64 = 1317; Min.u64 = 1; Max.u64 = 1; + l2cache_3.TotalEventsReplayed : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache_3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1844,16 +1919,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.GetS_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; + l2cache_3.GetS_recv : Accumulator : Sum.u64 = 536; SumSQ.u64 = 536; Count.u64 = 536; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l2cache_3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1862,13 +1939,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 155168; SumSQ.u64 = 2028048; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 16; + l2cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 171526; SumSQ.u64 = 2196414; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 16; l2cache_3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu4.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu4.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1876,26 +1956,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu4.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu4.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu4.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu4.cycles_with_issue : Accumulator : Sum.u64 = 609; SumSQ.u64 = 609; Count.u64 = 609; Min.u64 = 1; Max.u64 = 1; - cpu4.cycles_no_issue : Accumulator : Sum.u64 = 11448; SumSQ.u64 = 11448; Count.u64 = 11448; Min.u64 = 1; Max.u64 = 1; + cpu4.cycles_with_issue : Accumulator : Sum.u64 = 628; SumSQ.u64 = 628; Count.u64 = 628; Min.u64 = 1; Max.u64 = 1; + cpu4.cycles_no_issue : Accumulator : Sum.u64 = 13016; SumSQ.u64 = 13016; Count.u64 = 13016; Min.u64 = 1; Max.u64 = 1; cpu4.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu4.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu4.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu4.req_latency : Accumulator : Sum.u64 = 124196; SumSQ.u64 = 23691986; Count.u64 = 936; Min.u64 = 2; Max.u64 = 993; - cpu4.time : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 20548089; Count.u64 = 1; Min.u64 = 4533; Max.u64 = 4533; + cpu4.req_latency : Accumulator : Sum.u64 = 140424; SumSQ.u64 = 28743842; Count.u64 = 936; Min.u64 = 2; Max.u64 = 630; + cpu4.time : Accumulator : Sum.u64 = 5130; SumSQ.u64 = 26316900; Count.u64 = 1; Min.u64 = 5130; Max.u64 = 5130; cpu4.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu4.cycles_max_issue : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - cpu4.cycles_max_reorder : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - cpu4.cycles : Accumulator : Sum.u64 = 12058; SumSQ.u64 = 12058; Count.u64 = 12058; Min.u64 = 1; Max.u64 = 1; + cpu4.cycles_max_issue : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + cpu4.cycles_max_reorder : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + cpu4.cycles : Accumulator : Sum.u64 = 13645; SumSQ.u64 = 13645; Count.u64 = 13645; Min.u64 = 1; Max.u64 = 1; l1cache_4.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache_4.prefetches_issued : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache_4.prefetches_issued : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; l1cache_4.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache_4.prefetches_canceled_by_history : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache_4.Prefetch_requests : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache_4.prefetches_canceled_by_history : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache_4.Prefetch_requests : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; l1cache_4.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.stateEvent_GetS_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; - l1cache_4.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l1cache_4.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_4.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1903,8 +1983,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1952,7 +2032,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.eventSent_GetS : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l1cache_4.eventSent_GetS : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,13 +2040,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1974,15 +2057,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.evict_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_4.evict_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_4.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.latency_GetS_hit : Accumulator : Sum.u64 = 115905; SumSQ.u64 = 56874351; Count.u64 = 455; Min.u64 = 1; Max.u64 = 2633; - l1cache_4.latency_GetS_miss : Accumulator : Sum.u64 = 104763; SumSQ.u64 = 58508025; Count.u64 = 315; Min.u64 = 13; Max.u64 = 2641; + l1cache_4.latency_GetS_hit : Accumulator : Sum.u64 = 129919; SumSQ.u64 = 67066781; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1658; + l1cache_4.latency_GetS_miss : Accumulator : Sum.u64 = 119335; SumSQ.u64 = 68923425; Count.u64 = 316; Min.u64 = 13; Max.u64 = 1676; l1cache_4.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1993,29 +2076,30 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache_4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.GetSHit_Blocked : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; + l1cache_4.GetSHit_Blocked : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.GetSMiss_Arrival : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_4.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.CacheHits : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; - l1cache_4.CacheMisses : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_4.CacheHits : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; + l1cache_4.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_4.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.prefetch_useful : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l1cache_4.prefetch_useful : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; l1cache_4.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.prefetch_redundant : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; - l1cache_4.stateEvent_GetS_E : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; + l1cache_4.prefetch_redundant : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache_4.stateEvent_GetS_E : Accumulator : Sum.u64 = 450; SumSQ.u64 = 450; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1; l1cache_4.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2024,8 +2108,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_4.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.TotalEventsReceived : Accumulator : Sum.u64 = 1732; SumSQ.u64 = 1732; Count.u64 = 1732; Min.u64 = 1; Max.u64 = 1; - l1cache_4.TotalEventsReplayed : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; + l1cache_4.TotalEventsReceived : Accumulator : Sum.u64 = 1693; SumSQ.u64 = 1693; Count.u64 = 1693; Min.u64 = 1; Max.u64 = 1; + l1cache_4.TotalEventsReplayed : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; l1cache_4.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2038,36 +2122,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.GetS_recv : Accumulator : Sum.u64 = 770; SumSQ.u64 = 770; Count.u64 = 770; Min.u64 = 1; Max.u64 = 1; + l1cache_4.GetS_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache_4.NACK_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache_4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.NACK_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l1cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 216893; SumSQ.u64 = 4060397; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 245472; SumSQ.u64 = 4608178; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.packet_latency : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 644; Min.u64 = 0; Max.u64 = 1; - l2cache_4.send_bit_count : Accumulator : Sum.u64 = 66304; SumSQ.u64 = 9748480; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; - l2cache_4.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.idle_time : Accumulator : Sum.u64 = 3005330; SumSQ.u64 = 124566858862; Count.u64 = 647; Min.u64 = 2; Max.u64 = 100640; - l2cache_4.prefetch_opportunities : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; - l2cache_4.prefetches_issued : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; - l2cache_4.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache_4:lowlink.packet_latency : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 643; Min.u64 = 0; Max.u64 = 1; + l2cache_4:lowlink.send_bit_count : Accumulator : Sum.u64 = 66240; SumSQ.u64 = 9744384; Count.u64 = 643; Min.u64 = 64; Max.u64 = 576; + l2cache_4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.idle_time : Accumulator : Sum.u64 = 3339709; SumSQ.u64 = 172701656805; Count.u64 = 643; Min.u64 = 11; Max.u64 = 116571; + l2cache_4.prefetch_opportunities : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; + l2cache_4.prefetches_issued : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; + l2cache_4.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2cache_4.prefetches_canceled_by_history : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l2cache_4.Prefetch_requests : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; - l2cache_4.Prefetch_drops : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache_4.Prefetch_requests : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; + l2cache_4.Prefetch_drops : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l2cache_4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.evict_I : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; + l2cache_4.evict_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_4.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2080,8 +2168,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.stateEvent_GetS_I : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; - l2cache_4.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_4.stateEvent_GetS_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; + l2cache_4.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_4.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2089,7 +2177,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l2cache_4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2169,22 +2257,28 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.eventSent_GetS : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; + l2cache_4.eventSent_GetS : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_4.eventSent_NACK : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; - l2cache_4.eventSent_GetSResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l2cache_4.eventSent_NACK : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l2cache_4.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2196,8 +2290,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.latency_GetS_hit : Accumulator : Sum.u64 = 2980; SumSQ.u64 = 438436; Count.u64 = 143; Min.u64 = 1; Max.u64 = 344; - l2cache_4.latency_GetS_miss : Accumulator : Sum.u64 = 92058; SumSQ.u64 = 44960212; Count.u64 = 192; Min.u64 = 71; Max.u64 = 699; + l2cache_4.latency_GetS_hit : Accumulator : Sum.u64 = 4834; SumSQ.u64 = 1406298; Count.u64 = 138; Min.u64 = 1; Max.u64 = 718; + l2cache_4.latency_GetS_miss : Accumulator : Sum.u64 = 107059; SumSQ.u64 = 58721143; Count.u64 = 199; Min.u64 = 72; Max.u64 = 758; l2cache_4.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2209,30 +2303,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l2cache_4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.GetSHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache_4.GetSHit_Blocked : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.GetSMiss_Arrival : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; + l2cache_4.GetSMiss_Arrival : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.CacheHits : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; - l2cache_4.CacheMisses : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; + l2cache_4.CacheHits : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache_4.CacheMisses : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_4.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.prefetch_inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_4.prefetch_useful : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + l2cache_4.prefetch_useful : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l2cache_4.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.prefetch_redundant : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache_4.prefetch_redundant : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache_4.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.stateEvent_GetS_E : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache_4.stateEvent_GetS_E : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; l2cache_4.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2264,8 +2359,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.TotalEventsReceived : Accumulator : Sum.u64 = 1440; SumSQ.u64 = 1440; Count.u64 = 1440; Min.u64 = 1; Max.u64 = 1; - l2cache_4.TotalEventsReplayed : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache_4.TotalEventsReceived : Accumulator : Sum.u64 = 1400; SumSQ.u64 = 1400; Count.u64 = 1400; Min.u64 = 1; Max.u64 = 1; + l2cache_4.TotalEventsReplayed : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache_4.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2278,16 +2373,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.GetS_recv : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; + l2cache_4.GetS_recv : Accumulator : Sum.u64 = 659; SumSQ.u64 = 659; Count.u64 = 659; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXResp_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l2cache_4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2299,10 +2396,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_4.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 158552; SumSQ.u64 = 2139700; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 180027; SumSQ.u64 = 2456329; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu5.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu5.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2310,22 +2410,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu5.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu5.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu5.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu5.cycles_with_issue : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; - cpu5.cycles_no_issue : Accumulator : Sum.u64 = 11897; SumSQ.u64 = 11897; Count.u64 = 11897; Min.u64 = 1; Max.u64 = 1; + cpu5.cycles_with_issue : Accumulator : Sum.u64 = 659; SumSQ.u64 = 659; Count.u64 = 659; Min.u64 = 1; Max.u64 = 1; + cpu5.cycles_no_issue : Accumulator : Sum.u64 = 13366; SumSQ.u64 = 13366; Count.u64 = 13366; Min.u64 = 1; Max.u64 = 1; cpu5.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu5.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu5.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu5.req_latency : Accumulator : Sum.u64 = 126758; SumSQ.u64 = 21586626; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 415; - cpu5.time : Accumulator : Sum.u64 = 4722; SumSQ.u64 = 22297284; Count.u64 = 1; Min.u64 = 4722; Max.u64 = 4722; + cpu5.req_latency : Accumulator : Sum.u64 = 142551; SumSQ.u64 = 26992633; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 231; + cpu5.time : Accumulator : Sum.u64 = 5273; SumSQ.u64 = 27804529; Count.u64 = 1; Min.u64 = 5273; Max.u64 = 5273; cpu5.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu5.cycles_max_issue : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + cpu5.cycles_max_issue : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; cpu5.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu5.cycles : Accumulator : Sum.u64 = 12560; SumSQ.u64 = 12560; Count.u64 = 12560; Min.u64 = 1; Max.u64 = 1; + cpu5.cycles : Accumulator : Sum.u64 = 14026; SumSQ.u64 = 14026; Count.u64 = 14026; Min.u64 = 1; Max.u64 = 1; l1cache_5.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_5.prefetches_issued : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; - l1cache_5.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache_5.prefetches_canceled_by_history : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; - l1cache_5.Prefetch_requests : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l1cache_5.prefetches_issued : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; + l1cache_5.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_5.prefetches_canceled_by_history : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache_5.Prefetch_requests : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; l1cache_5.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -2386,7 +2486,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.eventSent_GetS : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; + l1cache_5.eventSent_GetS : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2394,13 +2494,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2415,8 +2518,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_5.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.latency_GetS_hit : Accumulator : Sum.u64 = 155006; SumSQ.u64 = 67355278; Count.u64 = 811; Min.u64 = 1; Max.u64 = 716; - l1cache_5.latency_GetS_miss : Accumulator : Sum.u64 = 83739; SumSQ.u64 = 40288429; Count.u64 = 316; Min.u64 = 13; Max.u64 = 1104; + l1cache_5.latency_GetS_hit : Accumulator : Sum.u64 = 170204; SumSQ.u64 = 80063210; Count.u64 = 818; Min.u64 = 1; Max.u64 = 607; + l1cache_5.latency_GetS_miss : Accumulator : Sum.u64 = 93716; SumSQ.u64 = 49515588; Count.u64 = 316; Min.u64 = 11; Max.u64 = 611; l1cache_5.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2427,10 +2530,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; + l1cache_5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.GetSHit_Blocked : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; + l1cache_5.GetSHit_Blocked : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -2439,27 +2543,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_5.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.CacheHits : Accumulator : Sum.u64 = 811; SumSQ.u64 = 811; Count.u64 = 811; Min.u64 = 1; Max.u64 = 1; + l1cache_5.CacheHits : Accumulator : Sum.u64 = 818; SumSQ.u64 = 818; Count.u64 = 818; Min.u64 = 1; Max.u64 = 1; l1cache_5.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_5.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.prefetch_useful : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l1cache_5.prefetch_useful : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l1cache_5.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.prefetch_redundant : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; - l1cache_5.stateEvent_GetS_E : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; + l1cache_5.prefetch_redundant : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache_5.stateEvent_GetS_E : Accumulator : Sum.u64 = 816; SumSQ.u64 = 816; Count.u64 = 816; Min.u64 = 1; Max.u64 = 1; l1cache_5.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache_5.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.TotalEventsReceived : Accumulator : Sum.u64 = 1901; SumSQ.u64 = 1901; Count.u64 = 1901; Min.u64 = 1; Max.u64 = 1; - l1cache_5.TotalEventsReplayed : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; + l1cache_5.TotalEventsReceived : Accumulator : Sum.u64 = 1884; SumSQ.u64 = 1884; Count.u64 = 1884; Min.u64 = 1; Max.u64 = 1; + l1cache_5.TotalEventsReplayed : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l1cache_5.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2472,36 +2576,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.GetS_recv : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache_5.GetS_recv : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache_5.NACK_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.NACK_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 232623; SumSQ.u64 = 4399503; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 257839; SumSQ.u64 = 4864289; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 23; l1cache_5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.packet_latency : Accumulator : Sum.u64 = 514; SumSQ.u64 = 514; Count.u64 = 641; Min.u64 = 0; Max.u64 = 1; - l2cache_5.send_bit_count : Accumulator : Sum.u64 = 64576; SumSQ.u64 = 8753152; Count.u64 = 641; Min.u64 = 64; Max.u64 = 576; - l2cache_5.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.idle_time : Accumulator : Sum.u64 = 3351001; SumSQ.u64 = 288051488563; Count.u64 = 633; Min.u64 = 6; Max.u64 = 153743; - l2cache_5.prefetch_opportunities : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; - l2cache_5.prefetches_issued : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; - l2cache_5.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; - l2cache_5.prefetches_canceled_by_history : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache_5.Prefetch_requests : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; - l2cache_5.Prefetch_drops : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache_5:lowlink.packet_latency : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 644; Min.u64 = 0; Max.u64 = 1; + l2cache_5:lowlink.send_bit_count : Accumulator : Sum.u64 = 64256; SumSQ.u64 = 8437760; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + l2cache_5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.idle_time : Accumulator : Sum.u64 = 3568323; SumSQ.u64 = 277962447585; Count.u64 = 646; Min.u64 = 2; Max.u64 = 161345; + l2cache_5.prefetch_opportunities : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l2cache_5.prefetches_issued : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l2cache_5.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_5.prefetches_canceled_by_history : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_5.Prefetch_requests : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l2cache_5.Prefetch_drops : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache_5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.evict_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_5.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_5.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2514,7 +2622,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.stateEvent_GetS_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_5.stateEvent_GetS_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2523,7 +2631,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2603,26 +2711,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.eventSent_GetS : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_5.eventSent_GetS : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.eventSent_NACK : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_5.eventSent_NACK : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.eventSent_FetchInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_5.eventSent_FetchInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2630,8 +2744,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.latency_GetS_hit : Accumulator : Sum.u64 = 3330; SumSQ.u64 = 840250; Count.u64 = 157; Min.u64 = 1; Max.u64 = 434; - l2cache_5.latency_GetS_miss : Accumulator : Sum.u64 = 76532; SumSQ.u64 = 36153438; Count.u64 = 168; Min.u64 = 75; Max.u64 = 517; + l2cache_5.latency_GetS_hit : Accumulator : Sum.u64 = 3850; SumSQ.u64 = 1026458; Count.u64 = 158; Min.u64 = 1; Max.u64 = 475; + l2cache_5.latency_GetS_miss : Accumulator : Sum.u64 = 87166; SumSQ.u64 = 46903400; Count.u64 = 167; Min.u64 = 76; Max.u64 = 601; l2cache_5.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2643,30 +2757,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache_5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.GetSHit_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_5.GetSHit_Blocked : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.GetSMiss_Arrival : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_5.GetSMiss_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.CacheHits : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; - l2cache_5.CacheMisses : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_5.CacheHits : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l2cache_5.CacheMisses : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_5.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.prefetch_useful : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l2cache_5.prefetch_useful : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l2cache_5.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.prefetch_redundant : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.stateEvent_GetS_E : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache_5.stateEvent_GetS_E : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2683,7 +2798,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache_5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2693,13 +2808,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_5.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache_5.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.TotalEventsReceived : Accumulator : Sum.u64 = 1294; SumSQ.u64 = 1294; Count.u64 = 1294; Min.u64 = 1; Max.u64 = 1; - l2cache_5.TotalEventsReplayed : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache_5.TotalEventsReceived : Accumulator : Sum.u64 = 1280; SumSQ.u64 = 1280; Count.u64 = 1280; Min.u64 = 1; Max.u64 = 1; + l2cache_5.TotalEventsReplayed : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_5.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2712,16 +2827,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.GetS_recv : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; + l2cache_5.GetS_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2730,13 +2847,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_5.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 150835; SumSQ.u64 = 1895443; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 172216; SumSQ.u64 = 2210438; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 16; l2cache_5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu6.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu6.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2744,26 +2864,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu6.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu6.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu6.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu6.cycles_with_issue : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; - cpu6.cycles_no_issue : Accumulator : Sum.u64 = 11891; SumSQ.u64 = 11891; Count.u64 = 11891; Min.u64 = 1; Max.u64 = 1; + cpu6.cycles_with_issue : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; + cpu6.cycles_no_issue : Accumulator : Sum.u64 = 13135; SumSQ.u64 = 13135; Count.u64 = 13135; Min.u64 = 1; Max.u64 = 1; cpu6.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu6.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu6.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu6.req_latency : Accumulator : Sum.u64 = 125016; SumSQ.u64 = 24937148; Count.u64 = 936; Min.u64 = 2; Max.u64 = 999; - cpu6.time : Accumulator : Sum.u64 = 4699; SumSQ.u64 = 22080601; Count.u64 = 1; Min.u64 = 4699; Max.u64 = 4699; + cpu6.req_latency : Accumulator : Sum.u64 = 139413; SumSQ.u64 = 30158231; Count.u64 = 936; Min.u64 = 2; Max.u64 = 634; + cpu6.time : Accumulator : Sum.u64 = 5164; SumSQ.u64 = 26666896; Count.u64 = 1; Min.u64 = 5164; Max.u64 = 5164; cpu6.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu6.cycles_max_issue : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; - cpu6.cycles_max_reorder : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - cpu6.cycles : Accumulator : Sum.u64 = 12499; SumSQ.u64 = 12499; Count.u64 = 12499; Min.u64 = 1; Max.u64 = 1; + cpu6.cycles_max_issue : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + cpu6.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu6.cycles : Accumulator : Sum.u64 = 13735; SumSQ.u64 = 13735; Count.u64 = 13735; Min.u64 = 1; Max.u64 = 1; l1cache_6.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l1cache_6.prefetches_issued : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l1cache_6.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_6.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_6.prefetches_canceled_by_history : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_6.Prefetch_requests : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l1cache_6.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_6.Prefetch_drops : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.stateEvent_GetS_I : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; - l1cache_6.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l1cache_6.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_6.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2772,7 +2892,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_6.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache_6.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_6.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_6.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2820,7 +2940,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_6.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.eventSent_GetS : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l1cache_6.eventSent_GetS : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2828,13 +2948,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2842,15 +2965,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_6.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.evict_I : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; + l1cache_6.evict_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_6.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.latency_GetS_hit : Accumulator : Sum.u64 = 120362; SumSQ.u64 = 69369484; Count.u64 = 446; Min.u64 = 1; Max.u64 = 2363; - l1cache_6.latency_GetS_miss : Accumulator : Sum.u64 = 110009; SumSQ.u64 = 67944627; Count.u64 = 317; Min.u64 = 11; Max.u64 = 2658; + l1cache_6.latency_GetS_hit : Accumulator : Sum.u64 = 131126; SumSQ.u64 = 74124510; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1242; + l1cache_6.latency_GetS_miss : Accumulator : Sum.u64 = 121097; SumSQ.u64 = 79841031; Count.u64 = 316; Min.u64 = 11; Max.u64 = 1685; l1cache_6.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2861,39 +2984,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_6.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l1cache_6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.GetSHit_Blocked : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l1cache_6.GetSHit_Blocked : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.GetSMiss_Arrival : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; + l1cache_6.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.CacheHits : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; - l1cache_6.CacheMisses : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; + l1cache_6.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_6.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.prefetch_useful : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l1cache_6.prefetch_useful : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l1cache_6.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.prefetch_redundant : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; - l1cache_6.stateEvent_GetS_E : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; + l1cache_6.prefetch_redundant : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache_6.stateEvent_GetS_E : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; l1cache_6.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_6.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_6.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.TotalEventsReceived : Accumulator : Sum.u64 = 1702; SumSQ.u64 = 1702; Count.u64 = 1702; Min.u64 = 1; Max.u64 = 1; - l1cache_6.TotalEventsReplayed : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l1cache_6.TotalEventsReceived : Accumulator : Sum.u64 = 1812; SumSQ.u64 = 1812; Count.u64 = 1812; Min.u64 = 1; Max.u64 = 1; + l1cache_6.TotalEventsReplayed : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; l1cache_6.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2912,30 +3036,34 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_6.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache_6.NACK_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.NACK_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; l1cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 226604; SumSQ.u64 = 4342176; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 23; + l1cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 248452; SumSQ.u64 = 4759172; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_6.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.packet_latency : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 649; Min.u64 = 0; Max.u64 = 1; - l2cache_6.send_bit_count : Accumulator : Sum.u64 = 66112; SumSQ.u64 = 9441280; Count.u64 = 649; Min.u64 = 64; Max.u64 = 576; - l2cache_6.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.idle_time : Accumulator : Sum.u64 = 2895535; SumSQ.u64 = 130351957215; Count.u64 = 652; Min.u64 = 3; Max.u64 = 102007; - l2cache_6.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l2cache_6.prefetches_issued : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; - l2cache_6.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache_6:lowlink.packet_latency : Accumulator : Sum.u64 = 493; SumSQ.u64 = 493; Count.u64 = 646; Min.u64 = 0; Max.u64 = 1; + l2cache_6:lowlink.send_bit_count : Accumulator : Sum.u64 = 66432; SumSQ.u64 = 9756672; Count.u64 = 646; Min.u64 = 64; Max.u64 = 576; + l2cache_6:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.idle_time : Accumulator : Sum.u64 = 3767634; SumSQ.u64 = 329959416848; Count.u64 = 645; Min.u64 = 5; Max.u64 = 166843; + l2cache_6.prefetch_opportunities : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; + l2cache_6.prefetches_issued : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; + l2cache_6.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_6.prefetches_canceled_by_history : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache_6.Prefetch_requests : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; - l2cache_6.Prefetch_drops : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache_6.Prefetch_requests : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; + l2cache_6.Prefetch_drops : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l2cache_6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.evict_I : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; + l2cache_6.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_6.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2948,8 +3076,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.stateEvent_GetS_I : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; - l2cache_6.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.stateEvent_GetS_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_6.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2957,7 +3085,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache_6.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3037,26 +3165,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.eventSent_GetS : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; + l2cache_6.eventSent_GetS : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_6.eventSent_NACK : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l2cache_6.eventSent_NACK : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_GetSResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.eventSent_FetchInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_6.eventSent_FetchInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3064,8 +3198,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.latency_GetS_hit : Accumulator : Sum.u64 = 1334; SumSQ.u64 = 73256; Count.u64 = 140; Min.u64 = 1; Max.u64 = 212; - l2cache_6.latency_GetS_miss : Accumulator : Sum.u64 = 97540; SumSQ.u64 = 47860218; Count.u64 = 203; Min.u64 = 85; Max.u64 = 764; + l2cache_6.latency_GetS_hit : Accumulator : Sum.u64 = 4146; SumSQ.u64 = 1475720; Count.u64 = 152; Min.u64 = 1; Max.u64 = 544; + l2cache_6.latency_GetS_miss : Accumulator : Sum.u64 = 100609; SumSQ.u64 = 55063393; Count.u64 = 188; Min.u64 = 88; Max.u64 = 861; l2cache_6.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3077,30 +3211,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l2cache_6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.GetSHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_6.GetSHit_Blocked : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.GetSMiss_Arrival : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; + l2cache_6.GetSMiss_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.CacheHits : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l2cache_6.CacheMisses : Accumulator : Sum.u64 = 327; SumSQ.u64 = 327; Count.u64 = 327; Min.u64 = 1; Max.u64 = 1; + l2cache_6.CacheHits : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache_6.CacheMisses : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache_6.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.prefetch_inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_6.prefetch_useful : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l2cache_6.prefetch_useful : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l2cache_6.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.prefetch_redundant : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache_6.prefetch_redundant : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.stateEvent_GetS_E : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache_6.stateEvent_GetS_E : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3117,7 +3252,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_6.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3127,13 +3262,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_6.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_6.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.TotalEventsReceived : Accumulator : Sum.u64 = 1415; SumSQ.u64 = 1415; Count.u64 = 1415; Min.u64 = 1; Max.u64 = 1; - l2cache_6.TotalEventsReplayed : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache_6.TotalEventsReceived : Accumulator : Sum.u64 = 1522; SumSQ.u64 = 1522; Count.u64 = 1522; Min.u64 = 1; Max.u64 = 1; + l2cache_6.TotalEventsReplayed : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache_6.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3146,16 +3281,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_6.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.GetS_recv : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l2cache_6.GetS_recv : Accumulator : Sum.u64 = 771; SumSQ.u64 = 771; Count.u64 = 771; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_6.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3164,13 +3301,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_6.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 159496; SumSQ.u64 = 2132004; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 181255; SumSQ.u64 = 2493927; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_6.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu7.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu7.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3178,22 +3318,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu7.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu7.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu7.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu7.cycles_with_issue : Accumulator : Sum.u64 = 666; SumSQ.u64 = 666; Count.u64 = 666; Min.u64 = 1; Max.u64 = 1; - cpu7.cycles_no_issue : Accumulator : Sum.u64 = 11872; SumSQ.u64 = 11872; Count.u64 = 11872; Min.u64 = 1; Max.u64 = 1; + cpu7.cycles_with_issue : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + cpu7.cycles_no_issue : Accumulator : Sum.u64 = 13274; SumSQ.u64 = 13274; Count.u64 = 13274; Min.u64 = 1; Max.u64 = 1; cpu7.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu7.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu7.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu7.req_latency : Accumulator : Sum.u64 = 127484; SumSQ.u64 = 21462902; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 253; - cpu7.time : Accumulator : Sum.u64 = 4714; SumSQ.u64 = 22221796; Count.u64 = 1; Min.u64 = 4714; Max.u64 = 4714; + cpu7.req_latency : Accumulator : Sum.u64 = 143555; SumSQ.u64 = 27859395; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 277; + cpu7.time : Accumulator : Sum.u64 = 5243; SumSQ.u64 = 27489049; Count.u64 = 1; Min.u64 = 5243; Max.u64 = 5243; cpu7.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu7.cycles_max_issue : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + cpu7.cycles_max_issue : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; cpu7.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu7.cycles : Accumulator : Sum.u64 = 12539; SumSQ.u64 = 12539; Count.u64 = 12539; Min.u64 = 1; Max.u64 = 1; + cpu7.cycles : Accumulator : Sum.u64 = 13945; SumSQ.u64 = 13945; Count.u64 = 13945; Min.u64 = 1; Max.u64 = 1; l1cache_7.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_7.prefetches_issued : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; - l1cache_7.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache_7.prefetches_canceled_by_history : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; - l1cache_7.Prefetch_requests : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l1cache_7.prefetches_issued : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; + l1cache_7.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_7.prefetches_canceled_by_history : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache_7.Prefetch_requests : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; l1cache_7.Prefetch_drops : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -3254,7 +3394,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_7.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.eventSent_GetS : Accumulator : Sum.u64 = 351; SumSQ.u64 = 351; Count.u64 = 351; Min.u64 = 1; Max.u64 = 1; + l1cache_7.eventSent_GetS : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3262,13 +3402,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3283,8 +3426,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_7.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.latency_GetS_hit : Accumulator : Sum.u64 = 154965; SumSQ.u64 = 65610749; Count.u64 = 813; Min.u64 = 1; Max.u64 = 625; - l1cache_7.latency_GetS_miss : Accumulator : Sum.u64 = 85744; SumSQ.u64 = 41107374; Count.u64 = 316; Min.u64 = 11; Max.u64 = 1098; + l1cache_7.latency_GetS_hit : Accumulator : Sum.u64 = 171081; SumSQ.u64 = 85317225; Count.u64 = 815; Min.u64 = 1; Max.u64 = 736; + l1cache_7.latency_GetS_miss : Accumulator : Sum.u64 = 94348; SumSQ.u64 = 51295478; Count.u64 = 316; Min.u64 = 13; Max.u64 = 1170; l1cache_7.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3295,10 +3438,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_7.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; + l1cache_7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.GetSHit_Blocked : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; + l1cache_7.GetSHit_Blocked : Accumulator : Sum.u64 = 534; SumSQ.u64 = 534; Count.u64 = 534; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; @@ -3307,27 +3451,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_7.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.CacheHits : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; + l1cache_7.CacheHits : Accumulator : Sum.u64 = 815; SumSQ.u64 = 815; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1; l1cache_7.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_7.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.prefetch_useful : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l1cache_7.prefetch_useful : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_7.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.prefetch_redundant : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l1cache_7.stateEvent_GetS_E : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; + l1cache_7.prefetch_redundant : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache_7.stateEvent_GetS_E : Accumulator : Sum.u64 = 815; SumSQ.u64 = 815; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1; l1cache_7.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache_7.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_7.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.TotalEventsReceived : Accumulator : Sum.u64 = 1924; SumSQ.u64 = 1924; Count.u64 = 1924; Min.u64 = 1; Max.u64 = 1; - l1cache_7.TotalEventsReplayed : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; + l1cache_7.TotalEventsReceived : Accumulator : Sum.u64 = 1915; SumSQ.u64 = 1915; Count.u64 = 1915; Min.u64 = 1; Max.u64 = 1; + l1cache_7.TotalEventsReplayed : Accumulator : Sum.u64 = 534; SumSQ.u64 = 534; Count.u64 = 534; Min.u64 = 1; Max.u64 = 1; l1cache_7.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3340,36 +3484,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.GetS_recv : Accumulator : Sum.u64 = 1132; SumSQ.u64 = 1132; Count.u64 = 1132; Min.u64 = 1; Max.u64 = 1; + l1cache_7.GetS_recv : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l1cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache_7.NACK_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.NACK_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l1cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 234542; SumSQ.u64 = 4494982; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 23; + l1cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 259238; SumSQ.u64 = 4921670; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.packet_latency : Accumulator : Sum.u64 = 529; SumSQ.u64 = 529; Count.u64 = 648; Min.u64 = 0; Max.u64 = 1; - l2cache_7.send_bit_count : Accumulator : Sum.u64 = 68096; SumSQ.u64 = 10747904; Count.u64 = 648; Min.u64 = 64; Max.u64 = 576; - l2cache_7.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.idle_time : Accumulator : Sum.u64 = 3127958; SumSQ.u64 = 235886166438; Count.u64 = 641; Min.u64 = 2; Max.u64 = 139942; - l2cache_7.prefetch_opportunities : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; - l2cache_7.prefetches_issued : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; - l2cache_7.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_7:lowlink.packet_latency : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 650; Min.u64 = 0; Max.u64 = 1; + l2cache_7:lowlink.send_bit_count : Accumulator : Sum.u64 = 66688; SumSQ.u64 = 9773056; Count.u64 = 650; Min.u64 = 64; Max.u64 = 576; + l2cache_7:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.idle_time : Accumulator : Sum.u64 = 3711657; SumSQ.u64 = 374320336169; Count.u64 = 658; Min.u64 = 1; Max.u64 = 179593; + l2cache_7.prefetch_opportunities : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l2cache_7.prefetches_issued : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l2cache_7.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_7.prefetches_canceled_by_history : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.Prefetch_requests : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; - l2cache_7.Prefetch_drops : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache_7.Prefetch_requests : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l2cache_7.Prefetch_drops : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache_7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_7.evict_I : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_7.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3382,8 +3530,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.stateEvent_GetS_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; - l2cache_7.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_7.stateEvent_GetS_I : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + l2cache_7.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3391,7 +3539,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_7.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_7.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l2cache_7.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3471,26 +3619,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.eventSent_GetS : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_7.eventSent_GetS : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.eventSent_NACK : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache_7.eventSent_NACK : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_GetSResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_GetXResp : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.eventSent_FetchInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache_7.eventSent_FetchInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3498,8 +3652,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.latency_GetS_hit : Accumulator : Sum.u64 = 4617; SumSQ.u64 = 1310713; Count.u64 = 170; Min.u64 = 1; Max.u64 = 444; - l2cache_7.latency_GetS_miss : Accumulator : Sum.u64 = 76670; SumSQ.u64 = 36371472; Count.u64 = 168; Min.u64 = 89; Max.u64 = 528; + l2cache_7.latency_GetS_hit : Accumulator : Sum.u64 = 3604; SumSQ.u64 = 996514; Count.u64 = 169; Min.u64 = 1; Max.u64 = 479; + l2cache_7.latency_GetS_miss : Accumulator : Sum.u64 = 86241; SumSQ.u64 = 46320545; Count.u64 = 166; Min.u64 = 92; Max.u64 = 590; l2cache_7.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3511,25 +3665,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l2cache_7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.GetSHit_Blocked : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache_7.GetSHit_Blocked : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.GetSMiss_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_7.GetSMiss_Arrival : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.CacheHits : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; - l2cache_7.CacheMisses : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_7.CacheHits : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l2cache_7.CacheMisses : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_7.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.prefetch_useful : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l2cache_7.prefetch_useful : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache_7.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.prefetch_redundant : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_7.prefetch_redundant : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache_7.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3551,7 +3706,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache_7.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_7.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3561,13 +3716,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache_7.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_7.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.TotalEventsReceived : Accumulator : Sum.u64 = 1324; SumSQ.u64 = 1324; Count.u64 = 1324; Min.u64 = 1; Max.u64 = 1; - l2cache_7.TotalEventsReplayed : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache_7.TotalEventsReceived : Accumulator : Sum.u64 = 1317; SumSQ.u64 = 1317; Count.u64 = 1317; Min.u64 = 1; Max.u64 = 1; + l2cache_7.TotalEventsReplayed : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache_7.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3580,16 +3735,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_7.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.GetS_recv : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; + l2cache_7.GetS_recv : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l2cache_7.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3600,11 +3757,14 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache_7.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 152415; SumSQ.u64 = 1941759; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 16; + l2cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 173767; SumSQ.u64 = 2247465; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 16; l2cache_7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu8.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu8.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3612,25 +3772,25 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu8.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu8.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu8.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu8.cycles_with_issue : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; - cpu8.cycles_no_issue : Accumulator : Sum.u64 = 11551; SumSQ.u64 = 11551; Count.u64 = 11551; Min.u64 = 1; Max.u64 = 1; + cpu8.cycles_with_issue : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + cpu8.cycles_no_issue : Accumulator : Sum.u64 = 12895; SumSQ.u64 = 12895; Count.u64 = 12895; Min.u64 = 1; Max.u64 = 1; cpu8.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu8.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu8.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu8.req_latency : Accumulator : Sum.u64 = 125246; SumSQ.u64 = 24023080; Count.u64 = 936; Min.u64 = 2; Max.u64 = 996; - cpu8.time : Accumulator : Sum.u64 = 4570; SumSQ.u64 = 20884900; Count.u64 = 1; Min.u64 = 4570; Max.u64 = 4570; + cpu8.req_latency : Accumulator : Sum.u64 = 140289; SumSQ.u64 = 28006543; Count.u64 = 936; Min.u64 = 2; Max.u64 = 484; + cpu8.time : Accumulator : Sum.u64 = 5081; SumSQ.u64 = 25816561; Count.u64 = 1; Min.u64 = 5081; Max.u64 = 5081; cpu8.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu8.cycles_max_issue : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; - cpu8.cycles_max_reorder : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - cpu8.cycles : Accumulator : Sum.u64 = 12155; SumSQ.u64 = 12155; Count.u64 = 12155; Min.u64 = 1; Max.u64 = 1; + cpu8.cycles_max_reorder : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + cpu8.cycles : Accumulator : Sum.u64 = 13515; SumSQ.u64 = 13515; Count.u64 = 13515; Min.u64 = 1; Max.u64 = 1; l1cache_8.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache_8.prefetches_issued : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; - l1cache_8.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache_8.prefetches_canceled_by_history : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l1cache_8.Prefetch_requests : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache_8.prefetches_issued : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache_8.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_8.prefetches_canceled_by_history : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache_8.Prefetch_requests : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; l1cache_8.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.stateEvent_GetS_I : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_8.stateEvent_GetS_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_8.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3639,7 +3799,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_8.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_8.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_8.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_8.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3688,7 +3848,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_8.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.eventSent_GetS : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l1cache_8.eventSent_GetS : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3696,13 +3856,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_8.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3710,15 +3873,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_8.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.evict_I : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_8.evict_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_8.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.latency_GetS_hit : Accumulator : Sum.u64 = 118816; SumSQ.u64 = 59299924; Count.u64 = 453; Min.u64 = 1; Max.u64 = 2629; - l1cache_8.latency_GetS_miss : Accumulator : Sum.u64 = 105604; SumSQ.u64 = 58848650; Count.u64 = 313; Min.u64 = 13; Max.u64 = 2647; + l1cache_8.latency_GetS_hit : Accumulator : Sum.u64 = 138071; SumSQ.u64 = 70255849; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1287; + l1cache_8.latency_GetS_miss : Accumulator : Sum.u64 = 121103; SumSQ.u64 = 70921419; Count.u64 = 315; Min.u64 = 13; Max.u64 = 1697; l1cache_8.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3729,39 +3892,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_8.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache_8.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.GetSHit_Blocked : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; + l1cache_8.GetSHit_Blocked : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.GetSMiss_Arrival : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_8.GetSMiss_Arrival : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.CacheHits : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; - l1cache_8.CacheMisses : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_8.CacheHits : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; + l1cache_8.CacheMisses : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_8.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.prefetch_useful : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache_8.prefetch_useful : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; l1cache_8.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.prefetch_redundant : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l1cache_8.stateEvent_GetS_E : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l1cache_8.prefetch_redundant : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache_8.stateEvent_GetS_E : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; l1cache_8.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_8.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_8.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.TotalEventsReceived : Accumulator : Sum.u64 = 1731; SumSQ.u64 = 1731; Count.u64 = 1731; Min.u64 = 1; Max.u64 = 1; - l1cache_8.TotalEventsReplayed : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; + l1cache_8.TotalEventsReceived : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; + l1cache_8.TotalEventsReplayed : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; l1cache_8.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3774,36 +3938,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.GetS_recv : Accumulator : Sum.u64 = 766; SumSQ.u64 = 766; Count.u64 = 766; Min.u64 = 1; Max.u64 = 1; + l1cache_8.GetS_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache_8.NACK_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_8.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.NACK_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l1cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 220639; SumSQ.u64 = 4160807; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 255390; SumSQ.u64 = 4957216; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_8.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.packet_latency : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 639; Min.u64 = 0; Max.u64 = 1; - l2cache_8.send_bit_count : Accumulator : Sum.u64 = 65472; SumSQ.u64 = 9400320; Count.u64 = 639; Min.u64 = 64; Max.u64 = 576; - l2cache_8.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.idle_time : Accumulator : Sum.u64 = 3027063; SumSQ.u64 = 136591984599; Count.u64 = 640; Min.u64 = 1; Max.u64 = 113714; - l2cache_8.prefetch_opportunities : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; - l2cache_8.prefetches_issued : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; - l2cache_8.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; - l2cache_8.prefetches_canceled_by_history : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l2cache_8.Prefetch_requests : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; - l2cache_8.Prefetch_drops : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache_8:lowlink.packet_latency : Accumulator : Sum.u64 = 506; SumSQ.u64 = 506; Count.u64 = 642; Min.u64 = 0; Max.u64 = 1; + l2cache_8:lowlink.send_bit_count : Accumulator : Sum.u64 = 66176; SumSQ.u64 = 9740288; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; + l2cache_8:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.idle_time : Accumulator : Sum.u64 = 3168808; SumSQ.u64 = 123042928718; Count.u64 = 625; Min.u64 = 12; Max.u64 = 104977; + l2cache_8.prefetch_opportunities : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; + l2cache_8.prefetches_issued : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; + l2cache_8.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache_8.prefetches_canceled_by_history : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_8.Prefetch_requests : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; + l2cache_8.Prefetch_drops : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache_8.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.evict_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache_8.evict_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_8.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3816,7 +3984,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.stateEvent_GetS_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache_8.stateEvent_GetS_I : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3825,7 +3993,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_8.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3905,26 +4073,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.eventSent_GetS : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache_8.eventSent_GetS : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.eventSent_NACK : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; - l2cache_8.eventSent_GetSResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_8.eventSent_NACK : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l2cache_8.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.eventSent_FetchInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_8.eventSent_FetchInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3932,8 +4106,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.latency_GetS_hit : Accumulator : Sum.u64 = 3753; SumSQ.u64 = 685775; Count.u64 = 143; Min.u64 = 1; Max.u64 = 346; - l2cache_8.latency_GetS_miss : Accumulator : Sum.u64 = 92022; SumSQ.u64 = 44645892; Count.u64 = 193; Min.u64 = 69; Max.u64 = 527; + l2cache_8.latency_GetS_hit : Accumulator : Sum.u64 = 1625; SumSQ.u64 = 125655; Count.u64 = 131; Min.u64 = 1; Max.u64 = 216; + l2cache_8.latency_GetS_miss : Accumulator : Sum.u64 = 112268; SumSQ.u64 = 62238386; Count.u64 = 207; Min.u64 = 70; Max.u64 = 1101; l2cache_8.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3945,30 +4119,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache_8.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.GetSHit_Blocked : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache_8.GetSHit_Blocked : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.GetSMiss_Arrival : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache_8.GetSMiss_Arrival : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.CacheHits : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; - l2cache_8.CacheMisses : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache_8.CacheHits : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache_8.CacheMisses : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_8.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.prefetch_useful : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l2cache_8.prefetch_useful : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache_8.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.prefetch_redundant : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.stateEvent_GetS_E : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache_8.stateEvent_GetS_E : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3985,7 +4160,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_8.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3995,13 +4170,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_8.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_8.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.TotalEventsReceived : Accumulator : Sum.u64 = 1434; SumSQ.u64 = 1434; Count.u64 = 1434; Min.u64 = 1; Max.u64 = 1; - l2cache_8.TotalEventsReplayed : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache_8.TotalEventsReceived : Accumulator : Sum.u64 = 1401; SumSQ.u64 = 1401; Count.u64 = 1401; Min.u64 = 1; Max.u64 = 1; + l2cache_8.TotalEventsReplayed : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache_8.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4014,16 +4189,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_8.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.GetS_recv : Accumulator : Sum.u64 = 688; SumSQ.u64 = 688; Count.u64 = 688; Min.u64 = 1; Max.u64 = 1; + l2cache_8.GetS_recv : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_8.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4032,13 +4209,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_8.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_8.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 156681; SumSQ.u64 = 2092515; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 176176; SumSQ.u64 = 2343528; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_8.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu9.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu9.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4046,25 +4226,25 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu9.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu9.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu9.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu9.cycles_with_issue : Accumulator : Sum.u64 = 650; SumSQ.u64 = 650; Count.u64 = 650; Min.u64 = 1; Max.u64 = 1; - cpu9.cycles_no_issue : Accumulator : Sum.u64 = 11874; SumSQ.u64 = 11874; Count.u64 = 11874; Min.u64 = 1; Max.u64 = 1; + cpu9.cycles_with_issue : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + cpu9.cycles_no_issue : Accumulator : Sum.u64 = 13360; SumSQ.u64 = 13360; Count.u64 = 13360; Min.u64 = 1; Max.u64 = 1; cpu9.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu9.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu9.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu9.req_latency : Accumulator : Sum.u64 = 127932; SumSQ.u64 = 21733494; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 235; - cpu9.time : Accumulator : Sum.u64 = 4709; SumSQ.u64 = 22174681; Count.u64 = 1; Min.u64 = 4709; Max.u64 = 4709; + cpu9.req_latency : Accumulator : Sum.u64 = 143196; SumSQ.u64 = 27229566; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 254; + cpu9.time : Accumulator : Sum.u64 = 5279; SumSQ.u64 = 27867841; Count.u64 = 1; Min.u64 = 5279; Max.u64 = 5279; cpu9.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu9.cycles_max_issue : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + cpu9.cycles_max_issue : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; cpu9.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu9.cycles : Accumulator : Sum.u64 = 12525; SumSQ.u64 = 12525; Count.u64 = 12525; Min.u64 = 1; Max.u64 = 1; + cpu9.cycles : Accumulator : Sum.u64 = 14042; SumSQ.u64 = 14042; Count.u64 = 14042; Min.u64 = 1; Max.u64 = 1; l1cache_9.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_9.prefetches_issued : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; - l1cache_9.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache_9.prefetches_canceled_by_history : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; - l1cache_9.Prefetch_requests : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; - l1cache_9.Prefetch_drops : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache_9.prefetches_issued : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; + l1cache_9.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_9.prefetches_canceled_by_history : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache_9.Prefetch_requests : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; + l1cache_9.Prefetch_drops : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_9.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.stateEvent_GetS_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_9.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_9.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_9.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4073,7 +4253,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_9.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache_9.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_9.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_9.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4122,7 +4302,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_9.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.eventSent_GetS : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l1cache_9.eventSent_GetS : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4130,13 +4310,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_9.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4144,15 +4327,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_9.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.evict_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_9.evict_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_9.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.latency_GetS_hit : Accumulator : Sum.u64 = 154129; SumSQ.u64 = 66467471; Count.u64 = 809; Min.u64 = 1; Max.u64 = 530; - l1cache_9.latency_GetS_miss : Accumulator : Sum.u64 = 84709; SumSQ.u64 = 39938777; Count.u64 = 315; Min.u64 = 11; Max.u64 = 624; + l1cache_9.latency_GetS_hit : Accumulator : Sum.u64 = 172052; SumSQ.u64 = 82142730; Count.u64 = 820; Min.u64 = 1; Max.u64 = 588; + l1cache_9.latency_GetS_miss : Accumulator : Sum.u64 = 95266; SumSQ.u64 = 50476272; Count.u64 = 316; Min.u64 = 13; Max.u64 = 752; l1cache_9.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4163,39 +4346,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_9.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l1cache_9.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 276; SumSQ.u64 = 276; Count.u64 = 276; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.GetSHit_Blocked : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; + l1cache_9.GetSHit_Blocked : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 544; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.GetSMiss_Arrival : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_9.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.CacheHits : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; - l1cache_9.CacheMisses : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_9.CacheHits : Accumulator : Sum.u64 = 820; SumSQ.u64 = 820; Count.u64 = 820; Min.u64 = 1; Max.u64 = 1; + l1cache_9.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_9.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.prefetch_useful : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_9.prefetch_useful : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l1cache_9.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.prefetch_redundant : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; - l1cache_9.stateEvent_GetS_E : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; + l1cache_9.prefetch_redundant : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache_9.stateEvent_GetS_E : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; l1cache_9.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_9.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_9.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.TotalEventsReceived : Accumulator : Sum.u64 = 1892; SumSQ.u64 = 1892; Count.u64 = 1892; Min.u64 = 1; Max.u64 = 1; - l1cache_9.TotalEventsReplayed : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; + l1cache_9.TotalEventsReceived : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; + l1cache_9.TotalEventsReplayed : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 544; Min.u64 = 1; Max.u64 = 1; l1cache_9.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4208,36 +4392,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_9.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_9.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.GetS_recv : Accumulator : Sum.u64 = 1129; SumSQ.u64 = 1129; Count.u64 = 1129; Min.u64 = 1; Max.u64 = 1; + l1cache_9.GetS_recv : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache_9.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache_9.NACK_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_9.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.NACK_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 232639; SumSQ.u64 = 4448335; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 23; + l1cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 261145; SumSQ.u64 = 5010673; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 23; l1cache_9.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.packet_latency : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 642; Min.u64 = 0; Max.u64 = 1; - l2cache_9.send_bit_count : Accumulator : Sum.u64 = 64128; SumSQ.u64 = 8429568; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; - l2cache_9.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.idle_time : Accumulator : Sum.u64 = 3351980; SumSQ.u64 = 291303384200; Count.u64 = 626; Min.u64 = 1; Max.u64 = 156423; - l2cache_9.prefetch_opportunities : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; - l2cache_9.prefetches_issued : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; - l2cache_9.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_9:lowlink.packet_latency : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 645; Min.u64 = 0; Max.u64 = 1; + l2cache_9:lowlink.send_bit_count : Accumulator : Sum.u64 = 65344; SumSQ.u64 = 9097216; Count.u64 = 645; Min.u64 = 64; Max.u64 = 576; + l2cache_9:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9:lowlink.idle_time : Accumulator : Sum.u64 = 3760632; SumSQ.u64 = 337319354334; Count.u64 = 638; Min.u64 = 5; Max.u64 = 165090; + l2cache_9.prefetch_opportunities : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l2cache_9.prefetches_issued : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l2cache_9.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache_9.prefetches_canceled_by_history : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.Prefetch_requests : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; - l2cache_9.Prefetch_drops : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache_9.Prefetch_requests : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l2cache_9.Prefetch_drops : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_9.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_9.evict_I : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l2cache_9.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4250,8 +4438,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.stateEvent_GetS_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; - l2cache_9.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.stateEvent_GetS_I : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; + l2cache_9.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4259,7 +4447,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_9.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4339,26 +4527,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.eventSent_GetS : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_9.eventSent_GetS : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.eventSent_NACK : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l2cache_9.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache_9.eventSent_NACK : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache_9.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.eventSent_FetchInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_9.eventSent_FetchInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4366,8 +4560,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.latency_GetS_hit : Accumulator : Sum.u64 = 3615; SumSQ.u64 = 1029823; Count.u64 = 163; Min.u64 = 1; Max.u64 = 446; - l2cache_9.latency_GetS_miss : Accumulator : Sum.u64 = 78210; SumSQ.u64 = 37314764; Count.u64 = 168; Min.u64 = 73; Max.u64 = 522; + l2cache_9.latency_GetS_hit : Accumulator : Sum.u64 = 3694; SumSQ.u64 = 1004406; Count.u64 = 168; Min.u64 = 1; Max.u64 = 494; + l2cache_9.latency_GetS_miss : Accumulator : Sum.u64 = 87732; SumSQ.u64 = 46920740; Count.u64 = 169; Min.u64 = 74; Max.u64 = 585; l2cache_9.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4379,30 +4573,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache_9.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.GetSHit_Blocked : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache_9.GetSHit_Blocked : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.GetSMiss_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_9.GetSMiss_Arrival : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.CacheHits : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; - l2cache_9.CacheMisses : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_9.CacheHits : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + l2cache_9.CacheMisses : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l2cache_9.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.prefetch_useful : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; l2cache_9.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.prefetch_redundant : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_9.prefetch_redundant : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.stateEvent_GetS_E : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; + l2cache_9.stateEvent_GetS_E : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4419,7 +4614,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_9.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4429,12 +4624,12 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_9.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache_9.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.TotalEventsReceived : Accumulator : Sum.u64 = 1286; SumSQ.u64 = 1286; Count.u64 = 1286; Min.u64 = 1; Max.u64 = 1; + l2cache_9.TotalEventsReceived : Accumulator : Sum.u64 = 1309; SumSQ.u64 = 1309; Count.u64 = 1309; Min.u64 = 1; Max.u64 = 1; l2cache_9.TotalEventsReplayed : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache_9.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4448,16 +4643,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_9.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.GetS_recv : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; + l2cache_9.GetS_recv : Accumulator : Sum.u64 = 546; SumSQ.u64 = 546; Count.u64 = 546; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_9.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_9.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4466,13 +4663,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache_9.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_9.FetchXResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_9.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 155746; SumSQ.u64 = 2038954; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 16; + l2cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 170884; SumSQ.u64 = 2191960; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 16; l2cache_9.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu10.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu10.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4480,26 +4680,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu10.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu10.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu10.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu10.cycles_with_issue : Accumulator : Sum.u64 = 622; SumSQ.u64 = 622; Count.u64 = 622; Min.u64 = 1; Max.u64 = 1; - cpu10.cycles_no_issue : Accumulator : Sum.u64 = 11533; SumSQ.u64 = 11533; Count.u64 = 11533; Min.u64 = 1; Max.u64 = 1; + cpu10.cycles_with_issue : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; + cpu10.cycles_no_issue : Accumulator : Sum.u64 = 12943; SumSQ.u64 = 12943; Count.u64 = 12943; Min.u64 = 1; Max.u64 = 1; cpu10.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu10.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu10.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu10.req_latency : Accumulator : Sum.u64 = 124191; SumSQ.u64 = 22985961; Count.u64 = 936; Min.u64 = 2; Max.u64 = 610; - cpu10.time : Accumulator : Sum.u64 = 4570; SumSQ.u64 = 20884900; Count.u64 = 1; Min.u64 = 4570; Max.u64 = 4570; + cpu10.req_latency : Accumulator : Sum.u64 = 139721; SumSQ.u64 = 31533709; Count.u64 = 936; Min.u64 = 2; Max.u64 = 631; + cpu10.time : Accumulator : Sum.u64 = 5095; SumSQ.u64 = 25959025; Count.u64 = 1; Min.u64 = 5095; Max.u64 = 5095; cpu10.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu10.cycles_max_issue : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - cpu10.cycles_max_reorder : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - cpu10.cycles : Accumulator : Sum.u64 = 12156; SumSQ.u64 = 12156; Count.u64 = 12156; Min.u64 = 1; Max.u64 = 1; + cpu10.cycles_max_issue : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + cpu10.cycles_max_reorder : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + cpu10.cycles : Accumulator : Sum.u64 = 13551; SumSQ.u64 = 13551; Count.u64 = 13551; Min.u64 = 1; Max.u64 = 1; l1cache_10.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache_10.prefetches_issued : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l1cache_10.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache_10.prefetches_canceled_by_history : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache_10.Prefetch_requests : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache_10.prefetches_issued : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache_10.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_10.prefetches_canceled_by_history : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache_10.Prefetch_requests : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l1cache_10.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_10.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.stateEvent_GetS_I : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; - l1cache_10.stateEvent_GetS_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_10.stateEvent_GetS_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache_10.stateEvent_GetS_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_10.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4507,8 +4707,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_10.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache_10.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; + l1cache_10.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_10.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l1cache_10.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4556,7 +4756,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_10.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.eventSent_GetS : Accumulator : Sum.u64 = 467; SumSQ.u64 = 467; Count.u64 = 467; Min.u64 = 1; Max.u64 = 1; + l1cache_10.eventSent_GetS : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4564,13 +4764,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_10.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4578,15 +4781,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_10.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.evict_I : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache_10.evict_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_10.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.latency_GetS_hit : Accumulator : Sum.u64 = 114788; SumSQ.u64 = 54076438; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1447; - l1cache_10.latency_GetS_miss : Accumulator : Sum.u64 = 105136; SumSQ.u64 = 57387472; Count.u64 = 314; Min.u64 = 11; Max.u64 = 1622; + l1cache_10.latency_GetS_hit : Accumulator : Sum.u64 = 129731; SumSQ.u64 = 77605743; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1288; + l1cache_10.latency_GetS_miss : Accumulator : Sum.u64 = 119030; SumSQ.u64 = 84707512; Count.u64 = 315; Min.u64 = 13; Max.u64 = 1678; l1cache_10.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4597,39 +4800,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_10.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l1cache_10.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.GetSHit_Blocked : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; + l1cache_10.GetSHit_Blocked : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.GetSMiss_Arrival : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache_10.GetSMiss_Arrival : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.CacheHits : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; - l1cache_10.CacheMisses : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache_10.CacheHits : Accumulator : Sum.u64 = 450; SumSQ.u64 = 450; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1; + l1cache_10.CacheMisses : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_10.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.prefetch_useful : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache_10.prefetch_useful : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; l1cache_10.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.prefetch_redundant : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; - l1cache_10.stateEvent_GetS_E : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l1cache_10.prefetch_redundant : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache_10.stateEvent_GetS_E : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; l1cache_10.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache_10.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_10.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.TotalEventsReceived : Accumulator : Sum.u64 = 1726; SumSQ.u64 = 1726; Count.u64 = 1726; Min.u64 = 1; Max.u64 = 1; - l1cache_10.TotalEventsReplayed : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; + l1cache_10.TotalEventsReceived : Accumulator : Sum.u64 = 1757; SumSQ.u64 = 1757; Count.u64 = 1757; Min.u64 = 1; Max.u64 = 1; + l1cache_10.TotalEventsReplayed : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; l1cache_10.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4642,36 +4846,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.GetS_recv : Accumulator : Sum.u64 = 764; SumSQ.u64 = 764; Count.u64 = 764; Min.u64 = 1; Max.u64 = 1; + l1cache_10.GetS_recv : Accumulator : Sum.u64 = 766; SumSQ.u64 = 766; Count.u64 = 766; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; + l1cache_10.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l1cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache_10.NACK_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_10.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.NACK_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l1cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 216170; SumSQ.u64 = 4053766; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 21; + l1cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 245006; SumSQ.u64 = 4635642; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_10.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.packet_latency : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 642; Min.u64 = 0; Max.u64 = 1; - l2cache_10.send_bit_count : Accumulator : Sum.u64 = 66688; SumSQ.u64 = 10067968; Count.u64 = 642; Min.u64 = 64; Max.u64 = 576; - l2cache_10.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.idle_time : Accumulator : Sum.u64 = 2873779; SumSQ.u64 = 114365008887; Count.u64 = 630; Min.u64 = 7; Max.u64 = 114607; - l2cache_10.prefetch_opportunities : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l2cache_10:lowlink.packet_latency : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 639; Min.u64 = 0; Max.u64 = 1; + l2cache_10:lowlink.send_bit_count : Accumulator : Sum.u64 = 65472; SumSQ.u64 = 9400320; Count.u64 = 639; Min.u64 = 64; Max.u64 = 576; + l2cache_10:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10:lowlink.idle_time : Accumulator : Sum.u64 = 3683925; SumSQ.u64 = 369089942239; Count.u64 = 655; Min.u64 = 6; Max.u64 = 164716; + l2cache_10.prefetch_opportunities : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l2cache_10.prefetches_issued : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; - l2cache_10.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache_10.prefetches_canceled_by_history : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_10.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache_10.prefetches_canceled_by_history : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_10.Prefetch_requests : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; - l2cache_10.Prefetch_drops : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache_10.Prefetch_drops : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l2cache_10.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.evict_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_10.evict_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l2cache_10.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4684,8 +4892,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.stateEvent_GetS_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; - l2cache_10.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.stateEvent_GetS_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache_10.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4693,7 +4901,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_10.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4773,26 +4981,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.eventSent_GetS : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_10.eventSent_GetS : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.eventSent_NACK : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; - l2cache_10.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache_10.eventSent_GetXResp : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; + l2cache_10.eventSent_NACK : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l2cache_10.eventSent_GetSResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_10.eventSent_GetXResp : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.eventSent_FetchInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_10.eventSent_FetchInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4800,8 +5014,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.latency_GetS_hit : Accumulator : Sum.u64 = 2163; SumSQ.u64 = 230585; Count.u64 = 139; Min.u64 = 1; Max.u64 = 281; - l2cache_10.latency_GetS_miss : Accumulator : Sum.u64 = 93983; SumSQ.u64 = 46340259; Count.u64 = 195; Min.u64 = 83; Max.u64 = 840; + l2cache_10.latency_GetS_hit : Accumulator : Sum.u64 = 4555; SumSQ.u64 = 1527097; Count.u64 = 155; Min.u64 = 1; Max.u64 = 522; + l2cache_10.latency_GetS_miss : Accumulator : Sum.u64 = 97730; SumSQ.u64 = 53269218; Count.u64 = 183; Min.u64 = 85; Max.u64 = 587; l2cache_10.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4813,30 +5027,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache_10.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.GetSHit_Blocked : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache_10.GetSHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.GetSMiss_Arrival : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_10.GetSMiss_Arrival : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.CacheHits : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; - l2cache_10.CacheMisses : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache_10.CacheHits : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache_10.CacheMisses : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l2cache_10.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.prefetch_useful : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l2cache_10.prefetch_useful : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l2cache_10.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.prefetch_redundant : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache_10.prefetch_redundant : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.stateEvent_GetS_E : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache_10.stateEvent_GetS_E : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4853,7 +5068,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_10.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4863,13 +5078,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_10.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_10.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.TotalEventsReceived : Accumulator : Sum.u64 = 1432; SumSQ.u64 = 1432; Count.u64 = 1432; Min.u64 = 1; Max.u64 = 1; - l2cache_10.TotalEventsReplayed : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache_10.TotalEventsReceived : Accumulator : Sum.u64 = 1460; SumSQ.u64 = 1460; Count.u64 = 1460; Min.u64 = 1; Max.u64 = 1; + l2cache_10.TotalEventsReplayed : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l2cache_10.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4882,16 +5097,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_10.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.GetS_recv : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l2cache_10.GetS_recv : Accumulator : Sum.u64 = 714; SumSQ.u64 = 714; Count.u64 = 714; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_10.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_10.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4900,13 +5117,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_10.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.FetchXResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_10.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_10.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 156829; SumSQ.u64 = 2139889; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 177049; SumSQ.u64 = 2440737; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_10.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu11.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu11.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4914,22 +5134,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu11.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu11.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu11.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu11.cycles_with_issue : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; - cpu11.cycles_no_issue : Accumulator : Sum.u64 = 11880; SumSQ.u64 = 11880; Count.u64 = 11880; Min.u64 = 1; Max.u64 = 1; + cpu11.cycles_with_issue : Accumulator : Sum.u64 = 656; SumSQ.u64 = 656; Count.u64 = 656; Min.u64 = 1; Max.u64 = 1; + cpu11.cycles_no_issue : Accumulator : Sum.u64 = 13346; SumSQ.u64 = 13346; Count.u64 = 13346; Min.u64 = 1; Max.u64 = 1; cpu11.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu11.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu11.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu11.req_latency : Accumulator : Sum.u64 = 127307; SumSQ.u64 = 21411857; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 418; - cpu11.time : Accumulator : Sum.u64 = 4719; SumSQ.u64 = 22268961; Count.u64 = 1; Min.u64 = 4719; Max.u64 = 4719; + cpu11.req_latency : Accumulator : Sum.u64 = 143111; SumSQ.u64 = 27370295; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 226; + cpu11.time : Accumulator : Sum.u64 = 5265; SumSQ.u64 = 27720225; Count.u64 = 1; Min.u64 = 5265; Max.u64 = 5265; cpu11.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu11.cycles_max_issue : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + cpu11.cycles_max_issue : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; cpu11.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu11.cycles : Accumulator : Sum.u64 = 12551; SumSQ.u64 = 12551; Count.u64 = 12551; Min.u64 = 1; Max.u64 = 1; + cpu11.cycles : Accumulator : Sum.u64 = 14003; SumSQ.u64 = 14003; Count.u64 = 14003; Min.u64 = 1; Max.u64 = 1; l1cache_11.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_11.prefetches_issued : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; - l1cache_11.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache_11.prefetches_canceled_by_history : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; - l1cache_11.Prefetch_requests : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l1cache_11.prefetches_issued : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; + l1cache_11.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache_11.prefetches_canceled_by_history : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache_11.Prefetch_requests : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l1cache_11.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_11.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_GetS_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; @@ -4990,7 +5210,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_11.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.eventSent_GetS : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; + l1cache_11.eventSent_GetS : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4998,13 +5218,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_11.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5019,8 +5242,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_11.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.latency_GetS_hit : Accumulator : Sum.u64 = 152515; SumSQ.u64 = 63829757; Count.u64 = 813; Min.u64 = 1; Max.u64 = 728; - l1cache_11.latency_GetS_miss : Accumulator : Sum.u64 = 86519; SumSQ.u64 = 41661561; Count.u64 = 318; Min.u64 = 13; Max.u64 = 1111; + l1cache_11.latency_GetS_hit : Accumulator : Sum.u64 = 168738; SumSQ.u64 = 81594368; Count.u64 = 807; Min.u64 = 1; Max.u64 = 597; + l1cache_11.latency_GetS_miss : Accumulator : Sum.u64 = 95708; SumSQ.u64 = 50276752; Count.u64 = 318; Min.u64 = 13; Max.u64 = 605; l1cache_11.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5031,10 +5254,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_11.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; + l1cache_11.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.GetSHit_Blocked : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l1cache_11.GetSHit_Blocked : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSMiss_Arrival : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; @@ -5043,27 +5267,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_11.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.CacheHits : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; + l1cache_11.CacheHits : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; l1cache_11.CacheMisses : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l1cache_11.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.prefetch_inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache_11.prefetch_useful : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache_11.prefetch_useful : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l1cache_11.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.prefetch_redundant : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; - l1cache_11.stateEvent_GetS_E : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; + l1cache_11.prefetch_redundant : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache_11.stateEvent_GetS_E : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; l1cache_11.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_11.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_11.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_11.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.TotalEventsReceived : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; - l1cache_11.TotalEventsReplayed : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l1cache_11.TotalEventsReceived : Accumulator : Sum.u64 = 1923; SumSQ.u64 = 1923; Count.u64 = 1923; Min.u64 = 1; Max.u64 = 1; + l1cache_11.TotalEventsReplayed : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; l1cache_11.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5076,34 +5300,38 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_11.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_11.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.GetS_recv : Accumulator : Sum.u64 = 1132; SumSQ.u64 = 1132; Count.u64 = 1132; Min.u64 = 1; Max.u64 = 1; + l1cache_11.GetS_recv : Accumulator : Sum.u64 = 1126; SumSQ.u64 = 1126; Count.u64 = 1126; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache_11.NACK_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache_11.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.NACK_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l1cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 232903; SumSQ.u64 = 4419813; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 258322; SumSQ.u64 = 4869928; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 23; l1cache_11.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.packet_latency : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 645; Min.u64 = 0; Max.u64 = 1; - l2cache_11.send_bit_count : Accumulator : Sum.u64 = 64832; SumSQ.u64 = 8769536; Count.u64 = 645; Min.u64 = 64; Max.u64 = 576; - l2cache_11.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.idle_time : Accumulator : Sum.u64 = 3192219; SumSQ.u64 = 177187647111; Count.u64 = 637; Min.u64 = 1; Max.u64 = 119992; - l2cache_11.prefetch_opportunities : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; - l2cache_11.prefetches_issued : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; - l2cache_11.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache_11:lowlink.packet_latency : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 644; Min.u64 = 0; Max.u64 = 1; + l2cache_11:lowlink.send_bit_count : Accumulator : Sum.u64 = 64256; SumSQ.u64 = 8437760; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + l2cache_11:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink.idle_time : Accumulator : Sum.u64 = 3912414; SumSQ.u64 = 403059087482; Count.u64 = 645; Min.u64 = 2; Max.u64 = 165817; + l2cache_11.prefetch_opportunities : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; + l2cache_11.prefetches_issued : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l2cache_11.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_11.prefetches_canceled_by_history : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache_11.Prefetch_requests : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; - l2cache_11.Prefetch_drops : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache_11.Prefetch_requests : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l2cache_11.Prefetch_drops : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_11.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.evict_I : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_11.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5119,7 +5347,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_GetS_I : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; - l2cache_11.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache_11.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache_11.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5213,20 +5441,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_11.eventSent_NACK : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache_11.eventSent_NACK : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_GetXResp : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FetchInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.eventSent_FetchInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_11.eventSent_FetchInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5234,8 +5468,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.latency_GetS_hit : Accumulator : Sum.u64 = 3004; SumSQ.u64 = 560204; Count.u64 = 160; Min.u64 = 1; Max.u64 = 375; - l2cache_11.latency_GetS_miss : Accumulator : Sum.u64 = 79425; SumSQ.u64 = 37517717; Count.u64 = 175; Min.u64 = 95; Max.u64 = 522; + l2cache_11.latency_GetS_hit : Accumulator : Sum.u64 = 4285; SumSQ.u64 = 1320193; Count.u64 = 169; Min.u64 = 1; Max.u64 = 523; + l2cache_11.latency_GetS_miss : Accumulator : Sum.u64 = 86573; SumSQ.u64 = 45965569; Count.u64 = 170; Min.u64 = 99; Max.u64 = 593; l2cache_11.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5247,10 +5481,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache_11.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.GetSHit_Blocked : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache_11.GetSHit_Blocked : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSMiss_Arrival : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; @@ -5259,18 +5494,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.CacheHits : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l2cache_11.CacheHits : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l2cache_11.CacheMisses : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_11.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.prefetch_inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_11.prefetch_useful : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache_11.prefetch_useful : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_11.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.prefetch_redundant : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache_11.prefetch_redundant : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache_11.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.stateEvent_GetS_E : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l2cache_11.stateEvent_GetS_E : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; l2cache_11.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5287,7 +5522,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_11.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_11.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -5297,13 +5532,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_11.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_11.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_11.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.TotalEventsReceived : Accumulator : Sum.u64 = 1309; SumSQ.u64 = 1309; Count.u64 = 1309; Min.u64 = 1; Max.u64 = 1; - l2cache_11.TotalEventsReplayed : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache_11.TotalEventsReceived : Accumulator : Sum.u64 = 1319; SumSQ.u64 = 1319; Count.u64 = 1319; Min.u64 = 1; Max.u64 = 1; + l2cache_11.TotalEventsReplayed : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache_11.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5316,16 +5551,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_11.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.GetS_recv : Accumulator : Sum.u64 = 537; SumSQ.u64 = 537; Count.u64 = 537; Min.u64 = 1; Max.u64 = 1; + l2cache_11.GetS_recv : Accumulator : Sum.u64 = 553; SumSQ.u64 = 553; Count.u64 = 553; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l2cache_11.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5334,13 +5571,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache_11.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_11.FetchXResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache_11.FetchXResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache_11.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 151202; SumSQ.u64 = 1905522; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 172086; SumSQ.u64 = 2189154; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_11.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu12.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu12.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5348,26 +5588,26 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu12.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu12.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu12.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu12.cycles_with_issue : Accumulator : Sum.u64 = 609; SumSQ.u64 = 609; Count.u64 = 609; Min.u64 = 1; Max.u64 = 1; - cpu12.cycles_no_issue : Accumulator : Sum.u64 = 11512; SumSQ.u64 = 11512; Count.u64 = 11512; Min.u64 = 1; Max.u64 = 1; + cpu12.cycles_with_issue : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; + cpu12.cycles_no_issue : Accumulator : Sum.u64 = 12587; SumSQ.u64 = 12587; Count.u64 = 12587; Min.u64 = 1; Max.u64 = 1; cpu12.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu12.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu12.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu12.req_latency : Accumulator : Sum.u64 = 124008; SumSQ.u64 = 22258978; Count.u64 = 936; Min.u64 = 2; Max.u64 = 438; - cpu12.time : Accumulator : Sum.u64 = 4557; SumSQ.u64 = 20766249; Count.u64 = 1; Min.u64 = 4557; Max.u64 = 4557; + cpu12.req_latency : Accumulator : Sum.u64 = 138509; SumSQ.u64 = 29348171; Count.u64 = 936; Min.u64 = 2; Max.u64 = 633; + cpu12.time : Accumulator : Sum.u64 = 4958; SumSQ.u64 = 24581764; Count.u64 = 1; Min.u64 = 4958; Max.u64 = 4958; cpu12.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu12.cycles_max_issue : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; - cpu12.cycles_max_reorder : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - cpu12.cycles : Accumulator : Sum.u64 = 12122; SumSQ.u64 = 12122; Count.u64 = 12122; Min.u64 = 1; Max.u64 = 1; + cpu12.cycles_max_issue : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + cpu12.cycles_max_reorder : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + cpu12.cycles : Accumulator : Sum.u64 = 13187; SumSQ.u64 = 13187; Count.u64 = 13187; Min.u64 = 1; Max.u64 = 1; l1cache_12.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache_12.prefetches_issued : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; - l1cache_12.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache_12.prefetches_canceled_by_history : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache_12.Prefetch_requests : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; - l1cache_12.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_12.prefetches_issued : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l1cache_12.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache_12.prefetches_canceled_by_history : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache_12.Prefetch_requests : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l1cache_12.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.stateEvent_GetS_I : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; - l1cache_12.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.stateEvent_GetS_I : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache_12.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_12.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5376,7 +5616,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_12.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_12.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_12.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5424,7 +5664,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.eventSent_GetS : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; + l1cache_12.eventSent_GetS : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5432,13 +5672,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5446,15 +5689,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.evict_I : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache_12.evict_I : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l1cache_12.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.latency_GetS_hit : Accumulator : Sum.u64 = 119361; SumSQ.u64 = 55109683; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1164; - l1cache_12.latency_GetS_miss : Accumulator : Sum.u64 = 106715; SumSQ.u64 = 55703409; Count.u64 = 314; Min.u64 = 12; Max.u64 = 1620; + l1cache_12.latency_GetS_hit : Accumulator : Sum.u64 = 128998; SumSQ.u64 = 72504804; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1673; + l1cache_12.latency_GetS_miss : Accumulator : Sum.u64 = 116807; SumSQ.u64 = 71806699; Count.u64 = 313; Min.u64 = 12; Max.u64 = 1681; l1cache_12.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5465,29 +5708,30 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache_12.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.GetSHit_Blocked : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; + l1cache_12.GetSHit_Blocked : Accumulator : Sum.u64 = 340; SumSQ.u64 = 340; Count.u64 = 340; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.GetSMiss_Arrival : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache_12.GetSMiss_Arrival : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.CacheHits : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; - l1cache_12.CacheMisses : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache_12.CacheMisses : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l1cache_12.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.prefetch_useful : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache_12.prefetch_useful : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l1cache_12.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.prefetch_redundant : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l1cache_12.stateEvent_GetS_E : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; + l1cache_12.prefetch_redundant : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache_12.stateEvent_GetS_E : Accumulator : Sum.u64 = 450; SumSQ.u64 = 450; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1; l1cache_12.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5496,8 +5740,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_12.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.TotalEventsReceived : Accumulator : Sum.u64 = 1692; SumSQ.u64 = 1692; Count.u64 = 1692; Min.u64 = 1; Max.u64 = 1; - l1cache_12.TotalEventsReplayed : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; + l1cache_12.TotalEventsReceived : Accumulator : Sum.u64 = 1694; SumSQ.u64 = 1694; Count.u64 = 1694; Min.u64 = 1; Max.u64 = 1; + l1cache_12.TotalEventsReplayed : Accumulator : Sum.u64 = 340; SumSQ.u64 = 340; Count.u64 = 340; Min.u64 = 1; Max.u64 = 1; l1cache_12.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5510,36 +5754,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.GetS_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; + l1cache_12.GetS_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache_12.NACK_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l1cache_12.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.NACK_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 222284; SumSQ.u64 = 4280012; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 242034; SumSQ.u64 = 4609176; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 21; l1cache_12.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.packet_latency : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 643; Min.u64 = 0; Max.u64 = 1; - l2cache_12.send_bit_count : Accumulator : Sum.u64 = 65728; SumSQ.u64 = 9416704; Count.u64 = 643; Min.u64 = 64; Max.u64 = 576; - l2cache_12.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.idle_time : Accumulator : Sum.u64 = 2929969; SumSQ.u64 = 181374936069; Count.u64 = 652; Min.u64 = 29; Max.u64 = 138444; - l2cache_12.prefetch_opportunities : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; - l2cache_12.prefetches_issued : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; - l2cache_12.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l2cache_12.prefetches_canceled_by_history : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache_12.Prefetch_requests : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; - l2cache_12.Prefetch_drops : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l2cache_12:lowlink.packet_latency : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 640; Min.u64 = 0; Max.u64 = 1; + l2cache_12:lowlink.send_bit_count : Accumulator : Sum.u64 = 65536; SumSQ.u64 = 9404416; Count.u64 = 640; Min.u64 = 64; Max.u64 = 576; + l2cache_12:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.idle_time : Accumulator : Sum.u64 = 3525010; SumSQ.u64 = 269655282440; Count.u64 = 632; Min.u64 = 8; Max.u64 = 177303; + l2cache_12.prefetch_opportunities : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; + l2cache_12.prefetches_issued : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l2cache_12.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache_12.prefetches_canceled_by_history : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_12.Prefetch_requests : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l2cache_12.Prefetch_drops : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache_12.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.evict_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_12.evict_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; l2cache_12.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5552,7 +5800,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.stateEvent_GetS_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_12.stateEvent_GetS_I : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; l2cache_12.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5561,7 +5809,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_12.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_12.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_12.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5641,22 +5889,28 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.eventSent_GetS : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_12.eventSent_GetS : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.eventSent_NACK : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l2cache_12.eventSent_NACK : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_GetSResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache_12.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache_12.eventSent_GetXResp : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5668,8 +5922,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.latency_GetS_hit : Accumulator : Sum.u64 = 2517; SumSQ.u64 = 531555; Count.u64 = 123; Min.u64 = 1; Max.u64 = 483; - l2cache_12.latency_GetS_miss : Accumulator : Sum.u64 = 96564; SumSQ.u64 = 47246736; Count.u64 = 201; Min.u64 = 67; Max.u64 = 771; + l2cache_12.latency_GetS_hit : Accumulator : Sum.u64 = 3671; SumSQ.u64 = 1004073; Count.u64 = 134; Min.u64 = 1; Max.u64 = 526; + l2cache_12.latency_GetS_miss : Accumulator : Sum.u64 = 103300; SumSQ.u64 = 56638800; Count.u64 = 192; Min.u64 = 68; Max.u64 = 814; l2cache_12.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5681,30 +5935,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache_12.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.GetSHit_Blocked : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache_12.GetSHit_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.GetSMiss_Arrival : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_12.GetSMiss_Arrival : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.CacheHits : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; - l2cache_12.CacheMisses : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_12.CacheHits : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l2cache_12.CacheMisses : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; l2cache_12.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.prefetch_useful : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l2cache_12.prefetch_useful : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l2cache_12.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.prefetch_redundant : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_12.prefetch_redundant : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache_12.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.stateEvent_GetS_E : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + l2cache_12.stateEvent_GetS_E : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; l2cache_12.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5736,8 +5991,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.TotalEventsReceived : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; - l2cache_12.TotalEventsReplayed : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache_12.TotalEventsReceived : Accumulator : Sum.u64 = 1398; SumSQ.u64 = 1398; Count.u64 = 1398; Min.u64 = 1; Max.u64 = 1; + l2cache_12.TotalEventsReplayed : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_12.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5750,16 +6005,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_12.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.GetS_recv : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; + l2cache_12.GetS_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_12.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_12.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5771,10 +6028,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache_12.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_12.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 158668; SumSQ.u64 = 2141344; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 176690; SumSQ.u64 = 2424902; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_12.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu13.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu13.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5782,22 +6042,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu13.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu13.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu13.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu13.cycles_with_issue : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; - cpu13.cycles_no_issue : Accumulator : Sum.u64 = 11873; SumSQ.u64 = 11873; Count.u64 = 11873; Min.u64 = 1; Max.u64 = 1; + cpu13.cycles_with_issue : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; + cpu13.cycles_no_issue : Accumulator : Sum.u64 = 13350; SumSQ.u64 = 13350; Count.u64 = 13350; Min.u64 = 1; Max.u64 = 1; cpu13.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu13.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu13.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu13.req_latency : Accumulator : Sum.u64 = 127465; SumSQ.u64 = 21689795; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 315; - cpu13.time : Accumulator : Sum.u64 = 4716; SumSQ.u64 = 22240656; Count.u64 = 1; Min.u64 = 4716; Max.u64 = 4716; + cpu13.req_latency : Accumulator : Sum.u64 = 142704; SumSQ.u64 = 26987184; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 438; + cpu13.time : Accumulator : Sum.u64 = 5274; SumSQ.u64 = 27815076; Count.u64 = 1; Min.u64 = 5274; Max.u64 = 5274; cpu13.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu13.cycles_max_issue : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + cpu13.cycles_max_issue : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; cpu13.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu13.cycles : Accumulator : Sum.u64 = 12545; SumSQ.u64 = 12545; Count.u64 = 12545; Min.u64 = 1; Max.u64 = 1; + cpu13.cycles : Accumulator : Sum.u64 = 14027; SumSQ.u64 = 14027; Count.u64 = 14027; Min.u64 = 1; Max.u64 = 1; l1cache_13.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_13.prefetches_issued : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; - l1cache_13.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache_13.prefetches_canceled_by_history : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; - l1cache_13.Prefetch_requests : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l1cache_13.prefetches_issued : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; + l1cache_13.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_13.prefetches_canceled_by_history : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache_13.Prefetch_requests : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; l1cache_13.Prefetch_drops : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_13.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_GetS_I : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; @@ -5809,7 +6069,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache_13.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_13.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_13.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5858,7 +6118,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.eventSent_GetS : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; + l1cache_13.eventSent_GetS : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5866,13 +6126,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5887,8 +6150,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.latency_GetS_hit : Accumulator : Sum.u64 = 151382; SumSQ.u64 = 65060140; Count.u64 = 802; Min.u64 = 1; Max.u64 = 576; - l1cache_13.latency_GetS_miss : Accumulator : Sum.u64 = 86137; SumSQ.u64 = 41380221; Count.u64 = 317; Min.u64 = 12; Max.u64 = 1084; + l1cache_13.latency_GetS_hit : Accumulator : Sum.u64 = 176578; SumSQ.u64 = 83501322; Count.u64 = 812; Min.u64 = 1; Max.u64 = 1161; + l1cache_13.latency_GetS_miss : Accumulator : Sum.u64 = 97876; SumSQ.u64 = 53802406; Count.u64 = 316; Min.u64 = 13; Max.u64 = 1164; l1cache_13.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5899,10 +6162,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; + l1cache_13.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.GetSHit_Blocked : Accumulator : Sum.u64 = 532; SumSQ.u64 = 532; Count.u64 = 532; Min.u64 = 1; Max.u64 = 1; + l1cache_13.GetSHit_Blocked : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSMiss_Arrival : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; @@ -5911,27 +6175,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.CacheHits : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; + l1cache_13.CacheHits : Accumulator : Sum.u64 = 812; SumSQ.u64 = 812; Count.u64 = 812; Min.u64 = 1; Max.u64 = 1; l1cache_13.CacheMisses : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l1cache_13.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.prefetch_useful : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache_13.prefetch_useful : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache_13.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.prefetch_redundant : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; - l1cache_13.stateEvent_GetS_E : Accumulator : Sum.u64 = 800; SumSQ.u64 = 800; Count.u64 = 800; Min.u64 = 1; Max.u64 = 1; + l1cache_13.prefetch_redundant : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l1cache_13.stateEvent_GetS_E : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; l1cache_13.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_13.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache_13.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.TotalEventsReceived : Accumulator : Sum.u64 = 1926; SumSQ.u64 = 1926; Count.u64 = 1926; Min.u64 = 1; Max.u64 = 1; - l1cache_13.TotalEventsReplayed : Accumulator : Sum.u64 = 532; SumSQ.u64 = 532; Count.u64 = 532; Min.u64 = 1; Max.u64 = 1; + l1cache_13.TotalEventsReceived : Accumulator : Sum.u64 = 1936; SumSQ.u64 = 1936; Count.u64 = 1936; Min.u64 = 1; Max.u64 = 1; + l1cache_13.TotalEventsReplayed : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; l1cache_13.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5944,36 +6208,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_13.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_13.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.GetS_recv : Accumulator : Sum.u64 = 1121; SumSQ.u64 = 1121; Count.u64 = 1121; Min.u64 = 1; Max.u64 = 1; + l1cache_13.GetS_recv : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache_13.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache_13.NACK_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache_13.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.NACK_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l1cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 231349; SumSQ.u64 = 4379585; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 268501; SumSQ.u64 = 5243361; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 24; l1cache_13.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.packet_latency : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 646; Min.u64 = 0; Max.u64 = 1; - l2cache_13.send_bit_count : Accumulator : Sum.u64 = 65920; SumSQ.u64 = 9428992; Count.u64 = 646; Min.u64 = 64; Max.u64 = 576; - l2cache_13.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.idle_time : Accumulator : Sum.u64 = 3136286; SumSQ.u64 = 257651586286; Count.u64 = 636; Min.u64 = 5; Max.u64 = 153513; - l2cache_13.prefetch_opportunities : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; - l2cache_13.prefetches_issued : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; - l2cache_13.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache_13:lowlink.packet_latency : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 642; Min.u64 = 0; Max.u64 = 1; + l2cache_13:lowlink.send_bit_count : Accumulator : Sum.u64 = 64768; SumSQ.u64 = 8765440; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + l2cache_13:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13:lowlink.idle_time : Accumulator : Sum.u64 = 3412169; SumSQ.u64 = 215666283343; Count.u64 = 628; Min.u64 = 14; Max.u64 = 132264; + l2cache_13.prefetch_opportunities : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l2cache_13.prefetches_issued : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache_13.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache_13.prefetches_canceled_by_history : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache_13.Prefetch_requests : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; - l2cache_13.Prefetch_drops : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_13.Prefetch_requests : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache_13.Prefetch_drops : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache_13.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_13.evict_I : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_13.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5986,7 +6254,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.stateEvent_GetS_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_13.stateEvent_GetS_I : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5995,7 +6263,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_13.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6075,26 +6343,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.eventSent_GetS : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_13.eventSent_GetS : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_13.eventSent_NACK : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; - l2cache_13.eventSent_GetSResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache_13.eventSent_NACK : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache_13.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.eventSent_FetchInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_13.eventSent_FetchInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6102,8 +6376,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.latency_GetS_hit : Accumulator : Sum.u64 = 4423; SumSQ.u64 = 1248863; Count.u64 = 164; Min.u64 = 1; Max.u64 = 448; - l2cache_13.latency_GetS_miss : Accumulator : Sum.u64 = 77257; SumSQ.u64 = 37224651; Count.u64 = 167; Min.u64 = 79; Max.u64 = 1078; + l2cache_13.latency_GetS_hit : Accumulator : Sum.u64 = 3401; SumSQ.u64 = 823195; Count.u64 = 163; Min.u64 = 1; Max.u64 = 498; + l2cache_13.latency_GetS_miss : Accumulator : Sum.u64 = 88973; SumSQ.u64 = 48052365; Count.u64 = 172; Min.u64 = 81; Max.u64 = 1063; l2cache_13.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6115,30 +6389,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l2cache_13.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.GetSHit_Blocked : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_13.GetSHit_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.GetSMiss_Arrival : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_13.GetSMiss_Arrival : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.CacheHits : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; - l2cache_13.CacheMisses : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache_13.CacheHits : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; + l2cache_13.CacheMisses : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache_13.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.prefetch_inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache_13.prefetch_useful : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l2cache_13.prefetch_useful : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l2cache_13.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.prefetch_redundant : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache_13.prefetch_redundant : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.stateEvent_GetS_E : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l2cache_13.stateEvent_GetS_E : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6155,7 +6430,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_13.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6165,13 +6440,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_13.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_13.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.TotalEventsReceived : Accumulator : Sum.u64 = 1324; SumSQ.u64 = 1324; Count.u64 = 1324; Min.u64 = 1; Max.u64 = 1; - l2cache_13.TotalEventsReplayed : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache_13.TotalEventsReceived : Accumulator : Sum.u64 = 1331; SumSQ.u64 = 1331; Count.u64 = 1331; Min.u64 = 1; Max.u64 = 1; + l2cache_13.TotalEventsReplayed : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_13.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6184,16 +6459,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_13.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.GetS_recv : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; + l2cache_13.GetS_recv : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_13.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_13.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6202,13 +6479,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache_13.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_13.FetchXResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache_13.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 154401; SumSQ.u64 = 1994965; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 16; + l2cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 169897; SumSQ.u64 = 2151485; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_13.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu14.read_reqs : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; cpu14.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6216,22 +6496,22 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu14.split_read_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu14.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu14.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu14.cycles_with_issue : Accumulator : Sum.u64 = 610; SumSQ.u64 = 610; Count.u64 = 610; Min.u64 = 1; Max.u64 = 1; - cpu14.cycles_no_issue : Accumulator : Sum.u64 = 11740; SumSQ.u64 = 11740; Count.u64 = 11740; Min.u64 = 1; Max.u64 = 1; + cpu14.cycles_with_issue : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; + cpu14.cycles_no_issue : Accumulator : Sum.u64 = 13042; SumSQ.u64 = 13042; Count.u64 = 13042; Min.u64 = 1; Max.u64 = 1; cpu14.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu14.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu14.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu14.req_latency : Accumulator : Sum.u64 = 124153; SumSQ.u64 = 24712435; Count.u64 = 936; Min.u64 = 2; Max.u64 = 996; - cpu14.time : Accumulator : Sum.u64 = 4643; SumSQ.u64 = 21557449; Count.u64 = 1; Min.u64 = 4643; Max.u64 = 4643; + cpu14.req_latency : Accumulator : Sum.u64 = 139097; SumSQ.u64 = 29620429; Count.u64 = 936; Min.u64 = 2; Max.u64 = 628; + cpu14.time : Accumulator : Sum.u64 = 5136; SumSQ.u64 = 26378496; Count.u64 = 1; Min.u64 = 5136; Max.u64 = 5136; cpu14.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu14.cycles_max_issue : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; - cpu14.cycles_max_reorder : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - cpu14.cycles : Accumulator : Sum.u64 = 12351; SumSQ.u64 = 12351; Count.u64 = 12351; Min.u64 = 1; Max.u64 = 1; + cpu14.cycles_max_issue : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + cpu14.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu14.cycles : Accumulator : Sum.u64 = 13660; SumSQ.u64 = 13660; Count.u64 = 13660; Min.u64 = 1; Max.u64 = 1; l1cache_14.prefetch_opportunities : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache_14.prefetches_issued : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache_14.prefetches_issued : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l1cache_14.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache_14.prefetches_canceled_by_history : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache_14.Prefetch_requests : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache_14.prefetches_canceled_by_history : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache_14.Prefetch_requests : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l1cache_14.Prefetch_drops : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_14.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_GetS_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; @@ -6243,8 +6523,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache_14.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_14.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_14.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_14.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6292,7 +6572,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.eventSent_GetS : Accumulator : Sum.u64 = 436; SumSQ.u64 = 436; Count.u64 = 436; Min.u64 = 1; Max.u64 = 1; + l1cache_14.eventSent_GetS : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6300,13 +6580,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_GetSResp : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6321,8 +6604,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.latency_GetS_hit : Accumulator : Sum.u64 = 113502; SumSQ.u64 = 60224620; Count.u64 = 448; Min.u64 = 1; Max.u64 = 2535; - l1cache_14.latency_GetS_miss : Accumulator : Sum.u64 = 105951; SumSQ.u64 = 63760981; Count.u64 = 315; Min.u64 = 12; Max.u64 = 2649; + l1cache_14.latency_GetS_hit : Accumulator : Sum.u64 = 131813; SumSQ.u64 = 75913281; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1669; + l1cache_14.latency_GetS_miss : Accumulator : Sum.u64 = 115769; SumSQ.u64 = 74127533; Count.u64 = 315; Min.u64 = 13; Max.u64 = 1683; l1cache_14.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6333,10 +6616,11 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache_14.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.GetSHit_Blocked : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; + l1cache_14.GetSHit_Blocked : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSMiss_Arrival : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; @@ -6345,27 +6629,27 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.CacheHits : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l1cache_14.CacheHits : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; l1cache_14.CacheMisses : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_14.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.prefetch_useful : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache_14.prefetch_useful : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l1cache_14.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.prefetch_redundant : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l1cache_14.stateEvent_GetS_E : Accumulator : Sum.u64 = 447; SumSQ.u64 = 447; Count.u64 = 447; Min.u64 = 1; Max.u64 = 1; + l1cache_14.prefetch_redundant : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l1cache_14.stateEvent_GetS_E : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; l1cache_14.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_14.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_14.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.TotalEventsReceived : Accumulator : Sum.u64 = 1693; SumSQ.u64 = 1693; Count.u64 = 1693; Min.u64 = 1; Max.u64 = 1; - l1cache_14.TotalEventsReplayed : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; + l1cache_14.TotalEventsReceived : Accumulator : Sum.u64 = 1757; SumSQ.u64 = 1757; Count.u64 = 1757; Min.u64 = 1; Max.u64 = 1; + l1cache_14.TotalEventsReplayed : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; l1cache_14.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6378,36 +6662,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.GetS_recv : Accumulator : Sum.u64 = 764; SumSQ.u64 = 764; Count.u64 = 764; Min.u64 = 1; Max.u64 = 1; + l1cache_14.GetS_recv : Accumulator : Sum.u64 = 768; SumSQ.u64 = 768; Count.u64 = 768; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache_14.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l1cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache_14.NACK_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_14.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.NACK_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; l1cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 215678; SumSQ.u64 = 4031768; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 22; + l1cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 243800; SumSQ.u64 = 4618370; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 22; l1cache_14.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.packet_latency : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 645; Min.u64 = 0; Max.u64 = 1; - l2cache_14.send_bit_count : Accumulator : Sum.u64 = 65856; SumSQ.u64 = 9424896; Count.u64 = 645; Min.u64 = 64; Max.u64 = 576; - l2cache_14.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.idle_time : Accumulator : Sum.u64 = 3196055; SumSQ.u64 = 225920086767; Count.u64 = 652; Min.u64 = 4; Max.u64 = 134060; - l2cache_14.prefetch_opportunities : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; - l2cache_14.prefetches_issued : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; - l2cache_14.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l2cache_14.prefetches_canceled_by_history : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache_14.Prefetch_requests : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; - l2cache_14.Prefetch_drops : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l2cache_14:lowlink.packet_latency : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 644; Min.u64 = 0; Max.u64 = 1; + l2cache_14:lowlink.send_bit_count : Accumulator : Sum.u64 = 66304; SumSQ.u64 = 9748480; Count.u64 = 644; Min.u64 = 64; Max.u64 = 576; + l2cache_14:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14:lowlink.idle_time : Accumulator : Sum.u64 = 3312618; SumSQ.u64 = 144810930980; Count.u64 = 629; Min.u64 = 20; Max.u64 = 101778; + l2cache_14.prefetch_opportunities : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; + l2cache_14.prefetches_issued : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; + l2cache_14.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache_14.prefetches_canceled_by_history : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_14.Prefetch_requests : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; + l2cache_14.Prefetch_drops : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l2cache_14.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.evict_I : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l2cache_14.evict_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; l2cache_14.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6420,8 +6708,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.stateEvent_GetS_I : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; - l2cache_14.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.stateEvent_GetS_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_14.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6429,7 +6717,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_14.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6509,26 +6797,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.eventSent_GetS : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l2cache_14.eventSent_GetS : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.eventSent_NACK : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; - l2cache_14.eventSent_GetSResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache_14.eventSent_GetXResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache_14.eventSent_NACK : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l2cache_14.eventSent_GetSResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache_14.eventSent_GetXResp : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.eventSent_FetchInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_14.eventSent_FetchInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6536,8 +6830,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.latency_GetS_hit : Accumulator : Sum.u64 = 3243; SumSQ.u64 = 810417; Count.u64 = 147; Min.u64 = 1; Max.u64 = 412; - l2cache_14.latency_GetS_miss : Accumulator : Sum.u64 = 91670; SumSQ.u64 = 45314400; Count.u64 = 190; Min.u64 = 81; Max.u64 = 868; + l2cache_14.latency_GetS_hit : Accumulator : Sum.u64 = 2299; SumSQ.u64 = 459191; Count.u64 = 151; Min.u64 = 1; Max.u64 = 432; + l2cache_14.latency_GetS_miss : Accumulator : Sum.u64 = 102482; SumSQ.u64 = 56787192; Count.u64 = 189; Min.u64 = 83; Max.u64 = 888; l2cache_14.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6549,30 +6843,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l2cache_14.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.GetSHit_Blocked : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_14.GetSHit_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.GetSMiss_Arrival : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l2cache_14.GetSMiss_Arrival : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.CacheHits : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; - l2cache_14.CacheMisses : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l2cache_14.CacheHits : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l2cache_14.CacheMisses : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; l2cache_14.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.prefetch_useful : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l2cache_14.prefetch_useful : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l2cache_14.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.prefetch_redundant : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_14.prefetch_redundant : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.stateEvent_GetS_E : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache_14.stateEvent_GetS_E : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6589,7 +6884,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_14.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6599,13 +6894,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_14.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_14.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.TotalEventsReceived : Accumulator : Sum.u64 = 1402; SumSQ.u64 = 1402; Count.u64 = 1402; Min.u64 = 1; Max.u64 = 1; - l2cache_14.TotalEventsReplayed : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache_14.TotalEventsReceived : Accumulator : Sum.u64 = 1465; SumSQ.u64 = 1465; Count.u64 = 1465; Min.u64 = 1; Max.u64 = 1; + l2cache_14.TotalEventsReplayed : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache_14.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6618,16 +6913,18 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_14.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.GetS_recv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l2cache_14.GetS_recv : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_14.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetXResp_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_14.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6636,13 +6933,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_14.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_14.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_14.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 161636; SumSQ.u64 = 2245156; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 15; + l2cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 178633; SumSQ.u64 = 2442613; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_14.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu15.read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu15.write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6650,25 +6950,25 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated cpu15.split_read_reqs : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; cpu15.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu15.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu15.cycles_with_issue : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; - cpu15.cycles_no_issue : Accumulator : Sum.u64 = 11927; SumSQ.u64 = 11927; Count.u64 = 11927; Min.u64 = 1; Max.u64 = 1; + cpu15.cycles_with_issue : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; + cpu15.cycles_no_issue : Accumulator : Sum.u64 = 13375; SumSQ.u64 = 13375; Count.u64 = 13375; Min.u64 = 1; Max.u64 = 1; cpu15.total_bytes_read : Accumulator : Sum.u64 = 19968; SumSQ.u64 = 638976; Count.u64 = 624; Min.u64 = 32; Max.u64 = 32; cpu15.total_bytes_write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu15.total_bytes_custom : Accumulator : Sum.u64 = 2496; SumSQ.u64 = 19968; Count.u64 = 312; Min.u64 = 8; Max.u64 = 8; - cpu15.req_latency : Accumulator : Sum.u64 = 127045; SumSQ.u64 = 21084003; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 200; - cpu15.time : Accumulator : Sum.u64 = 4733; SumSQ.u64 = 22401289; Count.u64 = 1; Min.u64 = 4733; Max.u64 = 4733; + cpu15.req_latency : Accumulator : Sum.u64 = 144101; SumSQ.u64 = 27006921; Count.u64 = 1248; Min.u64 = 2; Max.u64 = 224; + cpu15.time : Accumulator : Sum.u64 = 5282; SumSQ.u64 = 27899524; Count.u64 = 1; Min.u64 = 5282; Max.u64 = 5282; cpu15.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu15.cycles_max_issue : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + cpu15.cycles_max_issue : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; cpu15.cycles_max_reorder : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu15.cycles : Accumulator : Sum.u64 = 12590; SumSQ.u64 = 12590; Count.u64 = 12590; Min.u64 = 1; Max.u64 = 1; + cpu15.cycles : Accumulator : Sum.u64 = 14049; SumSQ.u64 = 14049; Count.u64 = 14049; Min.u64 = 1; Max.u64 = 1; l1cache_15.prefetch_opportunities : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache_15.prefetches_issued : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; - l1cache_15.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache_15.prefetches_canceled_by_history : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; - l1cache_15.Prefetch_requests : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; - l1cache_15.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.prefetches_issued : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l1cache_15.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache_15.prefetches_canceled_by_history : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache_15.Prefetch_requests : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l1cache_15.Prefetch_drops : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_15.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.stateEvent_GetS_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_15.stateEvent_GetS_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_15.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6677,8 +6977,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_15.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_15.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l1cache_15.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_15.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_15.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6726,7 +7026,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_15.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.eventSent_GetS : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l1cache_15.eventSent_GetS : Accumulator : Sum.u64 = 332; SumSQ.u64 = 332; Count.u64 = 332; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6734,13 +7034,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_15.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_GetSResp : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6748,15 +7051,15 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_15.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.evict_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_15.evict_I : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_15.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.latency_GetS_hit : Accumulator : Sum.u64 = 156485; SumSQ.u64 = 64468777; Count.u64 = 816; Min.u64 = 1; Max.u64 = 526; - l1cache_15.latency_GetS_miss : Accumulator : Sum.u64 = 84451; SumSQ.u64 = 38810735; Count.u64 = 318; Min.u64 = 13; Max.u64 = 605; + l1cache_15.latency_GetS_hit : Accumulator : Sum.u64 = 174656; SumSQ.u64 = 79933810; Count.u64 = 817; Min.u64 = 1; Max.u64 = 588; + l1cache_15.latency_GetS_miss : Accumulator : Sum.u64 = 97152; SumSQ.u64 = 50682948; Count.u64 = 316; Min.u64 = 13; Max.u64 = 605; l1cache_15.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6767,39 +7070,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_15.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l1cache_15.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.GetSHit_Blocked : Accumulator : Sum.u64 = 536; SumSQ.u64 = 536; Count.u64 = 536; Min.u64 = 1; Max.u64 = 1; + l1cache_15.GetSHit_Blocked : Accumulator : Sum.u64 = 549; SumSQ.u64 = 549; Count.u64 = 549; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.GetSMiss_Arrival : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_15.GetSMiss_Arrival : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.CacheHits : Accumulator : Sum.u64 = 816; SumSQ.u64 = 816; Count.u64 = 816; Min.u64 = 1; Max.u64 = 1; - l1cache_15.CacheMisses : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache_15.CacheHits : Accumulator : Sum.u64 = 817; SumSQ.u64 = 817; Count.u64 = 817; Min.u64 = 1; Max.u64 = 1; + l1cache_15.CacheMisses : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache_15.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.prefetch_useful : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache_15.prefetch_useful : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache_15.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.prefetch_redundant : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; - l1cache_15.stateEvent_GetS_E : Accumulator : Sum.u64 = 816; SumSQ.u64 = 816; Count.u64 = 816; Min.u64 = 1; Max.u64 = 1; + l1cache_15.prefetch_redundant : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache_15.stateEvent_GetS_E : Accumulator : Sum.u64 = 817; SumSQ.u64 = 817; Count.u64 = 817; Min.u64 = 1; Max.u64 = 1; l1cache_15.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache_15.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_15.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.TotalEventsReceived : Accumulator : Sum.u64 = 1909; SumSQ.u64 = 1909; Count.u64 = 1909; Min.u64 = 1; Max.u64 = 1; - l1cache_15.TotalEventsReplayed : Accumulator : Sum.u64 = 536; SumSQ.u64 = 536; Count.u64 = 536; Min.u64 = 1; Max.u64 = 1; + l1cache_15.TotalEventsReceived : Accumulator : Sum.u64 = 1902; SumSQ.u64 = 1902; Count.u64 = 1902; Min.u64 = 1; Max.u64 = 1; + l1cache_15.TotalEventsReplayed : Accumulator : Sum.u64 = 549; SumSQ.u64 = 549; Count.u64 = 549; Min.u64 = 1; Max.u64 = 1; l1cache_15.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6812,36 +7116,40 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_15.CustomResp_uncache_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache_15.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.GetS_recv : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; + l1cache_15.GetS_recv : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l1cache_15.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l1cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache_15.NACK_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_15.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.NACK_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 234783; SumSQ.u64 = 4447649; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 23; + l1cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 265641; SumSQ.u64 = 5096499; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 23; l1cache_15.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.packet_latency : Accumulator : Sum.u64 = 521; SumSQ.u64 = 521; Count.u64 = 650; Min.u64 = 0; Max.u64 = 1; - l2cache_15.send_bit_count : Accumulator : Sum.u64 = 67712; SumSQ.u64 = 10428416; Count.u64 = 650; Min.u64 = 64; Max.u64 = 576; - l2cache_15.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.idle_time : Accumulator : Sum.u64 = 2984105; SumSQ.u64 = 173473608727; Count.u64 = 629; Min.u64 = 2; Max.u64 = 141908; - l2cache_15.prefetch_opportunities : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; - l2cache_15.prefetches_issued : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; - l2cache_15.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache_15.prefetches_canceled_by_history : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l2cache_15.Prefetch_requests : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; - l2cache_15.Prefetch_drops : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache_15:lowlink.packet_latency : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 648; Min.u64 = 0; Max.u64 = 1; + l2cache_15:lowlink.send_bit_count : Accumulator : Sum.u64 = 67072; SumSQ.u64 = 10092544; Count.u64 = 648; Min.u64 = 64; Max.u64 = 576; + l2cache_15:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15:lowlink.idle_time : Accumulator : Sum.u64 = 3610108; SumSQ.u64 = 250633024888; Count.u64 = 621; Min.u64 = 3; Max.u64 = 139599; + l2cache_15.prefetch_opportunities : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l2cache_15.prefetches_issued : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l2cache_15.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache_15.prefetches_canceled_by_history : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache_15.Prefetch_requests : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l2cache_15.Prefetch_drops : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_15.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.evict_I : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l2cache_15.evict_I : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_15.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6854,8 +7162,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.stateEvent_GetS_I : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; - l2cache_15.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_GetS_I : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_15.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6863,8 +7171,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache_15.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_15.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6943,26 +7251,32 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.eventSent_GetS : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l2cache_15.eventSent_GetS : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.eventSent_NACK : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - l2cache_15.eventSent_GetSResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache_15.eventSent_GetXResp : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l2cache_15.eventSent_NACK : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_15.eventSent_GetSResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_15.eventSent_GetXResp : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.eventSent_FetchInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_15.eventSent_FetchInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6970,8 +7284,8 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.eventSent_CustomReq : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_CustomResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.latency_GetS_hit : Accumulator : Sum.u64 = 4150; SumSQ.u64 = 908126; Count.u64 = 163; Min.u64 = 1; Max.u64 = 413; - l2cache_15.latency_GetS_miss : Accumulator : Sum.u64 = 76776; SumSQ.u64 = 36061406; Count.u64 = 173; Min.u64 = 88; Max.u64 = 523; + l2cache_15.latency_GetS_hit : Accumulator : Sum.u64 = 3226; SumSQ.u64 = 545448; Count.u64 = 158; Min.u64 = 1; Max.u64 = 329; + l2cache_15.latency_GetS_miss : Accumulator : Sum.u64 = 90506; SumSQ.u64 = 48101738; Count.u64 = 179; Min.u64 = 97; Max.u64 = 590; l2cache_15.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.latency_GetX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6983,30 +7297,31 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache_15.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; l2cache_15.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.GetSHit_Blocked : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache_15.GetSHit_Blocked : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache_15.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.GetSMiss_Arrival : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l2cache_15.GetSMiss_Arrival : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_15.GetXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.CacheHits : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; - l2cache_15.CacheMisses : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l2cache_15.CacheHits : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l2cache_15.CacheMisses : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache_15.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.prefetch_useful : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l2cache_15.prefetch_useful : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; l2cache_15.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.prefetch_redundant : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_15.prefetch_redundant : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache_15.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.stateEvent_GetS_E : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_GetS_E : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; l2cache_15.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7023,7 +7338,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache_15.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7033,13 +7348,13 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_15.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_15.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.TotalEventsReceived : Accumulator : Sum.u64 = 1311; SumSQ.u64 = 1311; Count.u64 = 1311; Min.u64 = 1; Max.u64 = 1; - l2cache_15.TotalEventsReplayed : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache_15.TotalEventsReceived : Accumulator : Sum.u64 = 1302; SumSQ.u64 = 1302; Count.u64 = 1302; Min.u64 = 1; Max.u64 = 1; + l2cache_15.TotalEventsReplayed : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache_15.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7058,10 +7373,12 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache_15.GetXResp_recv : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l2cache_15.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache_15.GetXResp_recv : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; l2cache_15.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7070,13 +7387,16 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache_15.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.FetchXResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_15.FetchXResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache_15.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 149698; SumSQ.u64 = 1853564; Count.u64 = 12590; Min.u64 = 0; Max.u64 = 16; + l2cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 169086; SumSQ.u64 = 2117384; Count.u64 = 14049; Min.u64 = 0; Max.u64 = 15; l2cache_15.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory:backend.WR16 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory:backend.WR32 : Accumulator : Sum.u64 = 4992; SumSQ.u64 = 4992; Count.u64 = 4992; Min.u64 = 1; Max.u64 = 1; @@ -7090,7 +7410,7 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated memory:backend.RD16 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory:backend.RD32 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory:backend.RD48 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory:backend.RD64 : Accumulator : Sum.u64 = 5014; SumSQ.u64 = 5014; Count.u64 = 5014; Min.u64 = 1; Max.u64 = 1; + memory:backend.RD64 : Accumulator : Sum.u64 = 5012; SumSQ.u64 = 5012; Count.u64 = 5012; Min.u64 = 1; Max.u64 = 1; memory:backend.RD80 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory:backend.RD96 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory:backend.RD112 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7158,48 +7478,50 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated memory:backend.VaultRspSlotTherm : Accumulator : Sum.f32 = 0.000000; SumSQ.f32 = 0.000000; Count.u64 = 0; Min.f32 = 0; Max.f32 = 0; memory:backend.VaultCtrlTherm : Accumulator : Sum.f32 = 0.000000; SumSQ.f32 = 0.000000; Count.u64 = 0; Min.f32 = 0; Max.f32 = 0; memory:backend.RowAccessTherm : Accumulator : Sum.f32 = 0.000000; SumSQ.f32 = 0.000000; Count.u64 = 0; Min.f32 = 0; Max.f32 = 0; - memory.requests_received_GetS : Accumulator : Sum.u64 = 5014; SumSQ.u64 = 5014; Count.u64 = 5014; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetS : Accumulator : Sum.u64 = 5012; SumSQ.u64 = 5012; Count.u64 = 5012; Min.u64 = 1; Max.u64 = 1; memory.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.requests_received_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.requests_received_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory.outstanding_requests : Accumulator : Sum.u64 = 36942; SumSQ.u64 = 457982; Count.u64 = 4733; Min.u64 = 0; Max.u64 = 71; - memory.latency_GetS : Accumulator : Sum.u64 = 15695; SumSQ.u64 = 50393; Count.u64 = 5014; Min.u64 = 3; Max.u64 = 7; + memory.outstanding_requests : Accumulator : Sum.u64 = 36503; SumSQ.u64 = 404985; Count.u64 = 5282; Min.u64 = 0; Max.u64 = 60; + memory.latency_GetS : Accumulator : Sum.u64 = 15623; SumSQ.u64 = 49793; Count.u64 = 5012; Min.u64 = 3; Max.u64 = 6; memory.latency_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.latency_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.latency_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory.cycles_with_issue : Accumulator : Sum.u64 = 939; SumSQ.u64 = 939; Count.u64 = 939; Min.u64 = 1; Max.u64 = 1; - memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 991; SumSQ.u64 = 991; Count.u64 = 991; Min.u64 = 1; Max.u64 = 1; - memory.total_cycles : Accumulator : Sum.u64 = 4733; SumSQ.u64 = 22401289; Count.u64 = 1; Min.u64 = 4733; Max.u64 = 4733; - dc.packet_latency : Accumulator : Sum.u64 = 10402; SumSQ.u64 = 33118; Count.u64 = 10299; Min.u64 = 0; Max.u64 = 18; - dc.send_bit_count : Accumulator : Sum.u64 = 3619520; SumSQ.u64 = 1793699840; Count.u64 = 10299; Min.u64 = 64; Max.u64 = 576; - dc.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.idle_time : Accumulator : Sum.u64 = 18125; SumSQ.u64 = 79789667; Count.u64 = 7; Min.u64 = 142; Max.u64 = 5720; + memory.cycles_with_issue : Accumulator : Sum.u64 = 1048; SumSQ.u64 = 1048; Count.u64 = 1048; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + memory.total_cycles : Accumulator : Sum.u64 = 5282; SumSQ.u64 = 27899524; Count.u64 = 1; Min.u64 = 5282; Max.u64 = 5282; + dc:highlink.packet_latency : Accumulator : Sum.u64 = 10745; SumSQ.u64 = 39623; Count.u64 = 10302; Min.u64 = 0; Max.u64 = 20; + dc:highlink.send_bit_count : Accumulator : Sum.u64 = 3615488; SumSQ.u64 = 1791082496; Count.u64 = 10300; Min.u64 = 64; Max.u64 = 576; + dc:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc:highlink.idle_time : Accumulator : Sum.u64 = 9305; SumSQ.u64 = 39478825; Count.u64 = 3; Min.u64 = 1430; Max.u64 = 5730; dc.default_stat : Accumulator : Sum.u64 = 9984; SumSQ.u64 = 9984; Count.u64 = 9984; Min.u64 = 1; Max.u64 = 1; dc.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.get_request_latency : Accumulator : Sum.u64 = 24601; SumSQ.u64 = 225189; Count.u64 = 5158; Min.u64 = 4; Max.u64 = 67; - dc.directory_cache_hits : Accumulator : Sum.u64 = 5162; SumSQ.u64 = 5162; Count.u64 = 5162; Min.u64 = 1; Max.u64 = 1; + dc.get_request_latency : Accumulator : Sum.u64 = 24993; SumSQ.u64 = 278355; Count.u64 = 5150; Min.u64 = 4; Max.u64 = 92; + dc.directory_cache_hits : Accumulator : Sum.u64 = 5156; SumSQ.u64 = 5156; Count.u64 = 5156; Min.u64 = 1; Max.u64 = 1; dc.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.GetS_recv : Accumulator : Sum.u64 = 5158; SumSQ.u64 = 5158; Count.u64 = 5158; Min.u64 = 1; Max.u64 = 1; + dc.GetS_recv : Accumulator : Sum.u64 = 5152; SumSQ.u64 = 5152; Count.u64 = 5152; Min.u64 = 1; Max.u64 = 1; dc.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.NACK_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + dc.NACK_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; dc.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - dc.FetchXResp_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + dc.FetchXResp_recv : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; dc.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.GetXResp_recv : Accumulator : Sum.u64 = 5014; SumSQ.u64 = 5014; Count.u64 = 5014; Min.u64 = 1; Max.u64 = 1; + dc.GetXResp_recv : Accumulator : Sum.u64 = 5012; SumSQ.u64 = 5012; Count.u64 = 5012; Min.u64 = 1; Max.u64 = 1; dc.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.FetchInv_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; dc.AckInv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + dc.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7209,18 +7531,19 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated dc.CustomReq_uncache_recv : Accumulator : Sum.u64 = 4992; SumSQ.u64 = 4992; Count.u64 = 4992; Min.u64 = 1; Max.u64 = 1; dc.CustomResp_uncache_recv : Accumulator : Sum.u64 = 4992; SumSQ.u64 = 4992; Count.u64 = 4992; Min.u64 = 1; Max.u64 = 1; dc.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.eventSent_GetS : Accumulator : Sum.u64 = 5014; SumSQ.u64 = 5014; Count.u64 = 5014; Min.u64 = 1; Max.u64 = 1; + dc.eventSent_GetS : Accumulator : Sum.u64 = 5012; SumSQ.u64 = 5012; Count.u64 = 5012; Min.u64 = 1; Max.u64 = 1; dc.eventSent_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_Inv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; dc.eventSent_FetchInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - dc.eventSent_FetchInvX : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + dc.eventSent_FetchInvX : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; dc.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.eventSent_GetSResp : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; - dc.eventSent_GetXResp : Accumulator : Sum.u64 = 5011; SumSQ.u64 = 5011; Count.u64 = 5011; Min.u64 = 1; Max.u64 = 1; + dc.eventSent_GetSResp : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + dc.eventSent_GetXResp : Accumulator : Sum.u64 = 5009; SumSQ.u64 = 5009; Count.u64 = 5009; Min.u64 = 1; Max.u64 = 1; dc.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_AckInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -7228,7 +7551,9 @@ l2cache_15: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated dc.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc.MSHR_occupancy : Accumulator : Sum.u64 = 14347; SumSQ.u64 = 355585; Count.u64 = 946; Min.u64 = 0; Max.u64 = 142; -Simulation is complete, simulated time: 4.73384 us + dc.MSHR_occupancy : Accumulator : Sum.u64 = 14785; SumSQ.u64 = 353455; Count.u64 = 1056; Min.u64 = 0; Max.u64 = 129; +Simulation is complete, simulated time: 5.28242 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out index 639f45bf06..bf82d8e213 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_DistributedCaches.out @@ -105,10 +105,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core0.flushinvs : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; core0.llsc : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; core0.llsc_success : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; - l1cache0:memlink.packet_latency : Accumulator : Sum.u64 = 3251; SumSQ.u64 = 5511; Count.u64 = 2935; Min.u64 = 0; Max.u64 = 31; - l1cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 920192; SumSQ.u64 = 381231104; Count.u64 = 5634; Min.u64 = 64; Max.u64 = 576; - l1cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0:memlink.idle_time : Accumulator : Sum.u64 = 49337782; SumSQ.u64 = 2741076230510; Count.u64 = 2441; Min.u64 = 1; Max.u64 = 202882; + l1cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 3251; SumSQ.u64 = 5511; Count.u64 = 2935; Min.u64 = 0; Max.u64 = 31; + l1cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 920192; SumSQ.u64 = 381231104; Count.u64 = 5634; Min.u64 = 64; Max.u64 = 576; + l1cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0:lowlink.idle_time : Accumulator : Sum.u64 = 49337782; SumSQ.u64 = 2741076230510; Count.u64 = 2441; Min.u64 = 1; Max.u64 = 202882; l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1622; SumSQ.u64 = 1622; Count.u64 = 1622; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -176,13 +176,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1622; SumSQ.u64 = 1622; Count.u64 = 1622; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -209,6 +212,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 5286; SumSQ.u64 = 328614; Count.u64 = 94; Min.u64 = 46; Max.u64 = 173; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -255,14 +259,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.Write_recv : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2731; SumSQ.u64 = 2731; Count.u64 = 2731; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 5556478; SumSQ.u64 = 176590694; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -274,10 +282,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core1.flushinvs : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; core1.llsc : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; core1.llsc_success : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; - l1cache1:memlink.packet_latency : Accumulator : Sum.u64 = 3326; SumSQ.u64 = 6072; Count.u64 = 2943; Min.u64 = 0; Max.u64 = 28; - l1cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 922880; SumSQ.u64 = 382287872; Count.u64 = 5652; Min.u64 = 64; Max.u64 = 576; - l1cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1:memlink.idle_time : Accumulator : Sum.u64 = 47710513; SumSQ.u64 = 2894781115947; Count.u64 = 2448; Min.u64 = 7; Max.u64 = 258706; + l1cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 3326; SumSQ.u64 = 6072; Count.u64 = 2943; Min.u64 = 0; Max.u64 = 28; + l1cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 922880; SumSQ.u64 = 382287872; Count.u64 = 5652; Min.u64 = 64; Max.u64 = 576; + l1cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1:lowlink.idle_time : Accumulator : Sum.u64 = 47710513; SumSQ.u64 = 2894781115947; Count.u64 = 2448; Min.u64 = 7; Max.u64 = 258706; l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1631; SumSQ.u64 = 1631; Count.u64 = 1631; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -345,13 +353,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1631; SumSQ.u64 = 1631; Count.u64 = 1631; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1110; SumSQ.u64 = 1110; Count.u64 = 1110; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -378,6 +389,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 4805; SumSQ.u64 = 274191; Count.u64 = 89; Min.u64 = 42; Max.u64 = 158; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -424,14 +436,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.Write_recv : Accumulator : Sum.u64 = 1110; SumSQ.u64 = 1110; Count.u64 = 1110; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2741; SumSQ.u64 = 2741; Count.u64 = 2741; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 5535430; SumSQ.u64 = 175795424; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -443,10 +459,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core2.flushinvs : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; core2.llsc : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; core2.llsc_success : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; - l1cache2:memlink.packet_latency : Accumulator : Sum.u64 = 3225; SumSQ.u64 = 4815; Count.u64 = 2946; Min.u64 = 0; Max.u64 = 20; - l1cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 924160; SumSQ.u64 = 382959616; Count.u64 = 5656; Min.u64 = 64; Max.u64 = 576; - l1cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2:memlink.idle_time : Accumulator : Sum.u64 = 47970468; SumSQ.u64 = 2969053555620; Count.u64 = 2423; Min.u64 = 10; Max.u64 = 278923; + l1cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 3225; SumSQ.u64 = 4815; Count.u64 = 2946; Min.u64 = 0; Max.u64 = 20; + l1cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 924160; SumSQ.u64 = 382959616; Count.u64 = 5656; Min.u64 = 64; Max.u64 = 576; + l1cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2:lowlink.idle_time : Accumulator : Sum.u64 = 47970468; SumSQ.u64 = 2969053555620; Count.u64 = 2423; Min.u64 = 10; Max.u64 = 278923; l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1634; SumSQ.u64 = 1634; Count.u64 = 1634; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -514,13 +530,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1634; SumSQ.u64 = 1634; Count.u64 = 1634; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -547,6 +566,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 3959; SumSQ.u64 = 227331; Count.u64 = 73; Min.u64 = 44; Max.u64 = 142; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -593,14 +613,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.Write_recv : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 2742; SumSQ.u64 = 2742; Count.u64 = 2742; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 5582735; SumSQ.u64 = 177483079; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -612,10 +636,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core3.flushinvs : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; core3.llsc : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; core3.llsc_success : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache3:memlink.packet_latency : Accumulator : Sum.u64 = 3234; SumSQ.u64 = 4196; Count.u64 = 2939; Min.u64 = 0; Max.u64 = 4; - l1cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 916992; SumSQ.u64 = 378961920; Count.u64 = 5640; Min.u64 = 64; Max.u64 = 576; - l1cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3:memlink.idle_time : Accumulator : Sum.u64 = 48636964; SumSQ.u64 = 2779586073544; Count.u64 = 2532; Min.u64 = 7; Max.u64 = 260665; + l1cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 3234; SumSQ.u64 = 4196; Count.u64 = 2939; Min.u64 = 0; Max.u64 = 4; + l1cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 916992; SumSQ.u64 = 378961920; Count.u64 = 5640; Min.u64 = 64; Max.u64 = 576; + l1cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3:lowlink.idle_time : Accumulator : Sum.u64 = 48636964; SumSQ.u64 = 2779586073544; Count.u64 = 2532; Min.u64 = 7; Max.u64 = 260665; l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1633; SumSQ.u64 = 1633; Count.u64 = 1633; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -683,13 +707,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1633; SumSQ.u64 = 1633; Count.u64 = 1633; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -716,6 +743,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 4644; SumSQ.u64 = 246562; Count.u64 = 88; Min.u64 = 44; Max.u64 = 66; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -762,14 +790,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.Write_recv : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 2733; SumSQ.u64 = 2733; Count.u64 = 2733; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 5537282; SumSQ.u64 = 175844966; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -781,10 +813,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core4.flushinvs : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; core4.llsc : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; core4.llsc_success : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; - l1cache4:memlink.packet_latency : Accumulator : Sum.u64 = 3244; SumSQ.u64 = 4246; Count.u64 = 2929; Min.u64 = 0; Max.u64 = 9; - l1cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 942400; SumSQ.u64 = 395923456; Count.u64 = 5621; Min.u64 = 64; Max.u64 = 576; - l1cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4:memlink.idle_time : Accumulator : Sum.u64 = 48255327; SumSQ.u64 = 2781312828759; Count.u64 = 2401; Min.u64 = 10; Max.u64 = 198082; + l1cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 3244; SumSQ.u64 = 4246; Count.u64 = 2929; Min.u64 = 0; Max.u64 = 9; + l1cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 942400; SumSQ.u64 = 395923456; Count.u64 = 5621; Min.u64 = 64; Max.u64 = 576; + l1cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4:lowlink.idle_time : Accumulator : Sum.u64 = 48255327; SumSQ.u64 = 2781312828759; Count.u64 = 2401; Min.u64 = 10; Max.u64 = 198082; l1cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 1577; SumSQ.u64 = 1577; Count.u64 = 1577; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -852,13 +884,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 1577; SumSQ.u64 = 1577; Count.u64 = 1577; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -885,6 +920,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 5589; SumSQ.u64 = 305823; Count.u64 = 105; Min.u64 = 46; Max.u64 = 133; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -931,14 +967,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.Write_recv : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 2724; SumSQ.u64 = 2724; Count.u64 = 2724; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 5549105; SumSQ.u64 = 176279163; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -950,10 +990,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core5.flushinvs : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; core5.llsc : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; core5.llsc_success : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache5:memlink.packet_latency : Accumulator : Sum.u64 = 3234; SumSQ.u64 = 4148; Count.u64 = 2939; Min.u64 = 0; Max.u64 = 3; - l1cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 920512; SumSQ.u64 = 381841408; Count.u64 = 5623; Min.u64 = 64; Max.u64 = 576; - l1cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5:memlink.idle_time : Accumulator : Sum.u64 = 48206622; SumSQ.u64 = 2781304191084; Count.u64 = 2449; Min.u64 = 1; Max.u64 = 205438; + l1cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 3234; SumSQ.u64 = 4148; Count.u64 = 2939; Min.u64 = 0; Max.u64 = 3; + l1cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 920512; SumSQ.u64 = 381841408; Count.u64 = 5623; Min.u64 = 64; Max.u64 = 576; + l1cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5:lowlink.idle_time : Accumulator : Sum.u64 = 48206622; SumSQ.u64 = 2781304191084; Count.u64 = 2449; Min.u64 = 1; Max.u64 = 205438; l1cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 1609; SumSQ.u64 = 1609; Count.u64 = 1609; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,13 +1061,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 1609; SumSQ.u64 = 1609; Count.u64 = 1609; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1054,6 +1097,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 5412; SumSQ.u64 = 282486; Count.u64 = 104; Min.u64 = 45; Max.u64 = 64; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1100,14 +1144,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.Write_recv : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 2716; SumSQ.u64 = 2716; Count.u64 = 2716; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 5556775; SumSQ.u64 = 176528973; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -1119,10 +1167,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core6.flushinvs : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; core6.llsc : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; core6.llsc_success : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; - l1cache6:memlink.packet_latency : Accumulator : Sum.u64 = 3243; SumSQ.u64 = 4613; Count.u64 = 2941; Min.u64 = 0; Max.u64 = 21; - l1cache6:memlink.send_bit_count : Accumulator : Sum.u64 = 924352; SumSQ.u64 = 383561728; Count.u64 = 5643; Min.u64 = 64; Max.u64 = 576; - l1cache6:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache6:memlink.idle_time : Accumulator : Sum.u64 = 49231823; SumSQ.u64 = 3163613700173; Count.u64 = 2445; Min.u64 = 10; Max.u64 = 271200; + l1cache6:lowlink.packet_latency : Accumulator : Sum.u64 = 3243; SumSQ.u64 = 4613; Count.u64 = 2941; Min.u64 = 0; Max.u64 = 21; + l1cache6:lowlink.send_bit_count : Accumulator : Sum.u64 = 924352; SumSQ.u64 = 383561728; Count.u64 = 5643; Min.u64 = 64; Max.u64 = 576; + l1cache6:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6:lowlink.idle_time : Accumulator : Sum.u64 = 49231823; SumSQ.u64 = 3163613700173; Count.u64 = 2445; Min.u64 = 10; Max.u64 = 271200; l1cache6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.stateEvent_GetS_I : Accumulator : Sum.u64 = 1616; SumSQ.u64 = 1616; Count.u64 = 1616; Min.u64 = 1; Max.u64 = 1; l1cache6.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1190,13 +1238,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FlushLine : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_GetSResp : Accumulator : Sum.u64 = 1616; SumSQ.u64 = 1616; Count.u64 = 1616; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_GetXResp : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_WriteResp : Accumulator : Sum.u64 = 1118; SumSQ.u64 = 1118; Count.u64 = 1118; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l1cache6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1223,6 +1274,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.latency_FlushLineInv : Accumulator : Sum.u64 = 4826; SumSQ.u64 = 271522; Count.u64 = 91; Min.u64 = 44; Max.u64 = 172; l1cache6.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1269,14 +1321,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.Write_recv : Accumulator : Sum.u64 = 1118; SumSQ.u64 = 1118; Count.u64 = 1118; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetXResp_recv : Accumulator : Sum.u64 = 2734; SumSQ.u64 = 2734; Count.u64 = 2734; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLineResp_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l1cache6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.MSHR_occupancy : Accumulator : Sum.u64 = 5609039; SumSQ.u64 = 178453169; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; @@ -1288,10 +1344,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t core7.flushinvs : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; core7.llsc : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; core7.llsc_success : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; - l1cache7:memlink.packet_latency : Accumulator : Sum.u64 = 3301; SumSQ.u64 = 5255; Count.u64 = 2959; Min.u64 = 0; Max.u64 = 23; - l1cache7:memlink.send_bit_count : Accumulator : Sum.u64 = 923584; SumSQ.u64 = 381153280; Count.u64 = 5695; Min.u64 = 64; Max.u64 = 576; - l1cache7:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache7:memlink.idle_time : Accumulator : Sum.u64 = 49587746; SumSQ.u64 = 3052610099164; Count.u64 = 2464; Min.u64 = 16; Max.u64 = 233704; + l1cache7:lowlink.packet_latency : Accumulator : Sum.u64 = 3301; SumSQ.u64 = 5255; Count.u64 = 2959; Min.u64 = 0; Max.u64 = 23; + l1cache7:lowlink.send_bit_count : Accumulator : Sum.u64 = 923584; SumSQ.u64 = 381153280; Count.u64 = 5695; Min.u64 = 64; Max.u64 = 576; + l1cache7:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7:lowlink.idle_time : Accumulator : Sum.u64 = 49587746; SumSQ.u64 = 3052610099164; Count.u64 = 2464; Min.u64 = 16; Max.u64 = 233704; l1cache7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.stateEvent_GetS_I : Accumulator : Sum.u64 = 1664; SumSQ.u64 = 1664; Count.u64 = 1664; Min.u64 = 1; Max.u64 = 1; l1cache7.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1359,13 +1415,16 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FlushLine : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_GetSResp : Accumulator : Sum.u64 = 1664; SumSQ.u64 = 1664; Count.u64 = 1664; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_GetXResp : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_WriteResp : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l1cache7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1392,6 +1451,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.latency_FlushLineInv : Accumulator : Sum.u64 = 4740; SumSQ.u64 = 291228; Count.u64 = 85; Min.u64 = 45; Max.u64 = 175; l1cache7.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1438,22 +1498,26 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.Write_recv : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetXResp_recv : Accumulator : Sum.u64 = 2768; SumSQ.u64 = 2768; Count.u64 = 2768; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l1cache7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.MSHR_occupancy : Accumulator : Sum.u64 = 5589752; SumSQ.u64 = 177736866; Count.u64 = 176577; Min.u64 = 0; Max.u64 = 32; l1cache7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 21147; SumSQ.u64 = 39117; Count.u64 = 17306; Min.u64 = 0; Max.u64 = 23; - l2cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 3575360; SumSQ.u64 = 1850544128; Count.u64 = 11873; Min.u64 = 64; Max.u64 = 576; - l2cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:cpulink.idle_time : Accumulator : Sum.u64 = 38535213; SumSQ.u64 = 417488201441; Count.u64 = 9596; Min.u64 = 4; Max.u64 = 71673; + l2cache0:highlink.packet_latency : Accumulator : Sum.u64 = 21147; SumSQ.u64 = 39117; Count.u64 = 17306; Min.u64 = 0; Max.u64 = 23; + l2cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 3575360; SumSQ.u64 = 1850544128; Count.u64 = 11873; Min.u64 = 64; Max.u64 = 576; + l2cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:highlink.idle_time : Accumulator : Sum.u64 = 38535213; SumSQ.u64 = 417488201441; Count.u64 = 9596; Min.u64 = 4; Max.u64 = 71673; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_I : Accumulator : Sum.u64 = 5490; SumSQ.u64 = 5490; Count.u64 = 5490; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1563,8 +1627,11 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1573,6 +1640,9 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 5497; SumSQ.u64 = 5497; Count.u64 = 5497; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 440; SumSQ.u64 = 440; Count.u64 = 440; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1597,6 +1667,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 5742; SumSQ.u64 = 136334; Count.u64 = 249; Min.u64 = 19; Max.u64 = 67; l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 4481; SumSQ.u64 = 109055; Count.u64 = 191; Min.u64 = 19; Max.u64 = 59; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1667,10 +1738,12 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 5493; SumSQ.u64 = 5493; Count.u64 = 5493; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 440; SumSQ.u64 = 440; Count.u64 = 440; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutM_recv : Accumulator : Sum.u64 = 2202; SumSQ.u64 = 2202; Count.u64 = 2202; Min.u64 = 1; Max.u64 = 1; l2cache0.PutE_recv : Accumulator : Sum.u64 = 3231; SumSQ.u64 = 3231; Count.u64 = 3231; Min.u64 = 1; Max.u64 = 1; @@ -1682,15 +1755,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 4623086; SumSQ.u64 = 211920258; Count.u64 = 103126; Min.u64 = 0; Max.u64 = 59; l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 21101; SumSQ.u64 = 44807; Count.u64 = 16942; Min.u64 = 0; Max.u64 = 27; - l2cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 3512192; SumSQ.u64 = 1820254208; Count.u64 = 11598; Min.u64 = 64; Max.u64 = 576; - l2cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:cpulink.idle_time : Accumulator : Sum.u64 = 39606809; SumSQ.u64 = 532015362441; Count.u64 = 9474; Min.u64 = 4; Max.u64 = 248745; + l2cache1:highlink.packet_latency : Accumulator : Sum.u64 = 21101; SumSQ.u64 = 44807; Count.u64 = 16942; Min.u64 = 0; Max.u64 = 27; + l2cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 3512192; SumSQ.u64 = 1820254208; Count.u64 = 11598; Min.u64 = 64; Max.u64 = 576; + l2cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:highlink.idle_time : Accumulator : Sum.u64 = 39606809; SumSQ.u64 = 532015362441; Count.u64 = 9474; Min.u64 = 4; Max.u64 = 248745; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_I : Accumulator : Sum.u64 = 5406; SumSQ.u64 = 5406; Count.u64 = 5406; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1800,8 +1876,11 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1810,6 +1889,9 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 5408; SumSQ.u64 = 5408; Count.u64 = 5408; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1834,6 +1916,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 5075; SumSQ.u64 = 118423; Count.u64 = 219; Min.u64 = 19; Max.u64 = 32; l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 3946; SumSQ.u64 = 90602; Count.u64 = 173; Min.u64 = 19; Max.u64 = 29; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1904,10 +1987,12 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 5406; SumSQ.u64 = 5406; Count.u64 = 5406; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutM_recv : Accumulator : Sum.u64 = 2217; SumSQ.u64 = 2217; Count.u64 = 2217; Min.u64 = 1; Max.u64 = 1; l2cache1.PutE_recv : Accumulator : Sum.u64 = 3127; SumSQ.u64 = 3127; Count.u64 = 3127; Min.u64 = 1; Max.u64 = 1; @@ -1919,15 +2004,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 4119464; SumSQ.u64 = 171136950; Count.u64 = 103126; Min.u64 = 0; Max.u64 = 55; l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 21121; SumSQ.u64 = 39723; Count.u64 = 17212; Min.u64 = 0; Max.u64 = 25; - l2cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 3569664; SumSQ.u64 = 1850474496; Count.u64 = 11776; Min.u64 = 64; Max.u64 = 576; - l2cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:cpulink.idle_time : Accumulator : Sum.u64 = 39129881; SumSQ.u64 = 476489245949; Count.u64 = 9577; Min.u64 = 4; Max.u64 = 108514; + l2cache2:highlink.packet_latency : Accumulator : Sum.u64 = 21121; SumSQ.u64 = 39723; Count.u64 = 17212; Min.u64 = 0; Max.u64 = 25; + l2cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 3569664; SumSQ.u64 = 1850474496; Count.u64 = 11776; Min.u64 = 64; Max.u64 = 576; + l2cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:highlink.idle_time : Accumulator : Sum.u64 = 39129881; SumSQ.u64 = 476489245949; Count.u64 = 9577; Min.u64 = 4; Max.u64 = 108514; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_I : Accumulator : Sum.u64 = 5498; SumSQ.u64 = 5498; Count.u64 = 5498; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2037,8 +2125,11 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2047,6 +2138,9 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 5500; SumSQ.u64 = 5500; Count.u64 = 5500; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2071,6 +2165,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 5396; SumSQ.u64 = 126446; Count.u64 = 234; Min.u64 = 19; Max.u64 = 51; l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 3648; SumSQ.u64 = 88490; Count.u64 = 155; Min.u64 = 20; Max.u64 = 53; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2141,10 +2236,12 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 5498; SumSQ.u64 = 5498; Count.u64 = 5498; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutM_recv : Accumulator : Sum.u64 = 2189; SumSQ.u64 = 2189; Count.u64 = 2189; Min.u64 = 1; Max.u64 = 1; l2cache2.PutE_recv : Accumulator : Sum.u64 = 3247; SumSQ.u64 = 3247; Count.u64 = 3247; Min.u64 = 1; Max.u64 = 1; @@ -2156,15 +2253,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 4607785; SumSQ.u64 = 210414767; Count.u64 = 103126; Min.u64 = 0; Max.u64 = 60; l2cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:cpulink.packet_latency : Accumulator : Sum.u64 = 21647; SumSQ.u64 = 49225; Count.u64 = 17222; Min.u64 = 0; Max.u64 = 26; - l2cache3:cpulink.send_bit_count : Accumulator : Sum.u64 = 3563136; SumSQ.u64 = 1845338112; Count.u64 = 11802; Min.u64 = 64; Max.u64 = 576; - l2cache3:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:cpulink.idle_time : Accumulator : Sum.u64 = 39517285; SumSQ.u64 = 524828743645; Count.u64 = 9506; Min.u64 = 4; Max.u64 = 232323; + l2cache3:highlink.packet_latency : Accumulator : Sum.u64 = 21647; SumSQ.u64 = 49225; Count.u64 = 17222; Min.u64 = 0; Max.u64 = 26; + l2cache3:highlink.send_bit_count : Accumulator : Sum.u64 = 3563136; SumSQ.u64 = 1845338112; Count.u64 = 11802; Min.u64 = 64; Max.u64 = 576; + l2cache3:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:highlink.idle_time : Accumulator : Sum.u64 = 39517285; SumSQ.u64 = 524828743645; Count.u64 = 9506; Min.u64 = 4; Max.u64 = 232323; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_I : Accumulator : Sum.u64 = 5476; SumSQ.u64 = 5476; Count.u64 = 5476; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2274,8 +2374,11 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2284,6 +2387,9 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 5484; SumSQ.u64 = 5484; Count.u64 = 5484; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2308,6 +2414,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 4952; SumSQ.u64 = 119002; Count.u64 = 211; Min.u64 = 19; Max.u64 = 51; l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 4937; SumSQ.u64 = 121631; Count.u64 = 210; Min.u64 = 19; Max.u64 = 65; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2378,10 +2485,12 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 5476; SumSQ.u64 = 5476; Count.u64 = 5476; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutM_recv : Accumulator : Sum.u64 = 2190; SumSQ.u64 = 2190; Count.u64 = 2190; Min.u64 = 1; Max.u64 = 1; l2cache3.PutE_recv : Accumulator : Sum.u64 = 3230; SumSQ.u64 = 3230; Count.u64 = 3230; Min.u64 = 1; Max.u64 = 1; @@ -2393,15 +2502,18 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 4185424; SumSQ.u64 = 177129424; Count.u64 = 103126; Min.u64 = 0; Max.u64 = 60; l2cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 27174; SumSQ.u64 = 58844; Count.u64 = 23643; Min.u64 = 0; Max.u64 = 31; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 7142720; SumSQ.u64 = 3699691520; Count.u64 = 23645; Min.u64 = 64; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 41461133; SumSQ.u64 = 392163391873; Count.u64 = 9952; Min.u64 = 4; Max.u64 = 20400; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 27174; SumSQ.u64 = 58844; Count.u64 = 23643; Min.u64 = 0; Max.u64 = 31; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 7142720; SumSQ.u64 = 3699691520; Count.u64 = 23645; Min.u64 = 64; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 41461133; SumSQ.u64 = 392163391873; Count.u64 = 9952; Min.u64 = 4; Max.u64 = 20400; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 7420; SumSQ.u64 = 68352; Count.u64 = 832; Min.u64 = 2; Max.u64 = 17; directory0.get_request_latency : Accumulator : Sum.u64 = 9093148; SumSQ.u64 = 7712450708; Count.u64 = 10991; Min.u64 = 25; Max.u64 = 1406; @@ -2424,8 +2536,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2444,6 +2558,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 10991; SumSQ.u64 = 10991; Count.u64 = 10991; Min.u64 = 1; Max.u64 = 1; @@ -2454,6 +2569,8 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 9076922; SumSQ.u64 = 813412794; Count.u64 = 103116; Min.u64 = 0; Max.u64 = 115; @@ -2474,14 +2591,14 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t memory0.cycles_with_issue : Accumulator : Sum.u64 = 4450; SumSQ.u64 = 4450; Count.u64 = 4450; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 32339; SumSQ.u64 = 32339; Count.u64 = 32339; Min.u64 = 1; Max.u64 = 1; memory0.total_cycles : Accumulator : Sum.u64 = 36816; SumSQ.u64 = 1355417856; Count.u64 = 1; Min.u64 = 36816; Max.u64 = 36816; - memory0:cpulink.packet_latency : Accumulator : Sum.u64 = 12682; SumSQ.u64 = 18426; Count.u64 = 11822; Min.u64 = 0; Max.u64 = 8; - memory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 6383872; SumSQ.u64 = 3649945600; Count.u64 = 11820; Min.u64 = 64; Max.u64 = 576; - memory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:cpulink.idle_time : Accumulator : Sum.u64 = 34349909; SumSQ.u64 = 482971728481; Count.u64 = 4390; Min.u64 = 100; Max.u64 = 20800; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 27732; SumSQ.u64 = 65048; Count.u64 = 23390; Min.u64 = 0; Max.u64 = 30; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 7069568; SumSQ.u64 = 3662274560; Count.u64 = 23390; Min.u64 = 64; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 41648323; SumSQ.u64 = 452808202317; Count.u64 = 9675; Min.u64 = 4; Max.u64 = 235893; + memory0:highlink.packet_latency : Accumulator : Sum.u64 = 12682; SumSQ.u64 = 18426; Count.u64 = 11822; Min.u64 = 0; Max.u64 = 8; + memory0:highlink.send_bit_count : Accumulator : Sum.u64 = 6383872; SumSQ.u64 = 3649945600; Count.u64 = 11820; Min.u64 = 64; Max.u64 = 576; + memory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory0:highlink.idle_time : Accumulator : Sum.u64 = 34349909; SumSQ.u64 = 482971728481; Count.u64 = 4390; Min.u64 = 100; Max.u64 = 20800; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 27732; SumSQ.u64 = 65048; Count.u64 = 23390; Min.u64 = 0; Max.u64 = 30; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 7069568; SumSQ.u64 = 3662274560; Count.u64 = 23390; Min.u64 = 64; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 41648323; SumSQ.u64 = 452808202317; Count.u64 = 9675; Min.u64 = 4; Max.u64 = 235893; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 7267; SumSQ.u64 = 66581; Count.u64 = 813; Min.u64 = 6; Max.u64 = 14; directory1.get_request_latency : Accumulator : Sum.u64 = 8167973; SumSQ.u64 = 6280599383; Count.u64 = 10882; Min.u64 = 25; Max.u64 = 1042; @@ -2504,8 +2621,10 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 430; SumSQ.u64 = 430; Count.u64 = 430; Min.u64 = 1; Max.u64 = 1; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2524,6 +2643,7 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 10882; SumSQ.u64 = 10882; Count.u64 = 10882; Min.u64 = 1; Max.u64 = 1; @@ -2534,6 +2654,8 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 430; SumSQ.u64 = 430; Count.u64 = 430; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 8151850; SumSQ.u64 = 665717564; Count.u64 = 102794; Min.u64 = 0; Max.u64 = 109; @@ -2554,8 +2676,8 @@ l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t memory1.cycles_with_issue : Accumulator : Sum.u64 = 4437; SumSQ.u64 = 4437; Count.u64 = 4437; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 32222; SumSQ.u64 = 32222; Count.u64 = 32222; Min.u64 = 1; Max.u64 = 1; memory1.total_cycles : Accumulator : Sum.u64 = 36816; SumSQ.u64 = 1355417856; Count.u64 = 1; Min.u64 = 36816; Max.u64 = 36816; - memory1:cpulink.packet_latency : Accumulator : Sum.u64 = 12465; SumSQ.u64 = 16421; Count.u64 = 11695; Min.u64 = 0; Max.u64 = 4; - memory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 6320064; SumSQ.u64 = 3613716480; Count.u64 = 11695; Min.u64 = 64; Max.u64 = 576; - memory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:cpulink.idle_time : Accumulator : Sum.u64 = 32367009; SumSQ.u64 = 500025718481; Count.u64 = 4383; Min.u64 = 100; Max.u64 = 238809; + memory1:highlink.packet_latency : Accumulator : Sum.u64 = 12465; SumSQ.u64 = 16421; Count.u64 = 11695; Min.u64 = 0; Max.u64 = 4; + memory1:highlink.send_bit_count : Accumulator : Sum.u64 = 6320064; SumSQ.u64 = 3613716480; Count.u64 = 11695; Min.u64 = 64; Max.u64 = 576; + memory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory1:highlink.idle_time : Accumulator : Sum.u64 = 32367009; SumSQ.u64 = 500025718481; Count.u64 = 4383; Min.u64 = 100; Max.u64 = 238809; Simulation is complete, simulated time: 73.6326 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out index 4abe9cfd27..62f03bfb5b 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes.out @@ -138,13 +138,16 @@ l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 925; SumSQ.u64 = 925; Count.u64 = 925; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1514; SumSQ.u64 = 1514; Count.u64 = 1514; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -152,7 +155,7 @@ l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.evict_I : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_I : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_S : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_M : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_IS : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; @@ -171,6 +174,7 @@ l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 81749; SumSQ.u64 = 98051085; Count.u64 = 227; Min.u64 = 71; Max.u64 = 4313; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -217,24 +221,28 @@ l1cache0.Write_recv : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 949; SumSQ.u64 = 949; Count.u64 = 949; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 954; SumSQ.u64 = 954; Count.u64 = 954; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 432; SumSQ.u64 = 432; Count.u64 = 432; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 3736; SumSQ.u64 = 3736; Count.u64 = 3736; Min.u64 = 1; Max.u64 = 1; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 799022; SumSQ.u64 = 12314140; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 16; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 7113; SumSQ.u64 = 12243; Count.u64 = 5661; Min.u64 = 0; Max.u64 = 7; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 893184; SumSQ.u64 = 363282432; Count.u64 = 5652; Min.u64 = 64; Max.u64 = 576; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 10849619; SumSQ.u64 = 332305974621; Count.u64 = 4583; Min.u64 = 1; Max.u64 = 470844; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 7113; SumSQ.u64 = 12243; Count.u64 = 5661; Min.u64 = 0; Max.u64 = 7; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 893184; SumSQ.u64 = 363282432; Count.u64 = 5652; Min.u64 = 64; Max.u64 = 576; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 10849619; SumSQ.u64 = 332305974621; Count.u64 = 4583; Min.u64 = 1; Max.u64 = 470844; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.evict_I : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_I : Accumulator : Sum.u64 = 289; SumSQ.u64 = 289; Count.u64 = 289; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -342,8 +350,11 @@ l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; @@ -352,6 +363,9 @@ l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 954; SumSQ.u64 = 954; Count.u64 = 954; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -376,6 +390,7 @@ l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1752; SumSQ.u64 = 511166; Count.u64 = 10; Min.u64 = 69; Max.u64 = 520; l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 42472; SumSQ.u64 = 12970612; Count.u64 = 668; Min.u64 = 3; Max.u64 = 2227; l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 50126; SumSQ.u64 = 23428192; Count.u64 = 601; Min.u64 = 3; Max.u64 = 2448; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -446,10 +461,12 @@ l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 933; SumSQ.u64 = 933; Count.u64 = 933; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; l2cache0.PutM_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l2cache0.PutE_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; @@ -461,6 +478,9 @@ l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 1146; SumSQ.u64 = 1146; Count.u64 = 1146; Min.u64 = 1; Max.u64 = 1; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 925; SumSQ.u64 = 925; Count.u64 = 925; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -540,13 +560,16 @@ l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1505; SumSQ.u64 = 1505; Count.u64 = 1505; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -554,7 +577,7 @@ l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.evict_I : Accumulator : Sum.u64 = 939; SumSQ.u64 = 939; Count.u64 = 939; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_I : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_S : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_M : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_IS : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; @@ -573,6 +596,7 @@ l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 100703; SumSQ.u64 = 153012377; Count.u64 = 245; Min.u64 = 67; Max.u64 = 4309; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 274; SumSQ.u64 = 274; Count.u64 = 274; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -619,24 +643,28 @@ l1cache1.Write_recv : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 3738; SumSQ.u64 = 3738; Count.u64 = 3738; Min.u64 = 1; Max.u64 = 1; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 824656; SumSQ.u64 = 12740318; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 16; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 7102; SumSQ.u64 = 12174; Count.u64 = 5662; Min.u64 = 0; Max.u64 = 6; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 904960; SumSQ.u64 = 370819072; Count.u64 = 5652; Min.u64 = 64; Max.u64 = 576; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 10509064; SumSQ.u64 = 53857752958; Count.u64 = 4575; Min.u64 = 1; Max.u64 = 55237; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 7102; SumSQ.u64 = 12174; Count.u64 = 5662; Min.u64 = 0; Max.u64 = 6; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 904960; SumSQ.u64 = 370819072; Count.u64 = 5652; Min.u64 = 64; Max.u64 = 576; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 10509064; SumSQ.u64 = 53857752958; Count.u64 = 4575; Min.u64 = 1; Max.u64 = 55237; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.evict_I : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_I : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -744,8 +772,11 @@ l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; @@ -754,6 +785,9 @@ l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -778,6 +812,7 @@ l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 623; SumSQ.u64 = 85377; Count.u64 = 6; Min.u64 = 67; Max.u64 = 233; l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 45366; SumSQ.u64 = 27957094; Count.u64 = 624; Min.u64 = 3; Max.u64 = 3818; l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 52177; SumSQ.u64 = 24642629; Count.u64 = 665; Min.u64 = 3; Max.u64 = 2255; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -848,10 +883,12 @@ l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutS_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l2cache1.PutM_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache1.PutE_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; @@ -863,6 +900,9 @@ l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NACK_recv : Accumulator : Sum.u64 = 1079; SumSQ.u64 = 1079; Count.u64 = 1079; Min.u64 = 1; Max.u64 = 1; l2cache1.AckInv_recv : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -942,13 +982,16 @@ l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 837; SumSQ.u64 = 837; Count.u64 = 837; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 602; SumSQ.u64 = 602; Count.u64 = 602; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1448; SumSQ.u64 = 1448; Count.u64 = 1448; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -956,7 +999,7 @@ l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.evict_I : Accumulator : Sum.u64 = 888; SumSQ.u64 = 888; Count.u64 = 888; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_I : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_S : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_M : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_IS : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; @@ -975,6 +1018,7 @@ l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 81551; SumSQ.u64 = 88873829; Count.u64 = 219; Min.u64 = 78; Max.u64 = 3302; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -1021,24 +1065,28 @@ l1cache2.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 986; SumSQ.u64 = 986; Count.u64 = 986; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Inv_recv : Accumulator : Sum.u64 = 878; SumSQ.u64 = 878; Count.u64 = 878; Min.u64 = 1; Max.u64 = 1; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NACK_recv : Accumulator : Sum.u64 = 4033; SumSQ.u64 = 4033; Count.u64 = 4033; Min.u64 = 1; Max.u64 = 1; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 801519; SumSQ.u64 = 12334723; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 16; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 7393; SumSQ.u64 = 12975; Count.u64 = 5768; Min.u64 = 0; Max.u64 = 7; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 912512; SumSQ.u64 = 371892224; Count.u64 = 5754; Min.u64 = 64; Max.u64 = 576; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 11006120; SumSQ.u64 = 274540968752; Count.u64 = 4630; Min.u64 = 4; Max.u64 = 444573; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 7393; SumSQ.u64 = 12975; Count.u64 = 5768; Min.u64 = 0; Max.u64 = 7; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 912512; SumSQ.u64 = 371892224; Count.u64 = 5754; Min.u64 = 64; Max.u64 = 576; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 11006120; SumSQ.u64 = 274540968752; Count.u64 = 4630; Min.u64 = 4; Max.u64 = 444573; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.evict_I : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_I : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1146,8 +1194,11 @@ l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 1119; SumSQ.u64 = 1119; Count.u64 = 1119; Min.u64 = 1; Max.u64 = 1; @@ -1156,6 +1207,9 @@ l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 986; SumSQ.u64 = 986; Count.u64 = 986; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1180,6 +1234,7 @@ l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 4594; SumSQ.u64 = 12669394; Count.u64 = 13; Min.u64 = 66; Max.u64 = 3545; l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 47094; SumSQ.u64 = 11644150; Count.u64 = 837; Min.u64 = 3; Max.u64 = 1222; l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 45331; SumSQ.u64 = 14563331; Count.u64 = 602; Min.u64 = 3; Max.u64 = 1781; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1250,10 +1305,12 @@ l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 837; SumSQ.u64 = 837; Count.u64 = 837; Min.u64 = 1; Max.u64 = 1; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 602; SumSQ.u64 = 602; Count.u64 = 602; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutS_recv : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l2cache2.PutM_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache2.PutE_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; @@ -1265,6 +1322,9 @@ l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 559; SumSQ.u64 = 559; Count.u64 = 559; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NACK_recv : Accumulator : Sum.u64 = 1235; SumSQ.u64 = 1235; Count.u64 = 1235; Min.u64 = 1; Max.u64 = 1; l2cache2.AckInv_recv : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1344,13 +1404,16 @@ l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1501; SumSQ.u64 = 1501; Count.u64 = 1501; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1358,7 +1421,7 @@ l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.evict_I : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_I : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_S : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_M : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_IS : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; @@ -1377,6 +1440,7 @@ l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 69052; SumSQ.u64 = 71653600; Count.u64 = 238; Min.u64 = 68; Max.u64 = 5537; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -1423,24 +1487,28 @@ l1cache3.Write_recv : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 921; SumSQ.u64 = 921; Count.u64 = 921; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Inv_recv : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NACK_recv : Accumulator : Sum.u64 = 3553; SumSQ.u64 = 3553; Count.u64 = 3553; Min.u64 = 1; Max.u64 = 1; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 832152; SumSQ.u64 = 12818416; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 16; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 7173; SumSQ.u64 = 12501; Count.u64 = 5616; Min.u64 = 0; Max.u64 = 7; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 904576; SumSQ.u64 = 372563968; Count.u64 = 5598; Min.u64 = 64; Max.u64 = 576; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 10256724; SumSQ.u64 = 47846226474; Count.u64 = 4556; Min.u64 = 1; Max.u64 = 35679; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 7173; SumSQ.u64 = 12501; Count.u64 = 5616; Min.u64 = 0; Max.u64 = 7; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 904576; SumSQ.u64 = 372563968; Count.u64 = 5598; Min.u64 = 64; Max.u64 = 576; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 10256724; SumSQ.u64 = 47846226474; Count.u64 = 4556; Min.u64 = 1; Max.u64 = 35679; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.evict_I : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_I : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1548,8 +1616,11 @@ l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 1144; SumSQ.u64 = 1144; Count.u64 = 1144; Min.u64 = 1; Max.u64 = 1; @@ -1558,6 +1629,9 @@ l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1582,6 +1656,7 @@ l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 177201; Count.u64 = 8; Min.u64 = 63; Max.u64 = 295; l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 49653; SumSQ.u64 = 30610537; Count.u64 = 599; Min.u64 = 3; Max.u64 = 2280; l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 51237; SumSQ.u64 = 42392133; Count.u64 = 557; Min.u64 = 3; Max.u64 = 5490; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1652,10 +1727,12 @@ l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 946; SumSQ.u64 = 946; Count.u64 = 946; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutS_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; l2cache3.PutM_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.PutE_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; @@ -1667,6 +1744,9 @@ l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NACK_recv : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; l2cache3.AckInv_recv : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1746,13 +1826,16 @@ l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 696; SumSQ.u64 = 696; Count.u64 = 696; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 1478; SumSQ.u64 = 1478; Count.u64 = 1478; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 961; SumSQ.u64 = 961; Count.u64 = 961; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1760,7 +1843,7 @@ l1cache4.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.evict_I : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_I : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; l1cache4.evict_S : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; l1cache4.evict_M : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l1cache4.evict_IS : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; @@ -1779,6 +1862,7 @@ l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 95114; SumSQ.u64 = 132826586; Count.u64 = 249; Min.u64 = 68; Max.u64 = 4463; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -1825,24 +1909,28 @@ l1cache4.Write_recv : Accumulator : Sum.u64 = 961; SumSQ.u64 = 961; Count.u64 = 961; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 914; SumSQ.u64 = 914; Count.u64 = 914; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Inv_recv : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NACK_recv : Accumulator : Sum.u64 = 3771; SumSQ.u64 = 3771; Count.u64 = 3771; Min.u64 = 1; Max.u64 = 1; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 833422; SumSQ.u64 = 12822732; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 16; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 7271; SumSQ.u64 = 12535; Count.u64 = 5700; Min.u64 = 0; Max.u64 = 7; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 913280; SumSQ.u64 = 374890496; Count.u64 = 5686; Min.u64 = 64; Max.u64 = 576; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 10595772; SumSQ.u64 = 51315422670; Count.u64 = 4673; Min.u64 = 1; Max.u64 = 56611; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 7271; SumSQ.u64 = 12535; Count.u64 = 5700; Min.u64 = 0; Max.u64 = 7; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 913280; SumSQ.u64 = 374890496; Count.u64 = 5686; Min.u64 = 64; Max.u64 = 576; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 10595772; SumSQ.u64 = 51315422670; Count.u64 = 4673; Min.u64 = 1; Max.u64 = 56611; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.evict_I : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache4.evict_I : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1950,8 +2038,11 @@ l2cache4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 379; SumSQ.u64 = 379; Count.u64 = 379; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 411; SumSQ.u64 = 411; Count.u64 = 411; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 493; SumSQ.u64 = 493; Count.u64 = 493; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 1113; SumSQ.u64 = 1113; Count.u64 = 1113; Min.u64 = 1; Max.u64 = 1; @@ -1960,6 +2051,9 @@ l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1984,6 +2078,7 @@ l2cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1265; SumSQ.u64 = 163815; Count.u64 = 11; Min.u64 = 68; Max.u64 = 187; l2cache4.latency_FlushLine : Accumulator : Sum.u64 = 46023; SumSQ.u64 = 13390257; Count.u64 = 696; Min.u64 = 3; Max.u64 = 1324; l2cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 57660; SumSQ.u64 = 36478302; Count.u64 = 739; Min.u64 = 3; Max.u64 = 3324; + l2cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -2054,10 +2149,12 @@ l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 696; SumSQ.u64 = 696; Count.u64 = 696; Min.u64 = 1; Max.u64 = 1; l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutS_recv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; l2cache4.PutM_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l2cache4.PutE_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; @@ -2069,6 +2166,9 @@ l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NACK_recv : Accumulator : Sum.u64 = 1214; SumSQ.u64 = 1214; Count.u64 = 1214; Min.u64 = 1; Max.u64 = 1; l2cache4.AckInv_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2148,13 +2248,16 @@ l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 684; SumSQ.u64 = 684; Count.u64 = 684; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 613; SumSQ.u64 = 613; Count.u64 = 613; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 1408; SumSQ.u64 = 1408; Count.u64 = 1408; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 1045; SumSQ.u64 = 1045; Count.u64 = 1045; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2162,7 +2265,7 @@ l1cache5.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.evict_I : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_I : Accumulator : Sum.u64 = 883; SumSQ.u64 = 883; Count.u64 = 883; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_S : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_M : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_IS : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; @@ -2181,6 +2284,7 @@ l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 89981; SumSQ.u64 = 97300093; Count.u64 = 239; Min.u64 = 71; Max.u64 = 4464; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -2227,24 +2331,28 @@ l1cache5.Write_recv : Accumulator : Sum.u64 = 1045; SumSQ.u64 = 1045; Count.u64 = 1045; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 879; SumSQ.u64 = 879; Count.u64 = 879; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Inv_recv : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NACK_recv : Accumulator : Sum.u64 = 3865; SumSQ.u64 = 3865; Count.u64 = 3865; Min.u64 = 1; Max.u64 = 1; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 811422; SumSQ.u64 = 12496400; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 16; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 7306; SumSQ.u64 = 12734; Count.u64 = 5712; Min.u64 = 0; Max.u64 = 7; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 938048; SumSQ.u64 = 390631424; Count.u64 = 5689; Min.u64 = 64; Max.u64 = 576; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 11117472; SumSQ.u64 = 257916168128; Count.u64 = 4575; Min.u64 = 1; Max.u64 = 406209; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 7306; SumSQ.u64 = 12734; Count.u64 = 5712; Min.u64 = 0; Max.u64 = 7; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 938048; SumSQ.u64 = 390631424; Count.u64 = 5689; Min.u64 = 64; Max.u64 = 576; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 11117472; SumSQ.u64 = 257916168128; Count.u64 = 4575; Min.u64 = 1; Max.u64 = 406209; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.evict_I : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; + l2cache5.evict_I : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2352,8 +2460,11 @@ l2cache5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 377; SumSQ.u64 = 377; Count.u64 = 377; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 379; SumSQ.u64 = 379; Count.u64 = 379; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 543; SumSQ.u64 = 543; Count.u64 = 543; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; @@ -2362,6 +2473,9 @@ l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2386,6 +2500,7 @@ l2cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1329; SumSQ.u64 = 153959; Count.u64 = 13; Min.u64 = 64; Max.u64 = 205; l2cache5.latency_FlushLine : Accumulator : Sum.u64 = 42556; SumSQ.u64 = 17941802; Count.u64 = 684; Min.u64 = 3; Max.u64 = 3219; l2cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 51716; SumSQ.u64 = 19693114; Count.u64 = 613; Min.u64 = 3; Max.u64 = 1920; + l2cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2456,10 +2571,12 @@ l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 684; SumSQ.u64 = 684; Count.u64 = 684; Min.u64 = 1; Max.u64 = 1; l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 613; SumSQ.u64 = 613; Count.u64 = 613; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 1005; SumSQ.u64 = 1005; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.PutS_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l2cache5.PutM_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l2cache5.PutE_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; @@ -2471,17 +2588,20 @@ l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 586; SumSQ.u64 = 586; Count.u64 = 586; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NACK_recv : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; l2cache5.AckInv_recv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 332524; SumSQ.u64 = 2179750; Count.u64 = 54640; Min.u64 = 0; Max.u64 = 8; l2cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 19733; SumSQ.u64 = 45287; Count.u64 = 13605; Min.u64 = 0; Max.u64 = 11; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 3385280; SumSQ.u64 = 1664086016; Count.u64 = 13631; Min.u64 = 64; Max.u64 = 576; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 5983496; SumSQ.u64 = 91342485208; Count.u64 = 4923; Min.u64 = 4; Max.u64 = 275782; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 19733; SumSQ.u64 = 45287; Count.u64 = 13605; Min.u64 = 0; Max.u64 = 11; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 3385280; SumSQ.u64 = 1664086016; Count.u64 = 13631; Min.u64 = 64; Max.u64 = 576; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 5983496; SumSQ.u64 = 91342485208; Count.u64 = 4923; Min.u64 = 4; Max.u64 = 275782; l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.evict_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_I : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2589,8 +2709,11 @@ l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 506; SumSQ.u64 = 506; Count.u64 = 506; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2599,6 +2722,9 @@ l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2020; SumSQ.u64 = 2020; Count.u64 = 2020; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 1007; Count.u64 = 1007; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 941; SumSQ.u64 = 941; Count.u64 = 941; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2623,6 +2749,7 @@ l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 634; SumSQ.u64 = 28044; Count.u64 = 16; Min.u64 = 28; Max.u64 = 76; l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 36952; SumSQ.u64 = 3447434; Count.u64 = 779; Min.u64 = 7; Max.u64 = 684; l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 42523; SumSQ.u64 = 3741337; Count.u64 = 864; Min.u64 = 7; Max.u64 = 437; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 1627; SumSQ.u64 = 1627; Count.u64 = 1627; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; @@ -2693,10 +2820,12 @@ l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 779; SumSQ.u64 = 779; Count.u64 = 779; Min.u64 = 1; Max.u64 = 1; l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 864; SumSQ.u64 = 864; Count.u64 = 864; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 1007; Count.u64 = 1007; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2708,15 +2837,18 @@ l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NACK_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l3cache0.AckInv_recv : Accumulator : Sum.u64 = 2303; SumSQ.u64 = 2303; Count.u64 = 2303; Min.u64 = 1; Max.u64 = 1; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 173167; SumSQ.u64 = 1031057; Count.u64 = 31911; Min.u64 = 0; Max.u64 = 7; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 17385; SumSQ.u64 = 37939; Count.u64 = 12556; Min.u64 = 0; Max.u64 = 10; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 3164672; SumSQ.u64 = 1561493504; Count.u64 = 12584; Min.u64 = 64; Max.u64 = 576; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 6292372; SumSQ.u64 = 91676293040; Count.u64 = 5022; Min.u64 = 4; Max.u64 = 275470; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 17385; SumSQ.u64 = 37939; Count.u64 = 12556; Min.u64 = 0; Max.u64 = 10; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 3164672; SumSQ.u64 = 1561493504; Count.u64 = 12584; Min.u64 = 64; Max.u64 = 576; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 6292372; SumSQ.u64 = 91676293040; Count.u64 = 5022; Min.u64 = 4; Max.u64 = 275470; l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2826,8 +2958,11 @@ l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2836,6 +2971,9 @@ l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1849; SumSQ.u64 = 1849; Count.u64 = 1849; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 951; SumSQ.u64 = 951; Count.u64 = 951; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 816; SumSQ.u64 = 816; Count.u64 = 816; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2860,6 +2998,7 @@ l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 913; SumSQ.u64 = 54677; Count.u64 = 19; Min.u64 = 30; Max.u64 = 114; l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 35453; SumSQ.u64 = 2845057; Count.u64 = 748; Min.u64 = 7; Max.u64 = 270; l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 39623; SumSQ.u64 = 4134195; Count.u64 = 625; Min.u64 = 7; Max.u64 = 488; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 1375; SumSQ.u64 = 1375; Count.u64 = 1375; Min.u64 = 1; Max.u64 = 1; l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 1427; SumSQ.u64 = 1427; Count.u64 = 1427; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; @@ -2930,10 +3069,12 @@ l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 951; SumSQ.u64 = 951; Count.u64 = 951; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2945,15 +3086,18 @@ l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 1002; SumSQ.u64 = 1002; Count.u64 = 1002; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NACK_recv : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; l3cache1.AckInv_recv : Accumulator : Sum.u64 = 2266; SumSQ.u64 = 2266; Count.u64 = 2266; Min.u64 = 1; Max.u64 = 1; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 168949; SumSQ.u64 = 987535; Count.u64 = 31911; Min.u64 = 0; Max.u64 = 7; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 18181; SumSQ.u64 = 40419; Count.u64 = 12988; Min.u64 = 0; Max.u64 = 10; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 3262848; SumSQ.u64 = 1608179712; Count.u64 = 13022; Min.u64 = 64; Max.u64 = 576; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 6331380; SumSQ.u64 = 164212935328; Count.u64 = 5076; Min.u64 = 4; Max.u64 = 389184; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 18181; SumSQ.u64 = 40419; Count.u64 = 12988; Min.u64 = 0; Max.u64 = 10; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 3262848; SumSQ.u64 = 1608179712; Count.u64 = 13022; Min.u64 = 64; Max.u64 = 576; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 6331380; SumSQ.u64 = 164212935328; Count.u64 = 5076; Min.u64 = 4; Max.u64 = 389184; l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3063,8 +3207,11 @@ l3cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3073,6 +3220,9 @@ l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1905; SumSQ.u64 = 1905; Count.u64 = 1905; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 954; SumSQ.u64 = 954; Count.u64 = 954; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 844; SumSQ.u64 = 844; Count.u64 = 844; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3097,6 +3247,7 @@ l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1254; SumSQ.u64 = 126562; Count.u64 = 23; Min.u64 = 28; Max.u64 = 268; l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 34971; SumSQ.u64 = 3098029; Count.u64 = 761; Min.u64 = 7; Max.u64 = 650; l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 40943; SumSQ.u64 = 5233521; Count.u64 = 716; Min.u64 = 7; Max.u64 = 1093; + l3cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1379; SumSQ.u64 = 1379; Count.u64 = 1379; Min.u64 = 1; Max.u64 = 1; l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1529; SumSQ.u64 = 1529; Count.u64 = 1529; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; @@ -3167,10 +3318,12 @@ l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 732; SumSQ.u64 = 732; Count.u64 = 732; Min.u64 = 1; Max.u64 = 1; l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 954; SumSQ.u64 = 954; Count.u64 = 954; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3182,15 +3335,18 @@ l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 782; SumSQ.u64 = 782; Count.u64 = 782; Min.u64 = 1; Max.u64 = 1; l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 1013; SumSQ.u64 = 1013; Count.u64 = 1013; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NACK_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l3cache2.AckInv_recv : Accumulator : Sum.u64 = 2286; SumSQ.u64 = 2286; Count.u64 = 2286; Min.u64 = 1; Max.u64 = 1; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 172790; SumSQ.u64 = 1029316; Count.u64 = 31911; Min.u64 = 0; Max.u64 = 7; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 3205; SumSQ.u64 = 4943; Count.u64 = 2616; Min.u64 = 0; Max.u64 = 6; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 1137152; SumSQ.u64 = 631341056; Count.u64 = 2616; Min.u64 = 64; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 12083634; SumSQ.u64 = 308738695108; Count.u64 = 2132; Min.u64 = 16; Max.u64 = 308380; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 3205; SumSQ.u64 = 4943; Count.u64 = 2616; Min.u64 = 0; Max.u64 = 6; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 1137152; SumSQ.u64 = 631341056; Count.u64 = 2616; Min.u64 = 64; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 12083634; SumSQ.u64 = 308738695108; Count.u64 = 2132; Min.u64 = 16; Max.u64 = 308380; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 28829; SumSQ.u64 = 825403; Count.u64 = 1497; Min.u64 = 5; Max.u64 = 109; directory0.get_request_latency : Accumulator : Sum.u64 = 20324; SumSQ.u64 = 621146; Count.u64 = 1119; Min.u64 = 2; Max.u64 = 110; @@ -3213,8 +3369,10 @@ directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 753; SumSQ.u64 = 753; Count.u64 = 753; Min.u64 = 1; Max.u64 = 1; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3233,6 +3391,7 @@ directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 1119; SumSQ.u64 = 1119; Count.u64 = 1119; Min.u64 = 1; Max.u64 = 1; @@ -3243,6 +3402,8 @@ directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 753; SumSQ.u64 = 753; Count.u64 = 753; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 43921; SumSQ.u64 = 112429; Count.u64 = 31875; Min.u64 = 0; Max.u64 = 8; @@ -3263,10 +3424,10 @@ memory0.cycles_with_issue : Accumulator : Sum.u64 = 1384; SumSQ.u64 = 1384; Count.u64 = 1384; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 1626; SumSQ.u64 = 1626; Count.u64 = 1626; Min.u64 = 1; Max.u64 = 1; memory0.total_cycles : Accumulator : Sum.u64 = 11392; SumSQ.u64 = 129777664; Count.u64 = 1; Min.u64 = 11392; Max.u64 = 11392; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 3067; SumSQ.u64 = 4789; Count.u64 = 2502; Min.u64 = 0; Max.u64 = 6; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 1088896; SumSQ.u64 = 604659712; Count.u64 = 2502; Min.u64 = 64; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 12000964; SumSQ.u64 = 305809212592; Count.u64 = 2043; Min.u64 = 10; Max.u64 = 328546; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 3067; SumSQ.u64 = 4789; Count.u64 = 2502; Min.u64 = 0; Max.u64 = 6; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 1088896; SumSQ.u64 = 604659712; Count.u64 = 2502; Min.u64 = 64; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 12000964; SumSQ.u64 = 305809212592; Count.u64 = 2043; Min.u64 = 10; Max.u64 = 328546; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 27596; SumSQ.u64 = 755280; Count.u64 = 1415; Min.u64 = 5; Max.u64 = 77; directory1.get_request_latency : Accumulator : Sum.u64 = 19046; SumSQ.u64 = 593312; Count.u64 = 1087; Min.u64 = 2; Max.u64 = 82; @@ -3289,8 +3450,10 @@ directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 1415; SumSQ.u64 = 1415; Count.u64 = 1415; Min.u64 = 1; Max.u64 = 1; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3309,6 +3472,7 @@ directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; @@ -3319,6 +3483,8 @@ directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1415; SumSQ.u64 = 1415; Count.u64 = 1415; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 41638; SumSQ.u64 = 103110; Count.u64 = 31881; Min.u64 = 0; Max.u64 = 11; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out index ea930f1e80..07d918ce3b 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Flushes_2.out @@ -1,103 +1,103 @@ - network.send_bit_count.port0 : Accumulator : Sum.u64 = 1282880; SumSQ.u64 = 617510912; Count.u64 = 5462; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port0 : Accumulator : Sum.u64 = 5462; SumSQ.u64 = 5462; Count.u64 = 5462; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port0 : Accumulator : Sum.u64 = 1257472; SumSQ.u64 = 605544448; Count.u64 = 5348; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port0 : Accumulator : Sum.u64 = 5348; SumSQ.u64 = 5348; Count.u64 = 5348; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port0 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port0 : Accumulator : Sum.u64 = 17836314; SumSQ.u64 = 517103494596; Count.u64 = 3648; Min.u64 = 1200; Max.u64 = 577314; + network.idle_time.port0 : Accumulator : Sum.u64 = 17616300; SumSQ.u64 = 156383370000; Count.u64 = 3579; Min.u64 = 1200; Max.u64 = 43200; network.width_adj_count.port0 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port1 : Accumulator : Sum.u64 = 1314048; SumSQ.u64 = 631965696; Count.u64 = 5601; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port1 : Accumulator : Sum.u64 = 5601; SumSQ.u64 = 5601; Count.u64 = 5601; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port1 : Accumulator : Sum.u64 = 1320288; SumSQ.u64 = 637645824; Count.u64 = 5559; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port1 : Accumulator : Sum.u64 = 5559; SumSQ.u64 = 5559; Count.u64 = 5559; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port1 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port1 : Accumulator : Sum.u64 = 17727714; SumSQ.u64 = 181542591396; Count.u64 = 3742; Min.u64 = 1200; Max.u64 = 187914; + network.idle_time.port1 : Accumulator : Sum.u64 = 17432700; SumSQ.u64 = 176394690000; Count.u64 = 3706; Min.u64 = 1200; Max.u64 = 137700; network.width_adj_count.port1 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port2 : Accumulator : Sum.u64 = 1312896; SumSQ.u64 = 636592128; Count.u64 = 5458; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port2 : Accumulator : Sum.u64 = 5458; SumSQ.u64 = 5458; Count.u64 = 5458; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port2 : Accumulator : Sum.u64 = 1278240; SumSQ.u64 = 616141824; Count.u64 = 5404; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port2 : Accumulator : Sum.u64 = 5404; SumSQ.u64 = 5404; Count.u64 = 5404; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port2 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port2 : Accumulator : Sum.u64 = 17803914; SumSQ.u64 = 192997776996; Count.u64 = 3734; Min.u64 = 1200; Max.u64 = 179400; + network.idle_time.port2 : Accumulator : Sum.u64 = 17564100; SumSQ.u64 = 146556810000; Count.u64 = 3662; Min.u64 = 1200; Max.u64 = 54900; network.width_adj_count.port2 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port3 : Accumulator : Sum.u64 = 1347904; SumSQ.u64 = 652367872; Count.u64 = 5642; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port3 : Accumulator : Sum.u64 = 5642; SumSQ.u64 = 5642; Count.u64 = 5642; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port3 : Accumulator : Sum.u64 = 1304832; SumSQ.u64 = 627886080; Count.u64 = 5545; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port3 : Accumulator : Sum.u64 = 5545; SumSQ.u64 = 5545; Count.u64 = 5545; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port3 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port3 : Accumulator : Sum.u64 = 17665914; SumSQ.u64 = 193214734596; Count.u64 = 3713; Min.u64 = 1200; Max.u64 = 187314; + network.idle_time.port3 : Accumulator : Sum.u64 = 17459100; SumSQ.u64 = 176918130000; Count.u64 = 3676; Min.u64 = 1200; Max.u64 = 107400; network.width_adj_count.port3 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port4 : Accumulator : Sum.u64 = 1315872; SumSQ.u64 = 632921088; Count.u64 = 5613; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port4 : Accumulator : Sum.u64 = 5613; SumSQ.u64 = 5613; Count.u64 = 5613; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port4 : Accumulator : Sum.u64 = 1310688; SumSQ.u64 = 632878080; Count.u64 = 5525; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port4 : Accumulator : Sum.u64 = 5525; SumSQ.u64 = 5525; Count.u64 = 5525; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port4 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port4 : Accumulator : Sum.u64 = 17718714; SumSQ.u64 = 193455740196; Count.u64 = 3740; Min.u64 = 1200; Max.u64 = 181200; + network.idle_time.port4 : Accumulator : Sum.u64 = 17461500; SumSQ.u64 = 335862450000; Count.u64 = 3664; Min.u64 = 1200; Max.u64 = 345300; network.width_adj_count.port4 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port5 : Accumulator : Sum.u64 = 1325184; SumSQ.u64 = 640868352; Count.u64 = 5562; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port5 : Accumulator : Sum.u64 = 5562; SumSQ.u64 = 5562; Count.u64 = 5562; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port5 : Accumulator : Sum.u64 = 1301920; SumSQ.u64 = 625847296; Count.u64 = 5561; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port5 : Accumulator : Sum.u64 = 5561; SumSQ.u64 = 5561; Count.u64 = 5561; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port5 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port5 : Accumulator : Sum.u64 = 17734314; SumSQ.u64 = 218293450596; Count.u64 = 3666; Min.u64 = 1200; Max.u64 = 154314; + network.idle_time.port5 : Accumulator : Sum.u64 = 17453100; SumSQ.u64 = 865440090000; Count.u64 = 3591; Min.u64 = 1200; Max.u64 = 830700; network.width_adj_count.port5 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port6 : Accumulator : Sum.u64 = 2405696; SumSQ.u64 = 1058637824; Count.u64 = 12784; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port6 : Accumulator : Sum.u64 = 12784; SumSQ.u64 = 12784; Count.u64 = 12784; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port6 : Accumulator : Sum.u64 = 2506176; SumSQ.u64 = 1102270464; Count.u64 = 13339; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port6 : Accumulator : Sum.u64 = 13339; SumSQ.u64 = 13339; Count.u64 = 13339; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port6 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port6 : Accumulator : Sum.u64 = 12694914; SumSQ.u64 = 71166353796; Count.u64 = 4620; Min.u64 = 1200; Max.u64 = 123714; + network.idle_time.port6 : Accumulator : Sum.u64 = 11976900; SumSQ.u64 = 52489890000; Count.u64 = 4464; Min.u64 = 1200; Max.u64 = 24600; network.width_adj_count.port6 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port7 : Accumulator : Sum.u64 = 2498080; SumSQ.u64 = 1108986880; Count.u64 = 13155; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port7 : Accumulator : Sum.u64 = 13155; SumSQ.u64 = 13155; Count.u64 = 13155; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port7 : Accumulator : Sum.u64 = 2488096; SumSQ.u64 = 1101313024; Count.u64 = 13184; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port7 : Accumulator : Sum.u64 = 13184; SumSQ.u64 = 13184; Count.u64 = 13184; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port7 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port7 : Accumulator : Sum.u64 = 12379914; SumSQ.u64 = 70094705796; Count.u64 = 4524; Min.u64 = 1200; Max.u64 = 117714; + network.idle_time.port7 : Accumulator : Sum.u64 = 12067500; SumSQ.u64 = 50480010000; Count.u64 = 4609; Min.u64 = 1200; Max.u64 = 22800; network.width_adj_count.port7 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port8 : Accumulator : Sum.u64 = 2489248; SumSQ.u64 = 1105767424; Count.u64 = 13089; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port8 : Accumulator : Sum.u64 = 13089; SumSQ.u64 = 13089; Count.u64 = 13089; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port8 : Accumulator : Sum.u64 = 2387168; SumSQ.u64 = 1070425088; Count.u64 = 12263; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port8 : Accumulator : Sum.u64 = 12263; SumSQ.u64 = 12263; Count.u64 = 12263; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port8 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port8 : Accumulator : Sum.u64 = 12424914; SumSQ.u64 = 60756759396; Count.u64 = 4590; Min.u64 = 1200; Max.u64 = 77400; + network.idle_time.port8 : Accumulator : Sum.u64 = 12669900; SumSQ.u64 = 58922370000; Count.u64 = 4521; Min.u64 = 1200; Max.u64 = 38400; network.width_adj_count.port8 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port9 : Accumulator : Sum.u64 = 763872; SumSQ.u64 = 379106304; Count.u64 = 2909; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port9 : Accumulator : Sum.u64 = 2909; SumSQ.u64 = 2909; Count.u64 = 2909; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port9 : Accumulator : Sum.u64 = 787488; SumSQ.u64 = 391007232; Count.u64 = 2987; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port9 : Accumulator : Sum.u64 = 2987; SumSQ.u64 = 2987; Count.u64 = 2987; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port9 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port9 : Accumulator : Sum.u64 = 19785714; SumSQ.u64 = 375046328196; Count.u64 = 2340; Min.u64 = 1200; Max.u64 = 227400; + network.idle_time.port9 : Accumulator : Sum.u64 = 19408500; SumSQ.u64 = 291981330000; Count.u64 = 2370; Min.u64 = 1200; Max.u64 = 103800; network.width_adj_count.port9 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.send_bit_count.port10 : Accumulator : Sum.u64 = 762880; SumSQ.u64 = 379402240; Count.u64 = 2875; Min.u64 = 64; Max.u64 = 576; - network.send_packet_count.port10 : Accumulator : Sum.u64 = 2875; SumSQ.u64 = 2875; Count.u64 = 2875; Min.u64 = 1; Max.u64 = 1; + network.send_bit_count.port10 : Accumulator : Sum.u64 = 770784; SumSQ.u64 = 382540800; Count.u64 = 2930; Min.u64 = 64; Max.u64 = 576; + network.send_packet_count.port10 : Accumulator : Sum.u64 = 2930; SumSQ.u64 = 2930; Count.u64 = 2930; Min.u64 = 1; Max.u64 = 1; network.output_port_stalls.port10 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.idle_time.port10 : Accumulator : Sum.u64 = 19805514; SumSQ.u64 = 343921656996; Count.u64 = 2334; Min.u64 = 1200; Max.u64 = 163800; + network.idle_time.port10 : Accumulator : Sum.u64 = 19457700; SumSQ.u64 = 289021770000; Count.u64 = 2338; Min.u64 = 1200; Max.u64 = 56400; network.width_adj_count.port10 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - network.xbar_stalls.port0 : Accumulator : Sum.u64 = 2960; SumSQ.u64 = 2960; Count.u64 = 2960; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port1 : Accumulator : Sum.u64 = 2845; SumSQ.u64 = 2845; Count.u64 = 2845; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port2 : Accumulator : Sum.u64 = 2728; SumSQ.u64 = 2728; Count.u64 = 2728; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port3 : Accumulator : Sum.u64 = 3075; SumSQ.u64 = 3075; Count.u64 = 3075; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port4 : Accumulator : Sum.u64 = 2876; SumSQ.u64 = 2876; Count.u64 = 2876; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port5 : Accumulator : Sum.u64 = 2831; SumSQ.u64 = 2831; Count.u64 = 2831; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port6 : Accumulator : Sum.u64 = 1304; SumSQ.u64 = 1304; Count.u64 = 1304; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port7 : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port8 : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port9 : Accumulator : Sum.u64 = 1086; SumSQ.u64 = 1086; Count.u64 = 1086; Min.u64 = 1; Max.u64 = 1; - network.xbar_stalls.port10 : Accumulator : Sum.u64 = 1069; SumSQ.u64 = 1069; Count.u64 = 1069; Min.u64 = 1; Max.u64 = 1; - core0.pendCycle : Accumulator : Sum.u64 = 793698; SumSQ.u64 = 12448344; Count.u64 = 51351; Min.u64 = 0; Max.u64 = 16; - core0.reads : Accumulator : Sum.u64 = 1468; SumSQ.u64 = 1468; Count.u64 = 1468; Min.u64 = 1; Max.u64 = 1; - core0.writes : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; - core0.readNoncache : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; - core0.writeNoncache : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; - core0.flushes : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; - core0.flushinvs : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; - core0.llsc : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; - core0.llsc_success : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port0 : Accumulator : Sum.u64 = 2657; SumSQ.u64 = 2657; Count.u64 = 2657; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port1 : Accumulator : Sum.u64 = 2928; SumSQ.u64 = 2928; Count.u64 = 2928; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port2 : Accumulator : Sum.u64 = 2822; SumSQ.u64 = 2822; Count.u64 = 2822; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port3 : Accumulator : Sum.u64 = 2988; SumSQ.u64 = 2988; Count.u64 = 2988; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port4 : Accumulator : Sum.u64 = 2967; SumSQ.u64 = 2967; Count.u64 = 2967; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port5 : Accumulator : Sum.u64 = 2865; SumSQ.u64 = 2865; Count.u64 = 2865; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port6 : Accumulator : Sum.u64 = 1466; SumSQ.u64 = 1466; Count.u64 = 1466; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port7 : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port8 : Accumulator : Sum.u64 = 1359; SumSQ.u64 = 1359; Count.u64 = 1359; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port9 : Accumulator : Sum.u64 = 1159; SumSQ.u64 = 1159; Count.u64 = 1159; Min.u64 = 1; Max.u64 = 1; + network.xbar_stalls.port10 : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + core0.pendCycle : Accumulator : Sum.u64 = 824292; SumSQ.u64 = 12978414; Count.u64 = 52483; Min.u64 = 0; Max.u64 = 16; + core0.reads : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; + core0.readNoncache : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + core0.writeNoncache : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + core0.flushes : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; + core0.flushinvs : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 586; SumSQ.u64 = 586; Count.u64 = 586; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 806; SumSQ.u64 = 806; Count.u64 = 806; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -109,7 +109,7 @@ l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -123,30 +123,33 @@ l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 2391; SumSQ.u64 = 2391; Count.u64 = 2391; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1954; SumSQ.u64 = 1954; Count.u64 = 1954; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_Write : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 2256; SumSQ.u64 = 2256; Count.u64 = 2256; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1861; SumSQ.u64 = 1861; Count.u64 = 1861; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1468; SumSQ.u64 = 1468; Count.u64 = 1468; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 686; SumSQ.u64 = 686; Count.u64 = 686; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 831; SumSQ.u64 = 831; Count.u64 = 831; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 963; SumSQ.u64 = 963; Count.u64 = 963; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -154,89 +157,94 @@ l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.evict_I : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_S : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_M : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_IS : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_IM : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_SM : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_SB : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 86534; SumSQ.u64 = 165368592; Count.u64 = 417; Min.u64 = 4; Max.u64 = 4616; - l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 208044; SumSQ.u64 = 216155656; Count.u64 = 969; Min.u64 = 16; Max.u64 = 4243; - l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 69161; SumSQ.u64 = 127165679; Count.u64 = 193; Min.u64 = 2; Max.u64 = 4400; - l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 174293; SumSQ.u64 = 213632641; Count.u64 = 586; Min.u64 = 17; Max.u64 = 4724; - l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 54498; SumSQ.u64 = 76276974; Count.u64 = 149; Min.u64 = 68; Max.u64 = 4613; - l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 2761; SumSQ.u64 = 4376901; Count.u64 = 10; Min.u64 = 4; Max.u64 = 1954; - l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 16191; SumSQ.u64 = 13212083; Count.u64 = 57; Min.u64 = 73; Max.u64 = 2494; - l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 588; SumSQ.u64 = 122088; Count.u64 = 4; Min.u64 = 76; Max.u64 = 306; - l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 80798; SumSQ.u64 = 72499632; Count.u64 = 263; Min.u64 = 67; Max.u64 = 3410; + l1cache0.evict_I : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SB : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 96890; SumSQ.u64 = 225097498; Count.u64 = 430; Min.u64 = 4; Max.u64 = 7020; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 220980; SumSQ.u64 = 433424384; Count.u64 = 945; Min.u64 = 16; Max.u64 = 11001; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 53824; SumSQ.u64 = 148819224; Count.u64 = 183; Min.u64 = 2; Max.u64 = 7019; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 146524; SumSQ.u64 = 143317866; Count.u64 = 563; Min.u64 = 16; Max.u64 = 3323; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 71075; SumSQ.u64 = 222122811; Count.u64 = 160; Min.u64 = 64; Max.u64 = 8016; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 4663; SumSQ.u64 = 21594673; Count.u64 = 5; Min.u64 = 4; Max.u64 = 4647; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 11344; SumSQ.u64 = 4274372; Count.u64 = 55; Min.u64 = 73; Max.u64 = 1053; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1760; SumSQ.u64 = 428988; Count.u64 = 10; Min.u64 = 74; Max.u64 = 345; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 116038; SumSQ.u64 = 409266118; Count.u64 = 269; Min.u64 = 66; Max.u64 = 11601; l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 80767; SumSQ.u64 = 116359635; Count.u64 = 210; Min.u64 = 77; Max.u64 = 5365; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 81566; SumSQ.u64 = 124661404; Count.u64 = 244; Min.u64 = 69; Max.u64 = 8428; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 846; SumSQ.u64 = 846; Count.u64 = 846; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 622; SumSQ.u64 = 622; Count.u64 = 622; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache0.CacheHits : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; - l1cache0.CacheMisses : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 1733; SumSQ.u64 = 1733; Count.u64 = 1733; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 10442; SumSQ.u64 = 10442; Count.u64 = 10442; Min.u64 = 1; Max.u64 = 1; - l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 764; SumSQ.u64 = 764; Count.u64 = 764; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 10162; SumSQ.u64 = 10162; Count.u64 = 10162; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; - l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; - l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetS_recv : Accumulator : Sum.u64 = 1386; SumSQ.u64 = 1386; Count.u64 = 1386; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1375; SumSQ.u64 = 1375; Count.u64 = 1375; Min.u64 = 1; Max.u64 = 1; l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSX_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; - l1cache0.Write_recv : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; - l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; - l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; - l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; - l1cache0.Inv_recv : Accumulator : Sum.u64 = 856; SumSQ.u64 = 856; Count.u64 = 856; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 884; SumSQ.u64 = 884; Count.u64 = 884; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; - l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; - l1cache0.NACK_recv : Accumulator : Sum.u64 = 3459; SumSQ.u64 = 3459; Count.u64 = 3459; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 3252; SumSQ.u64 = 3252; Count.u64 = 3252; Min.u64 = 1; Max.u64 = 1; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 762574; SumSQ.u64 = 11523538; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 793655; SumSQ.u64 = 12067941; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 6845; SumSQ.u64 = 11669; Count.u64 = 5462; Min.u64 = 0; Max.u64 = 6; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 849856; SumSQ.u64 = 342114304; Count.u64 = 5449; Min.u64 = 64; Max.u64 = 576; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 11046402; SumSQ.u64 = 420485495958; Count.u64 = 4347; Min.u64 = 1; Max.u64 = 573009; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 6595; SumSQ.u64 = 10923; Count.u64 = 5348; Min.u64 = 0; Max.u64 = 6; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 816416; SumSQ.u64 = 324924416; Count.u64 = 5336; Min.u64 = 64; Max.u64 = 576; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 10482730; SumSQ.u64 = 59000050516; Count.u64 = 4234; Min.u64 = 1; Max.u64 = 34270; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.evict_I : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_I : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -249,48 +257,48 @@ l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 559; SumSQ.u64 = 559; Count.u64 = 559; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 631; SumSQ.u64 = 631; Count.u64 = 631; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 784; SumSQ.u64 = 784; Count.u64 = 784; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 605; SumSQ.u64 = 605; Count.u64 = 605; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 1157; SumSQ.u64 = 1157; Count.u64 = 1157; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 777; SumSQ.u64 = 777; Count.u64 = 777; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -302,7 +310,7 @@ l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -310,7 +318,7 @@ l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -323,75 +331,82 @@ l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1320; SumSQ.u64 = 1320; Count.u64 = 1320; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_Write : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 803; SumSQ.u64 = 803; Count.u64 = 803; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1123; SumSQ.u64 = 1123; Count.u64 = 1123; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 3611; SumSQ.u64 = 3611; Count.u64 = 3611; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 939; SumSQ.u64 = 939; Count.u64 = 939; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 1019; SumSQ.u64 = 1019; Count.u64 = 1019; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 3359; SumSQ.u64 = 3359; Count.u64 = 3359; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 884; SumSQ.u64 = 884; Count.u64 = 884; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 856; SumSQ.u64 = 856; Count.u64 = 856; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 779; SumSQ.u64 = 8489; Count.u64 = 72; Min.u64 = 10; Max.u64 = 14; - l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 94223; SumSQ.u64 = 15954969; Count.u64 = 897; Min.u64 = 37; Max.u64 = 689; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 899; SumSQ.u64 = 9973; Count.u64 = 82; Min.u64 = 10; Max.u64 = 18; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 96293; SumSQ.u64 = 24412069; Count.u64 = 863; Min.u64 = 37; Max.u64 = 1935; l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 101; SumSQ.u64 = 1135; Count.u64 = 9; Min.u64 = 11; Max.u64 = 12; - l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 95942; SumSQ.u64 = 60129368; Count.u64 = 559; Min.u64 = 42; Max.u64 = 4283; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 77; SumSQ.u64 = 849; Count.u64 = 7; Min.u64 = 10; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 84953; SumSQ.u64 = 40960229; Count.u64 = 533; Min.u64 = 47; Max.u64 = 3182; l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 20786; SumSQ.u64 = 3991066; Count.u64 = 167; Min.u64 = 59; Max.u64 = 813; - l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 11; SumSQ.u64 = 121; Count.u64 = 1; Min.u64 = 11; Max.u64 = 11; - l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 7223; SumSQ.u64 = 1499967; Count.u64 = 52; Min.u64 = 62; Max.u64 = 568; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 22206; SumSQ.u64 = 4506506; Count.u64 = 183; Min.u64 = 50; Max.u64 = 817; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 6888; SumSQ.u64 = 1134722; Count.u64 = 51; Min.u64 = 67; Max.u64 = 297; l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 653; SumSQ.u64 = 56641; Count.u64 = 8; Min.u64 = 61; Max.u64 = 127; - l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 47980; SumSQ.u64 = 13366216; Count.u64 = 727; Min.u64 = 3; Max.u64 = 1240; - l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 44636; SumSQ.u64 = 14734764; Count.u64 = 541; Min.u64 = 3; Max.u64 = 1733; - l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1563; SumSQ.u64 = 235381; Count.u64 = 14; Min.u64 = 67; Max.u64 = 303; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 53235; SumSQ.u64 = 41557813; Count.u64 = 686; Min.u64 = 3; Max.u64 = 5360; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 48929; SumSQ.u64 = 14899945; Count.u64 = 617; Min.u64 = 3; Max.u64 = 1739; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 723; SumSQ.u64 = 723; Count.u64 = 723; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.CacheHits : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; - l2cache0.CacheMisses : Accumulator : Sum.u64 = 1683; SumSQ.u64 = 1683; Count.u64 = 1683; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheHits : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 1644; SumSQ.u64 = 1644; Count.u64 = 1644; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -401,8 +416,8 @@ l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -413,93 +428,98 @@ l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 13298; SumSQ.u64 = 13298; Count.u64 = 13298; Min.u64 = 1; Max.u64 = 1; - l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1611; SumSQ.u64 = 1611; Count.u64 = 1611; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 12883; SumSQ.u64 = 12883; Count.u64 = 12883; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1536; SumSQ.u64 = 1536; Count.u64 = 1536; Min.u64 = 1; Max.u64 = 1; l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; - l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; - l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetS_recv : Accumulator : Sum.u64 = 2309; SumSQ.u64 = 2309; Count.u64 = 2309; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetX_recv : Accumulator : Sum.u64 = 1954; SumSQ.u64 = 1954; Count.u64 = 1954; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetSX_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 2177; SumSQ.u64 = 2177; Count.u64 = 2177; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1861; SumSQ.u64 = 1861; Count.u64 = 1861; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; - l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 884; SumSQ.u64 = 884; Count.u64 = 884; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 686; SumSQ.u64 = 686; Count.u64 = 686; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 784; SumSQ.u64 = 784; Count.u64 = 784; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 860; SumSQ.u64 = 860; Count.u64 = 860; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; - l2cache0.PutS_recv : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l2cache0.PutM_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; - l2cache0.PutE_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.Inv_recv : Accumulator : Sum.u64 = 1190; SumSQ.u64 = 1190; Count.u64 = 1190; Min.u64 = 1; Max.u64 = 1; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 1074; SumSQ.u64 = 1074; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 1; l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; - l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; - l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; - l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; - l2cache0.NACK_recv : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; - l2cache0.AckInv_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 1128; SumSQ.u64 = 1128; Count.u64 = 1128; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 831; SumSQ.u64 = 831; Count.u64 = 831; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 313994; SumSQ.u64 = 2022894; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 8; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 314132; SumSQ.u64 = 2000304; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 8; l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core1.pendCycle : Accumulator : Sum.u64 = 816994; SumSQ.u64 = 12865172; Count.u64 = 52086; Min.u64 = 0; Max.u64 = 16; - core1.reads : Accumulator : Sum.u64 = 1462; SumSQ.u64 = 1462; Count.u64 = 1462; Min.u64 = 1; Max.u64 = 1; - core1.writes : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; - core1.readNoncache : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - core1.writeNoncache : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - core1.flushes : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; - core1.flushinvs : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; - core1.llsc : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; - core1.llsc_success : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 804407; SumSQ.u64 = 12642727; Count.u64 = 51449; Min.u64 = 0; Max.u64 = 16; + core1.reads : Accumulator : Sum.u64 = 1502; SumSQ.u64 = 1502; Count.u64 = 1502; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + core1.readNoncache : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + core1.writeNoncache : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + core1.flushes : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + core1.flushinvs : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 818; SumSQ.u64 = 818; Count.u64 = 818; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -511,14 +531,14 @@ l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -527,30 +547,33 @@ l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 2119; SumSQ.u64 = 2119; Count.u64 = 2119; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_Write : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 2570; SumSQ.u64 = 2570; Count.u64 = 2570; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 2087; SumSQ.u64 = 2087; Count.u64 = 2087; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 871; SumSQ.u64 = 871; Count.u64 = 871; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1462; SumSQ.u64 = 1462; Count.u64 = 1462; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 998; SumSQ.u64 = 998; Count.u64 = 998; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 675; SumSQ.u64 = 675; Count.u64 = 675; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 655; SumSQ.u64 = 655; Count.u64 = 655; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 864; SumSQ.u64 = 864; Count.u64 = 864; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1502; SumSQ.u64 = 1502; Count.u64 = 1502; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 974; SumSQ.u64 = 974; Count.u64 = 974; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -558,89 +581,94 @@ l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.evict_I : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_S : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_M : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_IS : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_IM : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_SM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_SB : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 77515; SumSQ.u64 = 121997287; Count.u64 = 385; Min.u64 = 4; Max.u64 = 4480; - l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 230109; SumSQ.u64 = 259805727; Count.u64 = 969; Min.u64 = 16; Max.u64 = 4797; - l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 53623; SumSQ.u64 = 110973049; Count.u64 = 177; Min.u64 = 2; Max.u64 = 5291; - l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 176880; SumSQ.u64 = 256704406; Count.u64 = 588; Min.u64 = 16; Max.u64 = 5848; - l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 71010; SumSQ.u64 = 140332010; Count.u64 = 175; Min.u64 = 68; Max.u64 = 6396; - l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 5344; SumSQ.u64 = 18010638; Count.u64 = 8; Min.u64 = 4; Max.u64 = 4177; - l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 10001; SumSQ.u64 = 8587895; Count.u64 = 35; Min.u64 = 80; Max.u64 = 2256; - l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 2123; SumSQ.u64 = 610083; Count.u64 = 12; Min.u64 = 68; Max.u64 = 611; - l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 74293; SumSQ.u64 = 83754429; Count.u64 = 250; Min.u64 = 67; Max.u64 = 3510; + l1cache1.evict_I : Accumulator : Sum.u64 = 830; SumSQ.u64 = 830; Count.u64 = 830; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SB : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 98940; SumSQ.u64 = 157571420; Count.u64 = 422; Min.u64 = 4; Max.u64 = 3217; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 242192; SumSQ.u64 = 278539468; Count.u64 = 983; Min.u64 = 16; Max.u64 = 4376; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 41597; SumSQ.u64 = 52175525; Count.u64 = 158; Min.u64 = 2; Max.u64 = 3407; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 164094; SumSQ.u64 = 162850608; Count.u64 = 601; Min.u64 = 16; Max.u64 = 5033; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 58767; SumSQ.u64 = 98023093; Count.u64 = 155; Min.u64 = 51; Max.u64 = 4312; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 1240; SumSQ.u64 = 640670; Count.u64 = 6; Min.u64 = 4; Max.u64 = 690; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 8010; SumSQ.u64 = 7581474; Count.u64 = 28; Min.u64 = 75; Max.u64 = 2256; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1844; SumSQ.u64 = 493178; Count.u64 = 10; Min.u64 = 70; Max.u64 = 419; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 74791; SumSQ.u64 = 66483349; Count.u64 = 241; Min.u64 = 66; Max.u64 = 3371; l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 94615; SumSQ.u64 = 110087005; Count.u64 = 235; Min.u64 = 68; Max.u64 = 3916; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 91764; SumSQ.u64 = 127103676; Count.u64 = 239; Min.u64 = 68; Max.u64 = 5416; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 850; SumSQ.u64 = 850; Count.u64 = 850; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 657; SumSQ.u64 = 657; Count.u64 = 657; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 637; SumSQ.u64 = 637; Count.u64 = 637; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache1.CacheHits : Accumulator : Sum.u64 = 570; SumSQ.u64 = 570; Count.u64 = 570; Min.u64 = 1; Max.u64 = 1; - l1cache1.CacheMisses : Accumulator : Sum.u64 = 1779; SumSQ.u64 = 1779; Count.u64 = 1779; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 586; SumSQ.u64 = 586; Count.u64 = 586; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 1777; SumSQ.u64 = 1777; Count.u64 = 1777; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 10805; SumSQ.u64 = 10805; Count.u64 = 10805; Min.u64 = 1; Max.u64 = 1; - l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 675; SumSQ.u64 = 675; Count.u64 = 675; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 10770; SumSQ.u64 = 10770; Count.u64 = 10770; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 780; SumSQ.u64 = 780; Count.u64 = 780; Min.u64 = 1; Max.u64 = 1; l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetS_recv : Accumulator : Sum.u64 = 1354; SumSQ.u64 = 1354; Count.u64 = 1354; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1405; SumSQ.u64 = 1405; Count.u64 = 1405; Min.u64 = 1; Max.u64 = 1; l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSX_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; - l1cache1.Write_recv : Accumulator : Sum.u64 = 940; SumSQ.u64 = 940; Count.u64 = 940; Min.u64 = 1; Max.u64 = 1; - l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; - l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; - l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; - l1cache1.Inv_recv : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 914; SumSQ.u64 = 914; Count.u64 = 914; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; - l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; - l1cache1.NACK_recv : Accumulator : Sum.u64 = 3753; SumSQ.u64 = 3753; Count.u64 = 3753; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 3750; SumSQ.u64 = 3750; Count.u64 = 3750; Min.u64 = 1; Max.u64 = 1; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 784591; SumSQ.u64 = 11902231; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 772205; SumSQ.u64 = 11684637; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 6975; SumSQ.u64 = 11835; Count.u64 = 5601; Min.u64 = 0; Max.u64 = 7; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 865664; SumSQ.u64 = 347543552; Count.u64 = 5577; Min.u64 = 64; Max.u64 = 576; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 10747967; SumSQ.u64 = 88399193279; Count.u64 = 4597; Min.u64 = 1; Max.u64 = 183531; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 6923; SumSQ.u64 = 11563; Count.u64 = 5559; Min.u64 = 0; Max.u64 = 7; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 870784; SumSQ.u64 = 352006144; Count.u64 = 5544; Min.u64 = 64; Max.u64 = 576; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 10502783; SumSQ.u64 = 84262970195; Count.u64 = 4532; Min.u64 = 1; Max.u64 = 133308; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.evict_I : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_I : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -653,48 +681,48 @@ l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 571; SumSQ.u64 = 571; Count.u64 = 571; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 629; SumSQ.u64 = 629; Count.u64 = 629; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 914; SumSQ.u64 = 914; Count.u64 = 914; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 827; SumSQ.u64 = 827; Count.u64 = 827; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 1118; SumSQ.u64 = 1118; Count.u64 = 1118; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 796; SumSQ.u64 = 796; Count.u64 = 796; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -706,14 +734,14 @@ l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -727,186 +755,198 @@ l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 841; SumSQ.u64 = 841; Count.u64 = 841; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1392; SumSQ.u64 = 1392; Count.u64 = 1392; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 1213; SumSQ.u64 = 1213; Count.u64 = 1213; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_Write : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 840; SumSQ.u64 = 840; Count.u64 = 840; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1367; SumSQ.u64 = 1367; Count.u64 = 1367; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 1225; SumSQ.u64 = 1225; Count.u64 = 1225; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 1072; SumSQ.u64 = 1072; Count.u64 = 1072; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 3906; SumSQ.u64 = 3906; Count.u64 = 3906; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 1095; SumSQ.u64 = 1095; Count.u64 = 1095; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 3879; SumSQ.u64 = 3879; Count.u64 = 3879; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 974; SumSQ.u64 = 974; Count.u64 = 974; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 754; SumSQ.u64 = 9012; Count.u64 = 67; Min.u64 = 10; Max.u64 = 30; - l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 98791; SumSQ.u64 = 22975989; Count.u64 = 902; Min.u64 = 37; Max.u64 = 1478; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 769; SumSQ.u64 = 9265; Count.u64 = 69; Min.u64 = 10; Max.u64 = 34; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 105363; SumSQ.u64 = 32582991; Count.u64 = 914; Min.u64 = 38; Max.u64 = 2805; l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 116; SumSQ.u64 = 1228; Count.u64 = 11; Min.u64 = 10; Max.u64 = 12; - l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 99228; SumSQ.u64 = 59840718; Count.u64 = 571; Min.u64 = 46; Max.u64 = 3245; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 54; SumSQ.u64 = 584; Count.u64 = 5; Min.u64 = 10; Max.u64 = 11; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 95767; SumSQ.u64 = 50288967; Count.u64 = 574; Min.u64 = 62; Max.u64 = 3221; l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 25258; SumSQ.u64 = 16454894; Count.u64 = 181; Min.u64 = 59; Max.u64 = 3387; - l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 11; SumSQ.u64 = 121; Count.u64 = 1; Min.u64 = 11; Max.u64 = 11; - l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 4636; SumSQ.u64 = 909750; Count.u64 = 33; Min.u64 = 68; Max.u64 = 462; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 20966; SumSQ.u64 = 4361266; Count.u64 = 177; Min.u64 = 45; Max.u64 = 1076; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 3585; SumSQ.u64 = 632595; Count.u64 = 28; Min.u64 = 68; Max.u64 = 429; l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 536569; Count.u64 = 13; Min.u64 = 62; Max.u64 = 605; - l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 48207; SumSQ.u64 = 27005547; Count.u64 = 699; Min.u64 = 3; Max.u64 = 2821; - l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 56839; SumSQ.u64 = 29204311; Count.u64 = 641; Min.u64 = 3; Max.u64 = 2786; - l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1158; SumSQ.u64 = 203226; Count.u64 = 10; Min.u64 = 64; Max.u64 = 358; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 44753; SumSQ.u64 = 13618587; Count.u64 = 675; Min.u64 = 3; Max.u64 = 1443; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 54388; SumSQ.u64 = 21879614; Count.u64 = 655; Min.u64 = 3; Max.u64 = 2286; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 914; SumSQ.u64 = 914; Count.u64 = 914; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.CacheHits : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; - l2cache1.CacheMisses : Accumulator : Sum.u64 = 1700; SumSQ.u64 = 1700; Count.u64 = 1700; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheHits : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 1703; SumSQ.u64 = 1703; Count.u64 = 1703; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 13744; SumSQ.u64 = 13744; Count.u64 = 13744; Min.u64 = 1; Max.u64 = 1; - l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1629; SumSQ.u64 = 1629; Count.u64 = 1629; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 13704; SumSQ.u64 = 13704; Count.u64 = 13704; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1612; SumSQ.u64 = 1612; Count.u64 = 1612; Min.u64 = 1; Max.u64 = 1; l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetS_recv : Accumulator : Sum.u64 = 2430; SumSQ.u64 = 2430; Count.u64 = 2430; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetX_recv : Accumulator : Sum.u64 = 2119; SumSQ.u64 = 2119; Count.u64 = 2119; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetSX_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 2473; SumSQ.u64 = 2473; Count.u64 = 2473; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 2087; SumSQ.u64 = 2087; Count.u64 = 2087; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; - l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 675; SumSQ.u64 = 675; Count.u64 = 675; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 655; SumSQ.u64 = 655; Count.u64 = 655; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 827; SumSQ.u64 = 827; Count.u64 = 827; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 876; SumSQ.u64 = 876; Count.u64 = 876; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; - l2cache1.PutS_recv : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; - l2cache1.PutM_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; - l2cache1.PutE_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.Inv_recv : Accumulator : Sum.u64 = 1162; SumSQ.u64 = 1162; Count.u64 = 1162; Min.u64 = 1; Max.u64 = 1; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 1171; SumSQ.u64 = 1171; Count.u64 = 1171; Min.u64 = 1; Max.u64 = 1; l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 411; SumSQ.u64 = 411; Count.u64 = 411; Min.u64 = 1; Max.u64 = 1; - l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; - l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; - l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; - l2cache1.NACK_recv : Accumulator : Sum.u64 = 1167; SumSQ.u64 = 1167; Count.u64 = 1167; Min.u64 = 1; Max.u64 = 1; - l2cache1.AckInv_recv : Accumulator : Sum.u64 = 871; SumSQ.u64 = 871; Count.u64 = 871; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 864; SumSQ.u64 = 864; Count.u64 = 864; Min.u64 = 1; Max.u64 = 1; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 333554; SumSQ.u64 = 2197426; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 8; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 326040; SumSQ.u64 = 2139254; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 8; l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core2.pendCycle : Accumulator : Sum.u64 = 831814; SumSQ.u64 = 13086386; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; - core2.reads : Accumulator : Sum.u64 = 1455; SumSQ.u64 = 1455; Count.u64 = 1455; Min.u64 = 1; Max.u64 = 1; - core2.writes : Accumulator : Sum.u64 = 922; SumSQ.u64 = 922; Count.u64 = 922; Min.u64 = 1; Max.u64 = 1; - core2.readNoncache : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - core2.writeNoncache : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - core2.flushes : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; - core2.flushinvs : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - core2.llsc : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; - core2.llsc_success : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + core2.pendCycle : Accumulator : Sum.u64 = 817711; SumSQ.u64 = 12856763; Count.u64 = 52320; Min.u64 = 0; Max.u64 = 16; + core2.reads : Accumulator : Sum.u64 = 1470; SumSQ.u64 = 1470; Count.u64 = 1470; Min.u64 = 1; Max.u64 = 1; + core2.writes : Accumulator : Sum.u64 = 924; SumSQ.u64 = 924; Count.u64 = 924; Min.u64 = 1; Max.u64 = 1; + core2.readNoncache : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + core2.writeNoncache : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + core2.flushes : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; + core2.flushinvs : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + core2.llsc : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + core2.llsc_success : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 790; SumSQ.u64 = 790; Count.u64 = 790; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 577; SumSQ.u64 = 577; Count.u64 = 577; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 823; SumSQ.u64 = 823; Count.u64 = 823; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -915,14 +955,14 @@ l1cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -931,30 +971,33 @@ l1cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 2372; SumSQ.u64 = 2372; Count.u64 = 2372; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 1924; SumSQ.u64 = 1924; Count.u64 = 1924; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_Write : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 2361; SumSQ.u64 = 2361; Count.u64 = 2361; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 1931; SumSQ.u64 = 1931; Count.u64 = 1931; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Write : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1455; SumSQ.u64 = 1455; Count.u64 = 1455; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1470; SumSQ.u64 = 1470; Count.u64 = 1470; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -962,89 +1005,94 @@ l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.evict_I : Accumulator : Sum.u64 = 768; SumSQ.u64 = 768; Count.u64 = 768; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_S : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_M : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_I : Accumulator : Sum.u64 = 778; SumSQ.u64 = 778; Count.u64 = 778; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_S : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_M : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_IS : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_IM : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_SM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_SB : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 98788; SumSQ.u64 = 188897450; Count.u64 = 411; Min.u64 = 4; Max.u64 = 4418; - l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 226924; SumSQ.u64 = 314428242; Count.u64 = 945; Min.u64 = 16; Max.u64 = 5330; - l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 63853; SumSQ.u64 = 136462085; Count.u64 = 164; Min.u64 = 2; Max.u64 = 5208; - l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 150754; SumSQ.u64 = 175607434; Count.u64 = 596; Min.u64 = 17; Max.u64 = 4296; - l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 60912; SumSQ.u64 = 100877206; Count.u64 = 169; Min.u64 = 66; Max.u64 = 5216; - l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 1639; SumSQ.u64 = 1455421; Count.u64 = 9; Min.u64 = 4; Max.u64 = 1162; - l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 19830; SumSQ.u64 = 35226856; Count.u64 = 50; Min.u64 = 17; Max.u64 = 3453; - l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 4391; SumSQ.u64 = 11695203; Count.u64 = 9; Min.u64 = 69; Max.u64 = 3398; - l1cache2.latency_FlushLine : Accumulator : Sum.u64 = 94303; SumSQ.u64 = 117511615; Count.u64 = 253; Min.u64 = 67; Max.u64 = 3668; + l1cache2.evict_IM : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SM : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SB : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 115254; SumSQ.u64 = 261723902; Count.u64 = 434; Min.u64 = 4; Max.u64 = 6525; + l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 233779; SumSQ.u64 = 357783631; Count.u64 = 928; Min.u64 = 16; Max.u64 = 6428; + l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 50247; SumSQ.u64 = 96147791; Count.u64 = 161; Min.u64 = 2; Max.u64 = 5208; + l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 158760; SumSQ.u64 = 218232246; Count.u64 = 577; Min.u64 = 17; Max.u64 = 7004; + l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 56591; SumSQ.u64 = 96706745; Count.u64 = 183; Min.u64 = 63; Max.u64 = 5216; + l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 562700; Count.u64 = 10; Min.u64 = 4; Max.u64 = 637; + l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 10274; SumSQ.u64 = 7524522; Count.u64 = 44; Min.u64 = 17; Max.u64 = 2217; + l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 2183; SumSQ.u64 = 487661; Count.u64 = 12; Min.u64 = 79; Max.u64 = 384; + l1cache2.latency_FlushLine : Accumulator : Sum.u64 = 82134; SumSQ.u64 = 120825092; Count.u64 = 252; Min.u64 = 67; Max.u64 = 5505; l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 88458; SumSQ.u64 = 123990110; Count.u64 = 234; Min.u64 = 65; Max.u64 = 4635; + l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 83461; SumSQ.u64 = 110979307; Count.u64 = 222; Min.u64 = 66; Max.u64 = 5377; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache2.CacheHits : Accumulator : Sum.u64 = 584; SumSQ.u64 = 584; Count.u64 = 584; Min.u64 = 1; Max.u64 = 1; - l1cache2.CacheMisses : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 817; SumSQ.u64 = 817; Count.u64 = 817; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 667; SumSQ.u64 = 667; Count.u64 = 667; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheHits : Accumulator : Sum.u64 = 605; SumSQ.u64 = 605; Count.u64 = 605; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheMisses : Accumulator : Sum.u64 = 1744; SumSQ.u64 = 1744; Count.u64 = 1744; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 10393; SumSQ.u64 = 10393; Count.u64 = 10393; Min.u64 = 1; Max.u64 = 1; - l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 10345; SumSQ.u64 = 10345; Count.u64 = 10345; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; l1cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - l1cache2.Write_uncache_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_uncache_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - l1cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetS_recv : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1356; Count.u64 = 1356; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetS_recv : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; l1cache2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSX_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; - l1cache2.Write_recv : Accumulator : Sum.u64 = 929; SumSQ.u64 = 929; Count.u64 = 929; Min.u64 = 1; Max.u64 = 1; - l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; - l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 234; SumSQ.u64 = 234; Count.u64 = 234; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; - l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; - l1cache2.Inv_recv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSX_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_recv : Accumulator : Sum.u64 = 921; SumSQ.u64 = 921; Count.u64 = 921; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 823; SumSQ.u64 = 823; Count.u64 = 823; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 921; SumSQ.u64 = 921; Count.u64 = 921; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Inv_recv : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; - l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 411; SumSQ.u64 = 411; Count.u64 = 411; Min.u64 = 1; Max.u64 = 1; - l1cache2.NACK_recv : Accumulator : Sum.u64 = 3397; SumSQ.u64 = 3397; Count.u64 = 3397; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.NACK_recv : Accumulator : Sum.u64 = 3358; SumSQ.u64 = 3358; Count.u64 = 3358; Min.u64 = 1; Max.u64 = 1; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 798860; SumSQ.u64 = 12107096; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; + l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 783122; SumSQ.u64 = 11831950; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 6702; SumSQ.u64 = 11186; Count.u64 = 5458; Min.u64 = 0; Max.u64 = 6; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 862112; SumSQ.u64 = 350274560; Count.u64 = 5440; Min.u64 = 64; Max.u64 = 576; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 10187176; SumSQ.u64 = 48729088562; Count.u64 = 4439; Min.u64 = 1; Max.u64 = 35869; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 6688; SumSQ.u64 = 11104; Count.u64 = 5404; Min.u64 = 0; Max.u64 = 6; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 854240; SumSQ.u64 = 346846208; Count.u64 = 5393; Min.u64 = 64; Max.u64 = 576; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 10533526; SumSQ.u64 = 54127332214; Count.u64 = 4404; Min.u64 = 1; Max.u64 = 49491; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.evict_I : Accumulator : Sum.u64 = 296; SumSQ.u64 = 296; Count.u64 = 296; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_I : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1057,48 +1105,48 @@ l2cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 566; SumSQ.u64 = 566; Count.u64 = 566; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 806; SumSQ.u64 = 806; Count.u64 = 806; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 640; SumSQ.u64 = 640; Count.u64 = 640; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 610; SumSQ.u64 = 610; Count.u64 = 610; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 1061; SumSQ.u64 = 1061; Count.u64 = 1061; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 820; SumSQ.u64 = 820; Count.u64 = 820; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 842; SumSQ.u64 = 842; Count.u64 = 842; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1110,15 +1158,15 @@ l2cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1131,187 +1179,199 @@ l2cache2.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 805; SumSQ.u64 = 805; Count.u64 = 805; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 395; SumSQ.u64 = 395; Count.u64 = 395; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 806; SumSQ.u64 = 806; Count.u64 = 806; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 1357; SumSQ.u64 = 1357; Count.u64 = 1357; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 1186; SumSQ.u64 = 1186; Count.u64 = 1186; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetSX : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_Write : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 1143; SumSQ.u64 = 1143; Count.u64 = 1143; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSX : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Write : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 3527; SumSQ.u64 = 3527; Count.u64 = 3527; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 491; SumSQ.u64 = 491; Count.u64 = 491; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 1022; SumSQ.u64 = 1022; Count.u64 = 1022; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 3458; SumSQ.u64 = 3458; Count.u64 = 3458; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 931; SumSQ.u64 = 931; Count.u64 = 931; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 921; SumSQ.u64 = 921; Count.u64 = 921; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 411; SumSQ.u64 = 411; Count.u64 = 411; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 786; SumSQ.u64 = 9066; Count.u64 = 70; Min.u64 = 10; Max.u64 = 19; - l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 108380; SumSQ.u64 = 41294340; Count.u64 = 875; Min.u64 = 36; Max.u64 = 2183; + l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 685; SumSQ.u64 = 7509; Count.u64 = 63; Min.u64 = 10; Max.u64 = 15; + l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 107735; SumSQ.u64 = 61412827; Count.u64 = 865; Min.u64 = 37; Max.u64 = 5336; l2cache2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 56; SumSQ.u64 = 628; Count.u64 = 5; Min.u64 = 11; Max.u64 = 12; - l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 84263; SumSQ.u64 = 40136739; Count.u64 = 566; Min.u64 = 62; Max.u64 = 3309; + l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 91; SumSQ.u64 = 1037; Count.u64 = 8; Min.u64 = 11; Max.u64 = 12; + l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 90825; SumSQ.u64 = 64305737; Count.u64 = 550; Min.u64 = 65; Max.u64 = 3309; l2cache2.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 27712; SumSQ.u64 = 11531854; Count.u64 = 194; Min.u64 = 60; Max.u64 = 2145; - l2cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 11; SumSQ.u64 = 121; Count.u64 = 1; Min.u64 = 11; Max.u64 = 11; - l2cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 10684; SumSQ.u64 = 15731136; Count.u64 = 46; Min.u64 = 67; Max.u64 = 3431; + l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 23555; SumSQ.u64 = 8083157; Count.u64 = 202; Min.u64 = 56; Max.u64 = 2237; + l2cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 22; SumSQ.u64 = 242; Count.u64 = 2; Min.u64 = 11; Max.u64 = 11; + l2cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 5836; SumSQ.u64 = 1091348; Count.u64 = 42; Min.u64 = 67; Max.u64 = 415; l2cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 5059; SumSQ.u64 = 11878393; Count.u64 = 12; Min.u64 = 63; Max.u64 = 3367; - l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 49594; SumSQ.u64 = 19084400; Count.u64 = 679; Min.u64 = 3; Max.u64 = 2520; - l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 49608; SumSQ.u64 = 19635802; Count.u64 = 632; Min.u64 = 3; Max.u64 = 2515; - l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 220307; Count.u64 = 12; Min.u64 = 62; Max.u64 = 219; + l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 44633; SumSQ.u64 = 14794565; Count.u64 = 630; Min.u64 = 3; Max.u64 = 2520; + l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 48848; SumSQ.u64 = 18449056; Count.u64 = 645; Min.u64 = 3; Max.u64 = 1734; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.CacheHits : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; - l2cache2.CacheMisses : Accumulator : Sum.u64 = 1693; SumSQ.u64 = 1693; Count.u64 = 1693; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheHits : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheMisses : Accumulator : Sum.u64 = 1671; SumSQ.u64 = 1671; Count.u64 = 1671; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 13203; SumSQ.u64 = 13203; Count.u64 = 13203; Min.u64 = 1; Max.u64 = 1; - l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1589; SumSQ.u64 = 1589; Count.u64 = 1589; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 13092; SumSQ.u64 = 13092; Count.u64 = 13092; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; l2cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - l2cache2.Write_uncache_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l2cache2.Write_uncache_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - l2cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l2cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l2cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetS_recv : Accumulator : Sum.u64 = 2273; SumSQ.u64 = 2273; Count.u64 = 2273; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetX_recv : Accumulator : Sum.u64 = 1924; SumSQ.u64 = 1924; Count.u64 = 1924; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetSX_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetS_recv : Accumulator : Sum.u64 = 2253; SumSQ.u64 = 2253; Count.u64 = 2253; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetX_recv : Accumulator : Sum.u64 = 1931; SumSQ.u64 = 1931; Count.u64 = 1931; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSX_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; - l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 806; SumSQ.u64 = 806; Count.u64 = 806; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 899; SumSQ.u64 = 899; Count.u64 = 899; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; - l2cache2.PutS_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; - l2cache2.PutM_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; - l2cache2.PutE_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.PutS_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutM_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutE_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.Inv_recv : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; + l2cache2.Inv_recv : Accumulator : Sum.u64 = 1076; SumSQ.u64 = 1076; Count.u64 = 1076; Min.u64 = 1; Max.u64 = 1; l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 399; SumSQ.u64 = 399; Count.u64 = 399; Min.u64 = 1; Max.u64 = 1; - l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; - l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; - l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; - l2cache2.NACK_recv : Accumulator : Sum.u64 = 1120; SumSQ.u64 = 1120; Count.u64 = 1120; Min.u64 = 1; Max.u64 = 1; - l2cache2.AckInv_recv : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.NACK_recv : Accumulator : Sum.u64 = 1098; SumSQ.u64 = 1098; Count.u64 = 1098; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckInv_recv : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 334976; SumSQ.u64 = 2184266; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 8; + l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 320894; SumSQ.u64 = 2051846; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 8; l2cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core3.pendCycle : Accumulator : Sum.u64 = 815723; SumSQ.u64 = 12819401; Count.u64 = 52261; Min.u64 = 0; Max.u64 = 16; - core3.reads : Accumulator : Sum.u64 = 1506; SumSQ.u64 = 1506; Count.u64 = 1506; Min.u64 = 1; Max.u64 = 1; - core3.writes : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; - core3.readNoncache : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - core3.writeNoncache : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - core3.flushes : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; - core3.flushinvs : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; - core3.llsc : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; - core3.llsc_success : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + core3.pendCycle : Accumulator : Sum.u64 = 809251; SumSQ.u64 = 12689521; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; + core3.reads : Accumulator : Sum.u64 = 1503; SumSQ.u64 = 1503; Count.u64 = 1503; Min.u64 = 1; Max.u64 = 1; + core3.writes : Accumulator : Sum.u64 = 914; SumSQ.u64 = 914; Count.u64 = 914; Min.u64 = 1; Max.u64 = 1; + core3.readNoncache : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + core3.writeNoncache : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + core3.flushes : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; + core3.flushinvs : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + core3.llsc : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + core3.llsc_success : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 602; SumSQ.u64 = 602; Count.u64 = 602; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 590; SumSQ.u64 = 590; Count.u64 = 590; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 873; SumSQ.u64 = 873; Count.u64 = 873; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1319,13 +1379,13 @@ l1cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 296; SumSQ.u64 = 296; Count.u64 = 296; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1335,30 +1395,33 @@ l1cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 2344; SumSQ.u64 = 2344; Count.u64 = 2344; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_Write : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 2439; SumSQ.u64 = 2439; Count.u64 = 2439; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 2026; SumSQ.u64 = 2026; Count.u64 = 2026; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Write : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1506; SumSQ.u64 = 1506; Count.u64 = 1506; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1503; SumSQ.u64 = 1503; Count.u64 = 1503; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 970; SumSQ.u64 = 970; Count.u64 = 970; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1366,89 +1429,94 @@ l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.evict_I : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_S : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_M : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_IS : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_IM : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_I : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_S : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_M : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IS : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IM : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_SB : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 94786; SumSQ.u64 = 190536382; Count.u64 = 424; Min.u64 = 4; Max.u64 = 5595; - l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 225537; SumSQ.u64 = 305402585; Count.u64 = 990; Min.u64 = 16; Max.u64 = 6828; - l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 51931; SumSQ.u64 = 108369215; Count.u64 = 135; Min.u64 = 2; Max.u64 = 4239; - l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 166015; SumSQ.u64 = 222780895; Count.u64 = 602; Min.u64 = 17; Max.u64 = 6255; - l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 50620; SumSQ.u64 = 69703114; Count.u64 = 173; Min.u64 = 64; Max.u64 = 4926; - l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 133; SumSQ.u64 = 9021; Count.u64 = 6; Min.u64 = 4; Max.u64 = 91; - l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 8316; SumSQ.u64 = 7559510; Count.u64 = 38; Min.u64 = 18; Max.u64 = 2496; - l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 8515; SumSQ.u64 = 23925361; Count.u64 = 7; Min.u64 = 127; Max.u64 = 4244; - l1cache3.latency_FlushLine : Accumulator : Sum.u64 = 88514; SumSQ.u64 = 177990804; Count.u64 = 228; Min.u64 = 67; Max.u64 = 7406; + l1cache3.evict_SB : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 85264; SumSQ.u64 = 182493398; Count.u64 = 426; Min.u64 = 4; Max.u64 = 5452; + l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 226477; SumSQ.u64 = 266995713; Count.u64 = 968; Min.u64 = 16; Max.u64 = 5464; + l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 47661; SumSQ.u64 = 74553563; Count.u64 = 148; Min.u64 = 2; Max.u64 = 3143; + l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 149958; SumSQ.u64 = 165431972; Count.u64 = 590; Min.u64 = 16; Max.u64 = 4306; + l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 55790; SumSQ.u64 = 90787834; Count.u64 = 159; Min.u64 = 65; Max.u64 = 4648; + l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 4428; SumSQ.u64 = 10413902; Count.u64 = 8; Min.u64 = 4; Max.u64 = 3127; + l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 8030; SumSQ.u64 = 7845296; Count.u64 = 33; Min.u64 = 70; Max.u64 = 2496; + l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 5367; SumSQ.u64 = 7540223; Count.u64 = 15; Min.u64 = 74; Max.u64 = 2538; + l1cache3.latency_FlushLine : Accumulator : Sum.u64 = 88382; SumSQ.u64 = 166449822; Count.u64 = 227; Min.u64 = 68; Max.u64 = 6396; l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 100845; SumSQ.u64 = 142554843; Count.u64 = 247; Min.u64 = 69; Max.u64 = 4420; + l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 114294; SumSQ.u64 = 206822808; Count.u64 = 244; Min.u64 = 70; Max.u64 = 4846; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache3.CacheHits : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; - l1cache3.CacheMisses : Accumulator : Sum.u64 = 1810; SumSQ.u64 = 1810; Count.u64 = 1810; Min.u64 = 1; Max.u64 = 1; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 856; SumSQ.u64 = 856; Count.u64 = 856; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 657; SumSQ.u64 = 657; Count.u64 = 657; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheHits : Accumulator : Sum.u64 = 582; SumSQ.u64 = 582; Count.u64 = 582; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheMisses : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 10196; SumSQ.u64 = 10196; Count.u64 = 10196; Min.u64 = 1; Max.u64 = 1; - l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 10645; SumSQ.u64 = 10645; Count.u64 = 10645; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 661; SumSQ.u64 = 661; Count.u64 = 661; Min.u64 = 1; Max.u64 = 1; l1cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l1cache3.Write_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_uncache_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l1cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetS_recv : Accumulator : Sum.u64 = 1414; SumSQ.u64 = 1414; Count.u64 = 1414; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetS_recv : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; l1cache3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSX_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; - l1cache3.Write_recv : Accumulator : Sum.u64 = 910; SumSQ.u64 = 910; Count.u64 = 910; Min.u64 = 1; Max.u64 = 1; - l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; - l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; - l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; - l1cache3.Inv_recv : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSX_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_recv : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 873; SumSQ.u64 = 873; Count.u64 = 873; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 892; SumSQ.u64 = 892; Count.u64 = 892; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Inv_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; - l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; - l1cache3.NACK_recv : Accumulator : Sum.u64 = 3121; SumSQ.u64 = 3121; Count.u64 = 3121; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.NACK_recv : Accumulator : Sum.u64 = 3617; SumSQ.u64 = 3617; Count.u64 = 3617; Min.u64 = 1; Max.u64 = 1; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 784135; SumSQ.u64 = 11882219; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; + l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 774711; SumSQ.u64 = 11665759; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 7124; SumSQ.u64 = 12208; Count.u64 = 5642; Min.u64 = 0; Max.u64 = 6; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 890816; SumSQ.u64 = 361834496; Count.u64 = 5626; Min.u64 = 64; Max.u64 = 576; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 10692197; SumSQ.u64 = 94323460331; Count.u64 = 4530; Min.u64 = 1; Max.u64 = 185616; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 6922; SumSQ.u64 = 11666; Count.u64 = 5545; Min.u64 = 0; Max.u64 = 6; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 862880; SumSQ.u64 = 347116544; Count.u64 = 5534; Min.u64 = 64; Max.u64 = 576; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 10400060; SumSQ.u64 = 73101832810; Count.u64 = 4452; Min.u64 = 1; Max.u64 = 103408; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.evict_I : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_I : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1461,47 +1529,47 @@ l2cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 567; SumSQ.u64 = 567; Count.u64 = 567; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 631; SumSQ.u64 = 631; Count.u64 = 631; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 617; SumSQ.u64 = 617; Count.u64 = 617; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 1128; SumSQ.u64 = 1128; Count.u64 = 1128; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 1123; SumSQ.u64 = 1123; Count.u64 = 1123; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 847; SumSQ.u64 = 847; Count.u64 = 847; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1514,7 +1582,7 @@ l2cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1522,7 +1590,7 @@ l2cache3.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1535,187 +1603,199 @@ l2cache3.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 296; SumSQ.u64 = 296; Count.u64 = 296; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 289; SumSQ.u64 = 289; Count.u64 = 289; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 1404; SumSQ.u64 = 1404; Count.u64 = 1404; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 1174; SumSQ.u64 = 1174; Count.u64 = 1174; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetSX : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_Write : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 1380; SumSQ.u64 = 1380; Count.u64 = 1380; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 1172; SumSQ.u64 = 1172; Count.u64 = 1172; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSX : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Write : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 1093; SumSQ.u64 = 1093; Count.u64 = 1093; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 3250; SumSQ.u64 = 3250; Count.u64 = 3250; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 994; SumSQ.u64 = 994; Count.u64 = 994; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 1072; SumSQ.u64 = 1072; Count.u64 = 1072; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 3775; SumSQ.u64 = 3775; Count.u64 = 3775; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 892; SumSQ.u64 = 892; Count.u64 = 892; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 784; SumSQ.u64 = 8490; Count.u64 = 73; Min.u64 = 10; Max.u64 = 15; - l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 98735; SumSQ.u64 = 33720443; Count.u64 = 917; Min.u64 = 36; Max.u64 = 4273; + l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 774; SumSQ.u64 = 8376; Count.u64 = 72; Min.u64 = 10; Max.u64 = 14; + l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 101441; SumSQ.u64 = 24664915; Count.u64 = 896; Min.u64 = 37; Max.u64 = 2222; l2cache3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 45; SumSQ.u64 = 509; Count.u64 = 4; Min.u64 = 10; Max.u64 = 12; - l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 83122; SumSQ.u64 = 32964628; Count.u64 = 567; Min.u64 = 41; Max.u64 = 2305; + l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 67; SumSQ.u64 = 751; Count.u64 = 6; Min.u64 = 10; Max.u64 = 12; + l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 78354; SumSQ.u64 = 24316528; Count.u64 = 564; Min.u64 = 41; Max.u64 = 2305; l2cache3.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 29270; SumSQ.u64 = 12797100; Count.u64 = 204; Min.u64 = 58; Max.u64 = 2300; - l2cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; - l2cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 4533; SumSQ.u64 = 690377; Count.u64 = 39; Min.u64 = 52; Max.u64 = 342; + l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 23721; SumSQ.u64 = 6462881; Count.u64 = 179; Min.u64 = 59; Max.u64 = 1186; + l2cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 3947; SumSQ.u64 = 595327; Count.u64 = 33; Min.u64 = 64; Max.u64 = 342; l2cache3.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1265; SumSQ.u64 = 352247; Count.u64 = 5; Min.u64 = 116; Max.u64 = 355; - l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 46252; SumSQ.u64 = 30333598; Count.u64 = 620; Min.u64 = 3; Max.u64 = 3225; - l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 57345; SumSQ.u64 = 31835565; Count.u64 = 643; Min.u64 = 3; Max.u64 = 3846; - l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1664; SumSQ.u64 = 258750; Count.u64 = 15; Min.u64 = 58; Max.u64 = 355; + l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 51403; SumSQ.u64 = 50240319; Count.u64 = 630; Min.u64 = 3; Max.u64 = 5341; + l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 63435; SumSQ.u64 = 54085459; Count.u64 = 756; Min.u64 = 3; Max.u64 = 3905; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.CacheHits : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; - l2cache3.CacheMisses : Accumulator : Sum.u64 = 1732; SumSQ.u64 = 1732; Count.u64 = 1732; Min.u64 = 1; Max.u64 = 1; + l2cache3.CacheMisses : Accumulator : Sum.u64 = 1687; SumSQ.u64 = 1687; Count.u64 = 1687; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutE_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 13207; SumSQ.u64 = 13207; Count.u64 = 13207; Min.u64 = 1; Max.u64 = 1; - l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1644; SumSQ.u64 = 1644; Count.u64 = 1644; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 13536; SumSQ.u64 = 13536; Count.u64 = 13536; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1617; SumSQ.u64 = 1617; Count.u64 = 1617; Min.u64 = 1; Max.u64 = 1; l2cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l2cache3.Write_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache3.Write_uncache_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l2cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetS_recv : Accumulator : Sum.u64 = 2252; SumSQ.u64 = 2252; Count.u64 = 2252; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetX_recv : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetSX_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetS_recv : Accumulator : Sum.u64 = 2330; SumSQ.u64 = 2330; Count.u64 = 2330; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetX_recv : Accumulator : Sum.u64 = 2026; SumSQ.u64 = 2026; Count.u64 = 2026; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; - l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; - l2cache3.PutS_recv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; - l2cache3.PutM_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l2cache3.PutE_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.PutS_recv : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutM_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutE_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.Inv_recv : Accumulator : Sum.u64 = 1165; SumSQ.u64 = 1165; Count.u64 = 1165; Min.u64 = 1; Max.u64 = 1; + l2cache3.Inv_recv : Accumulator : Sum.u64 = 1158; SumSQ.u64 = 1158; Count.u64 = 1158; Min.u64 = 1; Max.u64 = 1; l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; - l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 523; SumSQ.u64 = 523; Count.u64 = 523; Min.u64 = 1; Max.u64 = 1; - l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; - l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; - l2cache3.NACK_recv : Accumulator : Sum.u64 = 1200; SumSQ.u64 = 1200; Count.u64 = 1200; Min.u64 = 1; Max.u64 = 1; - l2cache3.AckInv_recv : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 395; SumSQ.u64 = 395; Count.u64 = 395; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 520; SumSQ.u64 = 520; Count.u64 = 520; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.NACK_recv : Accumulator : Sum.u64 = 1132; SumSQ.u64 = 1132; Count.u64 = 1132; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckInv_recv : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 323425; SumSQ.u64 = 2088091; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 8; + l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 325374; SumSQ.u64 = 2135050; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 8; l2cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core4.pendCycle : Accumulator : Sum.u64 = 831459; SumSQ.u64 = 13090675; Count.u64 = 52992; Min.u64 = 0; Max.u64 = 16; - core4.reads : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; - core4.writes : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; - core4.readNoncache : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - core4.writeNoncache : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - core4.flushes : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; - core4.flushinvs : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + core4.pendCycle : Accumulator : Sum.u64 = 788184; SumSQ.u64 = 12379452; Count.u64 = 50614; Min.u64 = 0; Max.u64 = 16; + core4.reads : Accumulator : Sum.u64 = 1492; SumSQ.u64 = 1492; Count.u64 = 1492; Min.u64 = 1; Max.u64 = 1; + core4.writes : Accumulator : Sum.u64 = 901; SumSQ.u64 = 901; Count.u64 = 901; Min.u64 = 1; Max.u64 = 1; + core4.readNoncache : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + core4.writeNoncache : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + core4.flushes : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + core4.flushinvs : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; core4.llsc : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; core4.llsc_success : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 615; SumSQ.u64 = 615; Count.u64 = 615; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 932; SumSQ.u64 = 932; Count.u64 = 932; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 860; SumSQ.u64 = 860; Count.u64 = 860; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 684; SumSQ.u64 = 684; Count.u64 = 684; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 664; SumSQ.u64 = 664; Count.u64 = 664; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 806; SumSQ.u64 = 806; Count.u64 = 806; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_Inv_SB : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_Inv_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1725,11 +1805,11 @@ l1cache4.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1739,30 +1819,33 @@ l1cache4.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_GetS : Accumulator : Sum.u64 = 2602; SumSQ.u64 = 2602; Count.u64 = 2602; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_GetX : Accumulator : Sum.u64 = 1989; SumSQ.u64 = 1989; Count.u64 = 1989; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_GetSX : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_Write : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_PutM : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_GetS : Accumulator : Sum.u64 = 2544; SumSQ.u64 = 2544; Count.u64 = 2544; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_GetX : Accumulator : Sum.u64 = 2111; SumSQ.u64 = 2111; Count.u64 = 2111; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_GetSX : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_Write : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_PutM : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 660; SumSQ.u64 = 660; Count.u64 = 660; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 845; SumSQ.u64 = 845; Count.u64 = 845; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 1492; SumSQ.u64 = 1492; Count.u64 = 1492; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 962; SumSQ.u64 = 962; Count.u64 = 962; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1770,89 +1853,94 @@ l1cache4.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.evict_I : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_S : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_M : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_I : Accumulator : Sum.u64 = 811; SumSQ.u64 = 811; Count.u64 = 811; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_S : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_M : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l1cache4.evict_IS : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_IM : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_SM : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_SB : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l1cache4.latency_GetS_hit : Accumulator : Sum.u64 = 99434; SumSQ.u64 = 218109990; Count.u64 = 439; Min.u64 = 4; Max.u64 = 5973; - l1cache4.latency_GetS_miss : Accumulator : Sum.u64 = 242927; SumSQ.u64 = 316858521; Count.u64 = 959; Min.u64 = 16; Max.u64 = 6050; - l1cache4.latency_GetX_hit : Accumulator : Sum.u64 = 47614; SumSQ.u64 = 67006560; Count.u64 = 162; Min.u64 = 2; Max.u64 = 3852; - l1cache4.latency_GetX_miss : Accumulator : Sum.u64 = 186274; SumSQ.u64 = 262477024; Count.u64 = 615; Min.u64 = 16; Max.u64 = 6415; - l1cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 56175; SumSQ.u64 = 103561461; Count.u64 = 165; Min.u64 = 63; Max.u64 = 5368; - l1cache4.latency_GetSX_hit : Accumulator : Sum.u64 = 4159; SumSQ.u64 = 8134849; Count.u64 = 8; Min.u64 = 4; Max.u64 = 2678; - l1cache4.latency_GetSX_miss : Accumulator : Sum.u64 = 8157; SumSQ.u64 = 4089843; Count.u64 = 39; Min.u64 = 16; Max.u64 = 1384; - l1cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1884; SumSQ.u64 = 282898; Count.u64 = 14; Min.u64 = 82; Max.u64 = 238; - l1cache4.latency_FlushLine : Accumulator : Sum.u64 = 83929; SumSQ.u64 = 134482151; Count.u64 = 226; Min.u64 = 67; Max.u64 = 4436; + l1cache4.evict_IM : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_SB : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache4.latency_GetS_hit : Accumulator : Sum.u64 = 82204; SumSQ.u64 = 142318942; Count.u64 = 462; Min.u64 = 4; Max.u64 = 4994; + l1cache4.latency_GetS_miss : Accumulator : Sum.u64 = 228722; SumSQ.u64 = 313336316; Count.u64 = 932; Min.u64 = 16; Max.u64 = 5343; + l1cache4.latency_GetX_hit : Accumulator : Sum.u64 = 38049; SumSQ.u64 = 53547835; Count.u64 = 154; Min.u64 = 2; Max.u64 = 3360; + l1cache4.latency_GetX_miss : Accumulator : Sum.u64 = 182466; SumSQ.u64 = 260836242; Count.u64 = 592; Min.u64 = 16; Max.u64 = 5485; + l1cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 45993; SumSQ.u64 = 46578499; Count.u64 = 165; Min.u64 = 68; Max.u64 = 3342; + l1cache4.latency_GetSX_hit : Accumulator : Sum.u64 = 2751; SumSQ.u64 = 3792929; Count.u64 = 6; Min.u64 = 4; Max.u64 = 1795; + l1cache4.latency_GetSX_miss : Accumulator : Sum.u64 = 8030; SumSQ.u64 = 2041374; Count.u64 = 44; Min.u64 = 71; Max.u64 = 511; + l1cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 416249; Count.u64 = 11; Min.u64 = 82; Max.u64 = 458; + l1cache4.latency_FlushLine : Accumulator : Sum.u64 = 91826; SumSQ.u64 = 146980386; Count.u64 = 245; Min.u64 = 65; Max.u64 = 5449; l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 79283; SumSQ.u64 = 109477039; Count.u64 = 222; Min.u64 = 66; Max.u64 = 6552; + l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 85650; SumSQ.u64 = 81865046; Count.u64 = 240; Min.u64 = 69; Max.u64 = 3737; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXHit_Blocked : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXHit_Blocked : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l1cache4.CacheHits : Accumulator : Sum.u64 = 609; SumSQ.u64 = 609; Count.u64 = 609; Min.u64 = 1; Max.u64 = 1; - l1cache4.CacheMisses : Accumulator : Sum.u64 = 1792; SumSQ.u64 = 1792; Count.u64 = 1792; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache4.CacheHits : Accumulator : Sum.u64 = 622; SumSQ.u64 = 622; Count.u64 = 622; Min.u64 = 1; Max.u64 = 1; + l1cache4.CacheMisses : Accumulator : Sum.u64 = 1744; SumSQ.u64 = 1744; Count.u64 = 1744; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_PutS : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_PutE : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetS_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_PutS : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_PutE : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_E : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_GetX_E : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache4.TotalEventsReceived : Accumulator : Sum.u64 = 10622; SumSQ.u64 = 10622; Count.u64 = 10622; Min.u64 = 1; Max.u64 = 1; - l1cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 708; SumSQ.u64 = 708; Count.u64 = 708; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache4.TotalEventsReceived : Accumulator : Sum.u64 = 10757; SumSQ.u64 = 10757; Count.u64 = 10757; Min.u64 = 1; Max.u64 = 1; + l1cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 754; SumSQ.u64 = 754; Count.u64 = 754; Min.u64 = 1; Max.u64 = 1; l1cache4.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetS_uncache_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l1cache4.Write_uncache_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetS_uncache_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache4.Write_uncache_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSResp_uncache_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l1cache4.WriteResp_uncache_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSResp_uncache_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache4.WriteResp_uncache_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l1cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetS_recv : Accumulator : Sum.u64 = 1398; SumSQ.u64 = 1398; Count.u64 = 1398; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetS_recv : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; l1cache4.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSX_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache4.Write_recv : Accumulator : Sum.u64 = 942; SumSQ.u64 = 942; Count.u64 = 942; Min.u64 = 1; Max.u64 = 1; - l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; - l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 860; SumSQ.u64 = 860; Count.u64 = 860; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 932; SumSQ.u64 = 932; Count.u64 = 932; Min.u64 = 1; Max.u64 = 1; - l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; - l1cache4.Inv_recv : Accumulator : Sum.u64 = 847; SumSQ.u64 = 847; Count.u64 = 847; Min.u64 = 1; Max.u64 = 1; + l1cache4.Write_recv : Accumulator : Sum.u64 = 911; SumSQ.u64 = 911; Count.u64 = 911; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.Inv_recv : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; - l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; - l1cache4.NACK_recv : Accumulator : Sum.u64 = 3618; SumSQ.u64 = 3618; Count.u64 = 3618; Min.u64 = 1; Max.u64 = 1; + l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; + l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.NACK_recv : Accumulator : Sum.u64 = 3795; SumSQ.u64 = 3795; Count.u64 = 3795; Min.u64 = 1; Max.u64 = 1; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 798720; SumSQ.u64 = 12121676; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; + l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 756484; SumSQ.u64 = 11437698; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 7069; SumSQ.u64 = 12059; Count.u64 = 5613; Min.u64 = 0; Max.u64 = 6; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 857152; SumSQ.u64 = 341112832; Count.u64 = 5602; Min.u64 = 64; Max.u64 = 576; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 10434278; SumSQ.u64 = 78777840472; Count.u64 = 4506; Min.u64 = 1; Max.u64 = 170370; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 6904; SumSQ.u64 = 11794; Count.u64 = 5525; Min.u64 = 0; Max.u64 = 7; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 881568; SumSQ.u64 = 360336384; Count.u64 = 5509; Min.u64 = 64; Max.u64 = 576; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 10734074; SumSQ.u64 = 244360041668; Count.u64 = 4435; Min.u64 = 1; Max.u64 = 341157; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.evict_I : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l2cache4.evict_I : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1865,47 +1953,47 @@ l2cache4.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 582; SumSQ.u64 = 582; Count.u64 = 582; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 864; SumSQ.u64 = 864; Count.u64 = 864; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 561; SumSQ.u64 = 561; Count.u64 = 561; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutS_S : Accumulator : Sum.u64 = 285; SumSQ.u64 = 285; Count.u64 = 285; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutS_S : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutM_M : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutM_M : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 1117; SumSQ.u64 = 1117; Count.u64 = 1117; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 1114; SumSQ.u64 = 1114; Count.u64 = 1114; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_Inv_SB : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_Inv_SB : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_Inv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 841; SumSQ.u64 = 841; Count.u64 = 841; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 830; SumSQ.u64 = 830; Count.u64 = 830; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1918,15 +2006,15 @@ l2cache4.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 332; SumSQ.u64 = 332; Count.u64 = 332; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1939,75 +2027,82 @@ l2cache4.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 274; SumSQ.u64 = 274; Count.u64 = 274; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 814; SumSQ.u64 = 814; Count.u64 = 814; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 820; SumSQ.u64 = 820; Count.u64 = 820; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetS : Accumulator : Sum.u64 = 1325; SumSQ.u64 = 1325; Count.u64 = 1325; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetX : Accumulator : Sum.u64 = 1338; SumSQ.u64 = 1338; Count.u64 = 1338; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetSX : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_Write : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetS : Accumulator : Sum.u64 = 1276; SumSQ.u64 = 1276; Count.u64 = 1276; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetX : Accumulator : Sum.u64 = 1256; SumSQ.u64 = 1256; Count.u64 = 1256; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetSX : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_Write : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 379; SumSQ.u64 = 379; Count.u64 = 379; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 1080; SumSQ.u64 = 1080; Count.u64 = 1080; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_NACK : Accumulator : Sum.u64 = 3784; SumSQ.u64 = 3784; Count.u64 = 3784; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 949; SumSQ.u64 = 949; Count.u64 = 949; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 932; SumSQ.u64 = 932; Count.u64 = 932; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 352; SumSQ.u64 = 352; Count.u64 = 352; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 1061; SumSQ.u64 = 1061; Count.u64 = 1061; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_NACK : Accumulator : Sum.u64 = 3923; SumSQ.u64 = 3923; Count.u64 = 3923; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_FetchInvX : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_Inv : Accumulator : Sum.u64 = 847; SumSQ.u64 = 847; Count.u64 = 847; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FetchInvX : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_Inv : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetS_hit : Accumulator : Sum.u64 = 685; SumSQ.u64 = 7641; Count.u64 = 62; Min.u64 = 10; Max.u64 = 15; - l2cache4.latency_GetS_miss : Accumulator : Sum.u64 = 99920; SumSQ.u64 = 25289820; Count.u64 = 897; Min.u64 = 37; Max.u64 = 2237; + l2cache4.latency_GetS_hit : Accumulator : Sum.u64 = 728; SumSQ.u64 = 7838; Count.u64 = 68; Min.u64 = 10; Max.u64 = 13; + l2cache4.latency_GetS_miss : Accumulator : Sum.u64 = 97586; SumSQ.u64 = 34000864; Count.u64 = 864; Min.u64 = 37; Max.u64 = 3224; l2cache4.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetX_hit : Accumulator : Sum.u64 = 45; SumSQ.u64 = 511; Count.u64 = 4; Min.u64 = 10; Max.u64 = 13; - l2cache4.latency_GetX_miss : Accumulator : Sum.u64 = 103028; SumSQ.u64 = 81614048; Count.u64 = 582; Min.u64 = 56; Max.u64 = 5322; + l2cache4.latency_GetX_hit : Accumulator : Sum.u64 = 97; SumSQ.u64 = 1049; Count.u64 = 9; Min.u64 = 10; Max.u64 = 12; + l2cache4.latency_GetX_miss : Accumulator : Sum.u64 = 91398; SumSQ.u64 = 41498122; Count.u64 = 561; Min.u64 = 49; Max.u64 = 3239; l2cache4.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 31821; SumSQ.u64 = 26634445; Count.u64 = 194; Min.u64 = 57; Max.u64 = 3439; - l2cache4.latency_GetSX_hit : Accumulator : Sum.u64 = 10; SumSQ.u64 = 100; Count.u64 = 1; Min.u64 = 10; Max.u64 = 10; - l2cache4.latency_GetSX_miss : Accumulator : Sum.u64 = 6834; SumSQ.u64 = 3495278; Count.u64 = 38; Min.u64 = 70; Max.u64 = 1353; + l2cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 24829; SumSQ.u64 = 10273115; Count.u64 = 187; Min.u64 = 59; Max.u64 = 2188; + l2cache4.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.latency_GetSX_miss : Accumulator : Sum.u64 = 5725; SumSQ.u64 = 918545; Count.u64 = 45; Min.u64 = 65; Max.u64 = 406; l2cache4.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1448; SumSQ.u64 = 166710; Count.u64 = 14; Min.u64 = 66; Max.u64 = 173; - l2cache4.latency_FlushLine : Accumulator : Sum.u64 = 47361; SumSQ.u64 = 26231735; Count.u64 = 660; Min.u64 = 3; Max.u64 = 3197; - l2cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 46506; SumSQ.u64 = 29934402; Count.u64 = 585; Min.u64 = 3; Max.u64 = 4427; - l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1043; SumSQ.u64 = 117533; Count.u64 = 10; Min.u64 = 68; Max.u64 = 167; + l2cache4.latency_FlushLine : Accumulator : Sum.u64 = 51708; SumSQ.u64 = 26576060; Count.u64 = 693; Min.u64 = 3; Max.u64 = 2295; + l2cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 52308; SumSQ.u64 = 15342560; Count.u64 = 624; Min.u64 = 3; Max.u64 = 1201; + l2cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 897; SumSQ.u64 = 897; Count.u64 = 897; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 775; SumSQ.u64 = 775; Count.u64 = 775; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 864; SumSQ.u64 = 864; Count.u64 = 864; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.CacheHits : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; - l2cache4.CacheMisses : Accumulator : Sum.u64 = 1725; SumSQ.u64 = 1725; Count.u64 = 1725; Min.u64 = 1; Max.u64 = 1; + l2cache4.CacheHits : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache4.CacheMisses : Accumulator : Sum.u64 = 1667; SumSQ.u64 = 1667; Count.u64 = 1667; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2017,109 +2112,114 @@ l2cache4.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutE_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.stateEvent_PutE_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutE_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.TotalEventsReceived : Accumulator : Sum.u64 = 13609; SumSQ.u64 = 13609; Count.u64 = 13609; Min.u64 = 1; Max.u64 = 1; - l2cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 1617; SumSQ.u64 = 1617; Count.u64 = 1617; Min.u64 = 1; Max.u64 = 1; + l2cache4.TotalEventsReceived : Accumulator : Sum.u64 = 13645; SumSQ.u64 = 13645; Count.u64 = 13645; Min.u64 = 1; Max.u64 = 1; + l2cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 1589; SumSQ.u64 = 1589; Count.u64 = 1589; Min.u64 = 1; Max.u64 = 1; l2cache4.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetS_uncache_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l2cache4.Write_uncache_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetS_uncache_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache4.Write_uncache_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSResp_uncache_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l2cache4.WriteResp_uncache_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSResp_uncache_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache4.WriteResp_uncache_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache4.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetS_recv : Accumulator : Sum.u64 = 2513; SumSQ.u64 = 2513; Count.u64 = 2513; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetX_recv : Accumulator : Sum.u64 = 1989; SumSQ.u64 = 1989; Count.u64 = 1989; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetSX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetS_recv : Accumulator : Sum.u64 = 2446; SumSQ.u64 = 2446; Count.u64 = 2446; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetX_recv : Accumulator : Sum.u64 = 2111; SumSQ.u64 = 2111; Count.u64 = 2111; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSX_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 660; SumSQ.u64 = 660; Count.u64 = 660; Min.u64 = 1; Max.u64 = 1; - l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 891; SumSQ.u64 = 891; Count.u64 = 891; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; - l2cache4.PutS_recv : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; - l2cache4.PutM_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; - l2cache4.PutE_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.PutS_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l2cache4.PutM_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache4.PutE_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.Inv_recv : Accumulator : Sum.u64 = 1156; SumSQ.u64 = 1156; Count.u64 = 1156; Min.u64 = 1; Max.u64 = 1; + l2cache4.Inv_recv : Accumulator : Sum.u64 = 1146; SumSQ.u64 = 1146; Count.u64 = 1146; Min.u64 = 1; Max.u64 = 1; l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; - l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; - l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; - l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; - l2cache4.NACK_recv : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; - l2cache4.AckInv_recv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 520; SumSQ.u64 = 520; Count.u64 = 520; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.NACK_recv : Accumulator : Sum.u64 = 1182; SumSQ.u64 = 1182; Count.u64 = 1182; Min.u64 = 1; Max.u64 = 1; + l2cache4.AckInv_recv : Accumulator : Sum.u64 = 845; SumSQ.u64 = 845; Count.u64 = 845; Min.u64 = 1; Max.u64 = 1; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.MSHR_occupancy : Accumulator : Sum.u64 = 336699; SumSQ.u64 = 2212479; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 8; + l2cache4.MSHR_occupancy : Accumulator : Sum.u64 = 322095; SumSQ.u64 = 2118521; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 8; l2cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core5.pendCycle : Accumulator : Sum.u64 = 807510; SumSQ.u64 = 12632454; Count.u64 = 52611; Min.u64 = 0; Max.u64 = 16; - core5.reads : Accumulator : Sum.u64 = 1535; SumSQ.u64 = 1535; Count.u64 = 1535; Min.u64 = 1; Max.u64 = 1; - core5.writes : Accumulator : Sum.u64 = 895; SumSQ.u64 = 895; Count.u64 = 895; Min.u64 = 1; Max.u64 = 1; - core5.readNoncache : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - core5.writeNoncache : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - core5.flushes : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; - core5.flushinvs : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; - core5.llsc : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - core5.llsc_success : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + core5.pendCycle : Accumulator : Sum.u64 = 770509; SumSQ.u64 = 12075781; Count.u64 = 49686; Min.u64 = 0; Max.u64 = 16; + core5.reads : Accumulator : Sum.u64 = 1528; SumSQ.u64 = 1528; Count.u64 = 1528; Min.u64 = 1; Max.u64 = 1; + core5.writes : Accumulator : Sum.u64 = 909; SumSQ.u64 = 909; Count.u64 = 909; Min.u64 = 1; Max.u64 = 1; + core5.readNoncache : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + core5.writeNoncache : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + core5.flushes : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; + core5.flushinvs : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; + core5.llsc : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + core5.llsc_success : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetSX_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetSX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 883; SumSQ.u64 = 883; Count.u64 = 883; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_Inv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 859; SumSQ.u64 = 859; Count.u64 = 859; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 666; SumSQ.u64 = 666; Count.u64 = 666; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_I : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_Inv_SB : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_SB : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_Inv_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2127,13 +2227,13 @@ l1cache5.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2143,30 +2243,33 @@ l1cache5.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetS : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetX : Accumulator : Sum.u64 = 2035; SumSQ.u64 = 2035; Count.u64 = 2035; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetSX : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_Write : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_PutM : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_GetS : Accumulator : Sum.u64 = 2671; SumSQ.u64 = 2671; Count.u64 = 2671; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_GetX : Accumulator : Sum.u64 = 2089; SumSQ.u64 = 2089; Count.u64 = 2089; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_GetSX : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_Write : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_PutM : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 548; SumSQ.u64 = 548; Count.u64 = 548; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 1535; SumSQ.u64 = 1535; Count.u64 = 1535; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 956; SumSQ.u64 = 956; Count.u64 = 956; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 835; SumSQ.u64 = 835; Count.u64 = 835; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 1528; SumSQ.u64 = 1528; Count.u64 = 1528; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2174,89 +2277,94 @@ l1cache5.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.evict_I : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_S : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_M : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_IS : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_IM : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_SM : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_SB : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l1cache5.latency_GetS_hit : Accumulator : Sum.u64 = 74741; SumSQ.u64 = 122605011; Count.u64 = 454; Min.u64 = 4; Max.u64 = 4670; - l1cache5.latency_GetS_miss : Accumulator : Sum.u64 = 231795; SumSQ.u64 = 296285197; Count.u64 = 989; Min.u64 = 16; Max.u64 = 6398; - l1cache5.latency_GetX_hit : Accumulator : Sum.u64 = 54957; SumSQ.u64 = 120403449; Count.u64 = 158; Min.u64 = 2; Max.u64 = 4716; - l1cache5.latency_GetX_miss : Accumulator : Sum.u64 = 179849; SumSQ.u64 = 313111107; Count.u64 = 576; Min.u64 = 16; Max.u64 = 5678; - l1cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 64146; SumSQ.u64 = 98927358; Count.u64 = 170; Min.u64 = 68; Max.u64 = 5084; - l1cache5.latency_GetSX_hit : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1593305; Count.u64 = 6; Min.u64 = 4; Max.u64 = 1210; - l1cache5.latency_GetSX_miss : Accumulator : Sum.u64 = 8768; SumSQ.u64 = 3229438; Count.u64 = 47; Min.u64 = 76; Max.u64 = 1168; - l1cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 4973; SumSQ.u64 = 7000333; Count.u64 = 8; Min.u64 = 77; Max.u64 = 2116; - l1cache5.latency_FlushLine : Accumulator : Sum.u64 = 78741; SumSQ.u64 = 85646991; Count.u64 = 226; Min.u64 = 68; Max.u64 = 3108; + l1cache5.evict_I : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_S : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_M : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_IS : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_IM : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_SB : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache5.latency_GetS_hit : Accumulator : Sum.u64 = 99123; SumSQ.u64 = 179595017; Count.u64 = 465; Min.u64 = 4; Max.u64 = 4670; + l1cache5.latency_GetS_miss : Accumulator : Sum.u64 = 231285; SumSQ.u64 = 276702559; Count.u64 = 964; Min.u64 = 16; Max.u64 = 6398; + l1cache5.latency_GetX_hit : Accumulator : Sum.u64 = 38808; SumSQ.u64 = 54329168; Count.u64 = 159; Min.u64 = 2; Max.u64 = 4716; + l1cache5.latency_GetX_miss : Accumulator : Sum.u64 = 162598; SumSQ.u64 = 164084210; Count.u64 = 588; Min.u64 = 17; Max.u64 = 4589; + l1cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 52958; SumSQ.u64 = 65810022; Count.u64 = 166; Min.u64 = 69; Max.u64 = 5084; + l1cache5.latency_GetSX_hit : Accumulator : Sum.u64 = 2735; SumSQ.u64 = 2927553; Count.u64 = 6; Min.u64 = 4; Max.u64 = 1210; + l1cache5.latency_GetSX_miss : Accumulator : Sum.u64 = 8775; SumSQ.u64 = 3245581; Count.u64 = 46; Min.u64 = 16; Max.u64 = 1126; + l1cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 212651; Count.u64 = 8; Min.u64 = 80; Max.u64 = 294; + l1cache5.latency_FlushLine : Accumulator : Sum.u64 = 73368; SumSQ.u64 = 75266654; Count.u64 = 231; Min.u64 = 69; Max.u64 = 3908; l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 86515; SumSQ.u64 = 136472175; Count.u64 = 222; Min.u64 = 72; Max.u64 = 6811; + l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 77634; SumSQ.u64 = 119556264; Count.u64 = 212; Min.u64 = 73; Max.u64 = 6811; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXHit_Blocked : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXHit_Blocked : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXMiss_Arrival : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache5.CacheHits : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; - l1cache5.CacheMisses : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache5.CacheHits : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l1cache5.CacheMisses : Accumulator : Sum.u64 = 1772; SumSQ.u64 = 1772; Count.u64 = 1772; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_PutS : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_PutE : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetS_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_E : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_PutS : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_PutE : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_E : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l1cache5.TotalEventsReceived : Accumulator : Sum.u64 = 10662; SumSQ.u64 = 10662; Count.u64 = 10662; Min.u64 = 1; Max.u64 = 1; - l1cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache5.TotalEventsReceived : Accumulator : Sum.u64 = 10721; SumSQ.u64 = 10721; Count.u64 = 10721; Min.u64 = 1; Max.u64 = 1; + l1cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; l1cache5.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetS_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l1cache5.Write_uncache_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetS_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l1cache5.Write_uncache_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSResp_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l1cache5.WriteResp_uncache_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSResp_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l1cache5.WriteResp_uncache_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l1cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetS_recv : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetS_recv : Accumulator : Sum.u64 = 1429; SumSQ.u64 = 1429; Count.u64 = 1429; Min.u64 = 1; Max.u64 = 1; l1cache5.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSX_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; - l1cache5.Write_recv : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; - l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; - l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 883; SumSQ.u64 = 883; Count.u64 = 883; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; - l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; - l1cache5.Inv_recv : Accumulator : Sum.u64 = 838; SumSQ.u64 = 838; Count.u64 = 838; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSX_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache5.Write_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 859; SumSQ.u64 = 859; Count.u64 = 859; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.Inv_recv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; - l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; - l1cache5.NACK_recv : Accumulator : Sum.u64 = 3716; SumSQ.u64 = 3716; Count.u64 = 3716; Min.u64 = 1; Max.u64 = 1; + l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; + l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.NACK_recv : Accumulator : Sum.u64 = 3779; SumSQ.u64 = 3779; Count.u64 = 3779; Min.u64 = 1; Max.u64 = 1; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 775157; SumSQ.u64 = 11672069; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 16; + l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 737321; SumSQ.u64 = 11095341; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 16; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 7069; SumSQ.u64 = 12147; Count.u64 = 5562; Min.u64 = 0; Max.u64 = 6; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 872448; SumSQ.u64 = 352972800; Count.u64 = 5550; Min.u64 = 64; Max.u64 = 576; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 10669395; SumSQ.u64 = 96639989427; Count.u64 = 4542; Min.u64 = 1; Max.u64 = 145818; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 6987; SumSQ.u64 = 11835; Count.u64 = 5561; Min.u64 = 0; Max.u64 = 6; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 859968; SumSQ.u64 = 344813568; Count.u64 = 5553; Min.u64 = 64; Max.u64 = 576; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 10729147; SumSQ.u64 = 769778566961; Count.u64 = 4440; Min.u64 = 1; Max.u64 = 826545; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.evict_I : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + l2cache5.evict_I : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2269,48 +2377,48 @@ l2cache5.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 542; SumSQ.u64 = 542; Count.u64 = 542; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 556; SumSQ.u64 = 556; Count.u64 = 556; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_GetSX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 608; SumSQ.u64 = 608; Count.u64 = 608; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 621; SumSQ.u64 = 621; Count.u64 = 621; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutS_S : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutS_S : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutM_M : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutM_M : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 1112; SumSQ.u64 = 1112; Count.u64 = 1112; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_Inv_SB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_Inv_IB : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_Inv_SB : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_Inv_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2322,7 +2430,7 @@ l2cache5.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2330,7 +2438,7 @@ l2cache5.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2343,155 +2451,167 @@ l2cache5.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 801; SumSQ.u64 = 801; Count.u64 = 801; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetS : Accumulator : Sum.u64 = 1367; SumSQ.u64 = 1367; Count.u64 = 1367; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetX : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetSX : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_Write : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetS : Accumulator : Sum.u64 = 1351; SumSQ.u64 = 1351; Count.u64 = 1351; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetX : Accumulator : Sum.u64 = 1294; SumSQ.u64 = 1294; Count.u64 = 1294; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetSX : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_Write : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_NACK : Accumulator : Sum.u64 = 3878; SumSQ.u64 = 3878; Count.u64 = 3878; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 975; SumSQ.u64 = 975; Count.u64 = 975; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 385; SumSQ.u64 = 385; Count.u64 = 385; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 1054; SumSQ.u64 = 1054; Count.u64 = 1054; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_NACK : Accumulator : Sum.u64 = 3930; SumSQ.u64 = 3930; Count.u64 = 3930; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 958; SumSQ.u64 = 958; Count.u64 = 958; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_FetchInvX : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_Inv : Accumulator : Sum.u64 = 838; SumSQ.u64 = 838; Count.u64 = 838; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FetchInvX : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_Inv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetS_hit : Accumulator : Sum.u64 = 814; SumSQ.u64 = 8764; Count.u64 = 76; Min.u64 = 10; Max.u64 = 14; - l2cache5.latency_GetS_miss : Accumulator : Sum.u64 = 106091; SumSQ.u64 = 28615863; Count.u64 = 913; Min.u64 = 37; Max.u64 = 2187; + l2cache5.latency_GetS_hit : Accumulator : Sum.u64 = 683; SumSQ.u64 = 7331; Count.u64 = 64; Min.u64 = 10; Max.u64 = 13; + l2cache5.latency_GetS_miss : Accumulator : Sum.u64 = 95690; SumSQ.u64 = 17337242; Count.u64 = 900; Min.u64 = 37; Max.u64 = 1128; l2cache5.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetX_hit : Accumulator : Sum.u64 = 102; SumSQ.u64 = 1166; Count.u64 = 9; Min.u64 = 10; Max.u64 = 13; - l2cache5.latency_GetX_miss : Accumulator : Sum.u64 = 97882; SumSQ.u64 = 102699942; Count.u64 = 542; Min.u64 = 48; Max.u64 = 5332; + l2cache5.latency_GetX_hit : Accumulator : Sum.u64 = 124; SumSQ.u64 = 1406; Count.u64 = 11; Min.u64 = 10; Max.u64 = 13; + l2cache5.latency_GetX_miss : Accumulator : Sum.u64 = 95935; SumSQ.u64 = 49342451; Count.u64 = 556; Min.u64 = 61; Max.u64 = 2440; l2cache5.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 28569; SumSQ.u64 = 10578359; Count.u64 = 195; Min.u64 = 61; Max.u64 = 1652; - l2cache5.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetSX_miss : Accumulator : Sum.u64 = 5636; SumSQ.u64 = 1016422; Count.u64 = 45; Min.u64 = 67; Max.u64 = 500; + l2cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 23555; SumSQ.u64 = 4926439; Count.u64 = 187; Min.u64 = 59; Max.u64 = 761; + l2cache5.latency_GetSX_hit : Accumulator : Sum.u64 = 10; SumSQ.u64 = 100; Count.u64 = 1; Min.u64 = 10; Max.u64 = 10; + l2cache5.latency_GetSX_miss : Accumulator : Sum.u64 = 5451; SumSQ.u64 = 875893; Count.u64 = 43; Min.u64 = 66; Max.u64 = 382; l2cache5.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1452; SumSQ.u64 = 296884; Count.u64 = 10; Min.u64 = 71; Max.u64 = 377; - l2cache5.latency_FlushLine : Accumulator : Sum.u64 = 44108; SumSQ.u64 = 16732004; Count.u64 = 548; Min.u64 = 3; Max.u64 = 1983; - l2cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 49620; SumSQ.u64 = 17733992; Count.u64 = 663; Min.u64 = 3; Max.u64 = 1326; - l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1520; SumSQ.u64 = 314226; Count.u64 = 10; Min.u64 = 69; Max.u64 = 286; + l2cache5.latency_FlushLine : Accumulator : Sum.u64 = 45969; SumSQ.u64 = 19170993; Count.u64 = 625; Min.u64 = 3; Max.u64 = 2026; + l2cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 48714; SumSQ.u64 = 28287176; Count.u64 = 593; Min.u64 = 3; Max.u64 = 3316; + l2cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetSXMiss_Arrival : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 900; SumSQ.u64 = 900; Count.u64 = 900; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSXMiss_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.CacheHits : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; - l2cache5.CacheMisses : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.CacheHits : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache5.CacheMisses : Accumulator : Sum.u64 = 1696; SumSQ.u64 = 1696; Count.u64 = 1696; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutE_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_PutE_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutE_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.TotalEventsReceived : Accumulator : Sum.u64 = 13634; SumSQ.u64 = 13634; Count.u64 = 13634; Min.u64 = 1; Max.u64 = 1; - l2cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l2cache5.TotalEventsReceived : Accumulator : Sum.u64 = 13660; SumSQ.u64 = 13660; Count.u64 = 13660; Min.u64 = 1; Max.u64 = 1; + l2cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 1579; SumSQ.u64 = 1579; Count.u64 = 1579; Min.u64 = 1; Max.u64 = 1; l2cache5.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetS_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l2cache5.Write_uncache_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetS_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l2cache5.Write_uncache_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSResp_uncache_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; - l2cache5.WriteResp_uncache_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSResp_uncache_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l2cache5.WriteResp_uncache_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; l2cache5.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetS_recv : Accumulator : Sum.u64 = 2580; SumSQ.u64 = 2580; Count.u64 = 2580; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetX_recv : Accumulator : Sum.u64 = 2035; SumSQ.u64 = 2035; Count.u64 = 2035; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetSX_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetS_recv : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetX_recv : Accumulator : Sum.u64 = 2089; SumSQ.u64 = 2089; Count.u64 = 2089; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSX_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 548; SumSQ.u64 = 548; Count.u64 = 548; Min.u64 = 1; Max.u64 = 1; - l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 883; SumSQ.u64 = 883; Count.u64 = 883; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; - l2cache5.PutS_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; - l2cache5.PutM_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; - l2cache5.PutE_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.PutS_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; + l2cache5.PutM_recv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l2cache5.PutE_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.Inv_recv : Accumulator : Sum.u64 = 1167; SumSQ.u64 = 1167; Count.u64 = 1167; Min.u64 = 1; Max.u64 = 1; + l2cache5.Inv_recv : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; - l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 516; SumSQ.u64 = 516; Count.u64 = 516; Min.u64 = 1; Max.u64 = 1; - l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; - l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; - l2cache5.NACK_recv : Accumulator : Sum.u64 = 1176; SumSQ.u64 = 1176; Count.u64 = 1176; Min.u64 = 1; Max.u64 = 1; - l2cache5.AckInv_recv : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.NACK_recv : Accumulator : Sum.u64 = 1214; SumSQ.u64 = 1214; Count.u64 = 1214; Min.u64 = 1; Max.u64 = 1; + l2cache5.AckInv_recv : Accumulator : Sum.u64 = 835; SumSQ.u64 = 835; Count.u64 = 835; Min.u64 = 1; Max.u64 = 1; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 332721; SumSQ.u64 = 2191041; Count.u64 = 53242; Min.u64 = 0; Max.u64 = 8; + l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 317660; SumSQ.u64 = 2094244; Count.u64 = 52500; Min.u64 = 0; Max.u64 = 8; l2cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 17693; SumSQ.u64 = 38189; Count.u64 = 12784; Min.u64 = 0; Max.u64 = 10; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 3073024; SumSQ.u64 = 1484732416; Count.u64 = 12811; Min.u64 = 64; Max.u64 = 576; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 6136902; SumSQ.u64 = 27650784572; Count.u64 = 5081; Min.u64 = 4; Max.u64 = 114552; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 18830; SumSQ.u64 = 42166; Count.u64 = 13339; Min.u64 = 0; Max.u64 = 10; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 3174656; SumSQ.u64 = 1529323520; Count.u64 = 13360; Min.u64 = 64; Max.u64 = 576; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 5699056; SumSQ.u64 = 12654451528; Count.u64 = 4996; Min.u64 = 4; Max.u64 = 14164; l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2506,20 +2626,20 @@ l3cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 1259; SumSQ.u64 = 1259; Count.u64 = 1259; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 1106; SumSQ.u64 = 1106; Count.u64 = 1106; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 1422; SumSQ.u64 = 1422; Count.u64 = 1422; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2580,82 +2700,89 @@ l3cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 777; SumSQ.u64 = 777; Count.u64 = 777; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 768; SumSQ.u64 = 768; Count.u64 = 768; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 409; SumSQ.u64 = 409; Count.u64 = 409; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetS : Accumulator : Sum.u64 = 520; SumSQ.u64 = 520; Count.u64 = 520; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetX : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetSX : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_Write : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 399; SumSQ.u64 = 399; Count.u64 = 399; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetS : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetX : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Write : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 1936; SumSQ.u64 = 1936; Count.u64 = 1936; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1892; SumSQ.u64 = 1892; Count.u64 = 1892; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1761; SumSQ.u64 = 1761; Count.u64 = 1761; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 2349; SumSQ.u64 = 2349; Count.u64 = 2349; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1916; SumSQ.u64 = 1916; Count.u64 = 1916; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1801; SumSQ.u64 = 1801; Count.u64 = 1801; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 923; SumSQ.u64 = 923; Count.u64 = 923; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 2303; SumSQ.u64 = 2303; Count.u64 = 2303; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 1016; SumSQ.u64 = 1016; Count.u64 = 1016; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 2276; SumSQ.u64 = 2276; Count.u64 = 2276; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 16126; SumSQ.u64 = 625326; Count.u64 = 713; Min.u64 = 15; Max.u64 = 276; - l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 17010; SumSQ.u64 = 1406212; Count.u64 = 242; Min.u64 = 43; Max.u64 = 226; - l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 37972; SumSQ.u64 = 2220672; Count.u64 = 825; Min.u64 = 20; Max.u64 = 268; + l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 16889; SumSQ.u64 = 726213; Count.u64 = 742; Min.u64 = 15; Max.u64 = 276; + l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 17213; SumSQ.u64 = 1465591; Count.u64 = 239; Min.u64 = 44; Max.u64 = 214; + l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 37588; SumSQ.u64 = 2113178; Count.u64 = 825; Min.u64 = 19; Max.u64 = 233; l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 30; SumSQ.u64 = 450; Count.u64 = 2; Min.u64 = 15; Max.u64 = 15; - l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 11673; SumSQ.u64 = 1023363; Count.u64 = 163; Min.u64 = 45; Max.u64 = 259; - l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 54867; SumSQ.u64 = 5693669; Count.u64 = 1089; Min.u64 = 19; Max.u64 = 778; - l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 11414; SumSQ.u64 = 1002646; Count.u64 = 235; Min.u64 = 25; Max.u64 = 480; + l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 13870; SumSQ.u64 = 1358348; Count.u64 = 174; Min.u64 = 44; Max.u64 = 259; + l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 51400; SumSQ.u64 = 3078592; Count.u64 = 1117; Min.u64 = 24; Max.u64 = 260; + l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 11496; SumSQ.u64 = 746260; Count.u64 = 236; Min.u64 = 25; Max.u64 = 163; l3cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 1757; SumSQ.u64 = 237569; Count.u64 = 20; Min.u64 = 44; Max.u64 = 278; - l3cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 3335; SumSQ.u64 = 198679; Count.u64 = 72; Min.u64 = 26; Max.u64 = 179; - l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 534; SumSQ.u64 = 23768; Count.u64 = 14; Min.u64 = 25; Max.u64 = 90; - l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 33407; SumSQ.u64 = 2794787; Count.u64 = 716; Min.u64 = 7; Max.u64 = 316; - l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 39803; SumSQ.u64 = 3627369; Count.u64 = 719; Min.u64 = 7; Max.u64 = 276; - l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1287; SumSQ.u64 = 1287; Count.u64 = 1287; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 1316; SumSQ.u64 = 1316; Count.u64 = 1316; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 1172; SumSQ.u64 = 92136; Count.u64 = 18; Min.u64 = 46; Max.u64 = 167; + l3cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 3363; SumSQ.u64 = 234871; Count.u64 = 66; Min.u64 = 30; Max.u64 = 179; + l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 988; SumSQ.u64 = 72234; Count.u64 = 20; Min.u64 = 28; Max.u64 = 147; + l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 35075; SumSQ.u64 = 3020995; Count.u64 = 761; Min.u64 = 7; Max.u64 = 316; + l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 42561; SumSQ.u64 = 4105609; Count.u64 = 768; Min.u64 = 7; Max.u64 = 274; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 1505; SumSQ.u64 = 1505; Count.u64 = 1505; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l3cache0.CacheHits : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 3133; Count.u64 = 3133; Min.u64 = 1; Max.u64 = 1; - l3cache0.CacheMisses : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheHits : Accumulator : Sum.u64 = 3331; SumSQ.u64 = 3331; Count.u64 = 3331; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheMisses : Accumulator : Sum.u64 = 687; SumSQ.u64 = 687; Count.u64 = 687; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2679,36 +2806,38 @@ l3cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 12784; SumSQ.u64 = 12784; Count.u64 = 12784; Min.u64 = 1; Max.u64 = 1; - l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 3491; SumSQ.u64 = 3491; Count.u64 = 3491; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 13339; SumSQ.u64 = 13339; Count.u64 = 13339; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 3562; SumSQ.u64 = 3562; Count.u64 = 3562; Min.u64 = 1; Max.u64 = 1; l3cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; - l3cache0.Write_uncache_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l3cache0.Write_uncache_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; - l3cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l3cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.GetS_recv : Accumulator : Sum.u64 = 2427; SumSQ.u64 = 2427; Count.u64 = 2427; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetX_recv : Accumulator : Sum.u64 = 2199; SumSQ.u64 = 2199; Count.u64 = 2199; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetSX_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetS_recv : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetX_recv : Accumulator : Sum.u64 = 2488; SumSQ.u64 = 2488; Count.u64 = 2488; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSX_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; - l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 719; SumSQ.u64 = 719; Count.u64 = 719; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 768; SumSQ.u64 = 768; Count.u64 = 768; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 687; SumSQ.u64 = 687; Count.u64 = 687; Min.u64 = 1; Max.u64 = 1; l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 923; SumSQ.u64 = 923; Count.u64 = 923; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2718,17 +2847,20 @@ l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 698; SumSQ.u64 = 698; Count.u64 = 698; Min.u64 = 1; Max.u64 = 1; - l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; - l3cache0.NACK_recv : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; - l3cache0.AckInv_recv : Accumulator : Sum.u64 = 2150; SumSQ.u64 = 2150; Count.u64 = 2150; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NACK_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + l3cache0.AckInv_recv : Accumulator : Sum.u64 = 2146; SumSQ.u64 = 2146; Count.u64 = 2146; Min.u64 = 1; Max.u64 = 1; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 165693; SumSQ.u64 = 971807; Count.u64 = 31095; Min.u64 = 0; Max.u64 = 7; + l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 167735; SumSQ.u64 = 997977; Count.u64 = 30661; Min.u64 = 0; Max.u64 = 7; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 18494; SumSQ.u64 = 40576; Count.u64 = 13155; Min.u64 = 0; Max.u64 = 9; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 3191456; SumSQ.u64 = 1551494144; Count.u64 = 13189; Min.u64 = 64; Max.u64 = 576; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 6009654; SumSQ.u64 = 27074420460; Count.u64 = 5086; Min.u64 = 4; Max.u64 = 108240; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 18522; SumSQ.u64 = 41268; Count.u64 = 13184; Min.u64 = 0; Max.u64 = 11; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 3134624; SumSQ.u64 = 1513985024; Count.u64 = 13214; Min.u64 = 64; Max.u64 = 576; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 5698042; SumSQ.u64 = 11360592916; Count.u64 = 5050; Min.u64 = 4; Max.u64 = 10348; l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2743,20 +2875,20 @@ l3cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 1076; SumSQ.u64 = 1076; Count.u64 = 1076; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 1305; SumSQ.u64 = 1305; Count.u64 = 1305; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 1320; SumSQ.u64 = 1320; Count.u64 = 1320; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 265; SumSQ.u64 = 265; Count.u64 = 265; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2817,82 +2949,89 @@ l3cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 611; SumSQ.u64 = 611; Count.u64 = 611; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1736; SumSQ.u64 = 1736; Count.u64 = 1736; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 404; SumSQ.u64 = 404; Count.u64 = 404; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetS : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetX : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetSX : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_Write : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetS : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetX : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSX : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Write : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 516; SumSQ.u64 = 516; Count.u64 = 516; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 2529; SumSQ.u64 = 2529; Count.u64 = 2529; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1785; SumSQ.u64 = 1785; Count.u64 = 1785; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1767; SumSQ.u64 = 1767; Count.u64 = 1767; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 2662; SumSQ.u64 = 2662; Count.u64 = 2662; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1758; SumSQ.u64 = 1758; Count.u64 = 1758; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1737; SumSQ.u64 = 1737; Count.u64 = 1737; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 993; SumSQ.u64 = 993; Count.u64 = 993; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 796; SumSQ.u64 = 796; Count.u64 = 796; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 751; SumSQ.u64 = 751; Count.u64 = 751; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 1030; SumSQ.u64 = 1030; Count.u64 = 1030; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 2299; SumSQ.u64 = 2299; Count.u64 = 2299; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 1013; SumSQ.u64 = 1013; Count.u64 = 1013; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 2263; SumSQ.u64 = 2263; Count.u64 = 2263; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 18773; SumSQ.u64 = 831653; Count.u64 = 804; Min.u64 = 15; Max.u64 = 203; - l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 17736; SumSQ.u64 = 1592312; Count.u64 = 246; Min.u64 = 45; Max.u64 = 263; - l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 38496; SumSQ.u64 = 2934886; Count.u64 = 784; Min.u64 = 19; Max.u64 = 492; + l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 17382; SumSQ.u64 = 745236; Count.u64 = 741; Min.u64 = 15; Max.u64 = 227; + l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 17544; SumSQ.u64 = 1552642; Count.u64 = 244; Min.u64 = 45; Max.u64 = 263; + l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 38090; SumSQ.u64 = 2609978; Count.u64 = 788; Min.u64 = 19; Max.u64 = 382; l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 30; SumSQ.u64 = 450; Count.u64 = 2; Min.u64 = 15; Max.u64 = 15; - l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 11580; SumSQ.u64 = 951380; Count.u64 = 166; Min.u64 = 45; Max.u64 = 174; - l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 50338; SumSQ.u64 = 3615374; Count.u64 = 1045; Min.u64 = 24; Max.u64 = 594; - l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 14262; SumSQ.u64 = 1710442; Count.u64 = 260; Min.u64 = 25; Max.u64 = 611; + l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 12758; SumSQ.u64 = 1112866; Count.u64 = 177; Min.u64 = 45; Max.u64 = 257; + l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 46703; SumSQ.u64 = 2830403; Count.u64 = 1012; Min.u64 = 19; Max.u64 = 322; + l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 12813; SumSQ.u64 = 1035245; Count.u64 = 254; Min.u64 = 25; Max.u64 = 391; l3cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 845; SumSQ.u64 = 68167; Count.u64 = 12; Min.u64 = 46; Max.u64 = 138; - l3cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 4156; SumSQ.u64 = 292434; Count.u64 = 86; Min.u64 = 22; Max.u64 = 247; - l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 132283; Count.u64 = 20; Min.u64 = 31; Max.u64 = 309; - l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 40033; SumSQ.u64 = 3832421; Count.u64 = 883; Min.u64 = 7; Max.u64 = 654; - l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 41589; SumSQ.u64 = 3967135; Count.u64 = 795; Min.u64 = 7; Max.u64 = 284; - l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 1325; SumSQ.u64 = 1325; Count.u64 = 1325; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 1402; SumSQ.u64 = 1402; Count.u64 = 1402; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 1374; SumSQ.u64 = 140832; Count.u64 = 16; Min.u64 = 45; Max.u64 = 155; + l3cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 3908; SumSQ.u64 = 233408; Count.u64 = 80; Min.u64 = 27; Max.u64 = 126; + l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 51864; Count.u64 = 24; Min.u64 = 28; Max.u64 = 76; + l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 39597; SumSQ.u64 = 3302943; Count.u64 = 924; Min.u64 = 7; Max.u64 = 211; + l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 43624; SumSQ.u64 = 4392524; Count.u64 = 792; Min.u64 = 7; Max.u64 = 451; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 1263; SumSQ.u64 = 1263; Count.u64 = 1263; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 1426; SumSQ.u64 = 1426; Count.u64 = 1426; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l3cache1.CacheHits : Accumulator : Sum.u64 = 3305; SumSQ.u64 = 3305; Count.u64 = 3305; Min.u64 = 1; Max.u64 = 1; - l3cache1.CacheMisses : Accumulator : Sum.u64 = 704; SumSQ.u64 = 704; Count.u64 = 704; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheHits : Accumulator : Sum.u64 = 3226; SumSQ.u64 = 3226; Count.u64 = 3226; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheMisses : Accumulator : Sum.u64 = 715; SumSQ.u64 = 715; Count.u64 = 715; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 272; SumSQ.u64 = 272; Count.u64 = 272; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2916,36 +3055,38 @@ l3cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 13155; SumSQ.u64 = 13155; Count.u64 = 13155; Min.u64 = 1; Max.u64 = 1; - l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 3527; SumSQ.u64 = 3527; Count.u64 = 3527; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 13184; SumSQ.u64 = 13184; Count.u64 = 13184; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 3509; SumSQ.u64 = 3509; Count.u64 = 3509; Min.u64 = 1; Max.u64 = 1; l3cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; - l3cache1.Write_uncache_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l3cache1.Write_uncache_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; - l3cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l3cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetS_recv : Accumulator : Sum.u64 = 2649; SumSQ.u64 = 2649; Count.u64 = 2649; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetX_recv : Accumulator : Sum.u64 = 2406; SumSQ.u64 = 2406; Count.u64 = 2406; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetSX_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetS_recv : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetX_recv : Accumulator : Sum.u64 = 2484; SumSQ.u64 = 2484; Count.u64 = 2484; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSX_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 883; SumSQ.u64 = 883; Count.u64 = 883; Min.u64 = 1; Max.u64 = 1; - l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 924; SumSQ.u64 = 924; Count.u64 = 924; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 792; SumSQ.u64 = 792; Count.u64 = 792; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 704; SumSQ.u64 = 704; Count.u64 = 704; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 715; SumSQ.u64 = 715; Count.u64 = 715; Min.u64 = 1; Max.u64 = 1; l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 993; SumSQ.u64 = 993; Count.u64 = 993; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2955,17 +3096,20 @@ l3cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; - l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 924; SumSQ.u64 = 924; Count.u64 = 924; Min.u64 = 1; Max.u64 = 1; - l3cache1.NACK_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; - l3cache1.AckInv_recv : Accumulator : Sum.u64 = 2146; SumSQ.u64 = 2146; Count.u64 = 2146; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NACK_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckInv_recv : Accumulator : Sum.u64 = 2103; SumSQ.u64 = 2103; Count.u64 = 2103; Min.u64 = 1; Max.u64 = 1; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 173403; SumSQ.u64 = 1047797; Count.u64 = 31095; Min.u64 = 0; Max.u64 = 7; + l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 170352; SumSQ.u64 = 1023888; Count.u64 = 30661; Min.u64 = 0; Max.u64 = 7; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 17839; SumSQ.u64 = 37883; Count.u64 = 13089; Min.u64 = 0; Max.u64 = 9; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 3161056; SumSQ.u64 = 1534508032; Count.u64 = 13122; Min.u64 = 64; Max.u64 = 576; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 5915934; SumSQ.u64 = 17504886244; Count.u64 = 5108; Min.u64 = 4; Max.u64 = 66430; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 17042; SumSQ.u64 = 36908; Count.u64 = 12263; Min.u64 = 0; Max.u64 = 9; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 3022432; SumSQ.u64 = 1476183040; Count.u64 = 12285; Min.u64 = 64; Max.u64 = 576; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 6073650; SumSQ.u64 = 14763289204; Count.u64 = 5091; Min.u64 = 4; Max.u64 = 27442; l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2980,20 +3124,20 @@ l3cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 1106; SumSQ.u64 = 1106; Count.u64 = 1106; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 1494; SumSQ.u64 = 1494; Count.u64 = 1494; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 1235; SumSQ.u64 = 1235; Count.u64 = 1235; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3054,82 +3198,89 @@ l3cache2.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1801; SumSQ.u64 = 1801; Count.u64 = 1801; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1737; SumSQ.u64 = 1737; Count.u64 = 1737; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 302; SumSQ.u64 = 302; Count.u64 = 302; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetS : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetX : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetSX : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_Write : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 399; SumSQ.u64 = 399; Count.u64 = 399; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 444; SumSQ.u64 = 444; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetS : Accumulator : Sum.u64 = 388; SumSQ.u64 = 388; Count.u64 = 388; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetX : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetSX : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_Write : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_NACK : Accumulator : Sum.u64 = 2460; SumSQ.u64 = 2460; Count.u64 = 2460; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1774; SumSQ.u64 = 1774; Count.u64 = 1774; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1821; SumSQ.u64 = 1821; Count.u64 = 1821; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 929; SumSQ.u64 = 929; Count.u64 = 929; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_NACK : Accumulator : Sum.u64 = 1890; SumSQ.u64 = 1890; Count.u64 = 1890; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1751; SumSQ.u64 = 1751; Count.u64 = 1751; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 838; SumSQ.u64 = 838; Count.u64 = 838; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 773; SumSQ.u64 = 773; Count.u64 = 773; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 1032; SumSQ.u64 = 1032; Count.u64 = 1032; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_Inv : Accumulator : Sum.u64 = 2347; SumSQ.u64 = 2347; Count.u64 = 2347; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 1005; SumSQ.u64 = 1005; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_Inv : Accumulator : Sum.u64 = 2233; SumSQ.u64 = 2233; Count.u64 = 2233; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.latency_GetS_hit : Accumulator : Sum.u64 = 18113; SumSQ.u64 = 853923; Count.u64 = 764; Min.u64 = 15; Max.u64 = 279; - l3cache2.latency_GetS_miss : Accumulator : Sum.u64 = 14980; SumSQ.u64 = 1247196; Count.u64 = 218; Min.u64 = 45; Max.u64 = 223; - l3cache2.latency_GetS_inv : Accumulator : Sum.u64 = 38879; SumSQ.u64 = 3028667; Count.u64 = 805; Min.u64 = 20; Max.u64 = 623; + l3cache2.latency_GetS_hit : Accumulator : Sum.u64 = 16425; SumSQ.u64 = 632533; Count.u64 = 729; Min.u64 = 15; Max.u64 = 159; + l3cache2.latency_GetS_miss : Accumulator : Sum.u64 = 16531; SumSQ.u64 = 1385911; Count.u64 = 233; Min.u64 = 45; Max.u64 = 209; + l3cache2.latency_GetS_inv : Accumulator : Sum.u64 = 35707; SumSQ.u64 = 2294521; Count.u64 = 761; Min.u64 = 19; Max.u64 = 439; l3cache2.latency_GetX_hit : Accumulator : Sum.u64 = 15; SumSQ.u64 = 225; Count.u64 = 1; Min.u64 = 15; Max.u64 = 15; - l3cache2.latency_GetX_miss : Accumulator : Sum.u64 = 14375; SumSQ.u64 = 1323935; Count.u64 = 190; Min.u64 = 44; Max.u64 = 216; - l3cache2.latency_GetX_inv : Accumulator : Sum.u64 = 54200; SumSQ.u64 = 4135558; Count.u64 = 1128; Min.u64 = 19; Max.u64 = 592; - l3cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 12256; SumSQ.u64 = 1448828; Count.u64 = 241; Min.u64 = 25; Max.u64 = 802; + l3cache2.latency_GetX_miss : Accumulator : Sum.u64 = 13482; SumSQ.u64 = 1263594; Count.u64 = 178; Min.u64 = 45; Max.u64 = 223; + l3cache2.latency_GetX_inv : Accumulator : Sum.u64 = 47293; SumSQ.u64 = 2770729; Count.u64 = 1045; Min.u64 = 19; Max.u64 = 419; + l3cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 11957; SumSQ.u64 = 784987; Count.u64 = 255; Min.u64 = 25; Max.u64 = 256; l3cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 801; SumSQ.u64 = 54267; Count.u64 = 13; Min.u64 = 46; Max.u64 = 111; - l3cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 3918; SumSQ.u64 = 911670; Count.u64 = 63; Min.u64 = 28; Max.u64 = 782; - l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 770; SumSQ.u64 = 54880; Count.u64 = 15; Min.u64 = 28; Max.u64 = 154; - l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 36863; SumSQ.u64 = 3446135; Count.u64 = 738; Min.u64 = 7; Max.u64 = 595; - l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 39987; SumSQ.u64 = 3877879; Count.u64 = 731; Min.u64 = 7; Max.u64 = 395; - l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1294; SumSQ.u64 = 1294; Count.u64 = 1294; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1567; SumSQ.u64 = 1567; Count.u64 = 1567; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l3cache2.CacheHits : Accumulator : Sum.u64 = 3402; SumSQ.u64 = 3402; Count.u64 = 3402; Min.u64 = 1; Max.u64 = 1; - l3cache2.CacheMisses : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; + l3cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 400; SumSQ.u64 = 24718; Count.u64 = 7; Min.u64 = 47; Max.u64 = 94; + l3cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 2644; SumSQ.u64 = 132958; Count.u64 = 62; Min.u64 = 19; Max.u64 = 111; + l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 922; SumSQ.u64 = 51504; Count.u64 = 20; Min.u64 = 26; Max.u64 = 103; + l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 37104; SumSQ.u64 = 3091396; Count.u64 = 758; Min.u64 = 7; Max.u64 = 276; + l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 39575; SumSQ.u64 = 3898289; Count.u64 = 679; Min.u64 = 7; Max.u64 = 395; + l3cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1242; SumSQ.u64 = 1242; Count.u64 = 1242; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1321; SumSQ.u64 = 1321; Count.u64 = 1321; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache2.CacheHits : Accumulator : Sum.u64 = 3038; SumSQ.u64 = 3038; Count.u64 = 3038; Min.u64 = 1; Max.u64 = 1; + l3cache2.CacheMisses : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3153,36 +3304,38 @@ l3cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.TotalEventsReceived : Accumulator : Sum.u64 = 13089; SumSQ.u64 = 13089; Count.u64 = 13089; Min.u64 = 1; Max.u64 = 1; - l3cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 3557; SumSQ.u64 = 3557; Count.u64 = 3557; Min.u64 = 1; Max.u64 = 1; + l3cache2.TotalEventsReceived : Accumulator : Sum.u64 = 12263; SumSQ.u64 = 12263; Count.u64 = 12263; Min.u64 = 1; Max.u64 = 1; + l3cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 3368; SumSQ.u64 = 3368; Count.u64 = 3368; Min.u64 = 1; Max.u64 = 1; l3cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; - l3cache2.Write_uncache_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l3cache2.Write_uncache_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; - l3cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l3cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; l3cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetS_recv : Accumulator : Sum.u64 = 2527; SumSQ.u64 = 2527; Count.u64 = 2527; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetX_recv : Accumulator : Sum.u64 = 2666; SumSQ.u64 = 2666; Count.u64 = 2666; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetSX_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetS_recv : Accumulator : Sum.u64 = 2308; SumSQ.u64 = 2308; Count.u64 = 2308; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetX_recv : Accumulator : Sum.u64 = 2241; SumSQ.u64 = 2241; Count.u64 = 2241; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSX_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; - l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 929; SumSQ.u64 = 929; Count.u64 = 929; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3192,25 +3345,28 @@ l3cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; - l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 951; SumSQ.u64 = 951; Count.u64 = 951; Min.u64 = 1; Max.u64 = 1; - l3cache2.NACK_recv : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; - l3cache2.AckInv_recv : Accumulator : Sum.u64 = 2154; SumSQ.u64 = 2154; Count.u64 = 2154; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 710; SumSQ.u64 = 710; Count.u64 = 710; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 925; SumSQ.u64 = 925; Count.u64 = 925; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.NACK_recv : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l3cache2.AckInv_recv : Accumulator : Sum.u64 = 2074; SumSQ.u64 = 2074; Count.u64 = 2074; Min.u64 = 1; Max.u64 = 1; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 171400; SumSQ.u64 = 1028368; Count.u64 = 31095; Min.u64 = 0; Max.u64 = 7; + l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 160544; SumSQ.u64 = 929134; Count.u64 = 30661; Min.u64 = 0; Max.u64 = 7; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 3614; SumSQ.u64 = 5788; Count.u64 = 2909; Min.u64 = 0; Max.u64 = 6; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 1098528; SumSQ.u64 = 588708864; Count.u64 = 2909; Min.u64 = 64; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 10960186; SumSQ.u64 = 181479362636; Count.u64 = 2157; Min.u64 = 4; Max.u64 = 225556; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 3653; SumSQ.u64 = 5715; Count.u64 = 2987; Min.u64 = 0; Max.u64 = 6; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 1135936; SumSQ.u64 = 609452032; Count.u64 = 2987; Min.u64 = 64; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 10440938; SumSQ.u64 = 102983277076; Count.u64 = 2222; Min.u64 = 10; Max.u64 = 87502; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.replacement_request_latency : Accumulator : Sum.u64 = 34366; SumSQ.u64 = 1541026; Count.u64 = 1419; Min.u64 = 5; Max.u64 = 161; - directory0.get_request_latency : Accumulator : Sum.u64 = 23467; SumSQ.u64 = 1077721; Count.u64 = 1027; Min.u64 = 2; Max.u64 = 160; - directory0.directory_cache_hits : Accumulator : Sum.u64 = 2446; SumSQ.u64 = 2446; Count.u64 = 2446; Min.u64 = 1; Max.u64 = 1; + directory0.replacement_request_latency : Accumulator : Sum.u64 = 33939; SumSQ.u64 = 1442387; Count.u64 = 1449; Min.u64 = 5; Max.u64 = 138; + directory0.get_request_latency : Accumulator : Sum.u64 = 24996; SumSQ.u64 = 1177406; Count.u64 = 1054; Min.u64 = 2; Max.u64 = 140; + directory0.directory_cache_hits : Accumulator : Sum.u64 = 2503; SumSQ.u64 = 2503; Count.u64 = 2503; Min.u64 = 1; Max.u64 = 1; directory0.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.GetX_recv : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; - directory0.GetS_recv : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; - directory0.GetSX_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + directory0.GetX_recv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + directory0.GetS_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; + directory0.GetSX_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; directory0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3220,73 +3376,78 @@ directory0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.GetXResp_recv : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + directory0.GetXResp_recv : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; directory0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.FlushLine_recv : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; - directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 688; SumSQ.u64 = 688; Count.u64 = 688; Min.u64 = 1; Max.u64 = 1; - directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; - directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; - directory0.Write_uncache_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushLine_recv : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; + directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 1449; SumSQ.u64 = 1449; Count.u64 = 1449; Min.u64 = 1; Max.u64 = 1; + directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; + directory0.Write_uncache_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; directory0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; - directory0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + directory0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; + directory0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; directory0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.eventSent_GetS : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_GetX : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_GetSX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_Write : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetS : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetX : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetSX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_Write : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_WriteResp : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 1054; SumSQ.u64 = 1054; Count.u64 = 1054; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_WriteResp : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 688; SumSQ.u64 = 688; Count.u64 = 688; Min.u64 = 1; Max.u64 = 1; - directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1449; SumSQ.u64 = 1449; Count.u64 = 1449; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0.MSHR_occupancy : Accumulator : Sum.u64 = 52941; SumSQ.u64 = 165991; Count.u64 = 30918; Min.u64 = 0; Max.u64 = 10; + directory0.MSHR_occupancy : Accumulator : Sum.u64 = 53929; SumSQ.u64 = 166399; Count.u64 = 30627; Min.u64 = 0; Max.u64 = 9; memory0:backend.row_already_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:backend.no_row_open : Accumulator : Sum.u64 = 1981; SumSQ.u64 = 1981; Count.u64 = 1981; Min.u64 = 1; Max.u64 = 1; + memory0:backend.no_row_open : Accumulator : Sum.u64 = 2037; SumSQ.u64 = 2037; Count.u64 = 2037; Min.u64 = 1; Max.u64 = 1; memory0:backend.wrong_row_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0.requests_received_GetS : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; - memory0.requests_received_GetSX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - memory0.requests_received_GetX : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; - memory0.requests_received_Write : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; - memory0.requests_received_PutM : Accumulator : Sum.u64 = 883; SumSQ.u64 = 883; Count.u64 = 883; Min.u64 = 1; Max.u64 = 1; - memory0.outstanding_requests : Accumulator : Sum.u64 = 24216; SumSQ.u64 = 95496; Count.u64 = 11100; Min.u64 = 0; Max.u64 = 11; - memory0.latency_GetS : Accumulator : Sum.u64 = 8265; SumSQ.u64 = 147801; Count.u64 = 644; Min.u64 = 7; Max.u64 = 56; - memory0.latency_GetSX : Accumulator : Sum.u64 = 284; SumSQ.u64 = 6128; Count.u64 = 20; Min.u64 = 7; Max.u64 = 49; - memory0.latency_GetX : Accumulator : Sum.u64 = 3059; SumSQ.u64 = 46993; Count.u64 = 269; Min.u64 = 7; Max.u64 = 39; - memory0.latency_Write : Accumulator : Sum.u64 = 2310; SumSQ.u64 = 46072; Count.u64 = 165; Min.u64 = 7; Max.u64 = 57; - memory0.latency_PutM : Accumulator : Sum.u64 = 10298; SumSQ.u64 = 170084; Count.u64 = 883; Min.u64 = 7; Max.u64 = 56; - memory0.cycles_with_issue : Accumulator : Sum.u64 = 1396; SumSQ.u64 = 1396; Count.u64 = 1396; Min.u64 = 1; Max.u64 = 1; - memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 3809; SumSQ.u64 = 3809; Count.u64 = 3809; Min.u64 = 1; Max.u64 = 1; - memory0.total_cycles : Accumulator : Sum.u64 = 11100; SumSQ.u64 = 123210000; Count.u64 = 1; Min.u64 = 11100; Max.u64 = 11100; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 3560; SumSQ.u64 = 5628; Count.u64 = 2875; Min.u64 = 0; Max.u64 = 6; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 1096448; SumSQ.u64 = 588830720; Count.u64 = 2875; Min.u64 = 64; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 10849036; SumSQ.u64 = 144527395584; Count.u64 = 2208; Min.u64 = 4; Max.u64 = 146098; + memory0.requests_received_GetS : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + memory0.requests_received_GetSX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + memory0.requests_received_GetX : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; + memory0.requests_received_Write : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + memory0.requests_received_PutM : Accumulator : Sum.u64 = 891; SumSQ.u64 = 891; Count.u64 = 891; Min.u64 = 1; Max.u64 = 1; + memory0.outstanding_requests : Accumulator : Sum.u64 = 24436; SumSQ.u64 = 93808; Count.u64 = 10946; Min.u64 = 0; Max.u64 = 11; + memory0.latency_GetS : Accumulator : Sum.u64 = 8018; SumSQ.u64 = 134160; Count.u64 = 662; Min.u64 = 7; Max.u64 = 51; + memory0.latency_GetSX : Accumulator : Sum.u64 = 282; SumSQ.u64 = 5396; Count.u64 = 24; Min.u64 = 7; Max.u64 = 45; + memory0.latency_GetX : Accumulator : Sum.u64 = 3391; SumSQ.u64 = 59531; Count.u64 = 273; Min.u64 = 7; Max.u64 = 49; + memory0.latency_Write : Accumulator : Sum.u64 = 2659; SumSQ.u64 = 53671; Count.u64 = 187; Min.u64 = 7; Max.u64 = 61; + memory0.latency_PutM : Accumulator : Sum.u64 = 10086; SumSQ.u64 = 157342; Count.u64 = 891; Min.u64 = 7; Max.u64 = 48; + memory0.cycles_with_issue : Accumulator : Sum.u64 = 1455; SumSQ.u64 = 1455; Count.u64 = 1455; Min.u64 = 1; Max.u64 = 1; + memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 3897; SumSQ.u64 = 3897; Count.u64 = 3897; Min.u64 = 1; Max.u64 = 1; + memory0.total_cycles : Accumulator : Sum.u64 = 10946; SumSQ.u64 = 119814916; Count.u64 = 1; Min.u64 = 10946; Max.u64 = 10946; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 3560; SumSQ.u64 = 5480; Count.u64 = 2930; Min.u64 = 0; Max.u64 = 6; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 1099648; SumSQ.u64 = 588513280; Count.u64 = 2930; Min.u64 = 64; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 10461044; SumSQ.u64 = 97718930040; Count.u64 = 2233; Min.u64 = 4; Max.u64 = 52180; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.replacement_request_latency : Accumulator : Sum.u64 = 31055; SumSQ.u64 = 1114293; Count.u64 = 1397; Min.u64 = 5; Max.u64 = 132; - directory1.get_request_latency : Accumulator : Sum.u64 = 21567; SumSQ.u64 = 866709; Count.u64 = 1028; Min.u64 = 2; Max.u64 = 139; - directory1.directory_cache_hits : Accumulator : Sum.u64 = 2425; SumSQ.u64 = 2425; Count.u64 = 2425; Min.u64 = 1; Max.u64 = 1; + directory1.replacement_request_latency : Accumulator : Sum.u64 = 32892; SumSQ.u64 = 1289394; Count.u64 = 1417; Min.u64 = 5; Max.u64 = 120; + directory1.get_request_latency : Accumulator : Sum.u64 = 22480; SumSQ.u64 = 979010; Count.u64 = 1041; Min.u64 = 2; Max.u64 = 139; + directory1.directory_cache_hits : Accumulator : Sum.u64 = 2458; SumSQ.u64 = 2458; Count.u64 = 2458; Min.u64 = 1; Max.u64 = 1; directory1.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.GetX_recv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; - directory1.GetS_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; - directory1.GetSX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + directory1.GetX_recv : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + directory1.GetS_recv : Accumulator : Sum.u64 = 351; SumSQ.u64 = 351; Count.u64 = 351; Min.u64 = 1; Max.u64 = 1; + directory1.GetSX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; directory1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3296,59 +3457,64 @@ directory1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.GetXResp_recv : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + directory1.GetXResp_recv : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; directory1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.FlushLine_recv : Accumulator : Sum.u64 = 715; SumSQ.u64 = 715; Count.u64 = 715; Min.u64 = 1; Max.u64 = 1; - directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; - directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 1397; SumSQ.u64 = 1397; Count.u64 = 1397; Min.u64 = 1; Max.u64 = 1; - directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; - directory1.Write_uncache_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushLine_recv : Accumulator : Sum.u64 = 732; SumSQ.u64 = 732; Count.u64 = 732; Min.u64 = 1; Max.u64 = 1; + directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 685; SumSQ.u64 = 685; Count.u64 = 685; Min.u64 = 1; Max.u64 = 1; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 1417; SumSQ.u64 = 1417; Count.u64 = 1417; Min.u64 = 1; Max.u64 = 1; + directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; + directory1.Write_uncache_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; directory1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; - directory1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + directory1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; + directory1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; directory1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.eventSent_GetS : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_GetX : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_GetSX : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_Write : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetS : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetX : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetSX : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_Write : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_WriteResp : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_WriteResp : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 715; SumSQ.u64 = 715; Count.u64 = 715; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; - directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1397; SumSQ.u64 = 1397; Count.u64 = 1397; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 732; SumSQ.u64 = 732; Count.u64 = 732; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 685; SumSQ.u64 = 685; Count.u64 = 685; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 1417; SumSQ.u64 = 1417; Count.u64 = 1417; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1.MSHR_occupancy : Accumulator : Sum.u64 = 47772; SumSQ.u64 = 137990; Count.u64 = 31072; Min.u64 = 0; Max.u64 = 12; + directory1.MSHR_occupancy : Accumulator : Sum.u64 = 50456; SumSQ.u64 = 150646; Count.u64 = 30616; Min.u64 = 0; Max.u64 = 9; memory1:backend.row_already_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:backend.no_row_open : Accumulator : Sum.u64 = 1987; SumSQ.u64 = 1987; Count.u64 = 1987; Min.u64 = 1; Max.u64 = 1; + memory1:backend.no_row_open : Accumulator : Sum.u64 = 2002; SumSQ.u64 = 2002; Count.u64 = 2002; Min.u64 = 1; Max.u64 = 1; memory1:backend.wrong_row_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1.requests_received_GetS : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; - memory1.requests_received_GetSX : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - memory1.requests_received_GetX : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; - memory1.requests_received_Write : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; - memory1.requests_received_PutM : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; - memory1.outstanding_requests : Accumulator : Sum.u64 = 21100; SumSQ.u64 = 72508; Count.u64 = 11100; Min.u64 = 0; Max.u64 = 13; - memory1.latency_GetS : Accumulator : Sum.u64 = 6868; SumSQ.u64 = 99880; Count.u64 = 624; Min.u64 = 7; Max.u64 = 48; - memory1.latency_GetSX : Accumulator : Sum.u64 = 255; SumSQ.u64 = 2953; Count.u64 = 25; Min.u64 = 7; Max.u64 = 17; - memory1.latency_GetX : Accumulator : Sum.u64 = 2693; SumSQ.u64 = 39725; Count.u64 = 250; Min.u64 = 7; Max.u64 = 48; - memory1.latency_Write : Accumulator : Sum.u64 = 2130; SumSQ.u64 = 31844; Count.u64 = 186; Min.u64 = 7; Max.u64 = 38; - memory1.latency_PutM : Accumulator : Sum.u64 = 9154; SumSQ.u64 = 118086; Count.u64 = 902; Min.u64 = 7; Max.u64 = 46; - memory1.cycles_with_issue : Accumulator : Sum.u64 = 1480; SumSQ.u64 = 1480; Count.u64 = 1480; Min.u64 = 1; Max.u64 = 1; - memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 3095; SumSQ.u64 = 3095; Count.u64 = 3095; Min.u64 = 1; Max.u64 = 1; - memory1.total_cycles : Accumulator : Sum.u64 = 11100; SumSQ.u64 = 123210000; Count.u64 = 1; Min.u64 = 11100; Max.u64 = 11100; -Simulation is complete, simulated time: 22.2019 us + memory1.requests_received_GetS : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; + memory1.requests_received_GetSX : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + memory1.requests_received_GetX : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + memory1.requests_received_Write : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + memory1.requests_received_PutM : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; + memory1.outstanding_requests : Accumulator : Sum.u64 = 22794; SumSQ.u64 = 83138; Count.u64 = 10946; Min.u64 = 0; Max.u64 = 11; + memory1.latency_GetS : Accumulator : Sum.u64 = 7726; SumSQ.u64 = 124810; Count.u64 = 644; Min.u64 = 7; Max.u64 = 48; + memory1.latency_GetSX : Accumulator : Sum.u64 = 162; SumSQ.u64 = 1790; Count.u64 = 17; Min.u64 = 7; Max.u64 = 18; + memory1.latency_GetX : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 49736; Count.u64 = 256; Min.u64 = 7; Max.u64 = 48; + memory1.latency_Write : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 32279; Count.u64 = 179; Min.u64 = 7; Max.u64 = 37; + memory1.latency_PutM : Accumulator : Sum.u64 = 9793; SumSQ.u64 = 139251; Count.u64 = 906; Min.u64 = 7; Max.u64 = 42; + memory1.cycles_with_issue : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; + memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 3449; SumSQ.u64 = 3449; Count.u64 = 3449; Min.u64 = 1; Max.u64 = 1; + memory1.total_cycles : Accumulator : Sum.u64 = 10946; SumSQ.u64 = 119814916; Count.u64 = 1; Min.u64 = 10946; Max.u64 = 10946; +Simulation is complete, simulated time: 21.8925 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out index e8eb51c22a..6a3974e83d 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_HashXor.out @@ -71,13 +71,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 5908; SumSQ.u64 = 5908; Count.u64 = 5908; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 4092; SumSQ.u64 = 4092; Count.u64 = 4092; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +154,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c0.l1cache.Write_recv : Accumulator : Sum.u64 = 4092; SumSQ.u64 = 4092; Count.u64 = 4092; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 362589849; SumSQ.u64 = 11589580679; Count.u64 = 11372708; Min.u64 = 0; Max.u64 = 32; @@ -232,13 +240,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 5989; SumSQ.u64 = 5989; Count.u64 = 5989; Min.u64 = 1; Max.u64 = 1; c1.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 4011; SumSQ.u64 = 4011; Count.u64 = 4011; Min.u64 = 1; Max.u64 = 1; c1.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -265,6 +276,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,14 +323,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c1.l1cache.Write_recv : Accumulator : Sum.u64 = 4011; SumSQ.u64 = 4011; Count.u64 = 4011; Min.u64 = 1; Max.u64 = 1; c1.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; c1.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c1.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c1.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 362828046; SumSQ.u64 = 11602588814; Count.u64 = 11372708; Min.u64 = 0; Max.u64 = 32; @@ -432,8 +448,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_PutS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_PutM : Accumulator : Sum.u64 = 7902; SumSQ.u64 = 7902; Count.u64 = 7902; Min.u64 = 1; Max.u64 = 1; + n0.l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -442,6 +461,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; n0.l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -536,10 +559,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.GetXResp_recv : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; n0.l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.PutM_recv : Accumulator : Sum.u64 = 8054; SumSQ.u64 = 8054; Count.u64 = 8054; Min.u64 = 1; Max.u64 = 1; n0.l2cache.PutE_recv : Accumulator : Sum.u64 = 11818; SumSQ.u64 = 11818; Count.u64 = 11818; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n0.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n0.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n0.l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n0.l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,13 +654,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 6002; SumSQ.u64 = 6002; Count.u64 = 6002; Min.u64 = 1; Max.u64 = 1; c2.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 3998; SumSQ.u64 = 3998; Count.u64 = 3998; Min.u64 = 1; Max.u64 = 1; c2.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -659,6 +690,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -705,14 +737,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c2.l1cache.Write_recv : Accumulator : Sum.u64 = 3998; SumSQ.u64 = 3998; Count.u64 = 3998; Min.u64 = 1; Max.u64 = 1; c2.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; c2.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 9999; SumSQ.u64 = 9999; Count.u64 = 9999; Min.u64 = 1; Max.u64 = 1; c2.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c2.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c2.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 363334113; SumSQ.u64 = 11616728923; Count.u64 = 11372708; Min.u64 = 0; Max.u64 = 32; @@ -787,13 +823,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 5924; SumSQ.u64 = 5924; Count.u64 = 5924; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 4076; SumSQ.u64 = 4076; Count.u64 = 4076; Min.u64 = 1; Max.u64 = 1; c3.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -820,6 +859,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -866,14 +906,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to c3.l1cache.Write_recv : Accumulator : Sum.u64 = 4076; SumSQ.u64 = 4076; Count.u64 = 4076; Min.u64 = 1; Max.u64 = 1; c3.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; c3.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; c3.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c3.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c3.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 363484832; SumSQ.u64 = 11623590128; Count.u64 = 11372708; Min.u64 = 0; Max.u64 = 32; @@ -987,8 +1031,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_PutS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_PutM : Accumulator : Sum.u64 = 7876; SumSQ.u64 = 7876; Count.u64 = 7876; Min.u64 = 1; Max.u64 = 1; + n1.l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -997,6 +1044,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 19999; SumSQ.u64 = 19999; Count.u64 = 19999; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n1.l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1021,6 +1071,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1091,10 +1142,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n1.l2cache.GetXResp_recv : Accumulator : Sum.u64 = 19999; SumSQ.u64 = 19999; Count.u64 = 19999; Min.u64 = 1; Max.u64 = 1; n1.l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.PutS_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n1.l2cache.PutM_recv : Accumulator : Sum.u64 = 8016; SumSQ.u64 = 8016; Count.u64 = 8016; Min.u64 = 1; Max.u64 = 1; n1.l2cache.PutE_recv : Accumulator : Sum.u64 = 11854; SumSQ.u64 = 11854; Count.u64 = 11854; Min.u64 = 1; Max.u64 = 1; @@ -1106,15 +1159,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to n1.l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; n1.l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + n1.l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; n1.l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 701747401; SumSQ.u64 = 43355737913; Count.u64 = 11372708; Min.u64 = 0; Max.u64 = 64; n1.l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache:memlink.packet_latency : Accumulator : Sum.u64 = 8450004; SumSQ.u64 = 904150428; Count.u64 = 78972; Min.u64 = 107; Max.u64 = 107; - l3cache:memlink.send_bit_count : Accumulator : Sum.u64 = 13133056; SumSQ.u64 = 5493932032; Count.u64 = 78972; Min.u64 = 64; Max.u64 = 576; - l3cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache:memlink.idle_time : Accumulator : Sum.u64 = 144100; SumSQ.u64 = 10991410000; Count.u64 = 2; Min.u64 = 54600; Max.u64 = 89500; + l3cache:lowlink.packet_latency : Accumulator : Sum.u64 = 8450004; SumSQ.u64 = 904150428; Count.u64 = 78972; Min.u64 = 107; Max.u64 = 107; + l3cache:lowlink.send_bit_count : Accumulator : Sum.u64 = 13133056; SumSQ.u64 = 5493932032; Count.u64 = 78972; Min.u64 = 64; Max.u64 = 576; + l3cache:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache:lowlink.idle_time : Accumulator : Sum.u64 = 144100; SumSQ.u64 = 10991410000; Count.u64 = 2; Min.u64 = 54600; Max.u64 = 89500; l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1224,8 +1280,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_PutM : Accumulator : Sum.u64 = 15779; SumSQ.u64 = 15779; Count.u64 = 15779; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1234,6 +1293,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 39999; SumSQ.u64 = 39999; Count.u64 = 39999; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1258,6 +1320,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1328,10 +1391,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetXResp_recv : Accumulator : Sum.u64 = 39998; SumSQ.u64 = 39998; Count.u64 = 39998; Min.u64 = 1; Max.u64 = 1; l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutS_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache.PutM_recv : Accumulator : Sum.u64 = 15778; SumSQ.u64 = 15778; Count.u64 = 15778; Min.u64 = 1; Max.u64 = 1; l3cache.PutE_recv : Accumulator : Sum.u64 = 23195; SumSQ.u64 = 23195; Count.u64 = 23195; Min.u64 = 1; Max.u64 = 1; @@ -1343,15 +1408,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.AckPut_recv : Accumulator : Sum.u64 = 38974; SumSQ.u64 = 38974; Count.u64 = 38974; Min.u64 = 1; Max.u64 = 1; l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1402643566; SumSQ.u64 = 173255358220; Count.u64 = 11372708; Min.u64 = 0; Max.u64 = 128; l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dirctrl:cpulink.packet_latency : Accumulator : Sum.u64 = 10029444; SumSQ.u64 = 1273739388; Count.u64 = 78972; Min.u64 = 127; Max.u64 = 127; - dirctrl:cpulink.send_bit_count : Accumulator : Sum.u64 = 33612032; SumSQ.u64 = 18600476672; Count.u64 = 78972; Min.u64 = 64; Max.u64 = 576; - dirctrl:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dirctrl:cpulink.idle_time : Accumulator : Sum.u64 = 261100; SumSQ.u64 = 48724210000; Count.u64 = 2; Min.u64 = 45000; Max.u64 = 216100; + dirctrl:highlink.packet_latency : Accumulator : Sum.u64 = 10029444; SumSQ.u64 = 1273739388; Count.u64 = 78972; Min.u64 = 127; Max.u64 = 127; + dirctrl:highlink.send_bit_count : Accumulator : Sum.u64 = 33612032; SumSQ.u64 = 18600476672; Count.u64 = 78972; Min.u64 = 64; Max.u64 = 576; + dirctrl:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dirctrl:highlink.idle_time : Accumulator : Sum.u64 = 261100; SumSQ.u64 = 48724210000; Count.u64 = 2; Min.u64 = 45000; Max.u64 = 216100; dirctrl.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.replacement_request_latency : Accumulator : Sum.u64 = 77948; SumSQ.u64 = 155896; Count.u64 = 38974; Min.u64 = 2; Max.u64 = 2; dirctrl.get_request_latency : Accumulator : Sum.u64 = 1479926; SumSQ.u64 = 54757262; Count.u64 = 39998; Min.u64 = 37; Max.u64 = 37; @@ -1374,8 +1442,10 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to dirctrl.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dirctrl.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dirctrl.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1394,6 +1464,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to dirctrl.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dirctrl.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_GetXResp : Accumulator : Sum.u64 = 39998; SumSQ.u64 = 39998; Count.u64 = 39998; Min.u64 = 1; Max.u64 = 1; @@ -1404,6 +1475,8 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to dirctrl.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dirctrl.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dirctrl.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dirctrl.MSHR_occupancy : Accumulator : Sum.u64 = 1399930; SumSQ.u64 = 1399930; Count.u64 = 5686165; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out index 776dcc2b18..b17266b1c5 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Kingsley.out @@ -646,17 +646,17 @@ krtr_data_8.send_bit_count.local1 : Accumulator : Sum.u64 = 999360; SumSQ.u64 = 575631360; Count.u64 = 1735; Min.u64 = 576; Max.u64 = 576; krtr_data_8.output_port_stalls.local1 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; krtr_data_8.xbar_stalls.local1 : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache_0:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 65; SumSQ.u64 = 115; Count.u64 = 41; Min.u64 = 1; Max.u64 = 3; - l2cache_0:memlink:data.packet_latency : Accumulator : Sum.u64 = 2574; SumSQ.u64 = 4950; Count.u64 = 1542; Min.u64 = 1; Max.u64 = 5; - l2cache_0:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 41; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1542; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1583; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1583; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 65; SumSQ.u64 = 115; Count.u64 = 41; Min.u64 = 1; Max.u64 = 3; + l2cache_0:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2574; SumSQ.u64 = 4950; Count.u64 = 1542; Min.u64 = 1; Max.u64 = 5; + l2cache_0:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 41; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1542; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1583; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1583; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_0:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1494; SumSQ.u64 = 1494; Count.u64 = 1494; Min.u64 = 1; Max.u64 = 1; l2cache_0:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 558; SumSQ.u64 = 558; Count.u64 = 558; Min.u64 = 1; Max.u64 = 1; @@ -664,7 +664,7 @@ l2cache_0.Prefetch_requests : Accumulator : Sum.u64 = 1494; SumSQ.u64 = 1494; Count.u64 = 1494; Min.u64 = 1; Max.u64 = 1; l2cache_0.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.evict_I : Accumulator : Sum.u64 = 1541; SumSQ.u64 = 1541; Count.u64 = 1541; Min.u64 = 1; Max.u64 = 1; + l2cache_0.evict_I : Accumulator : Sum.u64 = 1542; SumSQ.u64 = 1542; Count.u64 = 1542; Min.u64 = 1; Max.u64 = 1; l2cache_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -772,8 +772,11 @@ l2cache_0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -782,6 +785,9 @@ l2cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -806,6 +812,7 @@ l2cache_0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 1022; SumSQ.u64 = 1022; Count.u64 = 1022; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -881,10 +888,12 @@ l2cache_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_0.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -896,6 +905,9 @@ l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -968,13 +980,16 @@ l1cache_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -982,7 +997,7 @@ l1cache_0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache_0.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache_0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_M : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; l1cache_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1001,6 +1016,7 @@ l1cache_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 2025; SumSQ.u64 = 2025; Count.u64 = 2025; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 590; SumSQ.u64 = 590; Count.u64 = 590; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1047,14 +1063,18 @@ l1cache_0.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 150197; SumSQ.u64 = 1503143; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -1160,13 +1180,16 @@ l1cache_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1193,6 +1216,7 @@ l1cache_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 532; SumSQ.u64 = 532; Count.u64 = 532; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1239,14 +1263,18 @@ l1cache_1.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 150801; SumSQ.u64 = 1504879; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -1299,28 +1327,28 @@ ddr_0.cycles_with_issue : Accumulator : Sum.u64 = 2325; SumSQ.u64 = 2325; Count.u64 = 2325; Min.u64 = 1; Max.u64 = 1; ddr_0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 2646; SumSQ.u64 = 2646; Count.u64 = 2646; Min.u64 = 1; Max.u64 = 1; ddr_0.total_cycles : Accumulator : Sum.u64 = 15380; SumSQ.u64 = 236544400; Count.u64 = 1; Min.u64 = 15380; Max.u64 = 15380; - ddr_0:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 3813; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 10; - ddr_0:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink:data.packet_latency : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 30; Min.u64 = 0; Max.u64 = 1; - ddr_0:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; - ddr_0:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 30; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; - ddr_0:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; - ddr_0:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 5; Min.u64 = 0; Max.u64 = 1; - l2cache_1:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 54; SumSQ.u64 = 84; Count.u64 = 43; Min.u64 = 0; Max.u64 = 2; - l2cache_1:memlink:data.packet_latency : Accumulator : Sum.u64 = 2153; SumSQ.u64 = 3601; Count.u64 = 1542; Min.u64 = 0; Max.u64 = 4; - l2cache_1:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1542; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink:req.packet_latency : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 3813; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 10; + ddr_0:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink:data.packet_latency : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 30; Min.u64 = 0; Max.u64 = 1; + ddr_0:highlink.outoforder_req_events : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; + ddr_0:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 30; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; + ddr_0:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; + ddr_0:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 5; Min.u64 = 0; Max.u64 = 1; + l2cache_1:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 54; SumSQ.u64 = 84; Count.u64 = 43; Min.u64 = 0; Max.u64 = 2; + l2cache_1:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2153; SumSQ.u64 = 3601; Count.u64 = 1542; Min.u64 = 0; Max.u64 = 4; + l2cache_1:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1542; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_1:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; l2cache_1:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; @@ -1436,8 +1464,11 @@ l2cache_1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -1446,6 +1477,9 @@ l2cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1470,6 +1504,7 @@ l2cache_1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 1020; SumSQ.u64 = 1020; Count.u64 = 1020; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1545,10 +1580,12 @@ l2cache_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_1.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -1560,6 +1597,9 @@ l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1632,13 +1672,16 @@ l1cache_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1665,6 +1708,7 @@ l1cache_2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1711,14 +1755,18 @@ l1cache_2.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 146711; SumSQ.u64 = 1452001; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -1824,13 +1872,16 @@ l1cache_3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1857,6 +1908,7 @@ l1cache_3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 1943; SumSQ.u64 = 1943; Count.u64 = 1943; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXHit_Arrival : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1903,14 +1955,18 @@ l1cache_3.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 140233; SumSQ.u64 = 1379425; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -1949,17 +2005,17 @@ thread_21.cycles_max_issue : Accumulator : Sum.u64 = 979; SumSQ.u64 = 979; Count.u64 = 979; Min.u64 = 1; Max.u64 = 1; thread_21.cycles_max_reorder : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; thread_21.cycles : Accumulator : Sum.u64 = 14986; SumSQ.u64 = 14986; Count.u64 = 14986; Min.u64 = 1; Max.u64 = 1; - ddr_dc_0:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 3384; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 8; - ddr_dc_0:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink:data.packet_latency : Accumulator : Sum.u64 = 782; SumSQ.u64 = 812; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 2; - ddr_dc_0:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; - ddr_dc_0:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink:req.packet_latency : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 3384; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 8; + ddr_dc_0:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink:data.packet_latency : Accumulator : Sum.u64 = 782; SumSQ.u64 = 812; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 2; + ddr_dc_0:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.get_request_latency : Accumulator : Sum.u64 = 297943; SumSQ.u64 = 515914849; Count.u64 = 1734; Min.u64 = 20; Max.u64 = 8061; @@ -1982,8 +2038,10 @@ ddr_dc_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2002,6 +2060,7 @@ ddr_dc_0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_FetchInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; ddr_dc_0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_GetSResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; ddr_dc_0.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -2012,20 +2071,22 @@ ddr_dc_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_0.MSHR_occupancy : Accumulator : Sum.u64 = 294475; SumSQ.u64 = 4076469; Count.u64 = 27361; Min.u64 = 0; Max.u64 = 30; - l2cache_2:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 60; SumSQ.u64 = 106; Count.u64 = 42; Min.u64 = 0; Max.u64 = 3; - l2cache_2:memlink:data.packet_latency : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 4394; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; - l2cache_2:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 42; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 60; SumSQ.u64 = 106; Count.u64 = 42; Min.u64 = 0; Max.u64 = 3; + l2cache_2:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 4394; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; + l2cache_2:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 42; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1585; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_2:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; l2cache_2:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; @@ -2141,8 +2202,11 @@ l2cache_2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -2151,6 +2215,9 @@ l2cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2175,6 +2242,7 @@ l2cache_2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 1026; SumSQ.u64 = 1026; Count.u64 = 1026; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2250,10 +2318,12 @@ l2cache_2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_2.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -2265,6 +2335,9 @@ l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2337,13 +2410,16 @@ l1cache_4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2370,6 +2446,7 @@ l1cache_4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 1891; SumSQ.u64 = 1891; Count.u64 = 1891; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetXHit_Arrival : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2416,14 +2493,18 @@ l1cache_4.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 126573; SumSQ.u64 = 1225883; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -2529,13 +2610,16 @@ l1cache_5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2562,6 +2646,7 @@ l1cache_5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetXHit_Arrival : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2608,14 +2693,18 @@ l1cache_5.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 128766; SumSQ.u64 = 1248992; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -2654,17 +2743,17 @@ thread_23.cycles_max_issue : Accumulator : Sum.u64 = 984; SumSQ.u64 = 984; Count.u64 = 984; Min.u64 = 1; Max.u64 = 1; thread_23.cycles_max_reorder : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; thread_23.cycles : Accumulator : Sum.u64 = 13623; SumSQ.u64 = 13623; Count.u64 = 13623; Min.u64 = 1; Max.u64 = 1; - ddr_dc_1:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2479; SumSQ.u64 = 5043; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 14; - ddr_dc_1:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 10; SumSQ.u64 = 16; Count.u64 = 8; Min.u64 = 0; Max.u64 = 2; - ddr_dc_1:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink:data.packet_latency : Accumulator : Sum.u64 = 1554; SumSQ.u64 = 1668; Count.u64 = 1736; Min.u64 = 0; Max.u64 = 3; - ddr_dc_1:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 8; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1736; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3488; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3488; Min.u64 = 0; Max.u64 = 0; - ddr_dc_1:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink:req.packet_latency : Accumulator : Sum.u64 = 2479; SumSQ.u64 = 5043; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 14; + ddr_dc_1:highlink:ack.packet_latency : Accumulator : Sum.u64 = 10; SumSQ.u64 = 16; Count.u64 = 8; Min.u64 = 0; Max.u64 = 2; + ddr_dc_1:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink:data.packet_latency : Accumulator : Sum.u64 = 1554; SumSQ.u64 = 1668; Count.u64 = 1736; Min.u64 = 0; Max.u64 = 3; + ddr_dc_1:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 8; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1736; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3488; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3488; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.get_request_latency : Accumulator : Sum.u64 = 313844; SumSQ.u64 = 552407690; Count.u64 = 1744; Min.u64 = 20; Max.u64 = 8206; @@ -2687,8 +2776,10 @@ ddr_dc_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.AckInv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + ddr_dc_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2707,6 +2798,7 @@ ddr_dc_1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_FetchInvX : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; ddr_dc_1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_GetSResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; ddr_dc_1.eventSent_GetXResp : Accumulator : Sum.u64 = 1689; SumSQ.u64 = 1689; Count.u64 = 1689; Min.u64 = 1; Max.u64 = 1; @@ -2717,6 +2809,8 @@ ddr_dc_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_1.MSHR_occupancy : Accumulator : Sum.u64 = 310356; SumSQ.u64 = 4553528; Count.u64 = 27245; Min.u64 = 0; Max.u64 = 28; @@ -2734,28 +2828,28 @@ ddr_1.cycles_with_issue : Accumulator : Sum.u64 = 2359; SumSQ.u64 = 2359; Count.u64 = 2359; Min.u64 = 1; Max.u64 = 1; ddr_1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 2489; SumSQ.u64 = 2489; Count.u64 = 2489; Min.u64 = 1; Max.u64 = 1; ddr_1.total_cycles : Accumulator : Sum.u64 = 15380; SumSQ.u64 = 236544400; Count.u64 = 1; Min.u64 = 15380; Max.u64 = 15380; - ddr_1:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2894; SumSQ.u64 = 3638; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 7; - ddr_1:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink:data.packet_latency : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 30; Min.u64 = 0; Max.u64 = 1; - ddr_1:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; - ddr_1:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 30; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; - ddr_1:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; - ddr_1:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 58; SumSQ.u64 = 92; Count.u64 = 43; Min.u64 = 0; Max.u64 = 2; - l2cache_3:memlink:data.packet_latency : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 4121; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; - l2cache_3:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink:req.packet_latency : Accumulator : Sum.u64 = 2894; SumSQ.u64 = 3638; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 7; + ddr_1:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink:data.packet_latency : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 30; Min.u64 = 0; Max.u64 = 1; + ddr_1:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; + ddr_1:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 30; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; + ddr_1:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3406; Min.u64 = 0; Max.u64 = 1; + ddr_1:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 58; SumSQ.u64 = 92; Count.u64 = 43; Min.u64 = 0; Max.u64 = 2; + l2cache_3:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 4121; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; + l2cache_3:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_3:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1493; SumSQ.u64 = 1493; Count.u64 = 1493; Min.u64 = 1; Max.u64 = 1; l2cache_3:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; @@ -2871,8 +2965,11 @@ l2cache_3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -2881,6 +2978,9 @@ l2cache_3.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2905,6 +3005,7 @@ l2cache_3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXHit_Arrival : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2980,10 +3081,12 @@ l2cache_3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_3.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -2995,6 +3098,9 @@ l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3067,13 +3173,16 @@ l1cache_6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3100,6 +3209,7 @@ l1cache_6.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 1938; SumSQ.u64 = 1938; Count.u64 = 1938; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetXHit_Arrival : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3146,14 +3256,18 @@ l1cache_6.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 141079; SumSQ.u64 = 1391069; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -3259,13 +3373,16 @@ l1cache_7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3292,6 +3409,7 @@ l1cache_7.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 1864; SumSQ.u64 = 1864; Count.u64 = 1864; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetXHit_Arrival : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3338,14 +3456,18 @@ l1cache_7.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 122677; SumSQ.u64 = 1182757; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -3384,17 +3506,17 @@ thread_25.cycles_max_issue : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; thread_25.cycles_max_reorder : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; thread_25.cycles : Accumulator : Sum.u64 = 13441; SumSQ.u64 = 13441; Count.u64 = 13441; Min.u64 = 1; Max.u64 = 1; - ddr_dc_2:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2186; SumSQ.u64 = 3888; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 13; - ddr_dc_2:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink:data.packet_latency : Accumulator : Sum.u64 = 801; SumSQ.u64 = 831; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 3; - ddr_dc_2:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; - ddr_dc_2:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink:req.packet_latency : Accumulator : Sum.u64 = 2186; SumSQ.u64 = 3888; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 13; + ddr_dc_2:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink:data.packet_latency : Accumulator : Sum.u64 = 801; SumSQ.u64 = 831; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 3; + ddr_dc_2:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.get_request_latency : Accumulator : Sum.u64 = 297052; SumSQ.u64 = 550979494; Count.u64 = 1734; Min.u64 = 20; Max.u64 = 8521; @@ -3417,8 +3539,10 @@ ddr_dc_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3437,6 +3561,7 @@ ddr_dc_2.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_FetchInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; ddr_dc_2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_GetSResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; ddr_dc_2.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -3447,20 +3572,22 @@ ddr_dc_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_2.MSHR_occupancy : Accumulator : Sum.u64 = 293584; SumSQ.u64 = 4043488; Count.u64 = 27460; Min.u64 = 0; Max.u64 = 25; - l2cache_4:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 51; SumSQ.u64 = 67; Count.u64 = 43; Min.u64 = 1; Max.u64 = 2; - l2cache_4:memlink:data.packet_latency : Accumulator : Sum.u64 = 1844; SumSQ.u64 = 2640; Count.u64 = 1541; Min.u64 = 0; Max.u64 = 4; - l2cache_4:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1541; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 51; SumSQ.u64 = 67; Count.u64 = 43; Min.u64 = 1; Max.u64 = 2; + l2cache_4:lowlink:data.packet_latency : Accumulator : Sum.u64 = 1844; SumSQ.u64 = 2640; Count.u64 = 1541; Min.u64 = 0; Max.u64 = 4; + l2cache_4:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1541; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_4:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; l2cache_4:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 687; SumSQ.u64 = 687; Count.u64 = 687; Min.u64 = 1; Max.u64 = 1; @@ -3576,8 +3703,11 @@ l2cache_4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -3586,6 +3716,9 @@ l2cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3610,6 +3743,7 @@ l2cache_4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 1019; SumSQ.u64 = 1019; Count.u64 = 1019; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXHit_Arrival : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3685,10 +3819,12 @@ l2cache_4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSResp_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutS_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_4.PutM_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l2cache_4.PutE_recv : Accumulator : Sum.u64 = 302; SumSQ.u64 = 302; Count.u64 = 302; Min.u64 = 1; Max.u64 = 1; @@ -3700,6 +3836,9 @@ l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_4.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FetchXResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache_4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3772,13 +3911,16 @@ l1cache_8.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3805,6 +3947,7 @@ l1cache_8.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 1925; SumSQ.u64 = 1925; Count.u64 = 1925; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXHit_Arrival : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3851,14 +3994,18 @@ l1cache_8.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache_8.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 204520; SumSQ.u64 = 2089602; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -3964,13 +4111,16 @@ l1cache_9.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3997,6 +4147,7 @@ l1cache_9.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 1977; SumSQ.u64 = 1977; Count.u64 = 1977; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXHit_Arrival : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4043,14 +4194,18 @@ l1cache_9.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 206240; SumSQ.u64 = 2111790; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -4089,17 +4244,17 @@ thread_27.cycles_max_issue : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; thread_27.cycles_max_reorder : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; thread_27.cycles : Accumulator : Sum.u64 = 20877; SumSQ.u64 = 20877; Count.u64 = 20877; Min.u64 = 1; Max.u64 = 1; - ddr_dc_3:cpulink:req.packet_latency : Accumulator : Sum.u64 = 1878; SumSQ.u64 = 2700; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 11; - ddr_dc_3:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink:data.packet_latency : Accumulator : Sum.u64 = 1738; SumSQ.u64 = 2080; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 4; - ddr_dc_3:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; - ddr_dc_3:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink:req.packet_latency : Accumulator : Sum.u64 = 1878; SumSQ.u64 = 2700; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 11; + ddr_dc_3:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink:data.packet_latency : Accumulator : Sum.u64 = 1738; SumSQ.u64 = 2080; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 4; + ddr_dc_3:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.get_request_latency : Accumulator : Sum.u64 = 307841; SumSQ.u64 = 522173475; Count.u64 = 1735; Min.u64 = 22; Max.u64 = 6940; @@ -4122,8 +4277,10 @@ ddr_dc_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4142,6 +4299,7 @@ ddr_dc_3.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_FetchInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_GetSResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_3.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -4152,6 +4310,8 @@ ddr_dc_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_3.MSHR_occupancy : Accumulator : Sum.u64 = 304371; SumSQ.u64 = 4269649; Count.u64 = 27452; Min.u64 = 0; Max.u64 = 23; @@ -4169,28 +4329,28 @@ ddr_2.cycles_with_issue : Accumulator : Sum.u64 = 2415; SumSQ.u64 = 2415; Count.u64 = 2415; Min.u64 = 1; Max.u64 = 1; ddr_2.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 2180; SumSQ.u64 = 2180; Count.u64 = 2180; Min.u64 = 1; Max.u64 = 1; ddr_2.total_cycles : Accumulator : Sum.u64 = 15380; SumSQ.u64 = 236544400; Count.u64 = 1; Min.u64 = 15380; Max.u64 = 15380; - ddr_2:cpulink:req.packet_latency : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 7071; Count.u64 = 3376; Min.u64 = 1; Max.u64 = 6; - ddr_2:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink:data.packet_latency : Accumulator : Sum.u64 = 40; SumSQ.u64 = 60; Count.u64 = 32; Min.u64 = 1; Max.u64 = 3; - ddr_2:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; - ddr_2:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 32; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 7; SumSQ.u64 = 11; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 2; - ddr_2:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 5; SumSQ.u64 = 7; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 2; - ddr_2:cpulink.ordering_latency : Accumulator : Sum.u64 = 5; SumSQ.u64 = 7; Count.u64 = 4; Min.u64 = 1; Max.u64 = 2; - l2cache_5:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 49; SumSQ.u64 = 71; Count.u64 = 41; Min.u64 = 0; Max.u64 = 2; - l2cache_5:memlink:data.packet_latency : Accumulator : Sum.u64 = 2067; SumSQ.u64 = 3347; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; - l2cache_5:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 41; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink:req.packet_latency : Accumulator : Sum.u64 = 4499; SumSQ.u64 = 7071; Count.u64 = 3376; Min.u64 = 1; Max.u64 = 6; + ddr_2:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink:data.packet_latency : Accumulator : Sum.u64 = 40; SumSQ.u64 = 60; Count.u64 = 32; Min.u64 = 1; Max.u64 = 3; + ddr_2:highlink.outoforder_req_events : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; + ddr_2:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 32; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 7; SumSQ.u64 = 11; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 2; + ddr_2:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 5; SumSQ.u64 = 7; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 2; + ddr_2:highlink.ordering_latency : Accumulator : Sum.u64 = 5; SumSQ.u64 = 7; Count.u64 = 4; Min.u64 = 1; Max.u64 = 2; + l2cache_5:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 49; SumSQ.u64 = 71; Count.u64 = 41; Min.u64 = 0; Max.u64 = 2; + l2cache_5:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2067; SumSQ.u64 = 3347; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; + l2cache_5:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 41; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1584; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_5:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1491; SumSQ.u64 = 1491; Count.u64 = 1491; Min.u64 = 1; Max.u64 = 1; l2cache_5:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; @@ -4306,8 +4466,11 @@ l2cache_5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -4316,6 +4479,9 @@ l2cache_5.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4340,6 +4506,7 @@ l2cache_5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 1006; SumSQ.u64 = 1006; Count.u64 = 1006; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXHit_Arrival : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4415,10 +4582,12 @@ l2cache_5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_5.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -4430,6 +4599,9 @@ l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_5.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4502,13 +4674,16 @@ l1cache_10.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4535,6 +4710,7 @@ l1cache_10.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 2004; SumSQ.u64 = 2004; Count.u64 = 2004; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetXHit_Arrival : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 489; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4581,14 +4757,18 @@ l1cache_10.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 197504; SumSQ.u64 = 2017614; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -4694,13 +4874,16 @@ l1cache_11.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4727,6 +4910,7 @@ l1cache_11.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 1901; SumSQ.u64 = 1901; Count.u64 = 1901; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetXHit_Arrival : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4773,14 +4957,18 @@ l1cache_11.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 204102; SumSQ.u64 = 2082728; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -4819,17 +5007,17 @@ thread_29.cycles_max_issue : Accumulator : Sum.u64 = 971; SumSQ.u64 = 971; Count.u64 = 971; Min.u64 = 1; Max.u64 = 1; thread_29.cycles_max_reorder : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; thread_29.cycles : Accumulator : Sum.u64 = 20769; SumSQ.u64 = 20769; Count.u64 = 20769; Min.u64 = 1; Max.u64 = 1; - ddr_dc_4:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2203; SumSQ.u64 = 3949; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 14; - ddr_dc_4:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2430; SumSQ.u64 = 3858; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 3; - ddr_dc_4:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; - ddr_dc_4:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink:req.packet_latency : Accumulator : Sum.u64 = 2203; SumSQ.u64 = 3949; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 14; + ddr_dc_4:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink:data.packet_latency : Accumulator : Sum.u64 = 2430; SumSQ.u64 = 3858; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 3; + ddr_dc_4:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.get_request_latency : Accumulator : Sum.u64 = 290759; SumSQ.u64 = 522461245; Count.u64 = 1735; Min.u64 = 20; Max.u64 = 8263; @@ -4852,8 +5040,10 @@ ddr_dc_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4872,6 +5062,7 @@ ddr_dc_4.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_FetchInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_GetSResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_4.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -4882,20 +5073,22 @@ ddr_dc_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_4.MSHR_occupancy : Accumulator : Sum.u64 = 287289; SumSQ.u64 = 3786953; Count.u64 = 27506; Min.u64 = 0; Max.u64 = 21; - l2cache_6:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 64; SumSQ.u64 = 112; Count.u64 = 43; Min.u64 = 0; Max.u64 = 3; - l2cache_6:memlink:data.packet_latency : Accumulator : Sum.u64 = 2398; SumSQ.u64 = 4640; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 5; - l2cache_6:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 64; SumSQ.u64 = 112; Count.u64 = 43; Min.u64 = 0; Max.u64 = 3; + l2cache_6:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2398; SumSQ.u64 = 4640; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 5; + l2cache_6:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_6:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1486; SumSQ.u64 = 1486; Count.u64 = 1486; Min.u64 = 1; Max.u64 = 1; l2cache_6:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -5011,8 +5204,11 @@ l2cache_6.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -5021,6 +5217,9 @@ l2cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5045,6 +5244,7 @@ l2cache_6.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXHit_Arrival : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5120,10 +5320,12 @@ l2cache_6.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_6.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_6.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -5135,6 +5337,9 @@ l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_6.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5207,13 +5412,16 @@ l1cache_12.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5240,6 +5448,7 @@ l1cache_12.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 1943; SumSQ.u64 = 1943; Count.u64 = 1943; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetXHit_Arrival : Accumulator : Sum.u64 = 538; SumSQ.u64 = 538; Count.u64 = 538; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5286,14 +5495,18 @@ l1cache_12.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 198372; SumSQ.u64 = 2026492; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -5399,13 +5612,16 @@ l1cache_13.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5432,6 +5648,7 @@ l1cache_13.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 1856; SumSQ.u64 = 1856; Count.u64 = 1856; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetXHit_Arrival : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5478,14 +5695,18 @@ l1cache_13.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 206649; SumSQ.u64 = 2110951; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -5524,17 +5745,17 @@ thread_31.cycles_max_issue : Accumulator : Sum.u64 = 973; SumSQ.u64 = 973; Count.u64 = 973; Min.u64 = 1; Max.u64 = 1; thread_31.cycles_max_reorder : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; thread_31.cycles : Accumulator : Sum.u64 = 21020; SumSQ.u64 = 21020; Count.u64 = 21020; Min.u64 = 1; Max.u64 = 1; - ddr_dc_5:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2444; SumSQ.u64 = 4524; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 10; - ddr_dc_5:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_5:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_5:cpulink:data.packet_latency : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1798; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 4; - ddr_dc_5:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 1; - ddr_dc_5:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_5:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_5:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; - ddr_dc_5:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; - ddr_dc_5:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; - ddr_dc_5:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + ddr_dc_5:highlink:req.packet_latency : Accumulator : Sum.u64 = 2444; SumSQ.u64 = 4524; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 10; + ddr_dc_5:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5:highlink:data.packet_latency : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1798; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 4; + ddr_dc_5:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 1; + ddr_dc_5:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; + ddr_dc_5:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; + ddr_dc_5:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; ddr_dc_5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.get_request_latency : Accumulator : Sum.u64 = 309969; SumSQ.u64 = 584772755; Count.u64 = 1735; Min.u64 = 20; Max.u64 = 8656; @@ -5557,8 +5778,10 @@ ddr_dc_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5577,6 +5800,7 @@ ddr_dc_5.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_FetchInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_GetSResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_5.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -5587,6 +5811,8 @@ ddr_dc_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_5.MSHR_occupancy : Accumulator : Sum.u64 = 306499; SumSQ.u64 = 4384161; Count.u64 = 27353; Min.u64 = 0; Max.u64 = 25; @@ -5604,28 +5830,28 @@ ddr_3.cycles_with_issue : Accumulator : Sum.u64 = 2583; SumSQ.u64 = 2583; Count.u64 = 2583; Min.u64 = 1; Max.u64 = 1; ddr_3.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 1545; SumSQ.u64 = 1545; Count.u64 = 1545; Min.u64 = 1; Max.u64 = 1; ddr_3.total_cycles : Accumulator : Sum.u64 = 15380; SumSQ.u64 = 236544400; Count.u64 = 1; Min.u64 = 15380; Max.u64 = 15380; - ddr_3:cpulink:req.packet_latency : Accumulator : Sum.u64 = 4463; SumSQ.u64 = 6749; Count.u64 = 3376; Min.u64 = 1; Max.u64 = 5; - ddr_3:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink:data.packet_latency : Accumulator : Sum.u64 = 46; SumSQ.u64 = 74; Count.u64 = 32; Min.u64 = 1; Max.u64 = 2; - ddr_3:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; - ddr_3:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 32; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 1; - ddr_3:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 1; - ddr_3:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 2; Min.u64 = 1; Max.u64 = 2; - l2cache_7:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 54; SumSQ.u64 = 80; Count.u64 = 43; Min.u64 = 0; Max.u64 = 2; - l2cache_7:memlink:data.packet_latency : Accumulator : Sum.u64 = 2080; SumSQ.u64 = 3386; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; - l2cache_7:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink:req.packet_latency : Accumulator : Sum.u64 = 4463; SumSQ.u64 = 6749; Count.u64 = 3376; Min.u64 = 1; Max.u64 = 5; + ddr_3:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink:data.packet_latency : Accumulator : Sum.u64 = 46; SumSQ.u64 = 74; Count.u64 = 32; Min.u64 = 1; Max.u64 = 2; + ddr_3:highlink.outoforder_req_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 3376; Min.u64 = 0; Max.u64 = 1; + ddr_3:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 32; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 1; + ddr_3:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 3408; Min.u64 = 0; Max.u64 = 1; + ddr_3:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 2; Min.u64 = 1; Max.u64 = 2; + l2cache_7:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 54; SumSQ.u64 = 80; Count.u64 = 43; Min.u64 = 0; Max.u64 = 2; + l2cache_7:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2080; SumSQ.u64 = 3386; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 4; + l2cache_7:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 43; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1543; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1586; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_7:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; l2cache_7:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 567; SumSQ.u64 = 567; Count.u64 = 567; Min.u64 = 1; Max.u64 = 1; @@ -5741,8 +5967,11 @@ l2cache_7.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -5751,6 +5980,9 @@ l2cache_7.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5775,6 +6007,7 @@ l2cache_7.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXHit_Arrival : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5850,10 +6083,12 @@ l2cache_7.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXResp_recv : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_7.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_7.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -5865,6 +6100,9 @@ l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_7.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5937,13 +6175,16 @@ l1cache_14.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5970,6 +6211,7 @@ l1cache_14.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetXHit_Arrival : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6016,14 +6258,18 @@ l1cache_14.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 212025; SumSQ.u64 = 2169677; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -6129,13 +6375,16 @@ l1cache_15.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6162,6 +6411,7 @@ l1cache_15.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 1915; SumSQ.u64 = 1915; Count.u64 = 1915; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetXHit_Arrival : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6208,14 +6458,18 @@ l1cache_15.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 208647; SumSQ.u64 = 2134453; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -6254,17 +6508,17 @@ thread_33.cycles_max_issue : Accumulator : Sum.u64 = 961; SumSQ.u64 = 961; Count.u64 = 961; Min.u64 = 1; Max.u64 = 1; thread_33.cycles_max_reorder : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; thread_33.cycles : Accumulator : Sum.u64 = 21232; SumSQ.u64 = 21232; Count.u64 = 21232; Min.u64 = 1; Max.u64 = 1; - ddr_dc_6:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2203; SumSQ.u64 = 3903; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 13; - ddr_dc_6:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 4465; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 5; - ddr_dc_6:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; - ddr_dc_6:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink:req.packet_latency : Accumulator : Sum.u64 = 2203; SumSQ.u64 = 3903; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 13; + ddr_dc_6:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink:data.packet_latency : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 4465; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 5; + ddr_dc_6:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1734; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3468; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.get_request_latency : Accumulator : Sum.u64 = 298389; SumSQ.u64 = 420122117; Count.u64 = 1734; Min.u64 = 20; Max.u64 = 7133; @@ -6287,8 +6541,10 @@ ddr_dc_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6307,6 +6563,7 @@ ddr_dc_6.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_FetchInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; ddr_dc_6.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_GetSResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; ddr_dc_6.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -6317,20 +6574,22 @@ ddr_dc_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_6.MSHR_occupancy : Accumulator : Sum.u64 = 294921; SumSQ.u64 = 4051321; Count.u64 = 27562; Min.u64 = 0; Max.u64 = 26; - l2cache_8:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 56; SumSQ.u64 = 88; Count.u64 = 44; Min.u64 = 0; Max.u64 = 2; - l2cache_8:memlink:data.packet_latency : Accumulator : Sum.u64 = 2122; SumSQ.u64 = 3508; Count.u64 = 1545; Min.u64 = 0; Max.u64 = 4; - l2cache_8:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 44; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1545; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1589; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1589; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 56; SumSQ.u64 = 88; Count.u64 = 44; Min.u64 = 0; Max.u64 = 2; + l2cache_8:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2122; SumSQ.u64 = 3508; Count.u64 = 1545; Min.u64 = 0; Max.u64 = 4; + l2cache_8:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 44; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1545; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1589; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1589; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8:prefetcher.prefetch_opportunities : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_8:prefetcher.prefetches_issued : Accumulator : Sum.u64 = 1488; SumSQ.u64 = 1488; Count.u64 = 1488; Min.u64 = 1; Max.u64 = 1; l2cache_8:prefetcher.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; @@ -6446,8 +6705,11 @@ l2cache_8.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -6456,6 +6718,9 @@ l2cache_8.eventSent_GetXResp : Accumulator : Sum.u64 = 1500; SumSQ.u64 = 1500; Count.u64 = 1500; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6480,6 +6745,7 @@ l2cache_8.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 1007; Count.u64 = 1007; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXHit_Arrival : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6555,10 +6821,12 @@ l2cache_8.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXResp_recv : Accumulator : Sum.u64 = 1505; SumSQ.u64 = 1505; Count.u64 = 1505; Min.u64 = 1; Max.u64 = 1; l2cache_8.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache_8.PutE_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; @@ -6570,6 +6838,9 @@ l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_8.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6642,13 +6913,16 @@ l1cache_16.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_16.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_16.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6675,6 +6949,7 @@ l1cache_16.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.GetSHit_Arrival : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache_16.GetXHit_Arrival : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l1cache_16.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6721,14 +6996,18 @@ l1cache_16.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_16.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.MSHR_occupancy : Accumulator : Sum.u64 = 229885; SumSQ.u64 = 2372817; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -6834,13 +7113,16 @@ l1cache_17.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_GetSResp : Accumulator : Sum.u64 = 4000; SumSQ.u64 = 4000; Count.u64 = 4000; Min.u64 = 1; Max.u64 = 1; l1cache_17.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_WriteResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_17.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6867,6 +7149,7 @@ l1cache_17.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.GetSHit_Arrival : Accumulator : Sum.u64 = 2186; SumSQ.u64 = 2186; Count.u64 = 2186; Min.u64 = 1; Max.u64 = 1; l1cache_17.GetXHit_Arrival : Accumulator : Sum.u64 = 664; SumSQ.u64 = 664; Count.u64 = 664; Min.u64 = 1; Max.u64 = 1; l1cache_17.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6913,14 +7196,18 @@ l1cache_17.Write_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_17.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.MSHR_occupancy : Accumulator : Sum.u64 = 190633; SumSQ.u64 = 1958261; Count.u64 = 23043; Min.u64 = 0; Max.u64 = 11; @@ -6959,17 +7246,17 @@ thread_35.cycles_max_issue : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; thread_35.cycles_max_reorder : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; thread_35.cycles : Accumulator : Sum.u64 = 19021; SumSQ.u64 = 19021; Count.u64 = 19021; Min.u64 = 1; Max.u64 = 1; - ddr_dc_7:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2449; SumSQ.u64 = 4771; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 13; - ddr_dc_7:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_7:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_7:cpulink:data.packet_latency : Accumulator : Sum.u64 = 1703; SumSQ.u64 = 2005; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 3; - ddr_dc_7:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 1; - ddr_dc_7:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_7:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_dc_7:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; - ddr_dc_7:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; - ddr_dc_7:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; - ddr_dc_7:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + ddr_dc_7:highlink:req.packet_latency : Accumulator : Sum.u64 = 2449; SumSQ.u64 = 4771; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 13; + ddr_dc_7:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7:highlink:data.packet_latency : Accumulator : Sum.u64 = 1703; SumSQ.u64 = 2005; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 3; + ddr_dc_7:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 1; + ddr_dc_7:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1735; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; + ddr_dc_7:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 3470; Min.u64 = 0; Max.u64 = 1; + ddr_dc_7:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; ddr_dc_7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.get_request_latency : Accumulator : Sum.u64 = 301846; SumSQ.u64 = 618091116; Count.u64 = 1735; Min.u64 = 20; Max.u64 = 8276; @@ -6992,8 +7279,10 @@ ddr_dc_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7012,6 +7301,7 @@ ddr_dc_7.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_FetchInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_7.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_GetSResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; ddr_dc_7.eventSent_GetXResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; @@ -7022,6 +7312,8 @@ ddr_dc_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_dc_7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; ddr_dc_7.MSHR_occupancy : Accumulator : Sum.u64 = 298376; SumSQ.u64 = 4232550; Count.u64 = 27261; Min.u64 = 0; Max.u64 = 25; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out index aeade7c58b..01083d9de0 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_MemoryCache.out @@ -2606,32 +2606,32 @@ Model complete hbm_0.cycles_with_issue : Accumulator : Sum.u64 = 4089; SumSQ.u64 = 4089; Count.u64 = 4089; Min.u64 = 1; Max.u64 = 1; hbm_0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_0.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_0:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8238; SumSQ.u64 = 38228; Count.u64 = 2322; Min.u64 = 0; Max.u64 = 25; - hbm_0:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_0:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_0:cpulink:data.packet_latency : Accumulator : Sum.u64 = 6244; SumSQ.u64 = 23718; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 11; - hbm_0:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 2322; Min.u64 = 0; Max.u64 = 1; - hbm_0:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_0:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_0:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 0; - hbm_0:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 4610; Min.u64 = 0; Max.u64 = 1; - hbm_0:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4610; Min.u64 = 0; Max.u64 = 1; - hbm_0:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + hbm_0:highlink:req.packet_latency : Accumulator : Sum.u64 = 8238; SumSQ.u64 = 38228; Count.u64 = 2322; Min.u64 = 0; Max.u64 = 25; + hbm_0:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_0:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_0:highlink:data.packet_latency : Accumulator : Sum.u64 = 6244; SumSQ.u64 = 23718; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 11; + hbm_0:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 2322; Min.u64 = 0; Max.u64 = 1; + hbm_0:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_0:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_0:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 0; + hbm_0:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 4610; Min.u64 = 0; Max.u64 = 1; + hbm_0:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4610; Min.u64 = 0; Max.u64 = 1; + hbm_0:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; hbm_0.CacheHits_Read : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; hbm_0.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_0.CacheHits_Write : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; hbm_0.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2658; SumSQ.u64 = 11872; Count.u64 = 699; Min.u64 = 0; Max.u64 = 8; - l2cache_0:memlink:data.packet_latency : Accumulator : Sum.u64 = 3483; SumSQ.u64 = 19455; Count.u64 = 780; Min.u64 = 0; Max.u64 = 18; - l2cache_0:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 699; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 780; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1479; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1479; Min.u64 = 0; Max.u64 = 0; - l2cache_0:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2658; SumSQ.u64 = 11872; Count.u64 = 699; Min.u64 = 0; Max.u64 = 8; + l2cache_0:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3483; SumSQ.u64 = 19455; Count.u64 = 780; Min.u64 = 0; Max.u64 = 18; + l2cache_0:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 699; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 780; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1479; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1479; Min.u64 = 0; Max.u64 = 0; + l2cache_0:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_0.prefetches_issued : Accumulator : Sum.u64 = 740; SumSQ.u64 = 740; Count.u64 = 740; Min.u64 = 1; Max.u64 = 1; l2cache_0.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; @@ -2639,7 +2639,7 @@ Model complete l2cache_0.Prefetch_requests : Accumulator : Sum.u64 = 740; SumSQ.u64 = 740; Count.u64 = 740; Min.u64 = 1; Max.u64 = 1; l2cache_0.Prefetch_drops : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_0.evict_I : Accumulator : Sum.u64 = 771; SumSQ.u64 = 771; Count.u64 = 771; Min.u64 = 1; Max.u64 = 1; + l2cache_0.evict_I : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; l2cache_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2747,8 +2747,11 @@ Model complete l2cache_0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; @@ -2757,6 +2760,9 @@ Model complete l2cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 730; SumSQ.u64 = 730; Count.u64 = 730; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2781,6 +2787,7 @@ Model complete l2cache_0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2856,10 +2863,12 @@ Model complete l2cache_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l2cache_0.GetXResp_recv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; l2cache_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2871,6 +2880,9 @@ Model complete l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; l2cache_0.FetchResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; + l2cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckInv_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; l2cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2943,13 +2955,16 @@ Model complete l1cache_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2957,7 +2972,7 @@ Model complete l1cache_0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.evict_I : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; + l1cache_0.evict_I : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; l1cache_0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2976,6 +2991,7 @@ Model complete l1cache_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3022,14 +3038,18 @@ Model complete l1cache_0.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l1cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 224212; SumSQ.u64 = 4076594; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -3118,13 +3138,16 @@ Model complete l1cache_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3151,6 +3174,7 @@ Model complete l1cache_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3197,14 +3221,18 @@ Model complete l1cache_1.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; + l1cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 242141; SumSQ.u64 = 4439193; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -3226,17 +3254,17 @@ Model complete core_1.cycles_max_issue : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; core_1.cycles_max_reorder : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; core_1.cycles : Accumulator : Sum.u64 = 13879; SumSQ.u64 = 13879; Count.u64 = 13879; Min.u64 = 1; Max.u64 = 1; - dc_0:cpulink:req.packet_latency : Accumulator : Sum.u64 = 3286; SumSQ.u64 = 15148; Count.u64 = 875; Min.u64 = 0; Max.u64 = 15; - dc_0:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 250; SumSQ.u64 = 784; Count.u64 = 101; Min.u64 = 0; Max.u64 = 5; - dc_0:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_0:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 14098; Count.u64 = 774; Min.u64 = 0; Max.u64 = 22; - dc_0:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 875; Min.u64 = 0; Max.u64 = 0; - dc_0:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 101; Min.u64 = 0; Max.u64 = 0; - dc_0:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_0:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 774; Min.u64 = 0; Max.u64 = 1; - dc_0:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_0:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_0:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1; Min.u64 = 0; Max.u64 = 0; + dc_0:highlink:req.packet_latency : Accumulator : Sum.u64 = 3286; SumSQ.u64 = 15148; Count.u64 = 875; Min.u64 = 0; Max.u64 = 15; + dc_0:highlink:ack.packet_latency : Accumulator : Sum.u64 = 250; SumSQ.u64 = 784; Count.u64 = 101; Min.u64 = 0; Max.u64 = 5; + dc_0:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_0:highlink:data.packet_latency : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 14098; Count.u64 = 774; Min.u64 = 0; Max.u64 = 22; + dc_0:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 875; Min.u64 = 0; Max.u64 = 0; + dc_0:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 101; Min.u64 = 0; Max.u64 = 0; + dc_0:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_0:highlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 774; Min.u64 = 0; Max.u64 = 1; + dc_0:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_0:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_0:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1; Min.u64 = 0; Max.u64 = 0; dc_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.get_request_latency : Accumulator : Sum.u64 = 180002; SumSQ.u64 = 410905528; Count.u64 = 875; Min.u64 = 16; Max.u64 = 13344; @@ -3259,8 +3287,10 @@ Model complete dc_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.AckInv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + dc_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3279,6 +3309,7 @@ Model complete dc_0.eventSent_FetchInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; dc_0.eventSent_FetchInvX : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; dc_0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.eventSent_GetSResp : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; dc_0.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -3289,6 +3320,8 @@ Model complete dc_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_0.MSHR_occupancy : Accumulator : Sum.u64 = 178252; SumSQ.u64 = 2332538; Count.u64 = 18239; Min.u64 = 0; Max.u64 = 28; @@ -3306,32 +3339,32 @@ Model complete hbm_1.cycles_with_issue : Accumulator : Sum.u64 = 4062; SumSQ.u64 = 4062; Count.u64 = 4062; Min.u64 = 1; Max.u64 = 1; hbm_1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_1.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_1:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8190; SumSQ.u64 = 37302; Count.u64 = 2299; Min.u64 = 0; Max.u64 = 18; - hbm_1:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_1:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_1:cpulink:data.packet_latency : Accumulator : Sum.u64 = 13628; SumSQ.u64 = 99316; Count.u64 = 2290; Min.u64 = 0; Max.u64 = 71; - hbm_1:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2299; Min.u64 = 0; Max.u64 = 1; - hbm_1:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_1:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_1:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2290; Min.u64 = 0; Max.u64 = 0; - hbm_1:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 4589; Min.u64 = 0; Max.u64 = 1; - hbm_1:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 4589; Min.u64 = 0; Max.u64 = 1; - hbm_1:cpulink.ordering_latency : Accumulator : Sum.u64 = 7; SumSQ.u64 = 37; Count.u64 = 2; Min.u64 = 1; Max.u64 = 6; + hbm_1:highlink:req.packet_latency : Accumulator : Sum.u64 = 8190; SumSQ.u64 = 37302; Count.u64 = 2299; Min.u64 = 0; Max.u64 = 18; + hbm_1:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_1:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_1:highlink:data.packet_latency : Accumulator : Sum.u64 = 13628; SumSQ.u64 = 99316; Count.u64 = 2290; Min.u64 = 0; Max.u64 = 71; + hbm_1:highlink.outoforder_req_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2299; Min.u64 = 0; Max.u64 = 1; + hbm_1:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_1:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_1:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2290; Min.u64 = 0; Max.u64 = 0; + hbm_1:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 4589; Min.u64 = 0; Max.u64 = 1; + hbm_1:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 4589; Min.u64 = 0; Max.u64 = 1; + hbm_1:highlink.ordering_latency : Accumulator : Sum.u64 = 7; SumSQ.u64 = 37; Count.u64 = 2; Min.u64 = 1; Max.u64 = 6; hbm_1.CacheHits_Read : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; hbm_1.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_1.CacheHits_Write : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; hbm_1.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2405; SumSQ.u64 = 9809; Count.u64 = 703; Min.u64 = 0; Max.u64 = 7; - l2cache_1:memlink:data.packet_latency : Accumulator : Sum.u64 = 3360; SumSQ.u64 = 19536; Count.u64 = 784; Min.u64 = 0; Max.u64 = 17; - l2cache_1:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 703; Min.u64 = 0; Max.u64 = 1; - l2cache_1:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 784; Min.u64 = 0; Max.u64 = 0; - l2cache_1:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 1; - l2cache_1:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 1; - l2cache_1:memlink.ordering_latency : Accumulator : Sum.u64 = 14; SumSQ.u64 = 38; Count.u64 = 6; Min.u64 = 1; Max.u64 = 4; + l2cache_1:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2405; SumSQ.u64 = 9809; Count.u64 = 703; Min.u64 = 0; Max.u64 = 7; + l2cache_1:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3360; SumSQ.u64 = 19536; Count.u64 = 784; Min.u64 = 0; Max.u64 = 17; + l2cache_1:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 703; Min.u64 = 0; Max.u64 = 1; + l2cache_1:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 784; Min.u64 = 0; Max.u64 = 0; + l2cache_1:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 1; + l2cache_1:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 1; + l2cache_1:lowlink.ordering_latency : Accumulator : Sum.u64 = 14; SumSQ.u64 = 38; Count.u64 = 6; Min.u64 = 1; Max.u64 = 4; l2cache_1.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_1.prefetches_issued : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; l2cache_1.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 434; SumSQ.u64 = 434; Count.u64 = 434; Min.u64 = 1; Max.u64 = 1; @@ -3447,8 +3480,11 @@ Model complete l2cache_1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; @@ -3457,6 +3493,9 @@ Model complete l2cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3481,6 +3520,7 @@ Model complete l2cache_1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3556,10 +3596,12 @@ Model complete l2cache_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_1.GetXResp_recv : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; l2cache_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3571,6 +3613,9 @@ Model complete l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; + l2cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckInv_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; l2cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3643,13 +3688,16 @@ Model complete l1cache_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3676,6 +3724,7 @@ Model complete l1cache_2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 606; SumSQ.u64 = 606; Count.u64 = 606; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3722,14 +3771,18 @@ Model complete l1cache_2.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l1cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; + l1cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 255490; SumSQ.u64 = 4589520; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -3818,13 +3871,16 @@ Model complete l1cache_3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3851,6 +3907,7 @@ Model complete l1cache_3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 551; SumSQ.u64 = 551; Count.u64 = 551; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXHit_Arrival : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3897,14 +3954,18 @@ Model complete l1cache_3.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache_3.GetXResp_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; l1cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l1cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_3.MSHR_occupancy : Accumulator : Sum.u64 = 273428; SumSQ.u64 = 5044238; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -3926,17 +3987,17 @@ Model complete core_3.cycles_max_issue : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; core_3.cycles_max_reorder : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; core_3.cycles : Accumulator : Sum.u64 = 15499; SumSQ.u64 = 15499; Count.u64 = 15499; Min.u64 = 1; Max.u64 = 1; - dc_1:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2976; SumSQ.u64 = 12842; Count.u64 = 876; Min.u64 = 0; Max.u64 = 14; - dc_1:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 213; SumSQ.u64 = 555; Count.u64 = 101; Min.u64 = 0; Max.u64 = 4; - dc_1:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink:data.packet_latency : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 7301; Count.u64 = 775; Min.u64 = 0; Max.u64 = 9; - dc_1:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 876; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 101; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; - dc_1:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink:req.packet_latency : Accumulator : Sum.u64 = 2976; SumSQ.u64 = 12842; Count.u64 = 876; Min.u64 = 0; Max.u64 = 14; + dc_1:highlink:ack.packet_latency : Accumulator : Sum.u64 = 213; SumSQ.u64 = 555; Count.u64 = 101; Min.u64 = 0; Max.u64 = 4; + dc_1:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink:data.packet_latency : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 7301; Count.u64 = 775; Min.u64 = 0; Max.u64 = 9; + dc_1:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 876; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 101; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; + dc_1:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.get_request_latency : Accumulator : Sum.u64 = 175785; SumSQ.u64 = 89362497; Count.u64 = 876; Min.u64 = 16; Max.u64 = 3515; @@ -3959,8 +4020,10 @@ Model complete dc_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.AckInv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + dc_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3979,6 +4042,7 @@ Model complete dc_1.eventSent_FetchInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; dc_1.eventSent_FetchInvX : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; dc_1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.eventSent_GetSResp : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; dc_1.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -3989,20 +4053,22 @@ Model complete dc_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_1.MSHR_occupancy : Accumulator : Sum.u64 = 174033; SumSQ.u64 = 2252839; Count.u64 = 18271; Min.u64 = 0; Max.u64 = 27; - l2cache_2:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2263; SumSQ.u64 = 8623; Count.u64 = 700; Min.u64 = 0; Max.u64 = 7; - l2cache_2:memlink:data.packet_latency : Accumulator : Sum.u64 = 3315; SumSQ.u64 = 19367; Count.u64 = 775; Min.u64 = 0; Max.u64 = 17; - l2cache_2:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_2:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 700; Min.u64 = 0; Max.u64 = 1; - l2cache_2:memlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 775; Min.u64 = 0; Max.u64 = 1; - l2cache_2:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 1475; Min.u64 = 0; Max.u64 = 1; - l2cache_2:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1475; Min.u64 = 0; Max.u64 = 1; - l2cache_2:memlink.ordering_latency : Accumulator : Sum.u64 = 5; SumSQ.u64 = 9; Count.u64 = 4; Min.u64 = 0; Max.u64 = 2; + l2cache_2:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2263; SumSQ.u64 = 8623; Count.u64 = 700; Min.u64 = 0; Max.u64 = 7; + l2cache_2:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3315; SumSQ.u64 = 19367; Count.u64 = 775; Min.u64 = 0; Max.u64 = 17; + l2cache_2:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 700; Min.u64 = 0; Max.u64 = 1; + l2cache_2:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 775; Min.u64 = 0; Max.u64 = 1; + l2cache_2:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 1475; Min.u64 = 0; Max.u64 = 1; + l2cache_2:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1475; Min.u64 = 0; Max.u64 = 1; + l2cache_2:lowlink.ordering_latency : Accumulator : Sum.u64 = 5; SumSQ.u64 = 9; Count.u64 = 4; Min.u64 = 0; Max.u64 = 2; l2cache_2.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_2.prefetches_issued : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; l2cache_2.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; @@ -4118,8 +4184,11 @@ Model complete l2cache_2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; @@ -4128,6 +4197,9 @@ Model complete l2cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 722; SumSQ.u64 = 722; Count.u64 = 722; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchInv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4152,6 +4224,7 @@ Model complete l2cache_2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4227,10 +4300,12 @@ Model complete l2cache_2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_2.GetXResp_recv : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; l2cache_2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4242,6 +4317,9 @@ Model complete l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 449; SumSQ.u64 = 449; Count.u64 = 449; Min.u64 = 1; Max.u64 = 1; l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; + l2cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckInv_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; l2cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4314,13 +4392,16 @@ Model complete l1cache_4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_FetchXResp : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_AckInv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache_4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4347,6 +4428,7 @@ Model complete l1cache_4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 547; SumSQ.u64 = 547; Count.u64 = 547; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetXHit_Arrival : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4393,14 +4475,18 @@ Model complete l1cache_4.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache_4.GetXResp_recv : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; l1cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Inv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l1cache_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.FetchInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l1cache_4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_4.MSHR_occupancy : Accumulator : Sum.u64 = 265257; SumSQ.u64 = 4942835; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -4489,13 +4575,16 @@ Model complete l1cache_5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_FetchResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_AckInv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache_5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4522,6 +4611,7 @@ Model complete l1cache_5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 489; SumSQ.u64 = 489; Count.u64 = 489; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetXHit_Arrival : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4568,14 +4658,18 @@ Model complete l1cache_5.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.GetSResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l1cache_5.GetXResp_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; l1cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Inv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1cache_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.FetchInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l1cache_5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_5.MSHR_occupancy : Accumulator : Sum.u64 = 265700; SumSQ.u64 = 4927974; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -4597,17 +4691,17 @@ Model complete core_5.cycles_max_issue : Accumulator : Sum.u64 = 1008; SumSQ.u64 = 1008; Count.u64 = 1008; Min.u64 = 1; Max.u64 = 1; core_5.cycles_max_reorder : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; core_5.cycles : Accumulator : Sum.u64 = 15013; SumSQ.u64 = 15013; Count.u64 = 15013; Min.u64 = 1; Max.u64 = 1; - dc_2:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2787; SumSQ.u64 = 11017; Count.u64 = 873; Min.u64 = 0; Max.u64 = 17; - dc_2:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 202; SumSQ.u64 = 480; Count.u64 = 103; Min.u64 = 0; Max.u64 = 4; - dc_2:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2876; SumSQ.u64 = 14212; Count.u64 = 772; Min.u64 = 0; Max.u64 = 14; - dc_2:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_2:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink:req.packet_latency : Accumulator : Sum.u64 = 2787; SumSQ.u64 = 11017; Count.u64 = 873; Min.u64 = 0; Max.u64 = 17; + dc_2:highlink:ack.packet_latency : Accumulator : Sum.u64 = 202; SumSQ.u64 = 480; Count.u64 = 103; Min.u64 = 0; Max.u64 = 4; + dc_2:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink:data.packet_latency : Accumulator : Sum.u64 = 2876; SumSQ.u64 = 14212; Count.u64 = 772; Min.u64 = 0; Max.u64 = 14; + dc_2:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_2:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.get_request_latency : Accumulator : Sum.u64 = 201614; SumSQ.u64 = 616407378; Count.u64 = 873; Min.u64 = 16; Max.u64 = 13766; @@ -4630,8 +4724,10 @@ Model complete dc_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4650,6 +4746,7 @@ Model complete dc_2.eventSent_FetchInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; dc_2.eventSent_FetchInvX : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; dc_2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.eventSent_GetSResp : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; dc_2.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -4660,20 +4757,22 @@ Model complete dc_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_2.MSHR_occupancy : Accumulator : Sum.u64 = 199868; SumSQ.u64 = 2877930; Count.u64 = 18310; Min.u64 = 0; Max.u64 = 25; - l2cache_3:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 8807; Count.u64 = 717; Min.u64 = 0; Max.u64 = 7; - l2cache_3:memlink:data.packet_latency : Accumulator : Sum.u64 = 3321; SumSQ.u64 = 19475; Count.u64 = 772; Min.u64 = 0; Max.u64 = 18; - l2cache_3:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_3:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 717; Min.u64 = 0; Max.u64 = 1; - l2cache_3:memlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 772; Min.u64 = 0; Max.u64 = 1; - l2cache_3:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1489; Min.u64 = 0; Max.u64 = 1; - l2cache_3:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1489; Min.u64 = 0; Max.u64 = 1; - l2cache_3:memlink.ordering_latency : Accumulator : Sum.u64 = 10; SumSQ.u64 = 66; Count.u64 = 4; Min.u64 = 0; Max.u64 = 8; + l2cache_3:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 8807; Count.u64 = 717; Min.u64 = 0; Max.u64 = 7; + l2cache_3:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3321; SumSQ.u64 = 19475; Count.u64 = 772; Min.u64 = 0; Max.u64 = 18; + l2cache_3:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 717; Min.u64 = 0; Max.u64 = 1; + l2cache_3:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 772; Min.u64 = 0; Max.u64 = 1; + l2cache_3:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1489; Min.u64 = 0; Max.u64 = 1; + l2cache_3:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1489; Min.u64 = 0; Max.u64 = 1; + l2cache_3:lowlink.ordering_latency : Accumulator : Sum.u64 = 10; SumSQ.u64 = 66; Count.u64 = 4; Min.u64 = 0; Max.u64 = 8; l2cache_3.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_3.prefetches_issued : Accumulator : Sum.u64 = 743; SumSQ.u64 = 743; Count.u64 = 743; Min.u64 = 1; Max.u64 = 1; l2cache_3.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; @@ -4789,8 +4888,11 @@ Model complete l2cache_3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; @@ -4799,6 +4901,9 @@ Model complete l2cache_3.eventSent_GetXResp : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4823,6 +4928,7 @@ Model complete l2cache_3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSHit_Arrival : Accumulator : Sum.u64 = 419; SumSQ.u64 = 419; Count.u64 = 419; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXHit_Arrival : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4898,10 +5004,12 @@ Model complete l2cache_3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_3.GetXResp_recv : Accumulator : Sum.u64 = 743; SumSQ.u64 = 743; Count.u64 = 743; Min.u64 = 1; Max.u64 = 1; l2cache_3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4913,6 +5021,9 @@ Model complete l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l2cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckInv_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l2cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4985,13 +5096,16 @@ Model complete l1cache_6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_FetchResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_AckInv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache_6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5018,6 +5132,7 @@ Model complete l1cache_6.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetXHit_Arrival : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5064,14 +5179,18 @@ Model complete l1cache_6.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_6.GetXResp_recv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; l1cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Inv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l1cache_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l1cache_6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_6.MSHR_occupancy : Accumulator : Sum.u64 = 259376; SumSQ.u64 = 4725850; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -5160,13 +5279,16 @@ Model complete l1cache_7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_AckInv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l1cache_7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5193,6 +5315,7 @@ Model complete l1cache_7.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetXHit_Arrival : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5239,14 +5362,18 @@ Model complete l1cache_7.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_7.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; l1cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Inv_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l1cache_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + l1cache_7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_7.MSHR_occupancy : Accumulator : Sum.u64 = 281980; SumSQ.u64 = 5419890; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -5268,17 +5395,17 @@ Model complete core_7.cycles_max_issue : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; core_7.cycles_max_reorder : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; core_7.cycles : Accumulator : Sum.u64 = 15367; SumSQ.u64 = 15367; Count.u64 = 15367; Min.u64 = 1; Max.u64 = 1; - dc_3:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2816; SumSQ.u64 = 11414; Count.u64 = 873; Min.u64 = 0; Max.u64 = 14; - dc_3:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 195; SumSQ.u64 = 471; Count.u64 = 102; Min.u64 = 0; Max.u64 = 4; - dc_3:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3236; SumSQ.u64 = 20268; Count.u64 = 773; Min.u64 = 0; Max.u64 = 25; - dc_3:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 102; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_3:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink:req.packet_latency : Accumulator : Sum.u64 = 2816; SumSQ.u64 = 11414; Count.u64 = 873; Min.u64 = 0; Max.u64 = 14; + dc_3:highlink:ack.packet_latency : Accumulator : Sum.u64 = 195; SumSQ.u64 = 471; Count.u64 = 102; Min.u64 = 0; Max.u64 = 4; + dc_3:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink:data.packet_latency : Accumulator : Sum.u64 = 3236; SumSQ.u64 = 20268; Count.u64 = 773; Min.u64 = 0; Max.u64 = 25; + dc_3:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 102; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_3:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.get_request_latency : Accumulator : Sum.u64 = 207867; SumSQ.u64 = 628957063; Count.u64 = 873; Min.u64 = 16; Max.u64 = 13553; @@ -5301,8 +5428,10 @@ Model complete dc_3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.AckInv_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + dc_3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5321,6 +5450,7 @@ Model complete dc_3.eventSent_FetchInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; dc_3.eventSent_FetchInvX : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; dc_3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.eventSent_GetSResp : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; dc_3.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -5331,6 +5461,8 @@ Model complete dc_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_3.MSHR_occupancy : Accumulator : Sum.u64 = 206121; SumSQ.u64 = 3050527; Count.u64 = 18332; Min.u64 = 0; Max.u64 = 25; @@ -5348,32 +5480,32 @@ Model complete hbm_2.cycles_with_issue : Accumulator : Sum.u64 = 4056; SumSQ.u64 = 4056; Count.u64 = 4056; Min.u64 = 1; Max.u64 = 1; hbm_2.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_2.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_2:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8731; SumSQ.u64 = 42093; Count.u64 = 2296; Min.u64 = 1; Max.u64 = 23; - hbm_2:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink:data.packet_latency : Accumulator : Sum.u64 = 13840; SumSQ.u64 = 98620; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 26; - hbm_2:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2296; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 0; - hbm_2:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink:req.packet_latency : Accumulator : Sum.u64 = 8731; SumSQ.u64 = 42093; Count.u64 = 2296; Min.u64 = 1; Max.u64 = 23; + hbm_2:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink:data.packet_latency : Accumulator : Sum.u64 = 13840; SumSQ.u64 = 98620; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 26; + hbm_2:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2296; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 0; + hbm_2:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_2.CacheHits_Read : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; hbm_2.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_2.CacheHits_Write : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; hbm_2.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2434; SumSQ.u64 = 9844; Count.u64 = 712; Min.u64 = 0; Max.u64 = 8; - l2cache_4:memlink:data.packet_latency : Accumulator : Sum.u64 = 3485; SumSQ.u64 = 20611; Count.u64 = 782; Min.u64 = 0; Max.u64 = 18; - l2cache_4:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 712; Min.u64 = 0; Max.u64 = 1; - l2cache_4:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 782; Min.u64 = 0; Max.u64 = 0; - l2cache_4:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1494; Min.u64 = 0; Max.u64 = 1; - l2cache_4:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1494; Min.u64 = 0; Max.u64 = 1; - l2cache_4:memlink.ordering_latency : Accumulator : Sum.u64 = 11; SumSQ.u64 = 35; Count.u64 = 4; Min.u64 = 1; Max.u64 = 4; + l2cache_4:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2434; SumSQ.u64 = 9844; Count.u64 = 712; Min.u64 = 0; Max.u64 = 8; + l2cache_4:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3485; SumSQ.u64 = 20611; Count.u64 = 782; Min.u64 = 0; Max.u64 = 18; + l2cache_4:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 712; Min.u64 = 0; Max.u64 = 1; + l2cache_4:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 782; Min.u64 = 0; Max.u64 = 0; + l2cache_4:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1494; Min.u64 = 0; Max.u64 = 1; + l2cache_4:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1494; Min.u64 = 0; Max.u64 = 1; + l2cache_4:lowlink.ordering_latency : Accumulator : Sum.u64 = 11; SumSQ.u64 = 35; Count.u64 = 4; Min.u64 = 1; Max.u64 = 4; l2cache_4.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_4.prefetches_issued : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; l2cache_4.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; @@ -5489,8 +5621,11 @@ Model complete l2cache_4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchResp : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_FetchXResp : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_AckInv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; @@ -5499,6 +5634,9 @@ Model complete l2cache_4.eventSent_GetXResp : Accumulator : Sum.u64 = 736; SumSQ.u64 = 736; Count.u64 = 736; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.eventSent_FetchInv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l2cache_4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5523,6 +5661,7 @@ Model complete l2cache_4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSHit_Arrival : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXHit_Arrival : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5598,10 +5737,12 @@ Model complete l2cache_4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.GetSResp_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_4.GetXResp_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l2cache_4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5613,6 +5754,9 @@ Model complete l2cache_4.FetchInvX_recv : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; l2cache_4.FetchResp_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l2cache_4.FetchXResp_recv : Accumulator : Sum.u64 = 450; SumSQ.u64 = 450; Count.u64 = 450; Min.u64 = 1; Max.u64 = 1; + l2cache_4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_4.AckInv_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; l2cache_4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5685,13 +5829,16 @@ Model complete l1cache_8.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_FetchResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_AckInv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache_8.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5718,6 +5865,7 @@ Model complete l1cache_8.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXHit_Arrival : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5764,14 +5912,18 @@ Model complete l1cache_8.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache_8.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; l1cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Inv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1cache_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.FetchInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; + l1cache_8.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_8.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_8.MSHR_occupancy : Accumulator : Sum.u64 = 240238; SumSQ.u64 = 4235278; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -5860,13 +6012,16 @@ Model complete l1cache_9.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_9.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_9.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5893,6 +6048,7 @@ Model complete l1cache_9.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 560; SumSQ.u64 = 560; Count.u64 = 560; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXHit_Arrival : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -5939,14 +6095,18 @@ Model complete l1cache_9.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache_9.GetXResp_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; l1cache_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l1cache_9.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_9.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_9.MSHR_occupancy : Accumulator : Sum.u64 = 259179; SumSQ.u64 = 4701619; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -5968,17 +6128,17 @@ Model complete core_9.cycles_max_issue : Accumulator : Sum.u64 = 1002; SumSQ.u64 = 1002; Count.u64 = 1002; Min.u64 = 1; Max.u64 = 1; core_9.cycles_max_reorder : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; core_9.cycles : Accumulator : Sum.u64 = 14912; SumSQ.u64 = 14912; Count.u64 = 14912; Min.u64 = 1; Max.u64 = 1; - dc_4:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2970; SumSQ.u64 = 12708; Count.u64 = 870; Min.u64 = 0; Max.u64 = 17; - dc_4:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 217; SumSQ.u64 = 581; Count.u64 = 103; Min.u64 = 0; Max.u64 = 4; - dc_4:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4255; SumSQ.u64 = 35079; Count.u64 = 769; Min.u64 = 0; Max.u64 = 34; - dc_4:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 870; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1742; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1742; Min.u64 = 0; Max.u64 = 0; - dc_4:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink:req.packet_latency : Accumulator : Sum.u64 = 2970; SumSQ.u64 = 12708; Count.u64 = 870; Min.u64 = 0; Max.u64 = 17; + dc_4:highlink:ack.packet_latency : Accumulator : Sum.u64 = 217; SumSQ.u64 = 581; Count.u64 = 103; Min.u64 = 0; Max.u64 = 4; + dc_4:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink:data.packet_latency : Accumulator : Sum.u64 = 4255; SumSQ.u64 = 35079; Count.u64 = 769; Min.u64 = 0; Max.u64 = 34; + dc_4:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 870; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1742; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1742; Min.u64 = 0; Max.u64 = 0; + dc_4:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.get_request_latency : Accumulator : Sum.u64 = 182894; SumSQ.u64 = 291725920; Count.u64 = 870; Min.u64 = 16; Max.u64 = 13349; @@ -6001,8 +6161,10 @@ Model complete dc_4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6021,6 +6183,7 @@ Model complete dc_4.eventSent_FetchInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; dc_4.eventSent_FetchInvX : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; dc_4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.eventSent_GetSResp : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_4.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -6031,6 +6194,8 @@ Model complete dc_4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_4.MSHR_occupancy : Accumulator : Sum.u64 = 181154; SumSQ.u64 = 2370558; Count.u64 = 18379; Min.u64 = 0; Max.u64 = 23; @@ -6048,32 +6213,32 @@ Model complete hbm_3.cycles_with_issue : Accumulator : Sum.u64 = 4077; SumSQ.u64 = 4077; Count.u64 = 4077; Min.u64 = 1; Max.u64 = 1; hbm_3.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_3.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_3:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8708; SumSQ.u64 = 41910; Count.u64 = 2296; Min.u64 = 1; Max.u64 = 24; - hbm_3:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_3:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_3:cpulink:data.packet_latency : Accumulator : Sum.u64 = 6208; SumSQ.u64 = 34126; Count.u64 = 2289; Min.u64 = 0; Max.u64 = 78; - hbm_3:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 2296; Min.u64 = 0; Max.u64 = 1; - hbm_3:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_3:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_3:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2289; Min.u64 = 0; Max.u64 = 0; - hbm_3:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4585; Min.u64 = 0; Max.u64 = 1; - hbm_3:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4585; Min.u64 = 0; Max.u64 = 1; - hbm_3:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + hbm_3:highlink:req.packet_latency : Accumulator : Sum.u64 = 8708; SumSQ.u64 = 41910; Count.u64 = 2296; Min.u64 = 1; Max.u64 = 24; + hbm_3:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_3:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_3:highlink:data.packet_latency : Accumulator : Sum.u64 = 6208; SumSQ.u64 = 34126; Count.u64 = 2289; Min.u64 = 0; Max.u64 = 78; + hbm_3:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 2296; Min.u64 = 0; Max.u64 = 1; + hbm_3:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_3:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_3:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2289; Min.u64 = 0; Max.u64 = 0; + hbm_3:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4585; Min.u64 = 0; Max.u64 = 1; + hbm_3:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4585; Min.u64 = 0; Max.u64 = 1; + hbm_3:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; hbm_3.CacheHits_Read : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; hbm_3.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_3.CacheHits_Write : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; hbm_3.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2679; SumSQ.u64 = 11931; Count.u64 = 707; Min.u64 = 0; Max.u64 = 8; - l2cache_5:memlink:data.packet_latency : Accumulator : Sum.u64 = 3800; SumSQ.u64 = 24680; Count.u64 = 780; Min.u64 = 0; Max.u64 = 23; - l2cache_5:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_5:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 707; Min.u64 = 0; Max.u64 = 1; - l2cache_5:memlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 780; Min.u64 = 0; Max.u64 = 1; - l2cache_5:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 11; SumSQ.u64 = 13; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 2; - l2cache_5:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 9; SumSQ.u64 = 11; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 2; - l2cache_5:memlink.ordering_latency : Accumulator : Sum.u64 = 20; SumSQ.u64 = 78; Count.u64 = 8; Min.u64 = 0; Max.u64 = 6; + l2cache_5:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2679; SumSQ.u64 = 11931; Count.u64 = 707; Min.u64 = 0; Max.u64 = 8; + l2cache_5:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3800; SumSQ.u64 = 24680; Count.u64 = 780; Min.u64 = 0; Max.u64 = 23; + l2cache_5:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 707; Min.u64 = 0; Max.u64 = 1; + l2cache_5:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 780; Min.u64 = 0; Max.u64 = 1; + l2cache_5:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 11; SumSQ.u64 = 13; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 2; + l2cache_5:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 9; SumSQ.u64 = 11; Count.u64 = 1487; Min.u64 = 0; Max.u64 = 2; + l2cache_5:lowlink.ordering_latency : Accumulator : Sum.u64 = 20; SumSQ.u64 = 78; Count.u64 = 8; Min.u64 = 0; Max.u64 = 6; l2cache_5.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_5.prefetches_issued : Accumulator : Sum.u64 = 728; SumSQ.u64 = 728; Count.u64 = 728; Min.u64 = 1; Max.u64 = 1; l2cache_5.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; @@ -6189,8 +6354,11 @@ Model complete l2cache_5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_FetchXResp : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_AckInv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; @@ -6199,6 +6367,9 @@ Model complete l2cache_5.eventSent_GetXResp : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.eventSent_FetchInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6223,6 +6394,7 @@ Model complete l2cache_5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSHit_Arrival : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXHit_Arrival : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6298,10 +6470,12 @@ Model complete l2cache_5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.GetSResp_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2cache_5.GetXResp_recv : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6313,6 +6487,9 @@ Model complete l2cache_5.FetchInvX_recv : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; l2cache_5.FetchResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_5.FetchXResp_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l2cache_5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_5.AckInv_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; l2cache_5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6385,13 +6562,16 @@ Model complete l1cache_10.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_10.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_10.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6418,6 +6598,7 @@ Model complete l1cache_10.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 555; SumSQ.u64 = 555; Count.u64 = 555; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetXHit_Arrival : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6464,14 +6645,18 @@ Model complete l1cache_10.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_10.GetXResp_recv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; l1cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; + l1cache_10.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_10.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_10.MSHR_occupancy : Accumulator : Sum.u64 = 266977; SumSQ.u64 = 4900327; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -6560,13 +6745,16 @@ Model complete l1cache_11.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_11.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_11.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6593,6 +6781,7 @@ Model complete l1cache_11.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetXHit_Arrival : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6639,14 +6828,18 @@ Model complete l1cache_11.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.GetSResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_11.GetXResp_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; l1cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; + l1cache_11.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_11.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_11.MSHR_occupancy : Accumulator : Sum.u64 = 242363; SumSQ.u64 = 4305831; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -6668,17 +6861,17 @@ Model complete core_11.cycles_max_issue : Accumulator : Sum.u64 = 1030; SumSQ.u64 = 1030; Count.u64 = 1030; Min.u64 = 1; Max.u64 = 1; core_11.cycles_max_reorder : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; core_11.cycles : Accumulator : Sum.u64 = 14269; SumSQ.u64 = 14269; Count.u64 = 14269; Min.u64 = 1; Max.u64 = 1; - dc_5:cpulink:req.packet_latency : Accumulator : Sum.u64 = 3342; SumSQ.u64 = 15852; Count.u64 = 871; Min.u64 = 0; Max.u64 = 20; - dc_5:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 255; SumSQ.u64 = 797; Count.u64 = 103; Min.u64 = 0; Max.u64 = 5; - dc_5:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3891; SumSQ.u64 = 25447; Count.u64 = 770; Min.u64 = 0; Max.u64 = 19; - dc_5:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 871; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 0; - dc_5:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink:req.packet_latency : Accumulator : Sum.u64 = 3342; SumSQ.u64 = 15852; Count.u64 = 871; Min.u64 = 0; Max.u64 = 20; + dc_5:highlink:ack.packet_latency : Accumulator : Sum.u64 = 255; SumSQ.u64 = 797; Count.u64 = 103; Min.u64 = 0; Max.u64 = 5; + dc_5:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink:data.packet_latency : Accumulator : Sum.u64 = 3891; SumSQ.u64 = 25447; Count.u64 = 770; Min.u64 = 0; Max.u64 = 19; + dc_5:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 871; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 0; + dc_5:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.get_request_latency : Accumulator : Sum.u64 = 189960; SumSQ.u64 = 309505438; Count.u64 = 871; Min.u64 = 16; Max.u64 = 12617; @@ -6701,8 +6894,10 @@ Model complete dc_5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6721,6 +6916,7 @@ Model complete dc_5.eventSent_FetchInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; dc_5.eventSent_FetchInvX : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; dc_5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.eventSent_GetSResp : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; dc_5.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -6731,6 +6927,8 @@ Model complete dc_5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_5.MSHR_occupancy : Accumulator : Sum.u64 = 188218; SumSQ.u64 = 2559496; Count.u64 = 18402; Min.u64 = 0; Max.u64 = 24; @@ -6748,28 +6946,28 @@ Model complete ddr_0.cycles_with_issue : Accumulator : Sum.u64 = 780; SumSQ.u64 = 780; Count.u64 = 780; Min.u64 = 1; Max.u64 = 1; ddr_0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 8661; SumSQ.u64 = 8661; Count.u64 = 8661; Min.u64 = 1; Max.u64 = 1; ddr_0.total_cycles : Accumulator : Sum.u64 = 13915; SumSQ.u64 = 193627225; Count.u64 = 1; Min.u64 = 13915; Max.u64 = 13915; - ddr_0:cpulink:req.packet_latency : Accumulator : Sum.u64 = 10681; SumSQ.u64 = 47419; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 10; - ddr_0:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; - ddr_0:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 9512; Count.u64 = 705; Min.u64 = 0; Max.u64 = 7; - l2cache_6:memlink:data.packet_latency : Accumulator : Sum.u64 = 3019; SumSQ.u64 = 14517; Count.u64 = 777; Min.u64 = 0; Max.u64 = 14; - l2cache_6:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 705; Min.u64 = 0; Max.u64 = 1; - l2cache_6:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 777; Min.u64 = 0; Max.u64 = 0; - l2cache_6:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1482; Min.u64 = 0; Max.u64 = 1; - l2cache_6:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1482; Min.u64 = 0; Max.u64 = 1; - l2cache_6:memlink.ordering_latency : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + ddr_0:highlink:req.packet_latency : Accumulator : Sum.u64 = 10681; SumSQ.u64 = 47419; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 10; + ddr_0:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; + ddr_0:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 9512; Count.u64 = 705; Min.u64 = 0; Max.u64 = 7; + l2cache_6:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3019; SumSQ.u64 = 14517; Count.u64 = 777; Min.u64 = 0; Max.u64 = 14; + l2cache_6:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 705; Min.u64 = 0; Max.u64 = 1; + l2cache_6:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 777; Min.u64 = 0; Max.u64 = 0; + l2cache_6:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1482; Min.u64 = 0; Max.u64 = 1; + l2cache_6:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1482; Min.u64 = 0; Max.u64 = 1; + l2cache_6:lowlink.ordering_latency : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; l2cache_6.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_6.prefetches_issued : Accumulator : Sum.u64 = 740; SumSQ.u64 = 740; Count.u64 = 740; Min.u64 = 1; Max.u64 = 1; l2cache_6.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; @@ -6885,8 +7083,11 @@ Model complete l2cache_6.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchResp : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_FetchXResp : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_AckInv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; @@ -6895,6 +7096,9 @@ Model complete l2cache_6.eventSent_GetXResp : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.eventSent_FetchInv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache_6.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6919,6 +7123,7 @@ Model complete l2cache_6.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSHit_Arrival : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXHit_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -6994,10 +7199,12 @@ Model complete l2cache_6.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.GetSResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_6.GetXResp_recv : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; l2cache_6.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7009,6 +7216,9 @@ Model complete l2cache_6.FetchInvX_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; l2cache_6.FetchResp_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l2cache_6.FetchXResp_recv : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + l2cache_6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_6.AckInv_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; l2cache_6.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7081,13 +7291,16 @@ Model complete l1cache_12.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_FetchResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_FetchXResp : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_AckInv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l1cache_12.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_12.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7114,6 +7327,7 @@ Model complete l1cache_12.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 564; SumSQ.u64 = 564; Count.u64 = 564; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetXHit_Arrival : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7160,14 +7374,18 @@ Model complete l1cache_12.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_12.GetXResp_recv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; l1cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Inv_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; l1cache_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.FetchInv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l1cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l1cache_12.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_12.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_12.MSHR_occupancy : Accumulator : Sum.u64 = 253599; SumSQ.u64 = 4721981; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -7256,13 +7474,16 @@ Model complete l1cache_13.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_FetchResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_AckInv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; + l1cache_13.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_13.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7289,6 +7510,7 @@ Model complete l1cache_13.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetXHit_Arrival : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7335,14 +7557,18 @@ Model complete l1cache_13.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.GetSResp_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache_13.GetXResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; l1cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Inv_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.FetchInv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l1cache_13.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_13.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_13.MSHR_occupancy : Accumulator : Sum.u64 = 256378; SumSQ.u64 = 4687672; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -7364,17 +7590,17 @@ Model complete core_13.cycles_max_issue : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; core_13.cycles_max_reorder : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; core_13.cycles : Accumulator : Sum.u64 = 14653; SumSQ.u64 = 14653; Count.u64 = 14653; Min.u64 = 1; Max.u64 = 1; - dc_6:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2884; SumSQ.u64 = 11644; Count.u64 = 872; Min.u64 = 0; Max.u64 = 9; - dc_6:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 249; SumSQ.u64 = 729; Count.u64 = 105; Min.u64 = 0; Max.u64 = 5; - dc_6:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3680; SumSQ.u64 = 22502; Count.u64 = 771; Min.u64 = 0; Max.u64 = 42; - dc_6:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 872; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_6:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink:req.packet_latency : Accumulator : Sum.u64 = 2884; SumSQ.u64 = 11644; Count.u64 = 872; Min.u64 = 0; Max.u64 = 9; + dc_6:highlink:ack.packet_latency : Accumulator : Sum.u64 = 249; SumSQ.u64 = 729; Count.u64 = 105; Min.u64 = 0; Max.u64 = 5; + dc_6:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink:data.packet_latency : Accumulator : Sum.u64 = 3680; SumSQ.u64 = 22502; Count.u64 = 771; Min.u64 = 0; Max.u64 = 42; + dc_6:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 872; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_6:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.get_request_latency : Accumulator : Sum.u64 = 182393; SumSQ.u64 = 276939039; Count.u64 = 872; Min.u64 = 16; Max.u64 = 12829; @@ -7397,8 +7623,10 @@ Model complete dc_6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.AckInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + dc_6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7417,6 +7645,7 @@ Model complete dc_6.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_6.eventSent_FetchInvX : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; dc_6.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.eventSent_GetSResp : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; dc_6.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -7427,20 +7656,22 @@ Model complete dc_6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_6.MSHR_occupancy : Accumulator : Sum.u64 = 180649; SumSQ.u64 = 2383593; Count.u64 = 18448; Min.u64 = 0; Max.u64 = 26; - l2cache_7:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2161; SumSQ.u64 = 7689; Count.u64 = 717; Min.u64 = 0; Max.u64 = 7; - l2cache_7:memlink:data.packet_latency : Accumulator : Sum.u64 = 2733; SumSQ.u64 = 12363; Count.u64 = 776; Min.u64 = 0; Max.u64 = 12; - l2cache_7:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 717; Min.u64 = 0; Max.u64 = 1; - l2cache_7:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; - l2cache_7:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1493; Min.u64 = 0; Max.u64 = 1; - l2cache_7:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1493; Min.u64 = 0; Max.u64 = 1; - l2cache_7:memlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_7:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2161; SumSQ.u64 = 7689; Count.u64 = 717; Min.u64 = 0; Max.u64 = 7; + l2cache_7:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2733; SumSQ.u64 = 12363; Count.u64 = 776; Min.u64 = 0; Max.u64 = 12; + l2cache_7:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 717; Min.u64 = 0; Max.u64 = 1; + l2cache_7:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; + l2cache_7:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1493; Min.u64 = 0; Max.u64 = 1; + l2cache_7:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1493; Min.u64 = 0; Max.u64 = 1; + l2cache_7:lowlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_7.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_7.prefetches_issued : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; l2cache_7.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; @@ -7556,8 +7787,11 @@ Model complete l2cache_7.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_FetchXResp : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_AckInv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; @@ -7566,6 +7800,9 @@ Model complete l2cache_7.eventSent_GetXResp : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.eventSent_FetchInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_7.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7590,6 +7827,7 @@ Model complete l2cache_7.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSHit_Arrival : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXHit_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7665,10 +7903,12 @@ Model complete l2cache_7.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.GetSResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache_7.GetXResp_recv : Accumulator : Sum.u64 = 749; SumSQ.u64 = 749; Count.u64 = 749; Min.u64 = 1; Max.u64 = 1; l2cache_7.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7680,6 +7920,9 @@ Model complete l2cache_7.FetchInvX_recv : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; l2cache_7.FetchResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l2cache_7.FetchXResp_recv : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; + l2cache_7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_7.AckInv_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; l2cache_7.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7752,13 +7995,16 @@ Model complete l1cache_14.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_14.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_14.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7785,6 +8031,7 @@ Model complete l1cache_14.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 613; SumSQ.u64 = 613; Count.u64 = 613; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetXHit_Arrival : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7831,14 +8078,18 @@ Model complete l1cache_14.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.GetSResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_14.GetXResp_recv : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; l1cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; + l1cache_14.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_14.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_14.MSHR_occupancy : Accumulator : Sum.u64 = 262678; SumSQ.u64 = 4876974; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -7927,13 +8178,16 @@ Model complete l1cache_15.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_15.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_15.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -7960,6 +8214,7 @@ Model complete l1cache_15.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetXHit_Arrival : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l1cache_15.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8006,14 +8261,18 @@ Model complete l1cache_15.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.GetXResp_recv : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; l1cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l1cache_15.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_15.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_15.MSHR_occupancy : Accumulator : Sum.u64 = 266530; SumSQ.u64 = 4939024; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -8035,17 +8294,17 @@ Model complete core_15.cycles_max_issue : Accumulator : Sum.u64 = 996; SumSQ.u64 = 996; Count.u64 = 996; Min.u64 = 1; Max.u64 = 1; core_15.cycles_max_reorder : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; core_15.cycles : Accumulator : Sum.u64 = 15025; SumSQ.u64 = 15025; Count.u64 = 15025; Min.u64 = 1; Max.u64 = 1; - dc_7:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2555; SumSQ.u64 = 9303; Count.u64 = 872; Min.u64 = 0; Max.u64 = 11; - dc_7:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 200; SumSQ.u64 = 474; Count.u64 = 104; Min.u64 = 0; Max.u64 = 4; - dc_7:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_7:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4060; SumSQ.u64 = 56962; Count.u64 = 772; Min.u64 = 0; Max.u64 = 157; - dc_7:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 872; Min.u64 = 0; Max.u64 = 0; - dc_7:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 104; Min.u64 = 0; Max.u64 = 1; - dc_7:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_7:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 772; Min.u64 = 0; Max.u64 = 1; - dc_7:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; - dc_7:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; - dc_7:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 2; Min.u64 = 0; Max.u64 = 3; + dc_7:highlink:req.packet_latency : Accumulator : Sum.u64 = 2555; SumSQ.u64 = 9303; Count.u64 = 872; Min.u64 = 0; Max.u64 = 11; + dc_7:highlink:ack.packet_latency : Accumulator : Sum.u64 = 200; SumSQ.u64 = 474; Count.u64 = 104; Min.u64 = 0; Max.u64 = 4; + dc_7:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_7:highlink:data.packet_latency : Accumulator : Sum.u64 = 4060; SumSQ.u64 = 56962; Count.u64 = 772; Min.u64 = 0; Max.u64 = 157; + dc_7:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 872; Min.u64 = 0; Max.u64 = 0; + dc_7:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 104; Min.u64 = 0; Max.u64 = 1; + dc_7:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_7:highlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 772; Min.u64 = 0; Max.u64 = 1; + dc_7:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; + dc_7:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; + dc_7:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 2; Min.u64 = 0; Max.u64 = 3; dc_7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.get_request_latency : Accumulator : Sum.u64 = 197439; SumSQ.u64 = 420507493; Count.u64 = 872; Min.u64 = 16; Max.u64 = 13492; @@ -8068,8 +8327,10 @@ Model complete dc_7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.AckInv_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + dc_7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8088,6 +8349,7 @@ Model complete dc_7.eventSent_FetchInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; dc_7.eventSent_FetchInvX : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; dc_7.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.eventSent_GetSResp : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; dc_7.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -8098,20 +8360,22 @@ Model complete dc_7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_7.MSHR_occupancy : Accumulator : Sum.u64 = 195695; SumSQ.u64 = 2762835; Count.u64 = 18453; Min.u64 = 0; Max.u64 = 26; - l2cache_8:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 7076; Count.u64 = 726; Min.u64 = 0; Max.u64 = 8; - l2cache_8:memlink:data.packet_latency : Accumulator : Sum.u64 = 2560; SumSQ.u64 = 10788; Count.u64 = 777; Min.u64 = 0; Max.u64 = 10; - l2cache_8:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 726; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 777; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1503; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1503; Min.u64 = 0; Max.u64 = 0; - l2cache_8:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2094; SumSQ.u64 = 7076; Count.u64 = 726; Min.u64 = 0; Max.u64 = 8; + l2cache_8:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2560; SumSQ.u64 = 10788; Count.u64 = 777; Min.u64 = 0; Max.u64 = 10; + l2cache_8:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 726; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 777; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1503; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1503; Min.u64 = 0; Max.u64 = 0; + l2cache_8:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_8.prefetches_issued : Accumulator : Sum.u64 = 732; SumSQ.u64 = 732; Count.u64 = 732; Min.u64 = 1; Max.u64 = 1; l2cache_8.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; @@ -8227,8 +8491,11 @@ Model complete l2cache_8.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchResp : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_FetchXResp : Accumulator : Sum.u64 = 467; SumSQ.u64 = 467; Count.u64 = 467; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_AckInv : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; @@ -8237,6 +8504,9 @@ Model complete l2cache_8.eventSent_GetXResp : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.eventSent_FetchInv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache_8.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8261,6 +8531,7 @@ Model complete l2cache_8.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSHit_Arrival : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXHit_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8336,10 +8607,12 @@ Model complete l2cache_8.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.GetSResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l2cache_8.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_8.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8351,6 +8624,9 @@ Model complete l2cache_8.FetchInvX_recv : Accumulator : Sum.u64 = 467; SumSQ.u64 = 467; Count.u64 = 467; Min.u64 = 1; Max.u64 = 1; l2cache_8.FetchResp_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache_8.FetchXResp_recv : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; + l2cache_8.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_8.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_8.AckInv_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; l2cache_8.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8423,13 +8699,16 @@ Model complete l1cache_16.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_FetchResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_16.eventSent_FetchXResp : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; l1cache_16.eventSent_AckInv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache_16.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_16.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_16.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8456,6 +8735,7 @@ Model complete l1cache_16.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.GetSHit_Arrival : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l1cache_16.GetXHit_Arrival : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l1cache_16.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8502,14 +8782,18 @@ Model complete l1cache_16.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_16.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_16.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.Inv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l1cache_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache_16.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_16.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_16.MSHR_occupancy : Accumulator : Sum.u64 = 257917; SumSQ.u64 = 4628931; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -8598,13 +8882,16 @@ Model complete l1cache_17.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_17.eventSent_FetchXResp : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; l1cache_17.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_17.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_17.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_17.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8631,6 +8918,7 @@ Model complete l1cache_17.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.GetSHit_Arrival : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; l1cache_17.GetXHit_Arrival : Accumulator : Sum.u64 = 167; SumSQ.u64 = 167; Count.u64 = 167; Min.u64 = 1; Max.u64 = 1; l1cache_17.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8677,14 +8965,18 @@ Model complete l1cache_17.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_17.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; l1cache_17.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + l1cache_17.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_17.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_17.MSHR_occupancy : Accumulator : Sum.u64 = 274608; SumSQ.u64 = 5015528; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -8706,17 +8998,17 @@ Model complete core_17.cycles_max_issue : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; core_17.cycles_max_reorder : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; core_17.cycles : Accumulator : Sum.u64 = 15729; SumSQ.u64 = 15729; Count.u64 = 15729; Min.u64 = 1; Max.u64 = 1; - dc_8:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2592; SumSQ.u64 = 9652; Count.u64 = 926; Min.u64 = 0; Max.u64 = 17; - dc_8:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 256; SumSQ.u64 = 658; Count.u64 = 130; Min.u64 = 0; Max.u64 = 6; - dc_8:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_8:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3216; SumSQ.u64 = 21012; Count.u64 = 798; Min.u64 = 0; Max.u64 = 43; - dc_8:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 926; Min.u64 = 0; Max.u64 = 0; - dc_8:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 130; Min.u64 = 0; Max.u64 = 1; - dc_8:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_8:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 798; Min.u64 = 0; Max.u64 = 0; - dc_8:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1854; Min.u64 = 0; Max.u64 = 1; - dc_8:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1854; Min.u64 = 0; Max.u64 = 1; - dc_8:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + dc_8:highlink:req.packet_latency : Accumulator : Sum.u64 = 2592; SumSQ.u64 = 9652; Count.u64 = 926; Min.u64 = 0; Max.u64 = 17; + dc_8:highlink:ack.packet_latency : Accumulator : Sum.u64 = 256; SumSQ.u64 = 658; Count.u64 = 130; Min.u64 = 0; Max.u64 = 6; + dc_8:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_8:highlink:data.packet_latency : Accumulator : Sum.u64 = 3216; SumSQ.u64 = 21012; Count.u64 = 798; Min.u64 = 0; Max.u64 = 43; + dc_8:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 926; Min.u64 = 0; Max.u64 = 0; + dc_8:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 130; Min.u64 = 0; Max.u64 = 1; + dc_8:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_8:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 798; Min.u64 = 0; Max.u64 = 0; + dc_8:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1854; Min.u64 = 0; Max.u64 = 1; + dc_8:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1854; Min.u64 = 0; Max.u64 = 1; + dc_8:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; dc_8.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.get_request_latency : Accumulator : Sum.u64 = 187852; SumSQ.u64 = 389044106; Count.u64 = 926; Min.u64 = 4; Max.u64 = 12839; @@ -8739,8 +9031,10 @@ Model complete dc_8.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.AckInv_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + dc_8.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_8.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8759,6 +9053,7 @@ Model complete dc_8.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_8.eventSent_FetchInvX : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_8.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_8.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.eventSent_GetSResp : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; dc_8.eventSent_GetXResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; @@ -8769,20 +9064,22 @@ Model complete dc_8.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_8.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_8.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_8.MSHR_occupancy : Accumulator : Sum.u64 = 185995; SumSQ.u64 = 2541801; Count.u64 = 18468; Min.u64 = 0; Max.u64 = 26; - l2cache_9:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2104; SumSQ.u64 = 7252; Count.u64 = 724; Min.u64 = 0; Max.u64 = 8; - l2cache_9:memlink:data.packet_latency : Accumulator : Sum.u64 = 2578; SumSQ.u64 = 11048; Count.u64 = 773; Min.u64 = 0; Max.u64 = 13; - l2cache_9:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_9:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 724; Min.u64 = 0; Max.u64 = 1; - l2cache_9:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - l2cache_9:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; - l2cache_9:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; - l2cache_9:memlink.ordering_latency : Accumulator : Sum.u64 = 6; SumSQ.u64 = 36; Count.u64 = 1; Min.u64 = 6; Max.u64 = 6; + l2cache_9:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2104; SumSQ.u64 = 7252; Count.u64 = 724; Min.u64 = 0; Max.u64 = 8; + l2cache_9:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2578; SumSQ.u64 = 11048; Count.u64 = 773; Min.u64 = 0; Max.u64 = 13; + l2cache_9:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 724; Min.u64 = 0; Max.u64 = 1; + l2cache_9:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + l2cache_9:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; + l2cache_9:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; + l2cache_9:lowlink.ordering_latency : Accumulator : Sum.u64 = 6; SumSQ.u64 = 36; Count.u64 = 1; Min.u64 = 6; Max.u64 = 6; l2cache_9.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_9.prefetches_issued : Accumulator : Sum.u64 = 736; SumSQ.u64 = 736; Count.u64 = 736; Min.u64 = 1; Max.u64 = 1; l2cache_9.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; @@ -8898,8 +9195,11 @@ Model complete l2cache_9.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FetchResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_FetchXResp : Accumulator : Sum.u64 = 465; SumSQ.u64 = 465; Count.u64 = 465; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_AckInv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; @@ -8908,6 +9208,9 @@ Model complete l2cache_9.eventSent_GetXResp : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.eventSent_FetchInv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_9.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -8932,6 +9235,7 @@ Model complete l2cache_9.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSHit_Arrival : Accumulator : Sum.u64 = 425; SumSQ.u64 = 425; Count.u64 = 425; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetXHit_Arrival : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9007,10 +9311,12 @@ Model complete l2cache_9.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.GetSResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache_9.GetXResp_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l2cache_9.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9022,6 +9328,9 @@ Model complete l2cache_9.FetchInvX_recv : Accumulator : Sum.u64 = 465; SumSQ.u64 = 465; Count.u64 = 465; Min.u64 = 1; Max.u64 = 1; l2cache_9.FetchResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_9.FetchXResp_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; + l2cache_9.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_9.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_9.AckInv_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l2cache_9.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9094,13 +9403,16 @@ Model complete l1cache_18.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_18.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_18.eventSent_FetchXResp : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; l1cache_18.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_18.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_18.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_18.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_18.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9127,6 +9439,7 @@ Model complete l1cache_18.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_18.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.GetSHit_Arrival : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; l1cache_18.GetXHit_Arrival : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l1cache_18.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9173,14 +9486,18 @@ Model complete l1cache_18.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_18.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_18.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_18.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; l1cache_18.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_18.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_18.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache_18.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_18.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_18.MSHR_occupancy : Accumulator : Sum.u64 = 254076; SumSQ.u64 = 4534756; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -9269,13 +9586,16 @@ Model complete l1cache_19.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_19.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_19.eventSent_FetchXResp : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l1cache_19.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_19.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_19.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_19.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_19.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9302,6 +9622,7 @@ Model complete l1cache_19.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_19.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.GetSHit_Arrival : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; l1cache_19.GetXHit_Arrival : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l1cache_19.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9348,14 +9669,18 @@ Model complete l1cache_19.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_19.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_19.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_19.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; l1cache_19.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_19.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_19.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l1cache_19.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_19.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_19.MSHR_occupancy : Accumulator : Sum.u64 = 265098; SumSQ.u64 = 4835778; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -9377,17 +9702,17 @@ Model complete core_19.cycles_max_issue : Accumulator : Sum.u64 = 995; SumSQ.u64 = 995; Count.u64 = 995; Min.u64 = 1; Max.u64 = 1; core_19.cycles_max_reorder : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; core_19.cycles : Accumulator : Sum.u64 = 15247; SumSQ.u64 = 15247; Count.u64 = 15247; Min.u64 = 1; Max.u64 = 1; - dc_9:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2361; SumSQ.u64 = 7933; Count.u64 = 876; Min.u64 = 0; Max.u64 = 12; - dc_9:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 182; SumSQ.u64 = 388; Count.u64 = 107; Min.u64 = 0; Max.u64 = 3; - dc_9:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_9:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2710; SumSQ.u64 = 11764; Count.u64 = 773; Min.u64 = 0; Max.u64 = 13; - dc_9:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 876; Min.u64 = 0; Max.u64 = 1; - dc_9:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 107; Min.u64 = 0; Max.u64 = 0; - dc_9:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_9:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_9:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; - dc_9:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; - dc_9:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + dc_9:highlink:req.packet_latency : Accumulator : Sum.u64 = 2361; SumSQ.u64 = 7933; Count.u64 = 876; Min.u64 = 0; Max.u64 = 12; + dc_9:highlink:ack.packet_latency : Accumulator : Sum.u64 = 182; SumSQ.u64 = 388; Count.u64 = 107; Min.u64 = 0; Max.u64 = 3; + dc_9:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_9:highlink:data.packet_latency : Accumulator : Sum.u64 = 2710; SumSQ.u64 = 11764; Count.u64 = 773; Min.u64 = 0; Max.u64 = 13; + dc_9:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 876; Min.u64 = 0; Max.u64 = 1; + dc_9:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 107; Min.u64 = 0; Max.u64 = 0; + dc_9:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_9:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_9:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; + dc_9:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; + dc_9:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; dc_9.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.get_request_latency : Accumulator : Sum.u64 = 195234; SumSQ.u64 = 439737198; Count.u64 = 876; Min.u64 = 16; Max.u64 = 13553; @@ -9410,8 +9735,10 @@ Model complete dc_9.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.AckInv_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + dc_9.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_9.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9430,6 +9757,7 @@ Model complete dc_9.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_9.eventSent_FetchInvX : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; dc_9.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_9.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.eventSent_GetSResp : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; dc_9.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -9440,20 +9768,22 @@ Model complete dc_9.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_9.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_9.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_9.MSHR_occupancy : Accumulator : Sum.u64 = 193482; SumSQ.u64 = 2720890; Count.u64 = 18484; Min.u64 = 0; Max.u64 = 26; - l2cache_10:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2246; SumSQ.u64 = 8504; Count.u64 = 719; Min.u64 = 0; Max.u64 = 8; - l2cache_10:memlink:data.packet_latency : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 11966; Count.u64 = 769; Min.u64 = 0; Max.u64 = 11; - l2cache_10:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_10:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 719; Min.u64 = 0; Max.u64 = 1; - l2cache_10:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; - l2cache_10:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1488; Min.u64 = 0; Max.u64 = 1; - l2cache_10:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1488; Min.u64 = 0; Max.u64 = 1; - l2cache_10:memlink.ordering_latency : Accumulator : Sum.u64 = 6; SumSQ.u64 = 36; Count.u64 = 1; Min.u64 = 6; Max.u64 = 6; + l2cache_10:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2246; SumSQ.u64 = 8504; Count.u64 = 719; Min.u64 = 0; Max.u64 = 8; + l2cache_10:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 11966; Count.u64 = 769; Min.u64 = 0; Max.u64 = 11; + l2cache_10:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 719; Min.u64 = 0; Max.u64 = 1; + l2cache_10:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; + l2cache_10:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1488; Min.u64 = 0; Max.u64 = 1; + l2cache_10:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1488; Min.u64 = 0; Max.u64 = 1; + l2cache_10:lowlink.ordering_latency : Accumulator : Sum.u64 = 6; SumSQ.u64 = 36; Count.u64 = 1; Min.u64 = 6; Max.u64 = 6; l2cache_10.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_10.prefetches_issued : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; l2cache_10.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; @@ -9569,8 +9899,11 @@ Model complete l2cache_10.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FetchResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_FetchXResp : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_AckInv : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; @@ -9579,6 +9912,9 @@ Model complete l2cache_10.eventSent_GetXResp : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.eventSent_FetchInv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_10.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9603,6 +9939,7 @@ Model complete l2cache_10.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSHit_Arrival : Accumulator : Sum.u64 = 411; SumSQ.u64 = 411; Count.u64 = 411; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetXHit_Arrival : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9678,10 +10015,12 @@ Model complete l2cache_10.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache_10.GetXResp_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l2cache_10.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9693,6 +10032,9 @@ Model complete l2cache_10.FetchInvX_recv : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; l2cache_10.FetchResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_10.FetchXResp_recv : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; + l2cache_10.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_10.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_10.AckInv_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l2cache_10.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9765,13 +10107,16 @@ Model complete l1cache_20.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_20.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_20.eventSent_FetchXResp : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; l1cache_20.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_20.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_20.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_20.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_20.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9798,6 +10143,7 @@ Model complete l1cache_20.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_20.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.GetSHit_Arrival : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; l1cache_20.GetXHit_Arrival : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l1cache_20.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9844,14 +10190,18 @@ Model complete l1cache_20.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_20.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_20.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_20.GetXResp_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; l1cache_20.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_20.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_20.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; + l1cache_20.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_20.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_20.MSHR_occupancy : Accumulator : Sum.u64 = 272421; SumSQ.u64 = 5200827; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -9940,13 +10290,16 @@ Model complete l1cache_21.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_21.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_21.eventSent_FetchXResp : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; l1cache_21.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_21.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_21.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_21.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_21.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -9973,6 +10326,7 @@ Model complete l1cache_21.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_21.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.GetSHit_Arrival : Accumulator : Sum.u64 = 479; SumSQ.u64 = 479; Count.u64 = 479; Min.u64 = 1; Max.u64 = 1; l1cache_21.GetXHit_Arrival : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l1cache_21.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10019,14 +10373,18 @@ Model complete l1cache_21.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_21.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_21.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_21.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; l1cache_21.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_21.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_21.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; + l1cache_21.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_21.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_21.MSHR_occupancy : Accumulator : Sum.u64 = 240578; SumSQ.u64 = 4311472; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -10048,17 +10406,17 @@ Model complete core_21.cycles_max_issue : Accumulator : Sum.u64 = 1015; SumSQ.u64 = 1015; Count.u64 = 1015; Min.u64 = 1; Max.u64 = 1; core_21.cycles_max_reorder : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; core_21.cycles : Accumulator : Sum.u64 = 14078; SumSQ.u64 = 14078; Count.u64 = 14078; Min.u64 = 1; Max.u64 = 1; - dc_10:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2559; SumSQ.u64 = 9583; Count.u64 = 876; Min.u64 = 0; Max.u64 = 14; - dc_10:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 204; SumSQ.u64 = 506; Count.u64 = 107; Min.u64 = 0; Max.u64 = 4; - dc_10:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_10:cpulink:data.packet_latency : Accumulator : Sum.u64 = 1961; SumSQ.u64 = 7641; Count.u64 = 772; Min.u64 = 0; Max.u64 = 37; - dc_10:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 876; Min.u64 = 0; Max.u64 = 1; - dc_10:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 107; Min.u64 = 0; Max.u64 = 0; - dc_10:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_10:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_10:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1755; Min.u64 = 0; Max.u64 = 1; - dc_10:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1755; Min.u64 = 0; Max.u64 = 1; - dc_10:cpulink.ordering_latency : Accumulator : Sum.u64 = 2; SumSQ.u64 = 4; Count.u64 = 1; Min.u64 = 2; Max.u64 = 2; + dc_10:highlink:req.packet_latency : Accumulator : Sum.u64 = 2559; SumSQ.u64 = 9583; Count.u64 = 876; Min.u64 = 0; Max.u64 = 14; + dc_10:highlink:ack.packet_latency : Accumulator : Sum.u64 = 204; SumSQ.u64 = 506; Count.u64 = 107; Min.u64 = 0; Max.u64 = 4; + dc_10:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_10:highlink:data.packet_latency : Accumulator : Sum.u64 = 1961; SumSQ.u64 = 7641; Count.u64 = 772; Min.u64 = 0; Max.u64 = 37; + dc_10:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 876; Min.u64 = 0; Max.u64 = 1; + dc_10:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 107; Min.u64 = 0; Max.u64 = 0; + dc_10:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_10:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_10:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1755; Min.u64 = 0; Max.u64 = 1; + dc_10:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1755; Min.u64 = 0; Max.u64 = 1; + dc_10:highlink.ordering_latency : Accumulator : Sum.u64 = 2; SumSQ.u64 = 4; Count.u64 = 1; Min.u64 = 2; Max.u64 = 2; dc_10.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.get_request_latency : Accumulator : Sum.u64 = 198324; SumSQ.u64 = 550455986; Count.u64 = 876; Min.u64 = 16; Max.u64 = 12803; @@ -10081,8 +10439,10 @@ Model complete dc_10.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.AckInv_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + dc_10.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_10.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10101,6 +10461,7 @@ Model complete dc_10.eventSent_FetchInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; dc_10.eventSent_FetchInvX : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; dc_10.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_10.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.eventSent_GetSResp : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; dc_10.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -10111,6 +10472,8 @@ Model complete dc_10.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_10.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_10.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_10.MSHR_occupancy : Accumulator : Sum.u64 = 196572; SumSQ.u64 = 2813112; Count.u64 = 18513; Min.u64 = 0; Max.u64 = 28; @@ -10128,28 +10491,28 @@ Model complete ddr_1.cycles_with_issue : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; ddr_1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 8937; SumSQ.u64 = 8937; Count.u64 = 8937; Min.u64 = 1; Max.u64 = 1; ddr_1.total_cycles : Accumulator : Sum.u64 = 13915; SumSQ.u64 = 193627225; Count.u64 = 1; Min.u64 = 13915; Max.u64 = 13915; - ddr_1:cpulink:req.packet_latency : Accumulator : Sum.u64 = 10616; SumSQ.u64 = 46966; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 11; - ddr_1:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; - ddr_1:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2477; SumSQ.u64 = 10307; Count.u64 = 716; Min.u64 = 0; Max.u64 = 11; - l2cache_11:memlink:data.packet_latency : Accumulator : Sum.u64 = 2946; SumSQ.u64 = 13728; Count.u64 = 776; Min.u64 = 0; Max.u64 = 15; - l2cache_11:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_11:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 716; Min.u64 = 0; Max.u64 = 1; - l2cache_11:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; - l2cache_11:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1492; Min.u64 = 0; Max.u64 = 1; - l2cache_11:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1492; Min.u64 = 0; Max.u64 = 1; - l2cache_11:memlink.ordering_latency : Accumulator : Sum.u64 = 2; SumSQ.u64 = 4; Count.u64 = 1; Min.u64 = 2; Max.u64 = 2; + ddr_1:highlink:req.packet_latency : Accumulator : Sum.u64 = 10616; SumSQ.u64 = 46966; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 11; + ddr_1:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3002; Min.u64 = 0; Max.u64 = 0; + ddr_1:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2477; SumSQ.u64 = 10307; Count.u64 = 716; Min.u64 = 0; Max.u64 = 11; + l2cache_11:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2946; SumSQ.u64 = 13728; Count.u64 = 776; Min.u64 = 0; Max.u64 = 15; + l2cache_11:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 716; Min.u64 = 0; Max.u64 = 1; + l2cache_11:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; + l2cache_11:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1492; Min.u64 = 0; Max.u64 = 1; + l2cache_11:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1492; Min.u64 = 0; Max.u64 = 1; + l2cache_11:lowlink.ordering_latency : Accumulator : Sum.u64 = 2; SumSQ.u64 = 4; Count.u64 = 1; Min.u64 = 2; Max.u64 = 2; l2cache_11.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_11.prefetches_issued : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; l2cache_11.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -10265,8 +10628,11 @@ Model complete l2cache_11.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FetchResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_FetchXResp : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_AckInv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; @@ -10275,6 +10641,9 @@ Model complete l2cache_11.eventSent_GetXResp : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.eventSent_FetchInv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_11.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10299,6 +10668,7 @@ Model complete l2cache_11.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSHit_Arrival : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetXHit_Arrival : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10374,10 +10744,12 @@ Model complete l2cache_11.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.GetSResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache_11.GetXResp_recv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; l2cache_11.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10389,6 +10761,9 @@ Model complete l2cache_11.FetchInvX_recv : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; l2cache_11.FetchResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_11.FetchXResp_recv : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l2cache_11.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_11.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_11.AckInv_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l2cache_11.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10461,13 +10836,16 @@ Model complete l1cache_22.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_22.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_22.eventSent_FetchXResp : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; l1cache_22.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_22.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_22.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_22.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_22.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10494,6 +10872,7 @@ Model complete l1cache_22.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_22.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.GetSHit_Arrival : Accumulator : Sum.u64 = 594; SumSQ.u64 = 594; Count.u64 = 594; Min.u64 = 1; Max.u64 = 1; l1cache_22.GetXHit_Arrival : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; l1cache_22.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10540,14 +10919,18 @@ Model complete l1cache_22.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_22.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_22.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_22.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; l1cache_22.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_22.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_22.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_22.FetchInvX_recv : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l1cache_22.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_22.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_22.MSHR_occupancy : Accumulator : Sum.u64 = 240796; SumSQ.u64 = 4276110; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -10636,13 +11019,16 @@ Model complete l1cache_23.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_23.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_23.eventSent_FetchXResp : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; l1cache_23.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_23.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_23.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_23.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_23.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10669,6 +11055,7 @@ Model complete l1cache_23.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_23.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.GetSHit_Arrival : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; l1cache_23.GetXHit_Arrival : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l1cache_23.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10715,14 +11102,18 @@ Model complete l1cache_23.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_23.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_23.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.GetSResp_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_23.GetXResp_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; l1cache_23.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_23.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_23.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; + l1cache_23.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_23.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_23.MSHR_occupancy : Accumulator : Sum.u64 = 243755; SumSQ.u64 = 4241675; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -10744,17 +11135,17 @@ Model complete core_23.cycles_max_issue : Accumulator : Sum.u64 = 1014; SumSQ.u64 = 1014; Count.u64 = 1014; Min.u64 = 1; Max.u64 = 1; core_23.cycles_max_reorder : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; core_23.cycles : Accumulator : Sum.u64 = 14637; SumSQ.u64 = 14637; Count.u64 = 14637; Min.u64 = 1; Max.u64 = 1; - dc_11:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2969; SumSQ.u64 = 12531; Count.u64 = 875; Min.u64 = 0; Max.u64 = 11; - dc_11:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 254; SumSQ.u64 = 766; Count.u64 = 105; Min.u64 = 0; Max.u64 = 5; - dc_11:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_11:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2868; SumSQ.u64 = 53214; Count.u64 = 772; Min.u64 = 0; Max.u64 = 143; - dc_11:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 875; Min.u64 = 0; Max.u64 = 1; - dc_11:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; - dc_11:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_11:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_11:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 1; - dc_11:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 1; - dc_11:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + dc_11:highlink:req.packet_latency : Accumulator : Sum.u64 = 2969; SumSQ.u64 = 12531; Count.u64 = 875; Min.u64 = 0; Max.u64 = 11; + dc_11:highlink:ack.packet_latency : Accumulator : Sum.u64 = 254; SumSQ.u64 = 766; Count.u64 = 105; Min.u64 = 0; Max.u64 = 5; + dc_11:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_11:highlink:data.packet_latency : Accumulator : Sum.u64 = 2868; SumSQ.u64 = 53214; Count.u64 = 772; Min.u64 = 0; Max.u64 = 143; + dc_11:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 875; Min.u64 = 0; Max.u64 = 1; + dc_11:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; + dc_11:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_11:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_11:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 1; + dc_11:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 1; + dc_11:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; dc_11.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.get_request_latency : Accumulator : Sum.u64 = 201203; SumSQ.u64 = 579600613; Count.u64 = 875; Min.u64 = 9; Max.u64 = 13278; @@ -10777,8 +11168,10 @@ Model complete dc_11.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.AckInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + dc_11.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_11.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10797,6 +11190,7 @@ Model complete dc_11.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_11.eventSent_FetchInvX : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; dc_11.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_11.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.eventSent_GetSResp : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; dc_11.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -10807,6 +11201,8 @@ Model complete dc_11.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_11.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_11.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_11.MSHR_occupancy : Accumulator : Sum.u64 = 199453; SumSQ.u64 = 2901273; Count.u64 = 18529; Min.u64 = 0; Max.u64 = 26; @@ -10824,28 +11220,28 @@ Model complete ddr_2.cycles_with_issue : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; ddr_2.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 8969; SumSQ.u64 = 8969; Count.u64 = 8969; Min.u64 = 1; Max.u64 = 1; ddr_2.total_cycles : Accumulator : Sum.u64 = 13915; SumSQ.u64 = 193627225; Count.u64 = 1; Min.u64 = 13915; Max.u64 = 13915; - ddr_2:cpulink:req.packet_latency : Accumulator : Sum.u64 = 10764; SumSQ.u64 = 45496; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 11; - ddr_2:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_2:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2354; SumSQ.u64 = 9120; Count.u64 = 727; Min.u64 = 0; Max.u64 = 8; - l2cache_12:memlink:data.packet_latency : Accumulator : Sum.u64 = 2687; SumSQ.u64 = 11375; Count.u64 = 774; Min.u64 = 0; Max.u64 = 10; - l2cache_12:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 727; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 0; - l2cache_12:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink:req.packet_latency : Accumulator : Sum.u64 = 10764; SumSQ.u64 = 45496; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 11; + ddr_2:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_2:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2354; SumSQ.u64 = 9120; Count.u64 = 727; Min.u64 = 0; Max.u64 = 8; + l2cache_12:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2687; SumSQ.u64 = 11375; Count.u64 = 774; Min.u64 = 0; Max.u64 = 10; + l2cache_12:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 727; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 0; + l2cache_12:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_12.prefetches_issued : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; l2cache_12.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; @@ -10961,8 +11357,11 @@ Model complete l2cache_12.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FetchResp : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_FetchXResp : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_AckInv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; @@ -10971,6 +11370,9 @@ Model complete l2cache_12.eventSent_GetXResp : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.eventSent_FetchInv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; l2cache_12.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -10995,6 +11397,7 @@ Model complete l2cache_12.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSHit_Arrival : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetXHit_Arrival : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11070,10 +11473,12 @@ Model complete l2cache_12.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.GetSResp_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache_12.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_12.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11085,6 +11490,9 @@ Model complete l2cache_12.FetchInvX_recv : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; l2cache_12.FetchResp_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; l2cache_12.FetchXResp_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; + l2cache_12.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_12.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_12.AckInv_recv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; l2cache_12.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11157,13 +11565,16 @@ Model complete l1cache_24.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_24.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_24.eventSent_FetchXResp : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; l1cache_24.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_24.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_24.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_24.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_24.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11190,6 +11601,7 @@ Model complete l1cache_24.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_24.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.GetSHit_Arrival : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; l1cache_24.GetXHit_Arrival : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; l1cache_24.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11236,14 +11648,18 @@ Model complete l1cache_24.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_24.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_24.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_24.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_24.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_24.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_24.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; + l1cache_24.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_24.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_24.MSHR_occupancy : Accumulator : Sum.u64 = 246034; SumSQ.u64 = 4279932; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -11332,13 +11748,16 @@ Model complete l1cache_25.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_25.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache_25.eventSent_FetchXResp : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; l1cache_25.eventSent_AckInv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache_25.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_25.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_25.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_25.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11365,6 +11784,7 @@ Model complete l1cache_25.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_25.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.GetSHit_Arrival : Accumulator : Sum.u64 = 577; SumSQ.u64 = 577; Count.u64 = 577; Min.u64 = 1; Max.u64 = 1; l1cache_25.GetXHit_Arrival : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l1cache_25.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11411,14 +11831,18 @@ Model complete l1cache_25.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_25.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_25.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_25.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_25.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.Inv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l1cache_25.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.FetchInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l1cache_25.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_25.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_25.MSHR_occupancy : Accumulator : Sum.u64 = 257383; SumSQ.u64 = 4558207; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -11440,17 +11864,17 @@ Model complete core_25.cycles_max_issue : Accumulator : Sum.u64 = 1014; SumSQ.u64 = 1014; Count.u64 = 1014; Min.u64 = 1; Max.u64 = 1; core_25.cycles_max_reorder : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; core_25.cycles : Accumulator : Sum.u64 = 15131; SumSQ.u64 = 15131; Count.u64 = 15131; Min.u64 = 1; Max.u64 = 1; - dc_12:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2727; SumSQ.u64 = 10901; Count.u64 = 877; Min.u64 = 0; Max.u64 = 19; - dc_12:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 266; SumSQ.u64 = 838; Count.u64 = 108; Min.u64 = 0; Max.u64 = 5; - dc_12:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_12:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 18726; Count.u64 = 773; Min.u64 = 0; Max.u64 = 51; - dc_12:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 877; Min.u64 = 0; Max.u64 = 1; - dc_12:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 108; Min.u64 = 0; Max.u64 = 1; - dc_12:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_12:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_12:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 1; - dc_12:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 1; - dc_12:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 2; Min.u64 = 1; Max.u64 = 2; + dc_12:highlink:req.packet_latency : Accumulator : Sum.u64 = 2727; SumSQ.u64 = 10901; Count.u64 = 877; Min.u64 = 0; Max.u64 = 19; + dc_12:highlink:ack.packet_latency : Accumulator : Sum.u64 = 266; SumSQ.u64 = 838; Count.u64 = 108; Min.u64 = 0; Max.u64 = 5; + dc_12:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_12:highlink:data.packet_latency : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 18726; Count.u64 = 773; Min.u64 = 0; Max.u64 = 51; + dc_12:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 877; Min.u64 = 0; Max.u64 = 1; + dc_12:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 108; Min.u64 = 0; Max.u64 = 1; + dc_12:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_12:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_12:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 1; + dc_12:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 1; + dc_12:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 2; Min.u64 = 1; Max.u64 = 2; dc_12.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.get_request_latency : Accumulator : Sum.u64 = 192713; SumSQ.u64 = 553545495; Count.u64 = 877; Min.u64 = 16; Max.u64 = 13336; @@ -11473,8 +11897,10 @@ Model complete dc_12.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.AckInv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + dc_12.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_12.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11493,6 +11919,7 @@ Model complete dc_12.eventSent_FetchInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; dc_12.eventSent_FetchInvX : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_12.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_12.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; dc_12.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -11503,20 +11930,22 @@ Model complete dc_12.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_12.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_12.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_12.MSHR_occupancy : Accumulator : Sum.u64 = 190959; SumSQ.u64 = 2662721; Count.u64 = 18359; Min.u64 = 0; Max.u64 = 26; - l2cache_13:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2083; SumSQ.u64 = 7083; Count.u64 = 729; Min.u64 = 0; Max.u64 = 6; - l2cache_13:memlink:data.packet_latency : Accumulator : Sum.u64 = 2648; SumSQ.u64 = 12436; Count.u64 = 768; Min.u64 = 0; Max.u64 = 19; - l2cache_13:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_13:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 729; Min.u64 = 0; Max.u64 = 1; - l2cache_13:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 768; Min.u64 = 0; Max.u64 = 0; - l2cache_13:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; - l2cache_13:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; - l2cache_13:memlink.ordering_latency : Accumulator : Sum.u64 = 11; SumSQ.u64 = 73; Count.u64 = 2; Min.u64 = 3; Max.u64 = 8; + l2cache_13:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2083; SumSQ.u64 = 7083; Count.u64 = 729; Min.u64 = 0; Max.u64 = 6; + l2cache_13:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2648; SumSQ.u64 = 12436; Count.u64 = 768; Min.u64 = 0; Max.u64 = 19; + l2cache_13:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 729; Min.u64 = 0; Max.u64 = 1; + l2cache_13:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 768; Min.u64 = 0; Max.u64 = 0; + l2cache_13:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; + l2cache_13:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; + l2cache_13:lowlink.ordering_latency : Accumulator : Sum.u64 = 11; SumSQ.u64 = 73; Count.u64 = 2; Min.u64 = 3; Max.u64 = 8; l2cache_13.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_13.prefetches_issued : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; l2cache_13.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; @@ -11632,8 +12061,11 @@ Model complete l2cache_13.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FetchResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_FetchXResp : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_AckInv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; @@ -11642,6 +12074,9 @@ Model complete l2cache_13.eventSent_GetXResp : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.eventSent_FetchInv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_13.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11666,6 +12101,7 @@ Model complete l2cache_13.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSHit_Arrival : Accumulator : Sum.u64 = 433; SumSQ.u64 = 433; Count.u64 = 433; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetXHit_Arrival : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11741,10 +12177,12 @@ Model complete l2cache_13.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.GetSResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache_13.GetXResp_recv : Accumulator : Sum.u64 = 749; SumSQ.u64 = 749; Count.u64 = 749; Min.u64 = 1; Max.u64 = 1; l2cache_13.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11756,6 +12194,9 @@ Model complete l2cache_13.FetchInvX_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; l2cache_13.FetchResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_13.FetchXResp_recv : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; + l2cache_13.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_13.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_13.AckInv_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; l2cache_13.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11828,13 +12269,16 @@ Model complete l1cache_26.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_26.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_FetchResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache_26.eventSent_FetchXResp : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; l1cache_26.eventSent_AckInv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l1cache_26.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_26.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_26.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_26.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11861,6 +12305,7 @@ Model complete l1cache_26.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_26.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.GetSHit_Arrival : Accumulator : Sum.u64 = 575; SumSQ.u64 = 575; Count.u64 = 575; Min.u64 = 1; Max.u64 = 1; l1cache_26.GetXHit_Arrival : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; l1cache_26.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -11907,14 +12352,18 @@ Model complete l1cache_26.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_26.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_26.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_26.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_26.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.Inv_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l1cache_26.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.FetchInv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; + l1cache_26.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_26.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_26.MSHR_occupancy : Accumulator : Sum.u64 = 286401; SumSQ.u64 = 5044641; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -12003,13 +12452,16 @@ Model complete l1cache_27.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_27.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_27.eventSent_FetchXResp : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; l1cache_27.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_27.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_27.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_27.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_27.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12036,6 +12488,7 @@ Model complete l1cache_27.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_27.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.GetSHit_Arrival : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; l1cache_27.GetXHit_Arrival : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; l1cache_27.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12082,14 +12535,18 @@ Model complete l1cache_27.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_27.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_27.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_27.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_27.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_27.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_27.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l1cache_27.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_27.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_27.MSHR_occupancy : Accumulator : Sum.u64 = 306247; SumSQ.u64 = 5520807; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -12111,17 +12568,17 @@ Model complete core_27.cycles_max_issue : Accumulator : Sum.u64 = 996; SumSQ.u64 = 996; Count.u64 = 996; Min.u64 = 1; Max.u64 = 1; core_27.cycles_max_reorder : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; core_27.cycles : Accumulator : Sum.u64 = 17721; SumSQ.u64 = 17721; Count.u64 = 17721; Min.u64 = 1; Max.u64 = 1; - dc_13:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 7639; Count.u64 = 877; Min.u64 = 0; Max.u64 = 8; - dc_13:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 217; SumSQ.u64 = 569; Count.u64 = 109; Min.u64 = 0; Max.u64 = 5; - dc_13:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2125; SumSQ.u64 = 8523; Count.u64 = 772; Min.u64 = 0; Max.u64 = 33; - dc_13:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 877; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 109; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 0; - dc_13:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink:req.packet_latency : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 7639; Count.u64 = 877; Min.u64 = 0; Max.u64 = 8; + dc_13:highlink:ack.packet_latency : Accumulator : Sum.u64 = 217; SumSQ.u64 = 569; Count.u64 = 109; Min.u64 = 0; Max.u64 = 5; + dc_13:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink:data.packet_latency : Accumulator : Sum.u64 = 2125; SumSQ.u64 = 8523; Count.u64 = 772; Min.u64 = 0; Max.u64 = 33; + dc_13:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 877; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 109; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1758; Min.u64 = 0; Max.u64 = 0; + dc_13:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.get_request_latency : Accumulator : Sum.u64 = 205636; SumSQ.u64 = 500957112; Count.u64 = 877; Min.u64 = 16; Max.u64 = 13639; @@ -12144,8 +12601,10 @@ Model complete dc_13.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.AckInv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + dc_13.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12164,6 +12623,7 @@ Model complete dc_13.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; dc_13.eventSent_FetchInvX : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_13.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; dc_13.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -12174,20 +12634,22 @@ Model complete dc_13.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_13.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_13.MSHR_occupancy : Accumulator : Sum.u64 = 203882; SumSQ.u64 = 3065042; Count.u64 = 18381; Min.u64 = 0; Max.u64 = 32; - l2cache_14:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 1929; SumSQ.u64 = 5987; Count.u64 = 726; Min.u64 = 0; Max.u64 = 7; - l2cache_14:memlink:data.packet_latency : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 12658; Count.u64 = 775; Min.u64 = 0; Max.u64 = 28; - l2cache_14:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_14:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 726; Min.u64 = 0; Max.u64 = 1; - l2cache_14:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; - l2cache_14:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 1; - l2cache_14:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 1; - l2cache_14:memlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + l2cache_14:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 1929; SumSQ.u64 = 5987; Count.u64 = 726; Min.u64 = 0; Max.u64 = 7; + l2cache_14:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 12658; Count.u64 = 775; Min.u64 = 0; Max.u64 = 28; + l2cache_14:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 726; Min.u64 = 0; Max.u64 = 1; + l2cache_14:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; + l2cache_14:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 1; + l2cache_14:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1501; Min.u64 = 0; Max.u64 = 1; + l2cache_14:lowlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; l2cache_14.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_14.prefetches_issued : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; l2cache_14.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; @@ -12303,8 +12765,11 @@ Model complete l2cache_14.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FetchResp : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_FetchXResp : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_AckInv : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; @@ -12313,6 +12778,9 @@ Model complete l2cache_14.eventSent_GetXResp : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.eventSent_FetchInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_14.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12337,6 +12805,7 @@ Model complete l2cache_14.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSHit_Arrival : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetXHit_Arrival : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12412,10 +12881,12 @@ Model complete l2cache_14.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.GetSResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache_14.GetXResp_recv : Accumulator : Sum.u64 = 749; SumSQ.u64 = 749; Count.u64 = 749; Min.u64 = 1; Max.u64 = 1; l2cache_14.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12427,6 +12898,9 @@ Model complete l2cache_14.FetchInvX_recv : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; l2cache_14.FetchResp_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; l2cache_14.FetchXResp_recv : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache_14.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_14.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_14.AckInv_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l2cache_14.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12499,13 +12973,16 @@ Model complete l1cache_28.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_28.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_28.eventSent_FetchXResp : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; l1cache_28.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_28.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_28.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_28.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_28.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12532,6 +13009,7 @@ Model complete l1cache_28.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_28.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.GetSHit_Arrival : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; l1cache_28.GetXHit_Arrival : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l1cache_28.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12578,14 +13056,18 @@ Model complete l1cache_28.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_28.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_28.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_28.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_28.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_28.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_28.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; + l1cache_28.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_28.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_28.MSHR_occupancy : Accumulator : Sum.u64 = 296986; SumSQ.u64 = 5266892; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -12674,13 +13156,16 @@ Model complete l1cache_29.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_29.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_FetchResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache_29.eventSent_FetchXResp : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; l1cache_29.eventSent_AckInv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache_29.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_29.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_29.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_29.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12707,6 +13192,7 @@ Model complete l1cache_29.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_29.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.GetSHit_Arrival : Accumulator : Sum.u64 = 612; SumSQ.u64 = 612; Count.u64 = 612; Min.u64 = 1; Max.u64 = 1; l1cache_29.GetXHit_Arrival : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l1cache_29.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12753,14 +13239,18 @@ Model complete l1cache_29.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_29.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_29.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_29.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_29.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_29.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.Inv_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache_29.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l1cache_29.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_29.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_29.MSHR_occupancy : Accumulator : Sum.u64 = 298197; SumSQ.u64 = 5237453; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -12782,17 +13272,17 @@ Model complete core_29.cycles_max_issue : Accumulator : Sum.u64 = 978; SumSQ.u64 = 978; Count.u64 = 978; Min.u64 = 1; Max.u64 = 1; core_29.cycles_max_reorder : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; core_29.cycles : Accumulator : Sum.u64 = 17620; SumSQ.u64 = 17620; Count.u64 = 17620; Min.u64 = 1; Max.u64 = 1; - dc_14:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2180; SumSQ.u64 = 6524; Count.u64 = 878; Min.u64 = 0; Max.u64 = 7; - dc_14:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 210; SumSQ.u64 = 480; Count.u64 = 110; Min.u64 = 0; Max.u64 = 4; - dc_14:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2939; SumSQ.u64 = 16341; Count.u64 = 773; Min.u64 = 0; Max.u64 = 47; - dc_14:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 878; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1761; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1761; Min.u64 = 0; Max.u64 = 0; - dc_14:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink:req.packet_latency : Accumulator : Sum.u64 = 2180; SumSQ.u64 = 6524; Count.u64 = 878; Min.u64 = 0; Max.u64 = 7; + dc_14:highlink:ack.packet_latency : Accumulator : Sum.u64 = 210; SumSQ.u64 = 480; Count.u64 = 110; Min.u64 = 0; Max.u64 = 4; + dc_14:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink:data.packet_latency : Accumulator : Sum.u64 = 2939; SumSQ.u64 = 16341; Count.u64 = 773; Min.u64 = 0; Max.u64 = 47; + dc_14:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 878; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1761; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1761; Min.u64 = 0; Max.u64 = 0; + dc_14:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.get_request_latency : Accumulator : Sum.u64 = 188326; SumSQ.u64 = 323739440; Count.u64 = 878; Min.u64 = 7; Max.u64 = 12826; @@ -12815,8 +13305,10 @@ Model complete dc_14.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.AckInv_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + dc_14.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -12835,6 +13327,7 @@ Model complete dc_14.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; dc_14.eventSent_FetchInvX : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; dc_14.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.eventSent_GetSResp : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; dc_14.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -12845,20 +13338,22 @@ Model complete dc_14.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_14.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_14.MSHR_occupancy : Accumulator : Sum.u64 = 186570; SumSQ.u64 = 2548974; Count.u64 = 18414; Min.u64 = 0; Max.u64 = 28; - l2cache_15:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 1901; SumSQ.u64 = 5823; Count.u64 = 721; Min.u64 = 0; Max.u64 = 7; - l2cache_15:memlink:data.packet_latency : Accumulator : Sum.u64 = 2690; SumSQ.u64 = 13352; Count.u64 = 778; Min.u64 = 0; Max.u64 = 21; - l2cache_15:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_15:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 721; Min.u64 = 0; Max.u64 = 1; - l2cache_15:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 778; Min.u64 = 0; Max.u64 = 0; - l2cache_15:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1499; Min.u64 = 0; Max.u64 = 1; - l2cache_15:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1499; Min.u64 = 0; Max.u64 = 1; - l2cache_15:memlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_15:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 1901; SumSQ.u64 = 5823; Count.u64 = 721; Min.u64 = 0; Max.u64 = 7; + l2cache_15:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2690; SumSQ.u64 = 13352; Count.u64 = 778; Min.u64 = 0; Max.u64 = 21; + l2cache_15:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 721; Min.u64 = 0; Max.u64 = 1; + l2cache_15:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 778; Min.u64 = 0; Max.u64 = 0; + l2cache_15:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1499; Min.u64 = 0; Max.u64 = 1; + l2cache_15:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1499; Min.u64 = 0; Max.u64 = 1; + l2cache_15:lowlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_15.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_15.prefetches_issued : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; l2cache_15.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; @@ -12974,8 +13469,11 @@ Model complete l2cache_15.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FetchResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_FetchXResp : Accumulator : Sum.u64 = 464; SumSQ.u64 = 464; Count.u64 = 464; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_AckInv : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; @@ -12984,6 +13482,9 @@ Model complete l2cache_15.eventSent_GetXResp : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.eventSent_FetchInv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_15.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13008,6 +13509,7 @@ Model complete l2cache_15.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSHit_Arrival : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; l2cache_15.GetXHit_Arrival : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; l2cache_15.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13083,10 +13585,12 @@ Model complete l2cache_15.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.GetSResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache_15.GetXResp_recv : Accumulator : Sum.u64 = 749; SumSQ.u64 = 749; Count.u64 = 749; Min.u64 = 1; Max.u64 = 1; l2cache_15.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13098,6 +13602,9 @@ Model complete l2cache_15.FetchInvX_recv : Accumulator : Sum.u64 = 464; SumSQ.u64 = 464; Count.u64 = 464; Min.u64 = 1; Max.u64 = 1; l2cache_15.FetchResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2cache_15.FetchXResp_recv : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; + l2cache_15.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_15.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_15.AckInv_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; l2cache_15.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13170,13 +13677,16 @@ Model complete l1cache_30.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_30.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_FetchResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache_30.eventSent_FetchXResp : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; l1cache_30.eventSent_AckInv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache_30.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_30.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_30.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_30.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13203,6 +13713,7 @@ Model complete l1cache_30.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_30.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.GetSHit_Arrival : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; l1cache_30.GetXHit_Arrival : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; l1cache_30.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13249,14 +13760,18 @@ Model complete l1cache_30.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_30.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_30.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_30.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_30.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_30.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.Inv_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache_30.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.FetchInv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache_30.FetchInvX_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; + l1cache_30.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_30.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_30.MSHR_occupancy : Accumulator : Sum.u64 = 306173; SumSQ.u64 = 5547517; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -13345,13 +13860,16 @@ Model complete l1cache_31.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_31.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_31.eventSent_FetchXResp : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; l1cache_31.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_31.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_31.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_31.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_31.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13378,6 +13896,7 @@ Model complete l1cache_31.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_31.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.GetSHit_Arrival : Accumulator : Sum.u64 = 609; SumSQ.u64 = 609; Count.u64 = 609; Min.u64 = 1; Max.u64 = 1; l1cache_31.GetXHit_Arrival : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; l1cache_31.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13424,14 +13943,18 @@ Model complete l1cache_31.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_31.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_31.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.GetSResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_31.GetXResp_recv : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; l1cache_31.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_31.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_31.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + l1cache_31.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_31.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_31.MSHR_occupancy : Accumulator : Sum.u64 = 305088; SumSQ.u64 = 5488200; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -13453,17 +13976,17 @@ Model complete core_31.cycles_max_issue : Accumulator : Sum.u64 = 971; SumSQ.u64 = 971; Count.u64 = 971; Min.u64 = 1; Max.u64 = 1; core_31.cycles_max_reorder : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; core_31.cycles : Accumulator : Sum.u64 = 17699; SumSQ.u64 = 17699; Count.u64 = 17699; Min.u64 = 1; Max.u64 = 1; - dc_15:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2170; SumSQ.u64 = 6586; Count.u64 = 878; Min.u64 = 0; Max.u64 = 9; - dc_15:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 205; SumSQ.u64 = 481; Count.u64 = 110; Min.u64 = 0; Max.u64 = 4; - dc_15:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4153; SumSQ.u64 = 102313; Count.u64 = 774; Min.u64 = 0; Max.u64 = 142; - dc_15:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 878; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; - dc_15:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink:req.packet_latency : Accumulator : Sum.u64 = 2170; SumSQ.u64 = 6586; Count.u64 = 878; Min.u64 = 0; Max.u64 = 9; + dc_15:highlink:ack.packet_latency : Accumulator : Sum.u64 = 205; SumSQ.u64 = 481; Count.u64 = 110; Min.u64 = 0; Max.u64 = 4; + dc_15:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink:data.packet_latency : Accumulator : Sum.u64 = 4153; SumSQ.u64 = 102313; Count.u64 = 774; Min.u64 = 0; Max.u64 = 142; + dc_15:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 878; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; + dc_15:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.get_request_latency : Accumulator : Sum.u64 = 192635; SumSQ.u64 = 425592469; Count.u64 = 878; Min.u64 = 16; Max.u64 = 13491; @@ -13486,8 +14009,10 @@ Model complete dc_15.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.AckInv_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + dc_15.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13506,6 +14031,7 @@ Model complete dc_15.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; dc_15.eventSent_FetchInvX : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; dc_15.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.eventSent_GetSResp : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; dc_15.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -13516,20 +14042,22 @@ Model complete dc_15.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_15.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_15.MSHR_occupancy : Accumulator : Sum.u64 = 190879; SumSQ.u64 = 2608419; Count.u64 = 18435; Min.u64 = 0; Max.u64 = 26; - l2cache_16:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_16:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_16:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2064; SumSQ.u64 = 6984; Count.u64 = 725; Min.u64 = 0; Max.u64 = 6; - l2cache_16:memlink:data.packet_latency : Accumulator : Sum.u64 = 2806; SumSQ.u64 = 15592; Count.u64 = 772; Min.u64 = 0; Max.u64 = 28; - l2cache_16:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_16:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_16:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 725; Min.u64 = 0; Max.u64 = 1; - l2cache_16:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - l2cache_16:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; - l2cache_16:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; - l2cache_16:memlink.ordering_latency : Accumulator : Sum.u64 = 26; SumSQ.u64 = 676; Count.u64 = 1; Min.u64 = 26; Max.u64 = 26; + l2cache_16:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2064; SumSQ.u64 = 6984; Count.u64 = 725; Min.u64 = 0; Max.u64 = 6; + l2cache_16:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2806; SumSQ.u64 = 15592; Count.u64 = 772; Min.u64 = 0; Max.u64 = 28; + l2cache_16:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 725; Min.u64 = 0; Max.u64 = 1; + l2cache_16:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + l2cache_16:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; + l2cache_16:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1497; Min.u64 = 0; Max.u64 = 1; + l2cache_16:lowlink.ordering_latency : Accumulator : Sum.u64 = 26; SumSQ.u64 = 676; Count.u64 = 1; Min.u64 = 26; Max.u64 = 26; l2cache_16.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_16.prefetches_issued : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; l2cache_16.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; @@ -13645,8 +14173,11 @@ Model complete l2cache_16.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_FetchResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_16.eventSent_FetchXResp : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l2cache_16.eventSent_AckInv : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; @@ -13655,6 +14186,9 @@ Model complete l2cache_16.eventSent_GetXResp : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_16.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.eventSent_FetchInv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_16.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13679,6 +14213,7 @@ Model complete l2cache_16.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.GetSHit_Arrival : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; l2cache_16.GetXHit_Arrival : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l2cache_16.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13754,10 +14289,12 @@ Model complete l2cache_16.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache_16.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_16.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13769,6 +14306,9 @@ Model complete l2cache_16.FetchInvX_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l2cache_16.FetchResp_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2cache_16.FetchXResp_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; + l2cache_16.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_16.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_16.AckInv_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; l2cache_16.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13841,13 +14381,16 @@ Model complete l1cache_32.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_32.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache_32.eventSent_FetchXResp : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; l1cache_32.eventSent_AckInv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l1cache_32.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_32.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_32.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_32.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13874,6 +14417,7 @@ Model complete l1cache_32.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_32.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.GetSHit_Arrival : Accumulator : Sum.u64 = 610; SumSQ.u64 = 610; Count.u64 = 610; Min.u64 = 1; Max.u64 = 1; l1cache_32.GetXHit_Arrival : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; l1cache_32.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -13920,14 +14464,18 @@ Model complete l1cache_32.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_32.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_32.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_32.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_32.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_32.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.Inv_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l1cache_32.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache_32.FetchInvX_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; + l1cache_32.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_32.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_32.MSHR_occupancy : Accumulator : Sum.u64 = 294118; SumSQ.u64 = 5169746; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -14016,13 +14564,16 @@ Model complete l1cache_33.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_33.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_33.eventSent_FetchXResp : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l1cache_33.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_33.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_33.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_33.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_33.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14049,6 +14600,7 @@ Model complete l1cache_33.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_33.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.GetSHit_Arrival : Accumulator : Sum.u64 = 526; SumSQ.u64 = 526; Count.u64 = 526; Min.u64 = 1; Max.u64 = 1; l1cache_33.GetXHit_Arrival : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l1cache_33.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14095,14 +14647,18 @@ Model complete l1cache_33.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_33.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_33.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_33.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_33.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_33.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_33.FetchInvX_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; + l1cache_33.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_33.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_33.MSHR_occupancy : Accumulator : Sum.u64 = 297118; SumSQ.u64 = 5285748; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -14124,17 +14680,17 @@ Model complete core_33.cycles_max_issue : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; core_33.cycles_max_reorder : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; core_33.cycles : Accumulator : Sum.u64 = 17416; SumSQ.u64 = 17416; Count.u64 = 17416; Min.u64 = 1; Max.u64 = 1; - dc_16:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2354; SumSQ.u64 = 7964; Count.u64 = 877; Min.u64 = 0; Max.u64 = 16; - dc_16:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 234; SumSQ.u64 = 608; Count.u64 = 112; Min.u64 = 0; Max.u64 = 4; - dc_16:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 46433; Count.u64 = 773; Min.u64 = 0; Max.u64 = 60; - dc_16:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 877; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 112; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; - dc_16:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink:req.packet_latency : Accumulator : Sum.u64 = 2354; SumSQ.u64 = 7964; Count.u64 = 877; Min.u64 = 0; Max.u64 = 16; + dc_16:highlink:ack.packet_latency : Accumulator : Sum.u64 = 234; SumSQ.u64 = 608; Count.u64 = 112; Min.u64 = 0; Max.u64 = 4; + dc_16:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink:data.packet_latency : Accumulator : Sum.u64 = 4503; SumSQ.u64 = 46433; Count.u64 = 773; Min.u64 = 0; Max.u64 = 60; + dc_16:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 877; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 112; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; + dc_16:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.get_request_latency : Accumulator : Sum.u64 = 188696; SumSQ.u64 = 394110764; Count.u64 = 877; Min.u64 = 16; Max.u64 = 12852; @@ -14157,8 +14713,10 @@ Model complete dc_16.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.AckInv_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + dc_16.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14177,6 +14735,7 @@ Model complete dc_16.eventSent_FetchInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; dc_16.eventSent_FetchInvX : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_16.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; dc_16.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -14187,6 +14746,8 @@ Model complete dc_16.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_16.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_16.MSHR_occupancy : Accumulator : Sum.u64 = 186942; SumSQ.u64 = 2505702; Count.u64 = 18481; Min.u64 = 0; Max.u64 = 25; @@ -14204,28 +14765,28 @@ Model complete ddr_3.cycles_with_issue : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; ddr_3.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 9148; SumSQ.u64 = 9148; Count.u64 = 9148; Min.u64 = 1; Max.u64 = 1; ddr_3.total_cycles : Accumulator : Sum.u64 = 13915; SumSQ.u64 = 193627225; Count.u64 = 1; Min.u64 = 13915; Max.u64 = 13915; - ddr_3:cpulink:req.packet_latency : Accumulator : Sum.u64 = 10673; SumSQ.u64 = 44787; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 10; - ddr_3:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_3:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_17:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_17:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_17:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 2360; SumSQ.u64 = 9186; Count.u64 = 719; Min.u64 = 0; Max.u64 = 8; - l2cache_17:memlink:data.packet_latency : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 19221; Count.u64 = 772; Min.u64 = 0; Max.u64 = 33; - l2cache_17:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_17:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_17:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 719; Min.u64 = 0; Max.u64 = 1; - l2cache_17:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - l2cache_17:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 1491; Min.u64 = 0; Max.u64 = 1; - l2cache_17:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1491; Min.u64 = 0; Max.u64 = 1; - l2cache_17:memlink.ordering_latency : Accumulator : Sum.u64 = 52; SumSQ.u64 = 2602; Count.u64 = 2; Min.u64 = 1; Max.u64 = 51; + ddr_3:highlink:req.packet_latency : Accumulator : Sum.u64 = 10673; SumSQ.u64 = 44787; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 10; + ddr_3:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_3:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 2360; SumSQ.u64 = 9186; Count.u64 = 719; Min.u64 = 0; Max.u64 = 8; + l2cache_17:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 19221; Count.u64 = 772; Min.u64 = 0; Max.u64 = 33; + l2cache_17:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 719; Min.u64 = 0; Max.u64 = 1; + l2cache_17:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + l2cache_17:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 1491; Min.u64 = 0; Max.u64 = 1; + l2cache_17:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1491; Min.u64 = 0; Max.u64 = 1; + l2cache_17:lowlink.ordering_latency : Accumulator : Sum.u64 = 52; SumSQ.u64 = 2602; Count.u64 = 2; Min.u64 = 1; Max.u64 = 51; l2cache_17.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_17.prefetches_issued : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; l2cache_17.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; @@ -14341,8 +14902,11 @@ Model complete l2cache_17.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_FetchResp : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_17.eventSent_FetchXResp : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; l2cache_17.eventSent_AckInv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; @@ -14351,6 +14915,9 @@ Model complete l2cache_17.eventSent_GetXResp : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l2cache_17.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.eventSent_FetchInv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_17.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14375,6 +14942,7 @@ Model complete l2cache_17.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.GetSHit_Arrival : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; l2cache_17.GetXHit_Arrival : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l2cache_17.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14450,10 +15018,12 @@ Model complete l2cache_17.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache_17.GetXResp_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_17.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14465,6 +15035,9 @@ Model complete l2cache_17.FetchInvX_recv : Accumulator : Sum.u64 = 468; SumSQ.u64 = 468; Count.u64 = 468; Min.u64 = 1; Max.u64 = 1; l2cache_17.FetchResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache_17.FetchXResp_recv : Accumulator : Sum.u64 = 465; SumSQ.u64 = 465; Count.u64 = 465; Min.u64 = 1; Max.u64 = 1; + l2cache_17.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_17.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_17.AckInv_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l2cache_17.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14537,13 +15110,16 @@ Model complete l1cache_34.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_34.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_FetchResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_34.eventSent_FetchXResp : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; l1cache_34.eventSent_AckInv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache_34.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_34.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_34.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_34.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14570,6 +15146,7 @@ Model complete l1cache_34.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_34.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.GetSHit_Arrival : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; l1cache_34.GetXHit_Arrival : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; l1cache_34.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14616,14 +15193,18 @@ Model complete l1cache_34.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_34.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_34.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.GetSResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_34.GetXResp_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l1cache_34.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_34.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.Inv_recv : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; l1cache_34.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_34.FetchInvX_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; + l1cache_34.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_34.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_34.MSHR_occupancy : Accumulator : Sum.u64 = 296075; SumSQ.u64 = 5250331; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -14712,13 +15293,16 @@ Model complete l1cache_35.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_35.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_FetchResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_35.eventSent_FetchXResp : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l1cache_35.eventSent_AckInv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache_35.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_35.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_35.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_35.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14745,6 +15329,7 @@ Model complete l1cache_35.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_35.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.GetSHit_Arrival : Accumulator : Sum.u64 = 598; SumSQ.u64 = 598; Count.u64 = 598; Min.u64 = 1; Max.u64 = 1; l1cache_35.GetXHit_Arrival : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l1cache_35.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14791,14 +15376,18 @@ Model complete l1cache_35.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_35.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_35.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_35.GetXResp_recv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; l1cache_35.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_35.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.Inv_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; l1cache_35.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l1cache_35.FetchInvX_recv : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; + l1cache_35.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_35.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_35.MSHR_occupancy : Accumulator : Sum.u64 = 294627; SumSQ.u64 = 5172431; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -14820,17 +15409,17 @@ Model complete core_35.cycles_max_issue : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; core_35.cycles_max_reorder : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; core_35.cycles : Accumulator : Sum.u64 = 17412; SumSQ.u64 = 17412; Count.u64 = 17412; Min.u64 = 1; Max.u64 = 1; - dc_17:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2691; SumSQ.u64 = 10113; Count.u64 = 877; Min.u64 = 0; Max.u64 = 10; - dc_17:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 278; SumSQ.u64 = 872; Count.u64 = 111; Min.u64 = 0; Max.u64 = 5; - dc_17:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_17:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3865; SumSQ.u64 = 23865; Count.u64 = 774; Min.u64 = 0; Max.u64 = 26; - dc_17:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 877; Min.u64 = 0; Max.u64 = 0; - dc_17:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 111; Min.u64 = 0; Max.u64 = 1; - dc_17:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_17:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; - dc_17:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 1; - dc_17:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 1; - dc_17:cpulink.ordering_latency : Accumulator : Sum.u64 = 5; SumSQ.u64 = 25; Count.u64 = 1; Min.u64 = 5; Max.u64 = 5; + dc_17:highlink:req.packet_latency : Accumulator : Sum.u64 = 2691; SumSQ.u64 = 10113; Count.u64 = 877; Min.u64 = 0; Max.u64 = 10; + dc_17:highlink:ack.packet_latency : Accumulator : Sum.u64 = 278; SumSQ.u64 = 872; Count.u64 = 111; Min.u64 = 0; Max.u64 = 5; + dc_17:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_17:highlink:data.packet_latency : Accumulator : Sum.u64 = 3865; SumSQ.u64 = 23865; Count.u64 = 774; Min.u64 = 0; Max.u64 = 26; + dc_17:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 877; Min.u64 = 0; Max.u64 = 0; + dc_17:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 111; Min.u64 = 0; Max.u64 = 1; + dc_17:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_17:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; + dc_17:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 1; + dc_17:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 1; + dc_17:highlink.ordering_latency : Accumulator : Sum.u64 = 5; SumSQ.u64 = 25; Count.u64 = 1; Min.u64 = 5; Max.u64 = 5; dc_17.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.get_request_latency : Accumulator : Sum.u64 = 193665; SumSQ.u64 = 400770727; Count.u64 = 877; Min.u64 = 16; Max.u64 = 13302; @@ -14853,8 +15442,10 @@ Model complete dc_17.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.AckInv_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + dc_17.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_17.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -14873,6 +15464,7 @@ Model complete dc_17.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; dc_17.eventSent_FetchInvX : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_17.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_17.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; dc_17.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -14883,6 +15475,8 @@ Model complete dc_17.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_17.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_17.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_17.MSHR_occupancy : Accumulator : Sum.u64 = 191911; SumSQ.u64 = 2646757; Count.u64 = 18505; Min.u64 = 0; Max.u64 = 25; @@ -14900,28 +15494,28 @@ Model complete ddr_4.cycles_with_issue : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; ddr_4.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 8867; SumSQ.u64 = 8867; Count.u64 = 8867; Min.u64 = 1; Max.u64 = 1; ddr_4.total_cycles : Accumulator : Sum.u64 = 13915; SumSQ.u64 = 193627225; Count.u64 = 1; Min.u64 = 13915; Max.u64 = 13915; - ddr_4:cpulink:req.packet_latency : Accumulator : Sum.u64 = 10734; SumSQ.u64 = 45460; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 11; - ddr_4:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_4:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_18:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_18:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_18:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 706; SumSQ.u64 = 2580; Count.u64 = 228; Min.u64 = 0; Max.u64 = 6; - l2cache_18:memlink:data.packet_latency : Accumulator : Sum.u64 = 3207; SumSQ.u64 = 19955; Count.u64 = 775; Min.u64 = 0; Max.u64 = 31; - l2cache_18:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_18:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_18:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 228; Min.u64 = 0; Max.u64 = 1; - l2cache_18:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; - l2cache_18:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 9; SumSQ.u64 = 13; Count.u64 = 1003; Min.u64 = 0; Max.u64 = 2; - l2cache_18:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1003; Min.u64 = 0; Max.u64 = 1; - l2cache_18:memlink.ordering_latency : Accumulator : Sum.u64 = 45; SumSQ.u64 = 1691; Count.u64 = 3; Min.u64 = 1; Max.u64 = 41; + ddr_4:highlink:req.packet_latency : Accumulator : Sum.u64 = 10734; SumSQ.u64 = 45460; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 11; + ddr_4:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_4:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 706; SumSQ.u64 = 2580; Count.u64 = 228; Min.u64 = 0; Max.u64 = 6; + l2cache_18:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3207; SumSQ.u64 = 19955; Count.u64 = 775; Min.u64 = 0; Max.u64 = 31; + l2cache_18:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 228; Min.u64 = 0; Max.u64 = 1; + l2cache_18:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; + l2cache_18:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 9; SumSQ.u64 = 13; Count.u64 = 1003; Min.u64 = 0; Max.u64 = 2; + l2cache_18:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1003; Min.u64 = 0; Max.u64 = 1; + l2cache_18:lowlink.ordering_latency : Accumulator : Sum.u64 = 45; SumSQ.u64 = 1691; Count.u64 = 3; Min.u64 = 1; Max.u64 = 41; l2cache_18.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_18.prefetches_issued : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; l2cache_18.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; @@ -15037,8 +15631,11 @@ Model complete l2cache_18.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_FetchXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache_18.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -15047,6 +15644,9 @@ Model complete l2cache_18.eventSent_GetXResp : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_18.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15071,6 +15671,7 @@ Model complete l2cache_18.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.GetSHit_Arrival : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; l2cache_18.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15146,10 +15747,12 @@ Model complete l2cache_18.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.GetSResp_recv : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; l2cache_18.GetXResp_recv : Accumulator : Sum.u64 = 505; SumSQ.u64 = 505; Count.u64 = 505; Min.u64 = 1; Max.u64 = 1; l2cache_18.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15161,6 +15764,9 @@ Model complete l2cache_18.FetchInvX_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache_18.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.FetchXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache_18.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_18.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_18.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15233,13 +15839,16 @@ Model complete l1cache_36.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache_36.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_36.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_36.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15266,6 +15875,7 @@ Model complete l1cache_36.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.GetSHit_Arrival : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; l1cache_36.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15312,14 +15922,18 @@ Model complete l1cache_36.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_36.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_36.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_36.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache_36.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_36.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_36.MSHR_occupancy : Accumulator : Sum.u64 = 294763; SumSQ.u64 = 5201855; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -15408,13 +16022,16 @@ Model complete l1cache_37.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_37.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_37.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_37.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15441,6 +16058,7 @@ Model complete l1cache_37.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.GetSHit_Arrival : Accumulator : Sum.u64 = 730; SumSQ.u64 = 730; Count.u64 = 730; Min.u64 = 1; Max.u64 = 1; l1cache_37.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_37.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15487,14 +16105,18 @@ Model complete l1cache_37.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_37.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; l1cache_37.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; l1cache_37.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_37.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_37.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_37.MSHR_occupancy : Accumulator : Sum.u64 = 298768; SumSQ.u64 = 5281370; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -15516,17 +16138,17 @@ Model complete core_37.cycles_max_issue : Accumulator : Sum.u64 = 987; SumSQ.u64 = 987; Count.u64 = 987; Min.u64 = 1; Max.u64 = 1; core_37.cycles_max_reorder : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; core_37.cycles : Accumulator : Sum.u64 = 17408; SumSQ.u64 = 17408; Count.u64 = 17408; Min.u64 = 1; Max.u64 = 1; - dc_18:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2657; SumSQ.u64 = 9975; Count.u64 = 876; Min.u64 = 0; Max.u64 = 8; - dc_18:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 355; SumSQ.u64 = 1333; Count.u64 = 111; Min.u64 = 0; Max.u64 = 6; - dc_18:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4255; SumSQ.u64 = 29557; Count.u64 = 773; Min.u64 = 0; Max.u64 = 45; - dc_18:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 876; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 111; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 0; - dc_18:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink:req.packet_latency : Accumulator : Sum.u64 = 2657; SumSQ.u64 = 9975; Count.u64 = 876; Min.u64 = 0; Max.u64 = 8; + dc_18:highlink:ack.packet_latency : Accumulator : Sum.u64 = 355; SumSQ.u64 = 1333; Count.u64 = 111; Min.u64 = 0; Max.u64 = 6; + dc_18:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink:data.packet_latency : Accumulator : Sum.u64 = 4255; SumSQ.u64 = 29557; Count.u64 = 773; Min.u64 = 0; Max.u64 = 45; + dc_18:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 876; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 111; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 0; + dc_18:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.get_request_latency : Accumulator : Sum.u64 = 192410; SumSQ.u64 = 417253334; Count.u64 = 876; Min.u64 = 19; Max.u64 = 13286; @@ -15549,8 +16171,10 @@ Model complete dc_18.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.AckInv_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + dc_18.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15569,6 +16193,7 @@ Model complete dc_18.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; dc_18.eventSent_FetchInvX : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; dc_18.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.eventSent_GetSResp : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; dc_18.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -15579,20 +16204,22 @@ Model complete dc_18.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_18.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_18.MSHR_occupancy : Accumulator : Sum.u64 = 190658; SumSQ.u64 = 2549470; Count.u64 = 18525; Min.u64 = 0; Max.u64 = 23; - l2cache_19:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_19:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_19:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 635; SumSQ.u64 = 2037; Count.u64 = 233; Min.u64 = 0; Max.u64 = 5; - l2cache_19:memlink:data.packet_latency : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 17013; Count.u64 = 776; Min.u64 = 0; Max.u64 = 32; - l2cache_19:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_19:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_19:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 233; Min.u64 = 0; Max.u64 = 1; - l2cache_19:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; - l2cache_19:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1009; Min.u64 = 0; Max.u64 = 1; - l2cache_19:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1009; Min.u64 = 0; Max.u64 = 1; - l2cache_19:memlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + l2cache_19:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 635; SumSQ.u64 = 2037; Count.u64 = 233; Min.u64 = 0; Max.u64 = 5; + l2cache_19:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 17013; Count.u64 = 776; Min.u64 = 0; Max.u64 = 32; + l2cache_19:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 233; Min.u64 = 0; Max.u64 = 1; + l2cache_19:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; + l2cache_19:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1009; Min.u64 = 0; Max.u64 = 1; + l2cache_19:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1009; Min.u64 = 0; Max.u64 = 1; + l2cache_19:lowlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; l2cache_19.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_19.prefetches_issued : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; l2cache_19.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; @@ -15708,8 +16335,11 @@ Model complete l2cache_19.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache_19.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -15718,6 +16348,9 @@ Model complete l2cache_19.eventSent_GetXResp : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; l2cache_19.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15742,6 +16375,7 @@ Model complete l2cache_19.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.GetSHit_Arrival : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; l2cache_19.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15817,10 +16451,12 @@ Model complete l2cache_19.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.GetSResp_recv : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; l2cache_19.GetXResp_recv : Accumulator : Sum.u64 = 506; SumSQ.u64 = 506; Count.u64 = 506; Min.u64 = 1; Max.u64 = 1; l2cache_19.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15832,6 +16468,9 @@ Model complete l2cache_19.FetchInvX_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache_19.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.FetchXResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache_19.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_19.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_19.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15904,13 +16543,16 @@ Model complete l1cache_38.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_38.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_38.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_38.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15937,6 +16579,7 @@ Model complete l1cache_38.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.GetSHit_Arrival : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; l1cache_38.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_38.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -15983,14 +16626,18 @@ Model complete l1cache_38.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_38.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_38.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_38.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache_38.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_38.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_38.MSHR_occupancy : Accumulator : Sum.u64 = 298394; SumSQ.u64 = 5250556; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -16079,13 +16726,16 @@ Model complete l1cache_39.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache_39.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_39.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_39.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16112,6 +16762,7 @@ Model complete l1cache_39.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.GetSHit_Arrival : Accumulator : Sum.u64 = 751; SumSQ.u64 = 751; Count.u64 = 751; Min.u64 = 1; Max.u64 = 1; l1cache_39.GetXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache_39.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16158,14 +16809,18 @@ Model complete l1cache_39.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_39.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; l1cache_39.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; l1cache_39.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache_39.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_39.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_39.MSHR_occupancy : Accumulator : Sum.u64 = 296736; SumSQ.u64 = 5221592; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -16187,17 +16842,17 @@ Model complete core_39.cycles_max_issue : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; core_39.cycles_max_reorder : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; core_39.cycles : Accumulator : Sum.u64 = 17368; SumSQ.u64 = 17368; Count.u64 = 17368; Min.u64 = 1; Max.u64 = 1; - dc_19:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 7621; Count.u64 = 875; Min.u64 = 0; Max.u64 = 13; - dc_19:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 298; SumSQ.u64 = 940; Count.u64 = 110; Min.u64 = 1; Max.u64 = 5; - dc_19:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_19:cpulink:data.packet_latency : Accumulator : Sum.u64 = 5129; SumSQ.u64 = 79883; Count.u64 = 772; Min.u64 = 0; Max.u64 = 105; - dc_19:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 875; Min.u64 = 0; Max.u64 = 1; - dc_19:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; - dc_19:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_19:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_19:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1757; Min.u64 = 0; Max.u64 = 1; - dc_19:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1757; Min.u64 = 0; Max.u64 = 1; - dc_19:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + dc_19:highlink:req.packet_latency : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 7621; Count.u64 = 875; Min.u64 = 0; Max.u64 = 13; + dc_19:highlink:ack.packet_latency : Accumulator : Sum.u64 = 298; SumSQ.u64 = 940; Count.u64 = 110; Min.u64 = 1; Max.u64 = 5; + dc_19:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_19:highlink:data.packet_latency : Accumulator : Sum.u64 = 5129; SumSQ.u64 = 79883; Count.u64 = 772; Min.u64 = 0; Max.u64 = 105; + dc_19:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 875; Min.u64 = 0; Max.u64 = 1; + dc_19:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; + dc_19:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_19:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_19:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1757; Min.u64 = 0; Max.u64 = 1; + dc_19:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1757; Min.u64 = 0; Max.u64 = 1; + dc_19:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; dc_19.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.get_request_latency : Accumulator : Sum.u64 = 214709; SumSQ.u64 = 629801095; Count.u64 = 874; Min.u64 = 17; Max.u64 = 13813; @@ -16220,8 +16875,10 @@ Model complete dc_19.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.AckInv_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + dc_19.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_19.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16240,6 +16897,7 @@ Model complete dc_19.eventSent_FetchInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; dc_19.eventSent_FetchInvX : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; dc_19.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_19.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.eventSent_GetSResp : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; dc_19.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -16250,20 +16908,22 @@ Model complete dc_19.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_19.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_19.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_19.MSHR_occupancy : Accumulator : Sum.u64 = 213003; SumSQ.u64 = 3140991; Count.u64 = 18545; Min.u64 = 0; Max.u64 = 24; - l2cache_20:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 632; SumSQ.u64 = 1846; Count.u64 = 246; Min.u64 = 0; Max.u64 = 5; - l2cache_20:memlink:data.packet_latency : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 15179; Count.u64 = 769; Min.u64 = 0; Max.u64 = 24; - l2cache_20:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 246; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1015; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1015; Min.u64 = 0; Max.u64 = 0; - l2cache_20:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 632; SumSQ.u64 = 1846; Count.u64 = 246; Min.u64 = 0; Max.u64 = 5; + l2cache_20:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 15179; Count.u64 = 769; Min.u64 = 0; Max.u64 = 24; + l2cache_20:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 246; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1015; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1015; Min.u64 = 0; Max.u64 = 0; + l2cache_20:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_20.prefetches_issued : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l2cache_20.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; @@ -16379,8 +17039,11 @@ Model complete l2cache_20.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_FetchXResp : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; l2cache_20.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16389,6 +17052,9 @@ Model complete l2cache_20.eventSent_GetXResp : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; l2cache_20.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16413,6 +17079,7 @@ Model complete l2cache_20.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.GetSHit_Arrival : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; l2cache_20.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16488,10 +17155,12 @@ Model complete l2cache_20.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.GetSResp_recv : Accumulator : Sum.u64 = 460; SumSQ.u64 = 460; Count.u64 = 460; Min.u64 = 1; Max.u64 = 1; l2cache_20.GetXResp_recv : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; l2cache_20.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16503,6 +17172,9 @@ Model complete l2cache_20.FetchInvX_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; l2cache_20.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.FetchXResp_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache_20.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_20.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_20.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16575,13 +17247,16 @@ Model complete l1cache_40.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache_40.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_40.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_40.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16608,6 +17283,7 @@ Model complete l1cache_40.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.GetSHit_Arrival : Accumulator : Sum.u64 = 707; SumSQ.u64 = 707; Count.u64 = 707; Min.u64 = 1; Max.u64 = 1; l1cache_40.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_40.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16654,14 +17330,18 @@ Model complete l1cache_40.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_40.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.GetSResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l1cache_40.GetXResp_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; l1cache_40.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.FetchInvX_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache_40.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_40.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_40.MSHR_occupancy : Accumulator : Sum.u64 = 296875; SumSQ.u64 = 5200917; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -16750,13 +17430,16 @@ Model complete l1cache_41.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_41.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_41.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_41.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16783,6 +17466,7 @@ Model complete l1cache_41.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.GetSHit_Arrival : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; l1cache_41.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_41.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16829,14 +17513,18 @@ Model complete l1cache_41.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_41.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.GetSResp_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l1cache_41.GetXResp_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; l1cache_41.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_41.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_41.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_41.MSHR_occupancy : Accumulator : Sum.u64 = 295295; SumSQ.u64 = 5155289; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -16858,17 +17546,17 @@ Model complete core_41.cycles_max_issue : Accumulator : Sum.u64 = 999; SumSQ.u64 = 999; Count.u64 = 999; Min.u64 = 1; Max.u64 = 1; core_41.cycles_max_reorder : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; core_41.cycles : Accumulator : Sum.u64 = 17407; SumSQ.u64 = 17407; Count.u64 = 17407; Min.u64 = 1; Max.u64 = 1; - dc_20:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2108; SumSQ.u64 = 6242; Count.u64 = 875; Min.u64 = 0; Max.u64 = 10; - dc_20:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 269; SumSQ.u64 = 755; Count.u64 = 107; Min.u64 = 0; Max.u64 = 5; - dc_20:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_20:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3952; SumSQ.u64 = 34340; Count.u64 = 774; Min.u64 = 0; Max.u64 = 40; - dc_20:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 875; Min.u64 = 0; Max.u64 = 0; - dc_20:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 107; Min.u64 = 0; Max.u64 = 0; - dc_20:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_20:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 774; Min.u64 = 0; Max.u64 = 1; - dc_20:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; - dc_20:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; - dc_20:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1; Min.u64 = 0; Max.u64 = 0; + dc_20:highlink:req.packet_latency : Accumulator : Sum.u64 = 2108; SumSQ.u64 = 6242; Count.u64 = 875; Min.u64 = 0; Max.u64 = 10; + dc_20:highlink:ack.packet_latency : Accumulator : Sum.u64 = 269; SumSQ.u64 = 755; Count.u64 = 107; Min.u64 = 0; Max.u64 = 5; + dc_20:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_20:highlink:data.packet_latency : Accumulator : Sum.u64 = 3952; SumSQ.u64 = 34340; Count.u64 = 774; Min.u64 = 0; Max.u64 = 40; + dc_20:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 875; Min.u64 = 0; Max.u64 = 0; + dc_20:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 107; Min.u64 = 0; Max.u64 = 0; + dc_20:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_20:highlink.outoforder_data_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 774; Min.u64 = 0; Max.u64 = 1; + dc_20:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; + dc_20:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; + dc_20:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1; Min.u64 = 0; Max.u64 = 0; dc_20.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.get_request_latency : Accumulator : Sum.u64 = 187211; SumSQ.u64 = 411126757; Count.u64 = 875; Min.u64 = 18; Max.u64 = 13372; @@ -16891,8 +17579,10 @@ Model complete dc_20.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.AckInv_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + dc_20.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_20.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -16911,6 +17601,7 @@ Model complete dc_20.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_20.eventSent_FetchInvX : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; dc_20.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_20.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.eventSent_GetSResp : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; dc_20.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -16921,20 +17612,22 @@ Model complete dc_20.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_20.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_20.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_20.MSHR_occupancy : Accumulator : Sum.u64 = 185461; SumSQ.u64 = 2479383; Count.u64 = 18167; Min.u64 = 0; Max.u64 = 24; - l2cache_21:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_21:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_21:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 599; SumSQ.u64 = 1767; Count.u64 = 234; Min.u64 = 0; Max.u64 = 5; - l2cache_21:memlink:data.packet_latency : Accumulator : Sum.u64 = 2633; SumSQ.u64 = 13385; Count.u64 = 771; Min.u64 = 0; Max.u64 = 28; - l2cache_21:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_21:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_21:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 234; Min.u64 = 0; Max.u64 = 1; - l2cache_21:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; - l2cache_21:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 1; - l2cache_21:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 1; - l2cache_21:memlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache_21:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 599; SumSQ.u64 = 1767; Count.u64 = 234; Min.u64 = 0; Max.u64 = 5; + l2cache_21:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2633; SumSQ.u64 = 13385; Count.u64 = 771; Min.u64 = 0; Max.u64 = 28; + l2cache_21:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 234; Min.u64 = 0; Max.u64 = 1; + l2cache_21:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; + l2cache_21:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 1; + l2cache_21:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 1; + l2cache_21:lowlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache_21.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_21.prefetches_issued : Accumulator : Sum.u64 = 746; SumSQ.u64 = 746; Count.u64 = 746; Min.u64 = 1; Max.u64 = 1; l2cache_21.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; @@ -17050,8 +17743,11 @@ Model complete l2cache_21.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_21.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -17060,6 +17756,9 @@ Model complete l2cache_21.eventSent_GetXResp : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; l2cache_21.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17084,6 +17783,7 @@ Model complete l2cache_21.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.GetSHit_Arrival : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; l2cache_21.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17159,10 +17859,12 @@ Model complete l2cache_21.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.GetSResp_recv : Accumulator : Sum.u64 = 479; SumSQ.u64 = 479; Count.u64 = 479; Min.u64 = 1; Max.u64 = 1; l2cache_21.GetXResp_recv : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; l2cache_21.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17174,6 +17876,9 @@ Model complete l2cache_21.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_21.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.FetchXResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache_21.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_21.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_21.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17246,13 +17951,16 @@ Model complete l1cache_42.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache_42.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_42.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_42.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17279,6 +17987,7 @@ Model complete l1cache_42.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.GetSHit_Arrival : Accumulator : Sum.u64 = 799; SumSQ.u64 = 799; Count.u64 = 799; Min.u64 = 1; Max.u64 = 1; l1cache_42.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_42.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17325,14 +18034,18 @@ Model complete l1cache_42.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_42.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_42.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_42.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache_42.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_42.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_42.MSHR_occupancy : Accumulator : Sum.u64 = 296471; SumSQ.u64 = 5223959; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -17421,13 +18134,16 @@ Model complete l1cache_43.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_FetchXResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_43.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_43.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_43.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17454,6 +18170,7 @@ Model complete l1cache_43.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.GetSHit_Arrival : Accumulator : Sum.u64 = 780; SumSQ.u64 = 780; Count.u64 = 780; Min.u64 = 1; Max.u64 = 1; l1cache_43.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17500,14 +18217,18 @@ Model complete l1cache_43.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_43.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.GetSResp_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l1cache_43.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; l1cache_43.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache_43.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_43.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_43.MSHR_occupancy : Accumulator : Sum.u64 = 297540; SumSQ.u64 = 5249310; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -17529,17 +18250,17 @@ Model complete core_43.cycles_max_issue : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; core_43.cycles_max_reorder : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; core_43.cycles : Accumulator : Sum.u64 = 17342; SumSQ.u64 = 17342; Count.u64 = 17342; Min.u64 = 1; Max.u64 = 1; - dc_21:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 6225; Count.u64 = 876; Min.u64 = 0; Max.u64 = 11; - dc_21:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 269; SumSQ.u64 = 749; Count.u64 = 110; Min.u64 = 1; Max.u64 = 4; - dc_21:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_21:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3305; SumSQ.u64 = 19479; Count.u64 = 774; Min.u64 = 0; Max.u64 = 28; - dc_21:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 876; Min.u64 = 0; Max.u64 = 1; - dc_21:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; - dc_21:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_21:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; - dc_21:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 2; - dc_21:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 2; - dc_21:cpulink.ordering_latency : Accumulator : Sum.u64 = 7; SumSQ.u64 = 25; Count.u64 = 2; Min.u64 = 3; Max.u64 = 4; + dc_21:highlink:req.packet_latency : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 6225; Count.u64 = 876; Min.u64 = 0; Max.u64 = 11; + dc_21:highlink:ack.packet_latency : Accumulator : Sum.u64 = 269; SumSQ.u64 = 749; Count.u64 = 110; Min.u64 = 1; Max.u64 = 4; + dc_21:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_21:highlink:data.packet_latency : Accumulator : Sum.u64 = 3305; SumSQ.u64 = 19479; Count.u64 = 774; Min.u64 = 0; Max.u64 = 28; + dc_21:highlink.outoforder_req_events : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 876; Min.u64 = 0; Max.u64 = 1; + dc_21:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 110; Min.u64 = 0; Max.u64 = 0; + dc_21:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_21:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; + dc_21:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 2; + dc_21:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 2; + dc_21:highlink.ordering_latency : Accumulator : Sum.u64 = 7; SumSQ.u64 = 25; Count.u64 = 2; Min.u64 = 3; Max.u64 = 4; dc_21.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.get_request_latency : Accumulator : Sum.u64 = 199317; SumSQ.u64 = 470857811; Count.u64 = 876; Min.u64 = 18; Max.u64 = 13394; @@ -17562,8 +18283,10 @@ Model complete dc_21.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.AckInv_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + dc_21.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_21.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17582,6 +18305,7 @@ Model complete dc_21.eventSent_FetchInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; dc_21.eventSent_FetchInvX : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; dc_21.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_21.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.eventSent_GetSResp : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; dc_21.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -17592,20 +18316,22 @@ Model complete dc_21.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_21.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_21.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_21.MSHR_occupancy : Accumulator : Sum.u64 = 197565; SumSQ.u64 = 2829463; Count.u64 = 18192; Min.u64 = 0; Max.u64 = 27; - l2cache_22:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 626; SumSQ.u64 = 1992; Count.u64 = 229; Min.u64 = 0; Max.u64 = 5; - l2cache_22:memlink:data.packet_latency : Accumulator : Sum.u64 = 2689; SumSQ.u64 = 13637; Count.u64 = 776; Min.u64 = 0; Max.u64 = 22; - l2cache_22:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 229; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 0; - l2cache_22:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 626; SumSQ.u64 = 1992; Count.u64 = 229; Min.u64 = 0; Max.u64 = 5; + l2cache_22:lowlink:data.packet_latency : Accumulator : Sum.u64 = 2689; SumSQ.u64 = 13637; Count.u64 = 776; Min.u64 = 0; Max.u64 = 22; + l2cache_22:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 229; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1005; Min.u64 = 0; Max.u64 = 0; + l2cache_22:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_22.prefetches_issued : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; l2cache_22.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; @@ -17721,8 +18447,11 @@ Model complete l2cache_22.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_FetchXResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache_22.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -17731,6 +18460,9 @@ Model complete l2cache_22.eventSent_GetXResp : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_22.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17755,6 +18487,7 @@ Model complete l2cache_22.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.GetSHit_Arrival : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l2cache_22.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17830,10 +18563,12 @@ Model complete l2cache_22.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.GetSResp_recv : Accumulator : Sum.u64 = 479; SumSQ.u64 = 479; Count.u64 = 479; Min.u64 = 1; Max.u64 = 1; l2cache_22.GetXResp_recv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; l2cache_22.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17845,6 +18580,9 @@ Model complete l2cache_22.FetchInvX_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache_22.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache_22.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_22.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_22.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17917,13 +18655,16 @@ Model complete l1cache_44.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_FetchXResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache_44.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_44.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_44.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17950,6 +18691,7 @@ Model complete l1cache_44.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.GetSHit_Arrival : Accumulator : Sum.u64 = 685; SumSQ.u64 = 685; Count.u64 = 685; Min.u64 = 1; Max.u64 = 1; l1cache_44.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_44.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -17996,14 +18738,18 @@ Model complete l1cache_44.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_44.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_44.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_44.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.FetchInvX_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache_44.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_44.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_44.MSHR_occupancy : Accumulator : Sum.u64 = 298132; SumSQ.u64 = 5256682; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -18092,13 +18838,16 @@ Model complete l1cache_45.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_45.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_45.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_45.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18125,6 +18874,7 @@ Model complete l1cache_45.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.GetSHit_Arrival : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; l1cache_45.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_45.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18171,14 +18921,18 @@ Model complete l1cache_45.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_45.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_45.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_45.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_45.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_45.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_45.MSHR_occupancy : Accumulator : Sum.u64 = 299370; SumSQ.u64 = 5257526; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -18200,17 +18954,17 @@ Model complete core_45.cycles_max_issue : Accumulator : Sum.u64 = 979; SumSQ.u64 = 979; Count.u64 = 979; Min.u64 = 1; Max.u64 = 1; core_45.cycles_max_reorder : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; core_45.cycles : Accumulator : Sum.u64 = 17538; SumSQ.u64 = 17538; Count.u64 = 17538; Min.u64 = 1; Max.u64 = 1; - dc_22:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2292; SumSQ.u64 = 7526; Count.u64 = 877; Min.u64 = 0; Max.u64 = 9; - dc_22:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 298; SumSQ.u64 = 920; Count.u64 = 108; Min.u64 = 1; Max.u64 = 5; - dc_22:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_22:cpulink:data.packet_latency : Accumulator : Sum.u64 = 2624; SumSQ.u64 = 14906; Count.u64 = 775; Min.u64 = 1; Max.u64 = 36; - dc_22:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 877; Min.u64 = 0; Max.u64 = 1; - dc_22:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 108; Min.u64 = 0; Max.u64 = 0; - dc_22:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_22:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; - dc_22:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 1; - dc_22:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 1; - dc_22:cpulink.ordering_latency : Accumulator : Sum.u64 = 2; SumSQ.u64 = 4; Count.u64 = 1; Min.u64 = 2; Max.u64 = 2; + dc_22:highlink:req.packet_latency : Accumulator : Sum.u64 = 2292; SumSQ.u64 = 7526; Count.u64 = 877; Min.u64 = 0; Max.u64 = 9; + dc_22:highlink:ack.packet_latency : Accumulator : Sum.u64 = 298; SumSQ.u64 = 920; Count.u64 = 108; Min.u64 = 1; Max.u64 = 5; + dc_22:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_22:highlink:data.packet_latency : Accumulator : Sum.u64 = 2624; SumSQ.u64 = 14906; Count.u64 = 775; Min.u64 = 1; Max.u64 = 36; + dc_22:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 877; Min.u64 = 0; Max.u64 = 1; + dc_22:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 108; Min.u64 = 0; Max.u64 = 0; + dc_22:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_22:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; + dc_22:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 1; + dc_22:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1760; Min.u64 = 0; Max.u64 = 1; + dc_22:highlink.ordering_latency : Accumulator : Sum.u64 = 2; SumSQ.u64 = 4; Count.u64 = 1; Min.u64 = 2; Max.u64 = 2; dc_22.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.get_request_latency : Accumulator : Sum.u64 = 189405; SumSQ.u64 = 423379495; Count.u64 = 877; Min.u64 = 19; Max.u64 = 13513; @@ -18233,8 +18987,10 @@ Model complete dc_22.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.AckInv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + dc_22.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_22.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18253,6 +19009,7 @@ Model complete dc_22.eventSent_FetchInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; dc_22.eventSent_FetchInvX : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; dc_22.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_22.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; dc_22.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -18263,6 +19020,8 @@ Model complete dc_22.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_22.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_22.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_22.MSHR_occupancy : Accumulator : Sum.u64 = 187651; SumSQ.u64 = 2507599; Count.u64 = 18226; Min.u64 = 0; Max.u64 = 25; @@ -18280,28 +19039,28 @@ Model complete ddr_5.cycles_with_issue : Accumulator : Sum.u64 = 763; SumSQ.u64 = 763; Count.u64 = 763; Min.u64 = 1; Max.u64 = 1; ddr_5.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 8833; SumSQ.u64 = 8833; Count.u64 = 8833; Min.u64 = 1; Max.u64 = 1; ddr_5.total_cycles : Accumulator : Sum.u64 = 13915; SumSQ.u64 = 193627225; Count.u64 = 1; Min.u64 = 13915; Max.u64 = 13915; - ddr_5:cpulink:req.packet_latency : Accumulator : Sum.u64 = 10670; SumSQ.u64 = 44806; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 12; - ddr_5:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; - ddr_5:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_23:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_23:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_23:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 731; SumSQ.u64 = 2701; Count.u64 = 230; Min.u64 = 0; Max.u64 = 6; - l2cache_23:memlink:data.packet_latency : Accumulator : Sum.u64 = 3050; SumSQ.u64 = 18264; Count.u64 = 771; Min.u64 = 0; Max.u64 = 34; - l2cache_23:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_23:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_23:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 230; Min.u64 = 0; Max.u64 = 1; - l2cache_23:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; - l2cache_23:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1001; Min.u64 = 0; Max.u64 = 1; - l2cache_23:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1001; Min.u64 = 0; Max.u64 = 1; - l2cache_23:memlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + ddr_5:highlink:req.packet_latency : Accumulator : Sum.u64 = 10670; SumSQ.u64 = 44806; Count.u64 = 3001; Min.u64 = 1; Max.u64 = 12; + ddr_5:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink:data.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 3001; Min.u64 = 0; Max.u64 = 0; + ddr_5:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 731; SumSQ.u64 = 2701; Count.u64 = 230; Min.u64 = 0; Max.u64 = 6; + l2cache_23:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3050; SumSQ.u64 = 18264; Count.u64 = 771; Min.u64 = 0; Max.u64 = 34; + l2cache_23:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 230; Min.u64 = 0; Max.u64 = 1; + l2cache_23:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; + l2cache_23:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1001; Min.u64 = 0; Max.u64 = 1; + l2cache_23:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1001; Min.u64 = 0; Max.u64 = 1; + l2cache_23:lowlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; l2cache_23.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_23.prefetches_issued : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; l2cache_23.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; @@ -18417,8 +19176,11 @@ Model complete l2cache_23.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache_23.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18427,6 +19189,9 @@ Model complete l2cache_23.eventSent_GetXResp : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_23.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18451,6 +19216,7 @@ Model complete l2cache_23.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.GetSHit_Arrival : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; l2cache_23.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18526,10 +19292,12 @@ Model complete l2cache_23.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.GetSResp_recv : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; l2cache_23.GetXResp_recv : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; l2cache_23.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18541,6 +19309,9 @@ Model complete l2cache_23.FetchInvX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache_23.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache_23.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_23.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_23.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18613,13 +19384,16 @@ Model complete l1cache_46.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_46.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_46.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_46.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18646,6 +19420,7 @@ Model complete l1cache_46.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.GetSHit_Arrival : Accumulator : Sum.u64 = 713; SumSQ.u64 = 713; Count.u64 = 713; Min.u64 = 1; Max.u64 = 1; l1cache_46.GetXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1cache_46.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18692,14 +19467,18 @@ Model complete l1cache_46.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_46.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_46.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_46.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache_46.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_46.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_46.MSHR_occupancy : Accumulator : Sum.u64 = 302287; SumSQ.u64 = 5398269; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -18788,13 +19567,16 @@ Model complete l1cache_47.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_47.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_47.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_47.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18821,6 +19603,7 @@ Model complete l1cache_47.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.GetSHit_Arrival : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; l1cache_47.GetXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache_47.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18867,14 +19650,18 @@ Model complete l1cache_47.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_47.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_47.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_47.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_47.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_47.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_47.MSHR_occupancy : Accumulator : Sum.u64 = 300022; SumSQ.u64 = 5281534; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -18896,17 +19683,17 @@ Model complete core_47.cycles_max_issue : Accumulator : Sum.u64 = 973; SumSQ.u64 = 973; Count.u64 = 973; Min.u64 = 1; Max.u64 = 1; core_47.cycles_max_reorder : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; core_47.cycles : Accumulator : Sum.u64 = 17557; SumSQ.u64 = 17557; Count.u64 = 17557; Min.u64 = 1; Max.u64 = 1; - dc_23:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2661; SumSQ.u64 = 10281; Count.u64 = 878; Min.u64 = 0; Max.u64 = 20; - dc_23:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 334; SumSQ.u64 = 1196; Count.u64 = 108; Min.u64 = 0; Max.u64 = 6; - dc_23:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3542; SumSQ.u64 = 50338; Count.u64 = 776; Min.u64 = 1; Max.u64 = 106; - dc_23:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 878; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 108; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; - dc_23:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink:req.packet_latency : Accumulator : Sum.u64 = 2661; SumSQ.u64 = 10281; Count.u64 = 878; Min.u64 = 0; Max.u64 = 20; + dc_23:highlink:ack.packet_latency : Accumulator : Sum.u64 = 334; SumSQ.u64 = 1196; Count.u64 = 108; Min.u64 = 0; Max.u64 = 6; + dc_23:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink:data.packet_latency : Accumulator : Sum.u64 = 3542; SumSQ.u64 = 50338; Count.u64 = 776; Min.u64 = 1; Max.u64 = 106; + dc_23:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 878; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 108; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1762; Min.u64 = 0; Max.u64 = 0; + dc_23:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.get_request_latency : Accumulator : Sum.u64 = 166702; SumSQ.u64 = 98681622; Count.u64 = 878; Min.u64 = 18; Max.u64 = 5934; @@ -18929,8 +19716,10 @@ Model complete dc_23.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.AckInv_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + dc_23.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -18949,6 +19738,7 @@ Model complete dc_23.eventSent_FetchInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; dc_23.eventSent_FetchInvX : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; dc_23.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.eventSent_GetSResp : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; dc_23.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -18959,20 +19749,22 @@ Model complete dc_23.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_23.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_23.MSHR_occupancy : Accumulator : Sum.u64 = 164946; SumSQ.u64 = 1973134; Count.u64 = 18254; Min.u64 = 0; Max.u64 = 22; - l2cache_24:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 731; SumSQ.u64 = 2825; Count.u64 = 225; Min.u64 = 0; Max.u64 = 6; - l2cache_24:memlink:data.packet_latency : Accumulator : Sum.u64 = 3160; SumSQ.u64 = 18968; Count.u64 = 769; Min.u64 = 0; Max.u64 = 30; - l2cache_24:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 225; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 994; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 994; Min.u64 = 0; Max.u64 = 0; - l2cache_24:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 731; SumSQ.u64 = 2825; Count.u64 = 225; Min.u64 = 0; Max.u64 = 6; + l2cache_24:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3160; SumSQ.u64 = 18968; Count.u64 = 769; Min.u64 = 0; Max.u64 = 30; + l2cache_24:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 225; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 994; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 994; Min.u64 = 0; Max.u64 = 0; + l2cache_24:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_24.prefetches_issued : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; l2cache_24.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; @@ -19088,8 +19880,11 @@ Model complete l2cache_24.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache_24.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19098,6 +19893,9 @@ Model complete l2cache_24.eventSent_GetXResp : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache_24.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19122,6 +19920,7 @@ Model complete l2cache_24.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.GetSHit_Arrival : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; l2cache_24.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19197,10 +19996,12 @@ Model complete l2cache_24.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.GetSResp_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l2cache_24.GetXResp_recv : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_24.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19212,6 +20013,9 @@ Model complete l2cache_24.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache_24.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.FetchXResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache_24.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_24.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_24.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19284,13 +20088,16 @@ Model complete l1cache_48.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_48.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_48.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_48.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19317,6 +20124,7 @@ Model complete l1cache_48.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.GetSHit_Arrival : Accumulator : Sum.u64 = 763; SumSQ.u64 = 763; Count.u64 = 763; Min.u64 = 1; Max.u64 = 1; l1cache_48.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1cache_48.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19363,14 +20171,18 @@ Model complete l1cache_48.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_48.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_48.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_48.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache_48.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_48.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_48.MSHR_occupancy : Accumulator : Sum.u64 = 298534; SumSQ.u64 = 5289332; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -19459,13 +20271,16 @@ Model complete l1cache_49.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_49.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_49.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_49.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19492,6 +20307,7 @@ Model complete l1cache_49.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.GetSHit_Arrival : Accumulator : Sum.u64 = 770; SumSQ.u64 = 770; Count.u64 = 770; Min.u64 = 1; Max.u64 = 1; l1cache_49.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache_49.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19538,14 +20354,18 @@ Model complete l1cache_49.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_49.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_49.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_49.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_49.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_49.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_49.MSHR_occupancy : Accumulator : Sum.u64 = 301947; SumSQ.u64 = 5387133; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -19567,17 +20387,17 @@ Model complete core_49.cycles_max_issue : Accumulator : Sum.u64 = 981; SumSQ.u64 = 981; Count.u64 = 981; Min.u64 = 1; Max.u64 = 1; core_49.cycles_max_reorder : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; core_49.cycles : Accumulator : Sum.u64 = 17446; SumSQ.u64 = 17446; Count.u64 = 17446; Min.u64 = 1; Max.u64 = 1; - dc_24:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2715; SumSQ.u64 = 10527; Count.u64 = 873; Min.u64 = 0; Max.u64 = 10; - dc_24:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 398; SumSQ.u64 = 1666; Count.u64 = 105; Min.u64 = 1; Max.u64 = 6; - dc_24:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_24:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3688; SumSQ.u64 = 38678; Count.u64 = 772; Min.u64 = 0; Max.u64 = 55; - dc_24:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; - dc_24:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 105; Min.u64 = 0; Max.u64 = 1; - dc_24:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_24:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_24:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_24:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_24:cpulink.ordering_latency : Accumulator : Sum.u64 = 45; SumSQ.u64 = 761; Count.u64 = 3; Min.u64 = 8; Max.u64 = 21; + dc_24:highlink:req.packet_latency : Accumulator : Sum.u64 = 2715; SumSQ.u64 = 10527; Count.u64 = 873; Min.u64 = 0; Max.u64 = 10; + dc_24:highlink:ack.packet_latency : Accumulator : Sum.u64 = 398; SumSQ.u64 = 1666; Count.u64 = 105; Min.u64 = 1; Max.u64 = 6; + dc_24:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_24:highlink:data.packet_latency : Accumulator : Sum.u64 = 3688; SumSQ.u64 = 38678; Count.u64 = 772; Min.u64 = 0; Max.u64 = 55; + dc_24:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; + dc_24:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 105; Min.u64 = 0; Max.u64 = 1; + dc_24:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_24:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_24:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_24:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_24:highlink.ordering_latency : Accumulator : Sum.u64 = 45; SumSQ.u64 = 761; Count.u64 = 3; Min.u64 = 8; Max.u64 = 21; dc_24.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.get_request_latency : Accumulator : Sum.u64 = 172254; SumSQ.u64 = 223929558; Count.u64 = 873; Min.u64 = 20; Max.u64 = 12612; @@ -19600,8 +20420,10 @@ Model complete dc_24.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.AckInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + dc_24.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_24.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19620,6 +20442,7 @@ Model complete dc_24.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_24.eventSent_FetchInvX : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; dc_24.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_24.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.eventSent_GetSResp : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; dc_24.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -19630,20 +20453,22 @@ Model complete dc_24.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_24.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_24.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_24.MSHR_occupancy : Accumulator : Sum.u64 = 170508; SumSQ.u64 = 2102216; Count.u64 = 18276; Min.u64 = 0; Max.u64 = 23; - l2cache_25:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 637; SumSQ.u64 = 2203; Count.u64 = 221; Min.u64 = 0; Max.u64 = 6; - l2cache_25:memlink:data.packet_latency : Accumulator : Sum.u64 = 3348; SumSQ.u64 = 27018; Count.u64 = 776; Min.u64 = 0; Max.u64 = 67; - l2cache_25:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 221; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 997; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 997; Min.u64 = 0; Max.u64 = 0; - l2cache_25:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 637; SumSQ.u64 = 2203; Count.u64 = 221; Min.u64 = 0; Max.u64 = 6; + l2cache_25:lowlink:data.packet_latency : Accumulator : Sum.u64 = 3348; SumSQ.u64 = 27018; Count.u64 = 776; Min.u64 = 0; Max.u64 = 67; + l2cache_25:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 221; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 776; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 997; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 997; Min.u64 = 0; Max.u64 = 0; + l2cache_25:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_25.prefetches_issued : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; l2cache_25.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; @@ -19759,8 +20584,11 @@ Model complete l2cache_25.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_25.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -19769,6 +20597,9 @@ Model complete l2cache_25.eventSent_GetXResp : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_25.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19793,6 +20624,7 @@ Model complete l2cache_25.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.GetSHit_Arrival : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; l2cache_25.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19868,10 +20700,12 @@ Model complete l2cache_25.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.GetSResp_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l2cache_25.GetXResp_recv : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache_25.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19883,6 +20717,9 @@ Model complete l2cache_25.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_25.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_25.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_25.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_25.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19955,13 +20792,16 @@ Model complete l1cache_50.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_50.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_50.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_50.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -19988,6 +20828,7 @@ Model complete l1cache_50.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.GetSHit_Arrival : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; l1cache_50.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_50.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20034,14 +20875,18 @@ Model complete l1cache_50.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_50.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_50.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_50.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache_50.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_50.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_50.MSHR_occupancy : Accumulator : Sum.u64 = 308502; SumSQ.u64 = 5427782; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -20130,13 +20975,16 @@ Model complete l1cache_51.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_51.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_51.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_51.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20163,6 +21011,7 @@ Model complete l1cache_51.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.GetSHit_Arrival : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; l1cache_51.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20209,14 +21058,18 @@ Model complete l1cache_51.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_51.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l1cache_51.GetXResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; l1cache_51.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_51.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_51.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_51.MSHR_occupancy : Accumulator : Sum.u64 = 371364; SumSQ.u64 = 6248292; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -20238,17 +21091,17 @@ Model complete core_51.cycles_max_issue : Accumulator : Sum.u64 = 1052; SumSQ.u64 = 1052; Count.u64 = 1052; Min.u64 = 1; Max.u64 = 1; core_51.cycles_max_reorder : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; core_51.cycles : Accumulator : Sum.u64 = 22493; SumSQ.u64 = 22493; Count.u64 = 22493; Min.u64 = 1; Max.u64 = 1; - dc_25:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2347; SumSQ.u64 = 8245; Count.u64 = 873; Min.u64 = 0; Max.u64 = 15; - dc_25:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 351; SumSQ.u64 = 1283; Count.u64 = 106; Min.u64 = 1; Max.u64 = 6; - dc_25:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_25:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3037; SumSQ.u64 = 23949; Count.u64 = 771; Min.u64 = 0; Max.u64 = 41; - dc_25:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; - dc_25:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 106; Min.u64 = 0; Max.u64 = 1; - dc_25:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_25:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; - dc_25:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_25:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_25:cpulink.ordering_latency : Accumulator : Sum.u64 = 66; SumSQ.u64 = 1802; Count.u64 = 3; Min.u64 = 7; Max.u64 = 32; + dc_25:highlink:req.packet_latency : Accumulator : Sum.u64 = 2347; SumSQ.u64 = 8245; Count.u64 = 873; Min.u64 = 0; Max.u64 = 15; + dc_25:highlink:ack.packet_latency : Accumulator : Sum.u64 = 351; SumSQ.u64 = 1283; Count.u64 = 106; Min.u64 = 1; Max.u64 = 6; + dc_25:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_25:highlink:data.packet_latency : Accumulator : Sum.u64 = 3037; SumSQ.u64 = 23949; Count.u64 = 771; Min.u64 = 0; Max.u64 = 41; + dc_25:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; + dc_25:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 106; Min.u64 = 0; Max.u64 = 1; + dc_25:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_25:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; + dc_25:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_25:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_25:highlink.ordering_latency : Accumulator : Sum.u64 = 66; SumSQ.u64 = 1802; Count.u64 = 3; Min.u64 = 7; Max.u64 = 32; dc_25.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.get_request_latency : Accumulator : Sum.u64 = 214819; SumSQ.u64 = 600058293; Count.u64 = 873; Min.u64 = 20; Max.u64 = 13367; @@ -20271,8 +21124,10 @@ Model complete dc_25.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.AckInv_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + dc_25.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_25.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20291,6 +21146,7 @@ Model complete dc_25.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_25.eventSent_FetchInvX : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; dc_25.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_25.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.eventSent_GetSResp : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; dc_25.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -20301,20 +21157,22 @@ Model complete dc_25.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_25.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_25.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_25.MSHR_occupancy : Accumulator : Sum.u64 = 213073; SumSQ.u64 = 3217109; Count.u64 = 18307; Min.u64 = 0; Max.u64 = 29; - l2cache_26:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_26:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_26:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 578; SumSQ.u64 = 1812; Count.u64 = 221; Min.u64 = 0; Max.u64 = 5; - l2cache_26:memlink:data.packet_latency : Accumulator : Sum.u64 = 4450; SumSQ.u64 = 75608; Count.u64 = 774; Min.u64 = 0; Max.u64 = 106; - l2cache_26:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_26:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_26:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 221; Min.u64 = 0; Max.u64 = 1; - l2cache_26:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; - l2cache_26:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 995; Min.u64 = 0; Max.u64 = 1; - l2cache_26:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 995; Min.u64 = 0; Max.u64 = 1; - l2cache_26:memlink.ordering_latency : Accumulator : Sum.u64 = 33; SumSQ.u64 = 1089; Count.u64 = 1; Min.u64 = 33; Max.u64 = 33; + l2cache_26:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 578; SumSQ.u64 = 1812; Count.u64 = 221; Min.u64 = 0; Max.u64 = 5; + l2cache_26:lowlink:data.packet_latency : Accumulator : Sum.u64 = 4450; SumSQ.u64 = 75608; Count.u64 = 774; Min.u64 = 0; Max.u64 = 106; + l2cache_26:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 221; Min.u64 = 0; Max.u64 = 1; + l2cache_26:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; + l2cache_26:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 995; Min.u64 = 0; Max.u64 = 1; + l2cache_26:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 995; Min.u64 = 0; Max.u64 = 1; + l2cache_26:lowlink.ordering_latency : Accumulator : Sum.u64 = 33; SumSQ.u64 = 1089; Count.u64 = 1; Min.u64 = 33; Max.u64 = 33; l2cache_26.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_26.prefetches_issued : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; l2cache_26.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; @@ -20430,8 +21288,11 @@ Model complete l2cache_26.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_26.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -20440,6 +21301,9 @@ Model complete l2cache_26.eventSent_GetXResp : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_26.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20464,6 +21328,7 @@ Model complete l2cache_26.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.GetSHit_Arrival : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; l2cache_26.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20539,10 +21404,12 @@ Model complete l2cache_26.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.GetSResp_recv : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; l2cache_26.GetXResp_recv : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache_26.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20554,6 +21421,9 @@ Model complete l2cache_26.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_26.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_26.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_26.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_26.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20626,13 +21496,16 @@ Model complete l1cache_52.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache_52.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_52.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_52.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20659,6 +21532,7 @@ Model complete l1cache_52.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.GetSHit_Arrival : Accumulator : Sum.u64 = 762; SumSQ.u64 = 762; Count.u64 = 762; Min.u64 = 1; Max.u64 = 1; l1cache_52.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_52.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20705,14 +21579,18 @@ Model complete l1cache_52.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_52.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_52.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_52.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache_52.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_52.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_52.MSHR_occupancy : Accumulator : Sum.u64 = 370350; SumSQ.u64 = 6260112; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -20801,13 +21679,16 @@ Model complete l1cache_53.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_53.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_53.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_53.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20834,6 +21715,7 @@ Model complete l1cache_53.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.GetSHit_Arrival : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache_53.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_53.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20880,14 +21762,18 @@ Model complete l1cache_53.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_53.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_53.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_53.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_53.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_53.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_53.MSHR_occupancy : Accumulator : Sum.u64 = 369196; SumSQ.u64 = 6175062; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -20909,17 +21795,17 @@ Model complete core_53.cycles_max_issue : Accumulator : Sum.u64 = 1057; SumSQ.u64 = 1057; Count.u64 = 1057; Min.u64 = 1; Max.u64 = 1; core_53.cycles_max_reorder : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; core_53.cycles : Accumulator : Sum.u64 = 22512; SumSQ.u64 = 22512; Count.u64 = 22512; Min.u64 = 1; Max.u64 = 1; - dc_26:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2224; SumSQ.u64 = 7432; Count.u64 = 871; Min.u64 = 0; Max.u64 = 11; - dc_26:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 323; SumSQ.u64 = 1087; Count.u64 = 103; Min.u64 = 1; Max.u64 = 5; - dc_26:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_26:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3811; SumSQ.u64 = 32725; Count.u64 = 770; Min.u64 = 0; Max.u64 = 56; - dc_26:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 871; Min.u64 = 0; Max.u64 = 1; - dc_26:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 103; Min.u64 = 0; Max.u64 = 1; - dc_26:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_26:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; - dc_26:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 1; - dc_26:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 1; - dc_26:cpulink.ordering_latency : Accumulator : Sum.u64 = 20; SumSQ.u64 = 250; Count.u64 = 2; Min.u64 = 5; Max.u64 = 15; + dc_26:highlink:req.packet_latency : Accumulator : Sum.u64 = 2224; SumSQ.u64 = 7432; Count.u64 = 871; Min.u64 = 0; Max.u64 = 11; + dc_26:highlink:ack.packet_latency : Accumulator : Sum.u64 = 323; SumSQ.u64 = 1087; Count.u64 = 103; Min.u64 = 1; Max.u64 = 5; + dc_26:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_26:highlink:data.packet_latency : Accumulator : Sum.u64 = 3811; SumSQ.u64 = 32725; Count.u64 = 770; Min.u64 = 0; Max.u64 = 56; + dc_26:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 871; Min.u64 = 0; Max.u64 = 1; + dc_26:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 103; Min.u64 = 0; Max.u64 = 1; + dc_26:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_26:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; + dc_26:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 1; + dc_26:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1744; Min.u64 = 0; Max.u64 = 1; + dc_26:highlink.ordering_latency : Accumulator : Sum.u64 = 20; SumSQ.u64 = 250; Count.u64 = 2; Min.u64 = 5; Max.u64 = 15; dc_26.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.get_request_latency : Accumulator : Sum.u64 = 190989; SumSQ.u64 = 403389893; Count.u64 = 871; Min.u64 = 20; Max.u64 = 13513; @@ -20942,8 +21828,10 @@ Model complete dc_26.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_26.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_26.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -20962,6 +21850,7 @@ Model complete dc_26.eventSent_FetchInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; dc_26.eventSent_FetchInvX : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; dc_26.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_26.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.eventSent_GetSResp : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; dc_26.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -20972,20 +21861,22 @@ Model complete dc_26.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_26.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_26.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_26.MSHR_occupancy : Accumulator : Sum.u64 = 189247; SumSQ.u64 = 2538807; Count.u64 = 18332; Min.u64 = 0; Max.u64 = 28; - l2cache_27:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 579; SumSQ.u64 = 1807; Count.u64 = 220; Min.u64 = 0; Max.u64 = 5; - l2cache_27:memlink:data.packet_latency : Accumulator : Sum.u64 = 4222; SumSQ.u64 = 51708; Count.u64 = 767; Min.u64 = 0; Max.u64 = 68; - l2cache_27:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 220; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 767; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 987; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 987; Min.u64 = 0; Max.u64 = 0; - l2cache_27:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 579; SumSQ.u64 = 1807; Count.u64 = 220; Min.u64 = 0; Max.u64 = 5; + l2cache_27:lowlink:data.packet_latency : Accumulator : Sum.u64 = 4222; SumSQ.u64 = 51708; Count.u64 = 767; Min.u64 = 0; Max.u64 = 68; + l2cache_27:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 220; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 767; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 987; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 987; Min.u64 = 0; Max.u64 = 0; + l2cache_27:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_27.prefetches_issued : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; l2cache_27.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; @@ -21101,8 +21992,11 @@ Model complete l2cache_27.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_27.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21111,6 +22005,9 @@ Model complete l2cache_27.eventSent_GetXResp : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_27.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21135,6 +22032,7 @@ Model complete l2cache_27.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.GetSHit_Arrival : Accumulator : Sum.u64 = 514; SumSQ.u64 = 514; Count.u64 = 514; Min.u64 = 1; Max.u64 = 1; l2cache_27.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21210,10 +22108,12 @@ Model complete l2cache_27.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.GetSResp_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; l2cache_27.GetXResp_recv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; l2cache_27.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21225,6 +22125,9 @@ Model complete l2cache_27.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_27.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.FetchXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache_27.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_27.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_27.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21297,13 +22200,16 @@ Model complete l1cache_54.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_FetchXResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l1cache_54.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_54.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_54.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21330,6 +22236,7 @@ Model complete l1cache_54.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.GetSHit_Arrival : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; l1cache_54.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21376,14 +22283,18 @@ Model complete l1cache_54.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_54.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_54.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_54.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.FetchInvX_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache_54.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_54.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_54.MSHR_occupancy : Accumulator : Sum.u64 = 369221; SumSQ.u64 = 6205807; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -21472,13 +22383,16 @@ Model complete l1cache_55.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_FetchXResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_55.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_55.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_55.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21505,6 +22419,7 @@ Model complete l1cache_55.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.GetSHit_Arrival : Accumulator : Sum.u64 = 705; SumSQ.u64 = 705; Count.u64 = 705; Min.u64 = 1; Max.u64 = 1; l1cache_55.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21551,14 +22466,18 @@ Model complete l1cache_55.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_55.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_55.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_55.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache_55.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_55.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_55.MSHR_occupancy : Accumulator : Sum.u64 = 365787; SumSQ.u64 = 6126991; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -21580,17 +22499,17 @@ Model complete core_55.cycles_max_issue : Accumulator : Sum.u64 = 1072; SumSQ.u64 = 1072; Count.u64 = 1072; Min.u64 = 1; Max.u64 = 1; core_55.cycles_max_reorder : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; core_55.cycles : Accumulator : Sum.u64 = 22253; SumSQ.u64 = 22253; Count.u64 = 22253; Min.u64 = 1; Max.u64 = 1; - dc_27:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2200; SumSQ.u64 = 6978; Count.u64 = 873; Min.u64 = 0; Max.u64 = 10; - dc_27:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 326; SumSQ.u64 = 1098; Count.u64 = 105; Min.u64 = 1; Max.u64 = 5; - dc_27:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_27:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4758; SumSQ.u64 = 78814; Count.u64 = 770; Min.u64 = 1; Max.u64 = 115; - dc_27:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 873; Min.u64 = 0; Max.u64 = 1; - dc_27:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 105; Min.u64 = 0; Max.u64 = 1; - dc_27:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_27:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; - dc_27:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; - dc_27:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; - dc_27:cpulink.ordering_latency : Accumulator : Sum.u64 = 21; SumSQ.u64 = 221; Count.u64 = 2; Min.u64 = 10; Max.u64 = 11; + dc_27:highlink:req.packet_latency : Accumulator : Sum.u64 = 2200; SumSQ.u64 = 6978; Count.u64 = 873; Min.u64 = 0; Max.u64 = 10; + dc_27:highlink:ack.packet_latency : Accumulator : Sum.u64 = 326; SumSQ.u64 = 1098; Count.u64 = 105; Min.u64 = 1; Max.u64 = 5; + dc_27:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_27:highlink:data.packet_latency : Accumulator : Sum.u64 = 4758; SumSQ.u64 = 78814; Count.u64 = 770; Min.u64 = 1; Max.u64 = 115; + dc_27:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 873; Min.u64 = 0; Max.u64 = 1; + dc_27:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 105; Min.u64 = 0; Max.u64 = 1; + dc_27:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_27:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; + dc_27:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; + dc_27:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 1; + dc_27:highlink.ordering_latency : Accumulator : Sum.u64 = 21; SumSQ.u64 = 221; Count.u64 = 2; Min.u64 = 10; Max.u64 = 11; dc_27.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.get_request_latency : Accumulator : Sum.u64 = 200878; SumSQ.u64 = 478448178; Count.u64 = 873; Min.u64 = 20; Max.u64 = 13540; @@ -21613,8 +22532,10 @@ Model complete dc_27.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.AckInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + dc_27.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_27.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21633,6 +22554,7 @@ Model complete dc_27.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_27.eventSent_FetchInvX : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; dc_27.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_27.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.eventSent_GetSResp : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; dc_27.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -21643,20 +22565,22 @@ Model complete dc_27.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_27.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_27.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_27.MSHR_occupancy : Accumulator : Sum.u64 = 199132; SumSQ.u64 = 2791660; Count.u64 = 18361; Min.u64 = 0; Max.u64 = 25; - l2cache_28:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 620; SumSQ.u64 = 2160; Count.u64 = 215; Min.u64 = 0; Max.u64 = 6; - l2cache_28:memlink:data.packet_latency : Accumulator : Sum.u64 = 4584; SumSQ.u64 = 60888; Count.u64 = 773; Min.u64 = 0; Max.u64 = 114; - l2cache_28:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 215; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 988; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 988; Min.u64 = 0; Max.u64 = 0; - l2cache_28:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 620; SumSQ.u64 = 2160; Count.u64 = 215; Min.u64 = 0; Max.u64 = 6; + l2cache_28:lowlink:data.packet_latency : Accumulator : Sum.u64 = 4584; SumSQ.u64 = 60888; Count.u64 = 773; Min.u64 = 0; Max.u64 = 114; + l2cache_28:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 215; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 988; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 988; Min.u64 = 0; Max.u64 = 0; + l2cache_28:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_28.prefetches_issued : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; l2cache_28.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; @@ -21772,8 +22696,11 @@ Model complete l2cache_28.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache_28.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -21782,6 +22709,9 @@ Model complete l2cache_28.eventSent_GetXResp : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_28.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21806,6 +22736,7 @@ Model complete l2cache_28.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.GetSHit_Arrival : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; l2cache_28.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21881,10 +22812,12 @@ Model complete l2cache_28.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.GetSResp_recv : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; l2cache_28.GetXResp_recv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; l2cache_28.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21896,6 +22829,9 @@ Model complete l2cache_28.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache_28.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.FetchXResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache_28.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_28.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_28.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -21968,13 +22904,16 @@ Model complete l1cache_56.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache_56.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_56.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_56.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22001,6 +22940,7 @@ Model complete l1cache_56.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.GetSHit_Arrival : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; l1cache_56.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22047,14 +22987,18 @@ Model complete l1cache_56.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_56.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_56.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_56.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.FetchInvX_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache_56.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_56.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_56.MSHR_occupancy : Accumulator : Sum.u64 = 369770; SumSQ.u64 = 6237132; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -22143,13 +23087,16 @@ Model complete l1cache_57.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_FetchXResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_57.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_57.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_57.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22176,6 +23123,7 @@ Model complete l1cache_57.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.GetSHit_Arrival : Accumulator : Sum.u64 = 704; SumSQ.u64 = 704; Count.u64 = 704; Min.u64 = 1; Max.u64 = 1; l1cache_57.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_57.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22222,14 +23170,18 @@ Model complete l1cache_57.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_57.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_57.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_57.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache_57.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_57.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_57.MSHR_occupancy : Accumulator : Sum.u64 = 367055; SumSQ.u64 = 6149595; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -22251,17 +23203,17 @@ Model complete core_57.cycles_max_issue : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; core_57.cycles_max_reorder : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; core_57.cycles : Accumulator : Sum.u64 = 22324; SumSQ.u64 = 22324; Count.u64 = 22324; Min.u64 = 1; Max.u64 = 1; - dc_28:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2384; SumSQ.u64 = 8484; Count.u64 = 875; Min.u64 = 0; Max.u64 = 13; - dc_28:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 342; SumSQ.u64 = 1252; Count.u64 = 103; Min.u64 = 1; Max.u64 = 6; - dc_28:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_28:cpulink:data.packet_latency : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 57393; Count.u64 = 772; Min.u64 = 1; Max.u64 = 41; - dc_28:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 875; Min.u64 = 0; Max.u64 = 0; - dc_28:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 103; Min.u64 = 0; Max.u64 = 1; - dc_28:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_28:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_28:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_28:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_28:cpulink.ordering_latency : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + dc_28:highlink:req.packet_latency : Accumulator : Sum.u64 = 2384; SumSQ.u64 = 8484; Count.u64 = 875; Min.u64 = 0; Max.u64 = 13; + dc_28:highlink:ack.packet_latency : Accumulator : Sum.u64 = 342; SumSQ.u64 = 1252; Count.u64 = 103; Min.u64 = 1; Max.u64 = 6; + dc_28:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_28:highlink:data.packet_latency : Accumulator : Sum.u64 = 5329; SumSQ.u64 = 57393; Count.u64 = 772; Min.u64 = 1; Max.u64 = 41; + dc_28:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 875; Min.u64 = 0; Max.u64 = 0; + dc_28:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 103; Min.u64 = 0; Max.u64 = 1; + dc_28:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_28:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_28:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_28:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_28:highlink.ordering_latency : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; dc_28.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.get_request_latency : Accumulator : Sum.u64 = 190407; SumSQ.u64 = 401147015; Count.u64 = 875; Min.u64 = 20; Max.u64 = 13373; @@ -22284,8 +23236,10 @@ Model complete dc_28.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_28.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_28.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22304,6 +23258,7 @@ Model complete dc_28.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_28.eventSent_FetchInvX : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; dc_28.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_28.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.eventSent_GetSResp : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; dc_28.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -22314,20 +23269,22 @@ Model complete dc_28.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_28.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_28.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_28.MSHR_occupancy : Accumulator : Sum.u64 = 188657; SumSQ.u64 = 2576829; Count.u64 = 18383; Min.u64 = 0; Max.u64 = 25; - l2cache_29:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_29:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_29:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 726; SumSQ.u64 = 2836; Count.u64 = 223; Min.u64 = 0; Max.u64 = 7; - l2cache_29:memlink:data.packet_latency : Accumulator : Sum.u64 = 4474; SumSQ.u64 = 46196; Count.u64 = 774; Min.u64 = 0; Max.u64 = 53; - l2cache_29:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_29:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_29:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 223; Min.u64 = 0; Max.u64 = 1; - l2cache_29:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; - l2cache_29:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 30; SumSQ.u64 = 42; Count.u64 = 997; Min.u64 = 0; Max.u64 = 2; - l2cache_29:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 997; Min.u64 = 0; Max.u64 = 1; - l2cache_29:memlink.ordering_latency : Accumulator : Sum.u64 = 156; SumSQ.u64 = 7074; Count.u64 = 8; Min.u64 = 1; Max.u64 = 59; + l2cache_29:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 726; SumSQ.u64 = 2836; Count.u64 = 223; Min.u64 = 0; Max.u64 = 7; + l2cache_29:lowlink:data.packet_latency : Accumulator : Sum.u64 = 4474; SumSQ.u64 = 46196; Count.u64 = 774; Min.u64 = 0; Max.u64 = 53; + l2cache_29:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 223; Min.u64 = 0; Max.u64 = 1; + l2cache_29:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 774; Min.u64 = 0; Max.u64 = 0; + l2cache_29:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 30; SumSQ.u64 = 42; Count.u64 = 997; Min.u64 = 0; Max.u64 = 2; + l2cache_29:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 997; Min.u64 = 0; Max.u64 = 1; + l2cache_29:lowlink.ordering_latency : Accumulator : Sum.u64 = 156; SumSQ.u64 = 7074; Count.u64 = 8; Min.u64 = 1; Max.u64 = 59; l2cache_29.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_29.prefetches_issued : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; l2cache_29.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; @@ -22443,8 +23400,11 @@ Model complete l2cache_29.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_FetchXResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_29.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -22453,6 +23413,9 @@ Model complete l2cache_29.eventSent_GetXResp : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; l2cache_29.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22477,6 +23440,7 @@ Model complete l2cache_29.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.GetSHit_Arrival : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l2cache_29.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22552,10 +23516,12 @@ Model complete l2cache_29.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.GetSResp_recv : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; l2cache_29.GetXResp_recv : Accumulator : Sum.u64 = 505; SumSQ.u64 = 505; Count.u64 = 505; Min.u64 = 1; Max.u64 = 1; l2cache_29.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22567,6 +23533,9 @@ Model complete l2cache_29.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache_29.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_29.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_29.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_29.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22639,13 +23608,16 @@ Model complete l1cache_58.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_58.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_58.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_58.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22672,6 +23644,7 @@ Model complete l1cache_58.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.GetSHit_Arrival : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; l1cache_58.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_58.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22718,14 +23691,18 @@ Model complete l1cache_58.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_58.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.GetSResp_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; l1cache_58.GetXResp_recv : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; l1cache_58.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache_58.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_58.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_58.MSHR_occupancy : Accumulator : Sum.u64 = 378522; SumSQ.u64 = 6391908; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -22814,13 +23791,16 @@ Model complete l1cache_59.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_FetchXResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_59.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_59.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_59.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22847,6 +23827,7 @@ Model complete l1cache_59.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.GetSHit_Arrival : Accumulator : Sum.u64 = 692; SumSQ.u64 = 692; Count.u64 = 692; Min.u64 = 1; Max.u64 = 1; l1cache_59.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_59.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22893,14 +23874,18 @@ Model complete l1cache_59.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_59.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.GetSResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l1cache_59.GetXResp_recv : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache_59.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache_59.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_59.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_59.MSHR_occupancy : Accumulator : Sum.u64 = 384006; SumSQ.u64 = 6484656; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -22922,17 +23907,17 @@ Model complete core_59.cycles_max_issue : Accumulator : Sum.u64 = 1036; SumSQ.u64 = 1036; Count.u64 = 1036; Min.u64 = 1; Max.u64 = 1; core_59.cycles_max_reorder : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; core_59.cycles : Accumulator : Sum.u64 = 23184; SumSQ.u64 = 23184; Count.u64 = 23184; Min.u64 = 1; Max.u64 = 1; - dc_29:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2742; SumSQ.u64 = 10638; Count.u64 = 876; Min.u64 = 0; Max.u64 = 9; - dc_29:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 391; SumSQ.u64 = 1643; Count.u64 = 104; Min.u64 = 1; Max.u64 = 6; - dc_29:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4710; SumSQ.u64 = 37464; Count.u64 = 772; Min.u64 = 1; Max.u64 = 34; - dc_29:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 876; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 104; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; - dc_29:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink:req.packet_latency : Accumulator : Sum.u64 = 2742; SumSQ.u64 = 10638; Count.u64 = 876; Min.u64 = 0; Max.u64 = 9; + dc_29:highlink:ack.packet_latency : Accumulator : Sum.u64 = 391; SumSQ.u64 = 1643; Count.u64 = 104; Min.u64 = 1; Max.u64 = 6; + dc_29:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink:data.packet_latency : Accumulator : Sum.u64 = 4710; SumSQ.u64 = 37464; Count.u64 = 772; Min.u64 = 1; Max.u64 = 34; + dc_29:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 876; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 104; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1752; Min.u64 = 0; Max.u64 = 0; + dc_29:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.get_request_latency : Accumulator : Sum.u64 = 204571; SumSQ.u64 = 455500233; Count.u64 = 876; Min.u64 = 20; Max.u64 = 12914; @@ -22955,8 +23940,10 @@ Model complete dc_29.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.AckInv_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + dc_29.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -22975,6 +23962,7 @@ Model complete dc_29.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_29.eventSent_FetchInvX : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; dc_29.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.eventSent_GetSResp : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; dc_29.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -22985,6 +23973,8 @@ Model complete dc_29.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_29.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_29.MSHR_occupancy : Accumulator : Sum.u64 = 202819; SumSQ.u64 = 2968589; Count.u64 = 18241; Min.u64 = 0; Max.u64 = 27; @@ -23002,32 +23992,32 @@ Model complete hbm_4.cycles_with_issue : Accumulator : Sum.u64 = 4079; SumSQ.u64 = 4079; Count.u64 = 4079; Min.u64 = 1; Max.u64 = 1; hbm_4.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_4.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_4:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8682; SumSQ.u64 = 41086; Count.u64 = 2296; Min.u64 = 1; Max.u64 = 26; - hbm_4:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_4:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_4:cpulink:data.packet_latency : Accumulator : Sum.u64 = 9163; SumSQ.u64 = 57493; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 38; - hbm_4:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 2296; Min.u64 = 0; Max.u64 = 1; - hbm_4:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_4:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_4:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 0; - hbm_4:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; - hbm_4:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; - hbm_4:cpulink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 3; Min.u64 = 0; Max.u64 = 2; + hbm_4:highlink:req.packet_latency : Accumulator : Sum.u64 = 8682; SumSQ.u64 = 41086; Count.u64 = 2296; Min.u64 = 1; Max.u64 = 26; + hbm_4:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_4:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_4:highlink:data.packet_latency : Accumulator : Sum.u64 = 9163; SumSQ.u64 = 57493; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 38; + hbm_4:highlink.outoforder_req_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 2296; Min.u64 = 0; Max.u64 = 1; + hbm_4:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_4:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_4:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2288; Min.u64 = 0; Max.u64 = 0; + hbm_4:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; + hbm_4:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; + hbm_4:highlink.ordering_latency : Accumulator : Sum.u64 = 3; SumSQ.u64 = 5; Count.u64 = 3; Min.u64 = 0; Max.u64 = 2; hbm_4.CacheHits_Read : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; hbm_4.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_4.CacheHits_Write : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; hbm_4.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 843; SumSQ.u64 = 3803; Count.u64 = 220; Min.u64 = 0; Max.u64 = 7; - l2cache_30:memlink:data.packet_latency : Accumulator : Sum.u64 = 5985; SumSQ.u64 = 81831; Count.u64 = 773; Min.u64 = 0; Max.u64 = 58; - l2cache_30:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 220; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 993; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 993; Min.u64 = 0; Max.u64 = 0; - l2cache_30:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 843; SumSQ.u64 = 3803; Count.u64 = 220; Min.u64 = 0; Max.u64 = 7; + l2cache_30:lowlink:data.packet_latency : Accumulator : Sum.u64 = 5985; SumSQ.u64 = 81831; Count.u64 = 773; Min.u64 = 0; Max.u64 = 58; + l2cache_30:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 220; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 993; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 993; Min.u64 = 0; Max.u64 = 0; + l2cache_30:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_30.prefetches_issued : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; l2cache_30.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; @@ -23143,8 +24133,11 @@ Model complete l2cache_30.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_30.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23153,6 +24146,9 @@ Model complete l2cache_30.eventSent_GetXResp : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_30.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23177,6 +24173,7 @@ Model complete l2cache_30.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.GetSHit_Arrival : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; l2cache_30.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23252,10 +24249,12 @@ Model complete l2cache_30.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.GetSResp_recv : Accumulator : Sum.u64 = 477; SumSQ.u64 = 477; Count.u64 = 477; Min.u64 = 1; Max.u64 = 1; l2cache_30.GetXResp_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_30.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23267,6 +24266,9 @@ Model complete l2cache_30.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_30.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_30.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_30.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_30.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23339,13 +24341,16 @@ Model complete l1cache_60.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_60.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_60.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_60.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23372,6 +24377,7 @@ Model complete l1cache_60.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.GetSHit_Arrival : Accumulator : Sum.u64 = 713; SumSQ.u64 = 713; Count.u64 = 713; Min.u64 = 1; Max.u64 = 1; l1cache_60.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_60.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23418,14 +24424,18 @@ Model complete l1cache_60.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_60.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_60.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_60.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache_60.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_60.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_60.MSHR_occupancy : Accumulator : Sum.u64 = 380634; SumSQ.u64 = 6427396; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -23514,13 +24524,16 @@ Model complete l1cache_61.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_61.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_61.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23547,6 +24560,7 @@ Model complete l1cache_61.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.GetSHit_Arrival : Accumulator : Sum.u64 = 685; SumSQ.u64 = 685; Count.u64 = 685; Min.u64 = 1; Max.u64 = 1; l1cache_61.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23593,14 +24607,18 @@ Model complete l1cache_61.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_61.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_61.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_61.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_61.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_61.MSHR_occupancy : Accumulator : Sum.u64 = 378310; SumSQ.u64 = 6362530; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -23622,17 +24640,17 @@ Model complete core_61.cycles_max_issue : Accumulator : Sum.u64 = 1059; SumSQ.u64 = 1059; Count.u64 = 1059; Min.u64 = 1; Max.u64 = 1; core_61.cycles_max_reorder : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; core_61.cycles : Accumulator : Sum.u64 = 22940; SumSQ.u64 = 22940; Count.u64 = 22940; Min.u64 = 1; Max.u64 = 1; - dc_30:cpulink:req.packet_latency : Accumulator : Sum.u64 = 3222; SumSQ.u64 = 15900; Count.u64 = 877; Min.u64 = 0; Max.u64 = 29; - dc_30:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 459; SumSQ.u64 = 2195; Count.u64 = 105; Min.u64 = 2; Max.u64 = 7; - dc_30:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_30:cpulink:data.packet_latency : Accumulator : Sum.u64 = 5448; SumSQ.u64 = 62542; Count.u64 = 772; Min.u64 = 1; Max.u64 = 51; - dc_30:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 877; Min.u64 = 0; Max.u64 = 1; - dc_30:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; - dc_30:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_30:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_30:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1754; Min.u64 = 0; Max.u64 = 1; - dc_30:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1754; Min.u64 = 0; Max.u64 = 1; - dc_30:cpulink.ordering_latency : Accumulator : Sum.u64 = 8; SumSQ.u64 = 64; Count.u64 = 1; Min.u64 = 8; Max.u64 = 8; + dc_30:highlink:req.packet_latency : Accumulator : Sum.u64 = 3222; SumSQ.u64 = 15900; Count.u64 = 877; Min.u64 = 0; Max.u64 = 29; + dc_30:highlink:ack.packet_latency : Accumulator : Sum.u64 = 459; SumSQ.u64 = 2195; Count.u64 = 105; Min.u64 = 2; Max.u64 = 7; + dc_30:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_30:highlink:data.packet_latency : Accumulator : Sum.u64 = 5448; SumSQ.u64 = 62542; Count.u64 = 772; Min.u64 = 1; Max.u64 = 51; + dc_30:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 877; Min.u64 = 0; Max.u64 = 1; + dc_30:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; + dc_30:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_30:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_30:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 1754; Min.u64 = 0; Max.u64 = 1; + dc_30:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1754; Min.u64 = 0; Max.u64 = 1; + dc_30:highlink.ordering_latency : Accumulator : Sum.u64 = 8; SumSQ.u64 = 64; Count.u64 = 1; Min.u64 = 8; Max.u64 = 8; dc_30.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.get_request_latency : Accumulator : Sum.u64 = 206863; SumSQ.u64 = 581346519; Count.u64 = 877; Min.u64 = 22; Max.u64 = 13341; @@ -23655,8 +24673,10 @@ Model complete dc_30.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.AckInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + dc_30.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_30.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23675,6 +24695,7 @@ Model complete dc_30.eventSent_FetchInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; dc_30.eventSent_FetchInvX : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; dc_30.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_30.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; dc_30.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -23685,6 +24706,8 @@ Model complete dc_30.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_30.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_30.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_30.MSHR_occupancy : Accumulator : Sum.u64 = 205109; SumSQ.u64 = 3045965; Count.u64 = 18283; Min.u64 = 0; Max.u64 = 32; @@ -23702,32 +24725,32 @@ Model complete hbm_5.cycles_with_issue : Accumulator : Sum.u64 = 4083; SumSQ.u64 = 4083; Count.u64 = 4083; Min.u64 = 1; Max.u64 = 1; hbm_5.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_5.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_5:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8797; SumSQ.u64 = 43133; Count.u64 = 2295; Min.u64 = 1; Max.u64 = 24; - hbm_5:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_5:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_5:cpulink:data.packet_latency : Accumulator : Sum.u64 = 17939; SumSQ.u64 = 233387; Count.u64 = 2289; Min.u64 = 1; Max.u64 = 100; - hbm_5:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 2295; Min.u64 = 0; Max.u64 = 1; - hbm_5:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_5:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_5:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2289; Min.u64 = 0; Max.u64 = 0; - hbm_5:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 14; SumSQ.u64 = 16; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 2; - hbm_5:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 5; SumSQ.u64 = 7; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 2; - hbm_5:cpulink.ordering_latency : Accumulator : Sum.u64 = 38; SumSQ.u64 = 738; Count.u64 = 4; Min.u64 = 2; Max.u64 = 26; + hbm_5:highlink:req.packet_latency : Accumulator : Sum.u64 = 8797; SumSQ.u64 = 43133; Count.u64 = 2295; Min.u64 = 1; Max.u64 = 24; + hbm_5:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_5:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_5:highlink:data.packet_latency : Accumulator : Sum.u64 = 17939; SumSQ.u64 = 233387; Count.u64 = 2289; Min.u64 = 1; Max.u64 = 100; + hbm_5:highlink.outoforder_req_events : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 2295; Min.u64 = 0; Max.u64 = 1; + hbm_5:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_5:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_5:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2289; Min.u64 = 0; Max.u64 = 0; + hbm_5:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 14; SumSQ.u64 = 16; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 2; + hbm_5:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 5; SumSQ.u64 = 7; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 2; + hbm_5:highlink.ordering_latency : Accumulator : Sum.u64 = 38; SumSQ.u64 = 738; Count.u64 = 4; Min.u64 = 2; Max.u64 = 26; hbm_5.CacheHits_Read : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; hbm_5.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_5.CacheHits_Write : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; hbm_5.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 782; SumSQ.u64 = 3144; Count.u64 = 231; Min.u64 = 0; Max.u64 = 6; - l2cache_31:memlink:data.packet_latency : Accumulator : Sum.u64 = 6644; SumSQ.u64 = 131666; Count.u64 = 767; Min.u64 = 0; Max.u64 = 116; - l2cache_31:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 231; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 767; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; - l2cache_31:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 782; SumSQ.u64 = 3144; Count.u64 = 231; Min.u64 = 0; Max.u64 = 6; + l2cache_31:lowlink:data.packet_latency : Accumulator : Sum.u64 = 6644; SumSQ.u64 = 131666; Count.u64 = 767; Min.u64 = 0; Max.u64 = 116; + l2cache_31:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 231; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 767; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; + l2cache_31:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_31.prefetches_issued : Accumulator : Sum.u64 = 749; SumSQ.u64 = 749; Count.u64 = 749; Min.u64 = 1; Max.u64 = 1; l2cache_31.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; @@ -23843,8 +24866,11 @@ Model complete l2cache_31.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_31.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23853,6 +24879,9 @@ Model complete l2cache_31.eventSent_GetXResp : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_31.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23877,6 +24906,7 @@ Model complete l2cache_31.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.GetSHit_Arrival : Accumulator : Sum.u64 = 506; SumSQ.u64 = 506; Count.u64 = 506; Min.u64 = 1; Max.u64 = 1; l2cache_31.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23952,10 +24982,12 @@ Model complete l2cache_31.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.GetSResp_recv : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; l2cache_31.GetXResp_recv : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache_31.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -23967,6 +24999,9 @@ Model complete l2cache_31.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_31.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.FetchXResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache_31.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_31.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_31.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24039,13 +25074,16 @@ Model complete l1cache_62.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_FetchXResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache_62.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_62.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_62.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24072,6 +25110,7 @@ Model complete l1cache_62.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.GetSHit_Arrival : Accumulator : Sum.u64 = 707; SumSQ.u64 = 707; Count.u64 = 707; Min.u64 = 1; Max.u64 = 1; l1cache_62.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24118,14 +25157,18 @@ Model complete l1cache_62.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_62.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_62.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_62.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.FetchInvX_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache_62.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_62.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_62.MSHR_occupancy : Accumulator : Sum.u64 = 375972; SumSQ.u64 = 6359590; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -24214,13 +25257,16 @@ Model complete l1cache_63.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_63.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_63.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_63.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24247,6 +25293,7 @@ Model complete l1cache_63.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.GetSHit_Arrival : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; l1cache_63.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24293,14 +25340,18 @@ Model complete l1cache_63.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_63.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_63.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_63.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_63.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_63.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_63.MSHR_occupancy : Accumulator : Sum.u64 = 371652; SumSQ.u64 = 6255690; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -24322,17 +25373,17 @@ Model complete core_63.cycles_max_issue : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; core_63.cycles_max_reorder : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; core_63.cycles : Accumulator : Sum.u64 = 22517; SumSQ.u64 = 22517; Count.u64 = 22517; Min.u64 = 1; Max.u64 = 1; - dc_31:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2809; SumSQ.u64 = 11431; Count.u64 = 878; Min.u64 = 0; Max.u64 = 12; - dc_31:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 407; SumSQ.u64 = 1709; Count.u64 = 105; Min.u64 = 2; Max.u64 = 6; - dc_31:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_31:cpulink:data.packet_latency : Accumulator : Sum.u64 = 6436; SumSQ.u64 = 138866; Count.u64 = 773; Min.u64 = 1; Max.u64 = 187; - dc_31:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 878; Min.u64 = 0; Max.u64 = 1; - dc_31:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; - dc_31:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_31:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - dc_31:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; - dc_31:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; - dc_31:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + dc_31:highlink:req.packet_latency : Accumulator : Sum.u64 = 2809; SumSQ.u64 = 11431; Count.u64 = 878; Min.u64 = 0; Max.u64 = 12; + dc_31:highlink:ack.packet_latency : Accumulator : Sum.u64 = 407; SumSQ.u64 = 1709; Count.u64 = 105; Min.u64 = 2; Max.u64 = 6; + dc_31:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_31:highlink:data.packet_latency : Accumulator : Sum.u64 = 6436; SumSQ.u64 = 138866; Count.u64 = 773; Min.u64 = 1; Max.u64 = 187; + dc_31:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 878; Min.u64 = 0; Max.u64 = 1; + dc_31:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 105; Min.u64 = 0; Max.u64 = 0; + dc_31:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_31:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + dc_31:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; + dc_31:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1756; Min.u64 = 0; Max.u64 = 1; + dc_31:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; dc_31.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.get_request_latency : Accumulator : Sum.u64 = 187167; SumSQ.u64 = 126208023; Count.u64 = 878; Min.u64 = 22; Max.u64 = 6861; @@ -24355,8 +25406,10 @@ Model complete dc_31.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.AckInv_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + dc_31.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_31.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24375,6 +25428,7 @@ Model complete dc_31.eventSent_FetchInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; dc_31.eventSent_FetchInvX : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; dc_31.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_31.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.eventSent_GetSResp : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; dc_31.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -24385,20 +25439,22 @@ Model complete dc_31.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_31.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_31.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_31.MSHR_occupancy : Accumulator : Sum.u64 = 185411; SumSQ.u64 = 2503721; Count.u64 = 18308; Min.u64 = 0; Max.u64 = 34; - l2cache_32:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 715; SumSQ.u64 = 2675; Count.u64 = 225; Min.u64 = 0; Max.u64 = 6; - l2cache_32:memlink:data.packet_latency : Accumulator : Sum.u64 = 6269; SumSQ.u64 = 96709; Count.u64 = 773; Min.u64 = 0; Max.u64 = 54; - l2cache_32:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 225; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; - l2cache_32:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 715; SumSQ.u64 = 2675; Count.u64 = 225; Min.u64 = 0; Max.u64 = 6; + l2cache_32:lowlink:data.packet_latency : Accumulator : Sum.u64 = 6269; SumSQ.u64 = 96709; Count.u64 = 773; Min.u64 = 0; Max.u64 = 54; + l2cache_32:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 225; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 773; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 998; Min.u64 = 0; Max.u64 = 0; + l2cache_32:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_32.prefetches_issued : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; l2cache_32.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; @@ -24514,8 +25570,11 @@ Model complete l2cache_32.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_FetchXResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_32.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24524,6 +25583,9 @@ Model complete l2cache_32.eventSent_GetXResp : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; l2cache_32.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24548,6 +25610,7 @@ Model complete l2cache_32.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.GetSHit_Arrival : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; l2cache_32.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24623,10 +25686,12 @@ Model complete l2cache_32.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.GetSResp_recv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; l2cache_32.GetXResp_recv : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache_32.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24638,6 +25703,9 @@ Model complete l2cache_32.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache_32.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache_32.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_32.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_32.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24710,13 +25778,16 @@ Model complete l1cache_64.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache_64.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_64.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_64.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24743,6 +25814,7 @@ Model complete l1cache_64.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.GetSHit_Arrival : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; l1cache_64.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24789,14 +25861,18 @@ Model complete l1cache_64.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_64.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_64.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_64.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache_64.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_64.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_64.MSHR_occupancy : Accumulator : Sum.u64 = 374863; SumSQ.u64 = 6296387; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -24885,13 +25961,16 @@ Model complete l1cache_65.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_65.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_65.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_65.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24918,6 +25997,7 @@ Model complete l1cache_65.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.GetSHit_Arrival : Accumulator : Sum.u64 = 726; SumSQ.u64 = 726; Count.u64 = 726; Min.u64 = 1; Max.u64 = 1; l1cache_65.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -24964,14 +26044,18 @@ Model complete l1cache_65.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_65.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l1cache_65.GetXResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; l1cache_65.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache_65.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_65.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_65.MSHR_occupancy : Accumulator : Sum.u64 = 375809; SumSQ.u64 = 6303219; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -24993,17 +26077,17 @@ Model complete core_65.cycles_max_issue : Accumulator : Sum.u64 = 1053; SumSQ.u64 = 1053; Count.u64 = 1053; Min.u64 = 1; Max.u64 = 1; core_65.cycles_max_reorder : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; core_65.cycles : Accumulator : Sum.u64 = 22817; SumSQ.u64 = 22817; Count.u64 = 22817; Min.u64 = 1; Max.u64 = 1; - dc_32:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2628; SumSQ.u64 = 10322; Count.u64 = 874; Min.u64 = 0; Max.u64 = 25; - dc_32:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 393; SumSQ.u64 = 1571; Count.u64 = 104; Min.u64 = 2; Max.u64 = 6; - dc_32:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink:data.packet_latency : Accumulator : Sum.u64 = 5462; SumSQ.u64 = 77362; Count.u64 = 770; Min.u64 = 1; Max.u64 = 63; - dc_32:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 874; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 104; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_32:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink:req.packet_latency : Accumulator : Sum.u64 = 2628; SumSQ.u64 = 10322; Count.u64 = 874; Min.u64 = 0; Max.u64 = 25; + dc_32:highlink:ack.packet_latency : Accumulator : Sum.u64 = 393; SumSQ.u64 = 1571; Count.u64 = 104; Min.u64 = 2; Max.u64 = 6; + dc_32:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink:data.packet_latency : Accumulator : Sum.u64 = 5462; SumSQ.u64 = 77362; Count.u64 = 770; Min.u64 = 1; Max.u64 = 63; + dc_32:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 874; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 104; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_32:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.get_request_latency : Accumulator : Sum.u64 = 190275; SumSQ.u64 = 426175847; Count.u64 = 874; Min.u64 = 22; Max.u64 = 13517; @@ -25026,8 +26110,10 @@ Model complete dc_32.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.AckInv_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + dc_32.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25046,6 +26132,7 @@ Model complete dc_32.eventSent_FetchInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; dc_32.eventSent_FetchInvX : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; dc_32.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.eventSent_GetSResp : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; dc_32.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -25056,20 +26143,22 @@ Model complete dc_32.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_32.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_32.MSHR_occupancy : Accumulator : Sum.u64 = 188527; SumSQ.u64 = 2618755; Count.u64 = 18324; Min.u64 = 0; Max.u64 = 30; - l2cache_33:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 704; SumSQ.u64 = 2610; Count.u64 = 221; Min.u64 = 0; Max.u64 = 6; - l2cache_33:memlink:data.packet_latency : Accumulator : Sum.u64 = 6559; SumSQ.u64 = 108943; Count.u64 = 775; Min.u64 = 0; Max.u64 = 111; - l2cache_33:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 221; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 996; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 996; Min.u64 = 0; Max.u64 = 0; - l2cache_33:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 704; SumSQ.u64 = 2610; Count.u64 = 221; Min.u64 = 0; Max.u64 = 6; + l2cache_33:lowlink:data.packet_latency : Accumulator : Sum.u64 = 6559; SumSQ.u64 = 108943; Count.u64 = 775; Min.u64 = 0; Max.u64 = 111; + l2cache_33:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 221; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 775; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 996; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 996; Min.u64 = 0; Max.u64 = 0; + l2cache_33:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_33.prefetches_issued : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; l2cache_33.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; @@ -25185,8 +26274,11 @@ Model complete l2cache_33.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache_33.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25195,6 +26287,9 @@ Model complete l2cache_33.eventSent_GetXResp : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_33.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25219,6 +26314,7 @@ Model complete l2cache_33.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.GetSHit_Arrival : Accumulator : Sum.u64 = 502; SumSQ.u64 = 502; Count.u64 = 502; Min.u64 = 1; Max.u64 = 1; l2cache_33.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25294,10 +26390,12 @@ Model complete l2cache_33.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.GetSResp_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; l2cache_33.GetXResp_recv : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache_33.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25309,6 +26407,9 @@ Model complete l2cache_33.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache_33.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_33.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_33.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_33.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25381,13 +26482,16 @@ Model complete l1cache_66.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_FetchXResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l1cache_66.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_66.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_66.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25414,6 +26518,7 @@ Model complete l1cache_66.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.GetSHit_Arrival : Accumulator : Sum.u64 = 724; SumSQ.u64 = 724; Count.u64 = 724; Min.u64 = 1; Max.u64 = 1; l1cache_66.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache_66.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25460,14 +26565,18 @@ Model complete l1cache_66.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_66.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_66.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_66.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.FetchInvX_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache_66.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_66.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_66.MSHR_occupancy : Accumulator : Sum.u64 = 375027; SumSQ.u64 = 6302035; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -25556,13 +26665,16 @@ Model complete l1cache_67.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_FetchXResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_67.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_67.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_67.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25589,6 +26701,7 @@ Model complete l1cache_67.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.GetSHit_Arrival : Accumulator : Sum.u64 = 744; SumSQ.u64 = 744; Count.u64 = 744; Min.u64 = 1; Max.u64 = 1; l1cache_67.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25635,14 +26748,18 @@ Model complete l1cache_67.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_67.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_67.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_67.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache_67.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_67.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_67.MSHR_occupancy : Accumulator : Sum.u64 = 373572; SumSQ.u64 = 6276814; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -25664,17 +26781,17 @@ Model complete core_67.cycles_max_issue : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; core_67.cycles_max_reorder : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; core_67.cycles : Accumulator : Sum.u64 = 22639; SumSQ.u64 = 22639; Count.u64 = 22639; Min.u64 = 1; Max.u64 = 1; - dc_33:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2575; SumSQ.u64 = 9453; Count.u64 = 875; Min.u64 = 0; Max.u64 = 8; - dc_33:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 382; SumSQ.u64 = 1506; Count.u64 = 103; Min.u64 = 2; Max.u64 = 5; - dc_33:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_33:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4645; SumSQ.u64 = 51093; Count.u64 = 772; Min.u64 = 1; Max.u64 = 46; - dc_33:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 875; Min.u64 = 0; Max.u64 = 1; - dc_33:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; - dc_33:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_33:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; - dc_33:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_33:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; - dc_33:cpulink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + dc_33:highlink:req.packet_latency : Accumulator : Sum.u64 = 2575; SumSQ.u64 = 9453; Count.u64 = 875; Min.u64 = 0; Max.u64 = 8; + dc_33:highlink:ack.packet_latency : Accumulator : Sum.u64 = 382; SumSQ.u64 = 1506; Count.u64 = 103; Min.u64 = 2; Max.u64 = 5; + dc_33:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_33:highlink:data.packet_latency : Accumulator : Sum.u64 = 4645; SumSQ.u64 = 51093; Count.u64 = 772; Min.u64 = 1; Max.u64 = 46; + dc_33:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 875; Min.u64 = 0; Max.u64 = 1; + dc_33:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; + dc_33:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_33:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 772; Min.u64 = 0; Max.u64 = 0; + dc_33:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_33:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1750; Min.u64 = 0; Max.u64 = 1; + dc_33:highlink.ordering_latency : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; dc_33.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.get_request_latency : Accumulator : Sum.u64 = 198335; SumSQ.u64 = 421084539; Count.u64 = 875; Min.u64 = 22; Max.u64 = 13385; @@ -25697,8 +26814,10 @@ Model complete dc_33.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_33.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_33.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25717,6 +26836,7 @@ Model complete dc_33.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_33.eventSent_FetchInvX : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; dc_33.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_33.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.eventSent_GetSResp : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; dc_33.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -25727,6 +26847,8 @@ Model complete dc_33.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_33.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_33.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_33.MSHR_occupancy : Accumulator : Sum.u64 = 196585; SumSQ.u64 = 2795343; Count.u64 = 18355; Min.u64 = 0; Max.u64 = 30; @@ -25744,32 +26866,32 @@ Model complete hbm_6.cycles_with_issue : Accumulator : Sum.u64 = 4060; SumSQ.u64 = 4060; Count.u64 = 4060; Min.u64 = 1; Max.u64 = 1; hbm_6.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_6.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_6:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8336; SumSQ.u64 = 40390; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 27; - hbm_6:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_6:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_6:cpulink:data.packet_latency : Accumulator : Sum.u64 = 16863; SumSQ.u64 = 171789; Count.u64 = 2287; Min.u64 = 0; Max.u64 = 44; - hbm_6:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 1; - hbm_6:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_6:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_6:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2287; Min.u64 = 0; Max.u64 = 0; - hbm_6:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; - hbm_6:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; - hbm_6:cpulink.ordering_latency : Accumulator : Sum.u64 = 9; SumSQ.u64 = 81; Count.u64 = 1; Min.u64 = 9; Max.u64 = 9; + hbm_6:highlink:req.packet_latency : Accumulator : Sum.u64 = 8336; SumSQ.u64 = 40390; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 27; + hbm_6:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_6:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_6:highlink:data.packet_latency : Accumulator : Sum.u64 = 16863; SumSQ.u64 = 171789; Count.u64 = 2287; Min.u64 = 0; Max.u64 = 44; + hbm_6:highlink.outoforder_req_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 1; + hbm_6:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_6:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_6:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2287; Min.u64 = 0; Max.u64 = 0; + hbm_6:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; + hbm_6:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 4584; Min.u64 = 0; Max.u64 = 1; + hbm_6:highlink.ordering_latency : Accumulator : Sum.u64 = 9; SumSQ.u64 = 81; Count.u64 = 1; Min.u64 = 9; Max.u64 = 9; hbm_6.CacheHits_Read : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; hbm_6.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_6.CacheHits_Write : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; hbm_6.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 739; SumSQ.u64 = 2937; Count.u64 = 220; Min.u64 = 0; Max.u64 = 7; - l2cache_34:memlink:data.packet_latency : Accumulator : Sum.u64 = 6082; SumSQ.u64 = 88360; Count.u64 = 769; Min.u64 = 0; Max.u64 = 62; - l2cache_34:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 220; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 989; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 989; Min.u64 = 0; Max.u64 = 0; - l2cache_34:memlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 739; SumSQ.u64 = 2937; Count.u64 = 220; Min.u64 = 0; Max.u64 = 7; + l2cache_34:lowlink:data.packet_latency : Accumulator : Sum.u64 = 6082; SumSQ.u64 = 88360; Count.u64 = 769; Min.u64 = 0; Max.u64 = 62; + l2cache_34:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 220; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 769; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 989; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 989; Min.u64 = 0; Max.u64 = 0; + l2cache_34:lowlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_34.prefetches_issued : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; l2cache_34.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; @@ -25885,8 +27007,11 @@ Model complete l2cache_34.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_34.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25895,6 +27020,9 @@ Model complete l2cache_34.eventSent_GetXResp : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; l2cache_34.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25919,6 +27047,7 @@ Model complete l2cache_34.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.GetSHit_Arrival : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l2cache_34.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -25994,10 +27123,12 @@ Model complete l2cache_34.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.GetSResp_recv : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; l2cache_34.GetXResp_recv : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_34.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26009,6 +27140,9 @@ Model complete l2cache_34.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache_34.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache_34.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_34.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_34.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26081,13 +27215,16 @@ Model complete l1cache_68.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_68.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_68.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_68.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26114,6 +27251,7 @@ Model complete l1cache_68.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.GetSHit_Arrival : Accumulator : Sum.u64 = 754; SumSQ.u64 = 754; Count.u64 = 754; Min.u64 = 1; Max.u64 = 1; l1cache_68.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache_68.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26160,14 +27298,18 @@ Model complete l1cache_68.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_68.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_68.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_68.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache_68.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_68.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_68.MSHR_occupancy : Accumulator : Sum.u64 = 375298; SumSQ.u64 = 6327700; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -26256,13 +27398,16 @@ Model complete l1cache_69.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_FetchXResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache_69.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_69.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_69.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26289,6 +27434,7 @@ Model complete l1cache_69.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.GetSHit_Arrival : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; l1cache_69.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26335,14 +27481,18 @@ Model complete l1cache_69.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_69.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.GetSResp_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l1cache_69.GetXResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; l1cache_69.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.FetchInvX_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache_69.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_69.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_69.MSHR_occupancy : Accumulator : Sum.u64 = 374513; SumSQ.u64 = 6297999; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -26364,17 +27514,17 @@ Model complete core_69.cycles_max_issue : Accumulator : Sum.u64 = 1072; SumSQ.u64 = 1072; Count.u64 = 1072; Min.u64 = 1; Max.u64 = 1; core_69.cycles_max_reorder : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; core_69.cycles : Accumulator : Sum.u64 = 22700; SumSQ.u64 = 22700; Count.u64 = 22700; Min.u64 = 1; Max.u64 = 1; - dc_34:cpulink:req.packet_latency : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 12433; Count.u64 = 873; Min.u64 = 0; Max.u64 = 25; - dc_34:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 408; SumSQ.u64 = 1732; Count.u64 = 103; Min.u64 = 2; Max.u64 = 6; - dc_34:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink:data.packet_latency : Accumulator : Sum.u64 = 3562; SumSQ.u64 = 39248; Count.u64 = 770; Min.u64 = 0; Max.u64 = 54; - dc_34:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1746; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1746; Min.u64 = 0; Max.u64 = 0; - dc_34:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink:req.packet_latency : Accumulator : Sum.u64 = 2833; SumSQ.u64 = 12433; Count.u64 = 873; Min.u64 = 0; Max.u64 = 25; + dc_34:highlink:ack.packet_latency : Accumulator : Sum.u64 = 408; SumSQ.u64 = 1732; Count.u64 = 103; Min.u64 = 2; Max.u64 = 6; + dc_34:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink:data.packet_latency : Accumulator : Sum.u64 = 3562; SumSQ.u64 = 39248; Count.u64 = 770; Min.u64 = 0; Max.u64 = 54; + dc_34:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 873; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 770; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1746; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1746; Min.u64 = 0; Max.u64 = 0; + dc_34:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.get_request_latency : Accumulator : Sum.u64 = 191208; SumSQ.u64 = 379659892; Count.u64 = 873; Min.u64 = 22; Max.u64 = 12582; @@ -26397,8 +27547,10 @@ Model complete dc_34.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_34.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26417,6 +27569,7 @@ Model complete dc_34.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_34.eventSent_FetchInvX : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; dc_34.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.eventSent_GetSResp : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; dc_34.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -26427,6 +27580,8 @@ Model complete dc_34.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_34.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_34.MSHR_occupancy : Accumulator : Sum.u64 = 189462; SumSQ.u64 = 2672052; Count.u64 = 18373; Min.u64 = 0; Max.u64 = 29; @@ -26444,32 +27599,32 @@ Model complete hbm_7.cycles_with_issue : Accumulator : Sum.u64 = 4061; SumSQ.u64 = 4061; Count.u64 = 4061; Min.u64 = 1; Max.u64 = 1; hbm_7.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; hbm_7.total_cycles : Accumulator : Sum.u64 = 13916; SumSQ.u64 = 193655056; Count.u64 = 1; Min.u64 = 13916; Max.u64 = 13916; - hbm_7:cpulink:req.packet_latency : Accumulator : Sum.u64 = 8191; SumSQ.u64 = 38523; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 28; - hbm_7:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_7:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_7:cpulink:data.packet_latency : Accumulator : Sum.u64 = 9969; SumSQ.u64 = 98597; Count.u64 = 2291; Min.u64 = 0; Max.u64 = 83; - hbm_7:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 1; - hbm_7:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_7:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - hbm_7:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2291; Min.u64 = 0; Max.u64 = 0; - hbm_7:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 4588; Min.u64 = 0; Max.u64 = 1; - hbm_7:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 4588; Min.u64 = 0; Max.u64 = 1; - hbm_7:cpulink.ordering_latency : Accumulator : Sum.u64 = 13; SumSQ.u64 = 145; Count.u64 = 3; Min.u64 = 0; Max.u64 = 12; + hbm_7:highlink:req.packet_latency : Accumulator : Sum.u64 = 8191; SumSQ.u64 = 38523; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 28; + hbm_7:highlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_7:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_7:highlink:data.packet_latency : Accumulator : Sum.u64 = 9969; SumSQ.u64 = 98597; Count.u64 = 2291; Min.u64 = 0; Max.u64 = 83; + hbm_7:highlink.outoforder_req_events : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 2297; Min.u64 = 0; Max.u64 = 1; + hbm_7:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_7:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + hbm_7:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 2291; Min.u64 = 0; Max.u64 = 0; + hbm_7:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 4588; Min.u64 = 0; Max.u64 = 1; + hbm_7:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 4588; Min.u64 = 0; Max.u64 = 1; + hbm_7:highlink.ordering_latency : Accumulator : Sum.u64 = 13; SumSQ.u64 = 145; Count.u64 = 3; Min.u64 = 0; Max.u64 = 12; hbm_7.CacheHits_Read : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; hbm_7.CacheMisses_Read : Accumulator : Sum.u64 = 2251; SumSQ.u64 = 2251; Count.u64 = 2251; Min.u64 = 1; Max.u64 = 1; hbm_7.CacheHits_Write : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; hbm_7.CacheMisses_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_35:memlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_35:memlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_35:memlink:fwd.packet_latency : Accumulator : Sum.u64 = 844; SumSQ.u64 = 3806; Count.u64 = 219; Min.u64 = 0; Max.u64 = 8; - l2cache_35:memlink:data.packet_latency : Accumulator : Sum.u64 = 6338; SumSQ.u64 = 101202; Count.u64 = 771; Min.u64 = 0; Max.u64 = 99; - l2cache_35:memlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_35:memlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache_35:memlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 219; Min.u64 = 0; Max.u64 = 1; - l2cache_35:memlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; - l2cache_35:memlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 990; Min.u64 = 0; Max.u64 = 1; - l2cache_35:memlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 990; Min.u64 = 0; Max.u64 = 1; - l2cache_35:memlink.ordering_latency : Accumulator : Sum.u64 = 11; SumSQ.u64 = 121; Count.u64 = 1; Min.u64 = 11; Max.u64 = 11; + l2cache_35:lowlink:req.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35:lowlink:ack.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35:lowlink:fwd.packet_latency : Accumulator : Sum.u64 = 844; SumSQ.u64 = 3806; Count.u64 = 219; Min.u64 = 0; Max.u64 = 8; + l2cache_35:lowlink:data.packet_latency : Accumulator : Sum.u64 = 6338; SumSQ.u64 = 101202; Count.u64 = 771; Min.u64 = 0; Max.u64 = 99; + l2cache_35:lowlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35:lowlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35:lowlink.outoforder_fwd_events : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 219; Min.u64 = 0; Max.u64 = 1; + l2cache_35:lowlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; + l2cache_35:lowlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 990; Min.u64 = 0; Max.u64 = 1; + l2cache_35:lowlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 990; Min.u64 = 0; Max.u64 = 1; + l2cache_35:lowlink.ordering_latency : Accumulator : Sum.u64 = 11; SumSQ.u64 = 121; Count.u64 = 1; Min.u64 = 11; Max.u64 = 11; l2cache_35.prefetch_opportunities : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l2cache_35.prefetches_issued : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; l2cache_35.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; @@ -26585,8 +27740,11 @@ Model complete l2cache_35.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_35.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -26595,6 +27753,9 @@ Model complete l2cache_35.eventSent_GetXResp : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; l2cache_35.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26619,6 +27780,7 @@ Model complete l2cache_35.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.GetSHit_Arrival : Accumulator : Sum.u64 = 516; SumSQ.u64 = 516; Count.u64 = 516; Min.u64 = 1; Max.u64 = 1; l2cache_35.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26694,10 +27856,12 @@ Model complete l2cache_35.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.GetSResp_recv : Accumulator : Sum.u64 = 465; SumSQ.u64 = 465; Count.u64 = 465; Min.u64 = 1; Max.u64 = 1; l2cache_35.GetXResp_recv : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; l2cache_35.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26709,6 +27873,9 @@ Model complete l2cache_35.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache_35.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.FetchXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache_35.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_35.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_35.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26781,13 +27948,16 @@ Model complete l1cache_70.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache_70.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_70.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_70.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26814,6 +27984,7 @@ Model complete l1cache_70.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.GetSHit_Arrival : Accumulator : Sum.u64 = 713; SumSQ.u64 = 713; Count.u64 = 713; Min.u64 = 1; Max.u64 = 1; l1cache_70.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26860,14 +28031,18 @@ Model complete l1cache_70.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_70.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_70.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_70.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache_70.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_70.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_70.MSHR_occupancy : Accumulator : Sum.u64 = 380282; SumSQ.u64 = 6403492; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -26956,13 +28131,16 @@ Model complete l1cache_71.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_GetSResp : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache_71.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_71.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -26989,6 +28167,7 @@ Model complete l1cache_71.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.GetSHit_Arrival : Accumulator : Sum.u64 = 706; SumSQ.u64 = 706; Count.u64 = 706; Min.u64 = 1; Max.u64 = 1; l1cache_71.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -27035,14 +28214,18 @@ Model complete l1cache_71.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache_71.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.GetSResp_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; l1cache_71.GetXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache_71.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_71.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_71.MSHR_occupancy : Accumulator : Sum.u64 = 379927; SumSQ.u64 = 6386585; Count.u64 = 23184; Min.u64 = 0; Max.u64 = 23; @@ -27064,17 +28247,17 @@ Model complete core_71.cycles_max_issue : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; core_71.cycles_max_reorder : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; core_71.cycles : Accumulator : Sum.u64 = 23013; SumSQ.u64 = 23013; Count.u64 = 23013; Min.u64 = 1; Max.u64 = 1; - dc_35:cpulink:req.packet_latency : Accumulator : Sum.u64 = 3200; SumSQ.u64 = 14650; Count.u64 = 874; Min.u64 = 0; Max.u64 = 15; - dc_35:cpulink:ack.packet_latency : Accumulator : Sum.u64 = 450; SumSQ.u64 = 2118; Count.u64 = 103; Min.u64 = 2; Max.u64 = 7; - dc_35:cpulink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink:data.packet_latency : Accumulator : Sum.u64 = 4807; SumSQ.u64 = 107941; Count.u64 = 771; Min.u64 = 0; Max.u64 = 155; - dc_35:cpulink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 874; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; - dc_35:cpulink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink:req.packet_latency : Accumulator : Sum.u64 = 3200; SumSQ.u64 = 14650; Count.u64 = 874; Min.u64 = 0; Max.u64 = 15; + dc_35:highlink:ack.packet_latency : Accumulator : Sum.u64 = 450; SumSQ.u64 = 2118; Count.u64 = 103; Min.u64 = 2; Max.u64 = 7; + dc_35:highlink:fwd.packet_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink:data.packet_latency : Accumulator : Sum.u64 = 4807; SumSQ.u64 = 107941; Count.u64 = 771; Min.u64 = 0; Max.u64 = 155; + dc_35:highlink.outoforder_req_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 874; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink.outoforder_ack_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 103; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink.outoforder_fwd_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink.outoforder_data_events : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 771; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink.outoforder_depth_at_event_receive : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink.outoforder_depth_at_event_receive_src : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 1748; Min.u64 = 0; Max.u64 = 0; + dc_35:highlink.ordering_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.get_request_latency : Accumulator : Sum.u64 = 202856; SumSQ.u64 = 510832656; Count.u64 = 874; Min.u64 = 22; Max.u64 = 13205; @@ -27097,8 +28280,10 @@ Model complete dc_35.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.AckInv_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + dc_35.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -27117,6 +28302,7 @@ Model complete dc_35.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; dc_35.eventSent_FetchInvX : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; dc_35.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.eventSent_GetSResp : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; dc_35.eventSent_GetXResp : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; @@ -27127,6 +28313,8 @@ Model complete dc_35.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dc_35.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dc_35.MSHR_occupancy : Accumulator : Sum.u64 = 201108; SumSQ.u64 = 2945736; Count.u64 = 18395; Min.u64 = 0; Max.u64 = 30; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out index 26e1d1d15b..68eb80dd2d 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_1.out @@ -72,13 +72,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3006; SumSQ.u64 = 3006; Count.u64 = 3006; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -151,22 +155,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.Write_recv : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 14686; SumSQ.u64 = 14686; Count.u64 = 14686; Min.u64 = 1; Max.u64 = 1; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 4968; SumSQ.u64 = 4968; Count.u64 = 4968; Min.u64 = 1; Max.u64 = 1; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 5738898; SumSQ.u64 = 90986354; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 12366; SumSQ.u64 = 15968; Count.u64 = 11163; Min.u64 = 0; Max.u64 = 5; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 1713856; SumSQ.u64 = 685355008; Count.u64 = 11163; Min.u64 = 64; Max.u64 = 576; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 53822606; SumSQ.u64 = 1051385897222; Count.u64 = 8805; Min.u64 = 1; Max.u64 = 124500; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 12366; SumSQ.u64 = 15968; Count.u64 = 11163; Min.u64 = 0; Max.u64 = 5; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 1713856; SumSQ.u64 = 685355008; Count.u64 = 11163; Min.u64 = 64; Max.u64 = 576; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 53822606; SumSQ.u64 = 1051385897222; Count.u64 = 8805; Min.u64 = 1; Max.u64 = 124500; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_I : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -258,6 +266,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -356,10 +369,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutM_recv : Accumulator : Sum.u64 = 1979; SumSQ.u64 = 1979; Count.u64 = 1979; Min.u64 = 1; Max.u64 = 1; l2cache0.PutE_recv : Accumulator : Sum.u64 = 2989; SumSQ.u64 = 2989; Count.u64 = 2989; Min.u64 = 1; Max.u64 = 1; @@ -371,6 +386,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 1259; SumSQ.u64 = 1259; Count.u64 = 1259; Min.u64 = 1; Max.u64 = 1; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 4904; SumSQ.u64 = 4904; Count.u64 = 4904; Min.u64 = 1; Max.u64 = 1; @@ -446,13 +464,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3016; SumSQ.u64 = 3016; Count.u64 = 3016; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1984; SumSQ.u64 = 1984; Count.u64 = 1984; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -479,6 +500,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -525,22 +547,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.Write_recv : Accumulator : Sum.u64 = 1984; SumSQ.u64 = 1984; Count.u64 = 1984; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 14497; SumSQ.u64 = 14497; Count.u64 = 14497; Min.u64 = 1; Max.u64 = 1; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 4968; SumSQ.u64 = 4968; Count.u64 = 4968; Min.u64 = 1; Max.u64 = 1; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 5811907; SumSQ.u64 = 92146663; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 12320; SumSQ.u64 = 16048; Count.u64 = 11099; Min.u64 = 0; Max.u64 = 4; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 1709248; SumSQ.u64 = 684765184; Count.u64 = 11099; Min.u64 = 64; Max.u64 = 576; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 53874453; SumSQ.u64 = 1115021650895; Count.u64 = 8698; Min.u64 = 4; Max.u64 = 135820; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 12320; SumSQ.u64 = 16048; Count.u64 = 11099; Min.u64 = 0; Max.u64 = 4; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 1709248; SumSQ.u64 = 684765184; Count.u64 = 11099; Min.u64 = 64; Max.u64 = 576; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 53874453; SumSQ.u64 = 1115021650895; Count.u64 = 8698; Min.u64 = 4; Max.u64 = 135820; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_I : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -632,6 +658,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -730,10 +761,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutM_recv : Accumulator : Sum.u64 = 1975; SumSQ.u64 = 1975; Count.u64 = 1975; Min.u64 = 1; Max.u64 = 1; l2cache1.PutE_recv : Accumulator : Sum.u64 = 2993; SumSQ.u64 = 2993; Count.u64 = 2993; Min.u64 = 1; Max.u64 = 1; @@ -745,6 +778,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NACK_recv : Accumulator : Sum.u64 = 1195; SumSQ.u64 = 1195; Count.u64 = 1195; Min.u64 = 1; Max.u64 = 1; l2cache1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 4903; SumSQ.u64 = 4903; Count.u64 = 4903; Min.u64 = 1; Max.u64 = 1; @@ -820,13 +856,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 2958; SumSQ.u64 = 2958; Count.u64 = 2958; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -853,6 +892,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -899,22 +939,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.Write_recv : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NACK_recv : Accumulator : Sum.u64 = 14937; SumSQ.u64 = 14937; Count.u64 = 14937; Min.u64 = 1; Max.u64 = 1; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 4967; SumSQ.u64 = 4967; Count.u64 = 4967; Min.u64 = 1; Max.u64 = 1; l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 5912753; SumSQ.u64 = 93801661; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 12362; SumSQ.u64 = 16076; Count.u64 = 11157; Min.u64 = 0; Max.u64 = 5; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 1744192; SumSQ.u64 = 704991232; Count.u64 = 11157; Min.u64 = 64; Max.u64 = 576; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 54562833; SumSQ.u64 = 1082144914153; Count.u64 = 8770; Min.u64 = 1; Max.u64 = 110872; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 12362; SumSQ.u64 = 16076; Count.u64 = 11157; Min.u64 = 0; Max.u64 = 5; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 1744192; SumSQ.u64 = 704991232; Count.u64 = 11157; Min.u64 = 64; Max.u64 = 576; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 54562833; SumSQ.u64 = 1082144914153; Count.u64 = 8770; Min.u64 = 1; Max.u64 = 110872; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_I : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1006,6 +1050,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1104,10 +1153,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutM_recv : Accumulator : Sum.u64 = 2030; SumSQ.u64 = 2030; Count.u64 = 2030; Min.u64 = 1; Max.u64 = 1; l2cache2.PutE_recv : Accumulator : Sum.u64 = 2937; SumSQ.u64 = 2937; Count.u64 = 2937; Min.u64 = 1; Max.u64 = 1; @@ -1119,6 +1170,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NACK_recv : Accumulator : Sum.u64 = 1253; SumSQ.u64 = 1253; Count.u64 = 1253; Min.u64 = 1; Max.u64 = 1; l2cache2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 4902; SumSQ.u64 = 4902; Count.u64 = 4902; Min.u64 = 1; Max.u64 = 1; @@ -1194,13 +1248,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 2975; SumSQ.u64 = 2975; Count.u64 = 2975; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 2025; SumSQ.u64 = 2025; Count.u64 = 2025; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1227,6 +1284,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1273,22 +1331,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.Write_recv : Accumulator : Sum.u64 = 2025; SumSQ.u64 = 2025; Count.u64 = 2025; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NACK_recv : Accumulator : Sum.u64 = 14697; SumSQ.u64 = 14697; Count.u64 = 14697; Min.u64 = 1; Max.u64 = 1; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 4968; SumSQ.u64 = 4968; Count.u64 = 4968; Min.u64 = 1; Max.u64 = 1; l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 5893124; SumSQ.u64 = 93465516; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 12470; SumSQ.u64 = 16320; Count.u64 = 11190; Min.u64 = 0; Max.u64 = 5; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 1734528; SumSQ.u64 = 697589760; Count.u64 = 11190; Min.u64 = 64; Max.u64 = 576; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 54697718; SumSQ.u64 = 1089454198252; Count.u64 = 8782; Min.u64 = 4; Max.u64 = 120883; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 12470; SumSQ.u64 = 16320; Count.u64 = 11190; Min.u64 = 0; Max.u64 = 5; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 1734528; SumSQ.u64 = 697589760; Count.u64 = 11190; Min.u64 = 64; Max.u64 = 576; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 54697718; SumSQ.u64 = 1089454198252; Count.u64 = 8782; Min.u64 = 4; Max.u64 = 120883; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_I : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1380,6 +1442,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1478,10 +1545,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutM_recv : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; l2cache3.PutE_recv : Accumulator : Sum.u64 = 2953; SumSQ.u64 = 2953; Count.u64 = 2953; Min.u64 = 1; Max.u64 = 1; @@ -1493,6 +1562,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NACK_recv : Accumulator : Sum.u64 = 1286; SumSQ.u64 = 1286; Count.u64 = 1286; Min.u64 = 1; Max.u64 = 1; l2cache3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 4904; SumSQ.u64 = 4904; Count.u64 = 4904; Min.u64 = 1; Max.u64 = 1; @@ -1568,13 +1640,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 2968; SumSQ.u64 = 2968; Count.u64 = 2968; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 2032; SumSQ.u64 = 2032; Count.u64 = 2032; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1601,6 +1676,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1647,22 +1723,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.Write_recv : Accumulator : Sum.u64 = 2032; SumSQ.u64 = 2032; Count.u64 = 2032; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NACK_recv : Accumulator : Sum.u64 = 15106; SumSQ.u64 = 15106; Count.u64 = 15106; Min.u64 = 1; Max.u64 = 1; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 4967; SumSQ.u64 = 4967; Count.u64 = 4967; Min.u64 = 1; Max.u64 = 1; l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 5813177; SumSQ.u64 = 92171275; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 12431; SumSQ.u64 = 16225; Count.u64 = 11189; Min.u64 = 0; Max.u64 = 4; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 1733952; SumSQ.u64 = 697257984; Count.u64 = 11189; Min.u64 = 64; Max.u64 = 576; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 54004768; SumSQ.u64 = 1048783133606; Count.u64 = 8770; Min.u64 = 1; Max.u64 = 108654; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 12431; SumSQ.u64 = 16225; Count.u64 = 11189; Min.u64 = 0; Max.u64 = 4; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 1733952; SumSQ.u64 = 697257984; Count.u64 = 11189; Min.u64 = 64; Max.u64 = 576; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 54004768; SumSQ.u64 = 1048783133606; Count.u64 = 8770; Min.u64 = 1; Max.u64 = 108654; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_I : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1754,6 +1834,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache4.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1852,10 +1937,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutM_recv : Accumulator : Sum.u64 = 2016; SumSQ.u64 = 2016; Count.u64 = 2016; Min.u64 = 1; Max.u64 = 1; l2cache4.PutE_recv : Accumulator : Sum.u64 = 2951; SumSQ.u64 = 2951; Count.u64 = 2951; Min.u64 = 1; Max.u64 = 1; @@ -1867,6 +1954,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NACK_recv : Accumulator : Sum.u64 = 1285; SumSQ.u64 = 1285; Count.u64 = 1285; Min.u64 = 1; Max.u64 = 1; l2cache4.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 4902; SumSQ.u64 = 4902; Count.u64 = 4902; Min.u64 = 1; Max.u64 = 1; @@ -1942,13 +2032,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 2989; SumSQ.u64 = 2989; Count.u64 = 2989; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1975,6 +2068,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2021,22 +2115,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.Write_recv : Accumulator : Sum.u64 = 2011; SumSQ.u64 = 2011; Count.u64 = 2011; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NACK_recv : Accumulator : Sum.u64 = 14987; SumSQ.u64 = 14987; Count.u64 = 14987; Min.u64 = 1; Max.u64 = 1; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 4968; SumSQ.u64 = 4968; Count.u64 = 4968; Min.u64 = 1; Max.u64 = 1; l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 5884564; SumSQ.u64 = 93339914; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 12407; SumSQ.u64 = 16285; Count.u64 = 11148; Min.u64 = 0; Max.u64 = 5; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 1724672; SumSQ.u64 = 692830208; Count.u64 = 11148; Min.u64 = 64; Max.u64 = 576; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 54004483; SumSQ.u64 = 1041728520003; Count.u64 = 8808; Min.u64 = 7; Max.u64 = 129087; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 12407; SumSQ.u64 = 16285; Count.u64 = 11148; Min.u64 = 0; Max.u64 = 5; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 1724672; SumSQ.u64 = 692830208; Count.u64 = 11148; Min.u64 = 64; Max.u64 = 576; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 54004483; SumSQ.u64 = 1041728520003; Count.u64 = 8808; Min.u64 = 7; Max.u64 = 129087; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_I : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2128,6 +2226,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache5.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2226,10 +2329,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.PutM_recv : Accumulator : Sum.u64 = 1999; SumSQ.u64 = 1999; Count.u64 = 1999; Min.u64 = 1; Max.u64 = 1; l2cache5.PutE_recv : Accumulator : Sum.u64 = 2969; SumSQ.u64 = 2969; Count.u64 = 2969; Min.u64 = 1; Max.u64 = 1; @@ -2241,6 +2346,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NACK_recv : Accumulator : Sum.u64 = 1244; SumSQ.u64 = 1244; Count.u64 = 1244; Min.u64 = 1; Max.u64 = 1; l2cache5.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 4904; SumSQ.u64 = 4904; Count.u64 = 4904; Min.u64 = 1; Max.u64 = 1; @@ -2316,13 +2424,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_GetSResp : Accumulator : Sum.u64 = 3014; SumSQ.u64 = 3014; Count.u64 = 3014; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_WriteResp : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2349,6 +2460,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2395,22 +2507,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.Write_recv : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.NACK_recv : Accumulator : Sum.u64 = 14135; SumSQ.u64 = 14135; Count.u64 = 14135; Min.u64 = 1; Max.u64 = 1; l1cache6.AckPut_recv : Accumulator : Sum.u64 = 4968; SumSQ.u64 = 4968; Count.u64 = 4968; Min.u64 = 1; Max.u64 = 1; l1cache6.MSHR_occupancy : Accumulator : Sum.u64 = 5839886; SumSQ.u64 = 92561552; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache6.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache6:memlink.packet_latency : Accumulator : Sum.u64 = 12507; SumSQ.u64 = 16329; Count.u64 = 11214; Min.u64 = 0; Max.u64 = 4; - l2cache6:memlink.send_bit_count : Accumulator : Sum.u64 = 1713536; SumSQ.u64 = 683270144; Count.u64 = 11214; Min.u64 = 64; Max.u64 = 576; - l2cache6:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache6:memlink.idle_time : Accumulator : Sum.u64 = 54612759; SumSQ.u64 = 1067965608905; Count.u64 = 8904; Min.u64 = 4; Max.u64 = 147904; + l2cache6:lowlink.packet_latency : Accumulator : Sum.u64 = 12507; SumSQ.u64 = 16329; Count.u64 = 11214; Min.u64 = 0; Max.u64 = 4; + l2cache6:lowlink.send_bit_count : Accumulator : Sum.u64 = 1713536; SumSQ.u64 = 683270144; Count.u64 = 11214; Min.u64 = 64; Max.u64 = 576; + l2cache6:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6:lowlink.idle_time : Accumulator : Sum.u64 = 54612759; SumSQ.u64 = 1067965608905; Count.u64 = 8904; Min.u64 = 4; Max.u64 = 147904; l2cache6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.evict_I : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache6.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2502,6 +2618,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache6.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2600,10 +2721,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache6.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache6.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.PutM_recv : Accumulator : Sum.u64 = 1975; SumSQ.u64 = 1975; Count.u64 = 1975; Min.u64 = 1; Max.u64 = 1; l2cache6.PutE_recv : Accumulator : Sum.u64 = 2993; SumSQ.u64 = 2993; Count.u64 = 2993; Min.u64 = 1; Max.u64 = 1; @@ -2615,6 +2738,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.NACK_recv : Accumulator : Sum.u64 = 1310; SumSQ.u64 = 1310; Count.u64 = 1310; Min.u64 = 1; Max.u64 = 1; l2cache6.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.AckPut_recv : Accumulator : Sum.u64 = 4904; SumSQ.u64 = 4904; Count.u64 = 4904; Min.u64 = 1; Max.u64 = 1; @@ -2690,13 +2816,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_GetSResp : Accumulator : Sum.u64 = 2980; SumSQ.u64 = 2980; Count.u64 = 2980; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_WriteResp : Accumulator : Sum.u64 = 2020; SumSQ.u64 = 2020; Count.u64 = 2020; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2723,6 +2852,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2769,22 +2899,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.Write_recv : Accumulator : Sum.u64 = 2020; SumSQ.u64 = 2020; Count.u64 = 2020; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.NACK_recv : Accumulator : Sum.u64 = 14394; SumSQ.u64 = 14394; Count.u64 = 14394; Min.u64 = 1; Max.u64 = 1; l1cache7.AckPut_recv : Accumulator : Sum.u64 = 4968; SumSQ.u64 = 4968; Count.u64 = 4968; Min.u64 = 1; Max.u64 = 1; l1cache7.MSHR_occupancy : Accumulator : Sum.u64 = 5880706; SumSQ.u64 = 93266632; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 16; l1cache7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache7:memlink.packet_latency : Accumulator : Sum.u64 = 12387; SumSQ.u64 = 16021; Count.u64 = 11220; Min.u64 = 0; Max.u64 = 5; - l2cache7:memlink.send_bit_count : Accumulator : Sum.u64 = 1732864; SumSQ.u64 = 695418880; Count.u64 = 11220; Min.u64 = 64; Max.u64 = 576; - l2cache7:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache7:memlink.idle_time : Accumulator : Sum.u64 = 54723803; SumSQ.u64 = 1096352844707; Count.u64 = 8808; Min.u64 = 1; Max.u64 = 109726; + l2cache7:lowlink.packet_latency : Accumulator : Sum.u64 = 12387; SumSQ.u64 = 16021; Count.u64 = 11220; Min.u64 = 0; Max.u64 = 5; + l2cache7:lowlink.send_bit_count : Accumulator : Sum.u64 = 1732864; SumSQ.u64 = 695418880; Count.u64 = 11220; Min.u64 = 64; Max.u64 = 576; + l2cache7:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7:lowlink.idle_time : Accumulator : Sum.u64 = 54723803; SumSQ.u64 = 1096352844707; Count.u64 = 8808; Min.u64 = 1; Max.u64 = 109726; l2cache7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.evict_I : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache7.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2876,6 +3010,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache7.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_FetchResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache7.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2974,10 +3113,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache7.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.GetXResp_recv : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; l2cache7.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.PutM_recv : Accumulator : Sum.u64 = 2006; SumSQ.u64 = 2006; Count.u64 = 2006; Min.u64 = 1; Max.u64 = 1; l2cache7.PutE_recv : Accumulator : Sum.u64 = 2962; SumSQ.u64 = 2962; Count.u64 = 2962; Min.u64 = 1; Max.u64 = 1; @@ -2989,16 +3130,19 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache7.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.NACK_recv : Accumulator : Sum.u64 = 1316; SumSQ.u64 = 1316; Count.u64 = 1316; Min.u64 = 1; Max.u64 = 1; l2cache7.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.AckPut_recv : Accumulator : Sum.u64 = 4903; SumSQ.u64 = 4903; Count.u64 = 4903; Min.u64 = 1; Max.u64 = 1; l2cache7.MSHR_occupancy : Accumulator : Sum.u64 = 969636; SumSQ.u64 = 2688800; Count.u64 = 373483; Min.u64 = 0; Max.u64 = 3; l2cache7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 36469; SumSQ.u64 = 52181; Count.u64 = 32077; Min.u64 = 0; Max.u64 = 9; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 9106752; SumSQ.u64 = 4645834752; Count.u64 = 32077; Min.u64 = 64; Max.u64 = 576; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 83401938; SumSQ.u64 = 1025056321748; Count.u64 = 20385; Min.u64 = 4; Max.u64 = 205796; - l3cache0.default_stat : Accumulator : Sum.u64 = 9671; SumSQ.u64 = 9671; Count.u64 = 9671; Min.u64 = 1; Max.u64 = 1; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 36469; SumSQ.u64 = 52181; Count.u64 = 32077; Min.u64 = 0; Max.u64 = 9; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 9106752; SumSQ.u64 = 4645834752; Count.u64 = 32077; Min.u64 = 64; Max.u64 = 576; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 83401938; SumSQ.u64 = 1025056321748; Count.u64 = 20385; Min.u64 = 4; Max.u64 = 205796; + l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_I : Accumulator : Sum.u64 = 9830; SumSQ.u64 = 9830; Count.u64 = 9830; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3107,8 +3251,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 9671; SumSQ.u64 = 9671; Count.u64 = 9671; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3117,6 +3264,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 9864; SumSQ.u64 = 9864; Count.u64 = 9864; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3141,6 +3291,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3211,10 +3362,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 9851; SumSQ.u64 = 9851; Count.u64 = 9851; Min.u64 = 1; Max.u64 = 1; l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutM_recv : Accumulator : Sum.u64 = 3904; SumSQ.u64 = 3904; Count.u64 = 3904; Min.u64 = 1; Max.u64 = 1; l3cache0.PutE_recv : Accumulator : Sum.u64 = 5767; SumSQ.u64 = 5767; Count.u64 = 5767; Min.u64 = 1; Max.u64 = 1; @@ -3226,16 +3379,19 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 872238; SumSQ.u64 = 4442606; Count.u64 = 218126; Min.u64 = 0; Max.u64 = 7; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 35952; SumSQ.u64 = 50646; Count.u64 = 31974; Min.u64 = 0; Max.u64 = 6; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 9212288; SumSQ.u64 = 4717174784; Count.u64 = 31974; Min.u64 = 64; Max.u64 = 576; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 83267670; SumSQ.u64 = 1075443789252; Count.u64 = 20501; Min.u64 = 4; Max.u64 = 300532; - l3cache1.default_stat : Accumulator : Sum.u64 = 9808; SumSQ.u64 = 9808; Count.u64 = 9808; Min.u64 = 1; Max.u64 = 1; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 35952; SumSQ.u64 = 50646; Count.u64 = 31974; Min.u64 = 0; Max.u64 = 6; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 9212288; SumSQ.u64 = 4717174784; Count.u64 = 31974; Min.u64 = 64; Max.u64 = 576; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 83267670; SumSQ.u64 = 1075443789252; Count.u64 = 20501; Min.u64 = 4; Max.u64 = 300532; + l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_I : Accumulator : Sum.u64 = 9986; SumSQ.u64 = 9986; Count.u64 = 9986; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3344,8 +3500,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 9808; SumSQ.u64 = 9808; Count.u64 = 9808; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3354,6 +3513,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 10002; SumSQ.u64 = 10002; Count.u64 = 10002; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3378,6 +3540,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3448,10 +3611,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 9994; SumSQ.u64 = 9994; Count.u64 = 9994; Min.u64 = 1; Max.u64 = 1; l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutM_recv : Accumulator : Sum.u64 = 3989; SumSQ.u64 = 3989; Count.u64 = 3989; Min.u64 = 1; Max.u64 = 1; l3cache1.PutE_recv : Accumulator : Sum.u64 = 5819; SumSQ.u64 = 5819; Count.u64 = 5819; Min.u64 = 1; Max.u64 = 1; @@ -3463,16 +3628,19 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 837722; SumSQ.u64 = 4135910; Count.u64 = 218126; Min.u64 = 0; Max.u64 = 7; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 37239; SumSQ.u64 = 53021; Count.u64 = 32834; Min.u64 = 0; Max.u64 = 6; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 9280640; SumSQ.u64 = 4729217024; Count.u64 = 32834; Min.u64 = 64; Max.u64 = 576; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 82729756; SumSQ.u64 = 1248813809200; Count.u64 = 20711; Min.u64 = 4; Max.u64 = 587786; - l3cache2.default_stat : Accumulator : Sum.u64 = 9849; SumSQ.u64 = 9849; Count.u64 = 9849; Min.u64 = 1; Max.u64 = 1; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 37239; SumSQ.u64 = 53021; Count.u64 = 32834; Min.u64 = 0; Max.u64 = 6; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 9280640; SumSQ.u64 = 4729217024; Count.u64 = 32834; Min.u64 = 64; Max.u64 = 576; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 82729756; SumSQ.u64 = 1248813809200; Count.u64 = 20711; Min.u64 = 4; Max.u64 = 587786; + l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_I : Accumulator : Sum.u64 = 10023; SumSQ.u64 = 10023; Count.u64 = 10023; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3581,8 +3749,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 9849; SumSQ.u64 = 9849; Count.u64 = 9849; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3591,6 +3762,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 10043; SumSQ.u64 = 10043; Count.u64 = 10043; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3615,6 +3789,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3685,10 +3860,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 10030; SumSQ.u64 = 10030; Count.u64 = 10030; Min.u64 = 1; Max.u64 = 1; l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutM_recv : Accumulator : Sum.u64 = 3974; SumSQ.u64 = 3974; Count.u64 = 3974; Min.u64 = 1; Max.u64 = 1; l3cache2.PutE_recv : Accumulator : Sum.u64 = 5875; SumSQ.u64 = 5875; Count.u64 = 5875; Min.u64 = 1; Max.u64 = 1; @@ -3700,16 +3877,19 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 889304; SumSQ.u64 = 4574328; Count.u64 = 218126; Min.u64 = 0; Max.u64 = 7; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache3:cpulink.packet_latency : Accumulator : Sum.u64 = 36796; SumSQ.u64 = 52268; Count.u64 = 32506; Min.u64 = 0; Max.u64 = 7; - l3cache3:cpulink.send_bit_count : Accumulator : Sum.u64 = 9255040; SumSQ.u64 = 4724924416; Count.u64 = 32506; Min.u64 = 64; Max.u64 = 576; - l3cache3:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache3:cpulink.idle_time : Accumulator : Sum.u64 = 83369306; SumSQ.u64 = 1116927906220; Count.u64 = 20581; Min.u64 = 4; Max.u64 = 343598; - l3cache3.default_stat : Accumulator : Sum.u64 = 9898; SumSQ.u64 = 9898; Count.u64 = 9898; Min.u64 = 1; Max.u64 = 1; + l3cache3:highlink.packet_latency : Accumulator : Sum.u64 = 36796; SumSQ.u64 = 52268; Count.u64 = 32506; Min.u64 = 0; Max.u64 = 7; + l3cache3:highlink.send_bit_count : Accumulator : Sum.u64 = 9255040; SumSQ.u64 = 4724924416; Count.u64 = 32506; Min.u64 = 64; Max.u64 = 576; + l3cache3:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3:highlink.idle_time : Accumulator : Sum.u64 = 83369306; SumSQ.u64 = 1116927906220; Count.u64 = 20581; Min.u64 = 4; Max.u64 = 343598; + l3cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.evict_I : Accumulator : Sum.u64 = 10067; SumSQ.u64 = 10067; Count.u64 = 10067; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3818,8 +3998,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_AckPut : Accumulator : Sum.u64 = 9898; SumSQ.u64 = 9898; Count.u64 = 9898; Min.u64 = 1; Max.u64 = 1; l3cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3828,6 +4011,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 10091; SumSQ.u64 = 10091; Count.u64 = 10091; Min.u64 = 1; Max.u64 = 1; l3cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3852,6 +4038,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l3cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l3cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3922,10 +4109,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.GetXResp_recv : Accumulator : Sum.u64 = 10081; SumSQ.u64 = 10081; Count.u64 = 10081; Min.u64 = 1; Max.u64 = 1; l3cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.PutM_recv : Accumulator : Sum.u64 = 3921; SumSQ.u64 = 3921; Count.u64 = 3921; Min.u64 = 1; Max.u64 = 1; l3cache3.PutE_recv : Accumulator : Sum.u64 = 5977; SumSQ.u64 = 5977; Count.u64 = 5977; Min.u64 = 1; Max.u64 = 1; @@ -3937,15 +4126,18 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FetchResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.AckPut_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l3cache3.MSHR_occupancy : Accumulator : Sum.u64 = 847270; SumSQ.u64 = 4233004; Count.u64 = 218126; Min.u64 = 0; Max.u64 = 7; l3cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 20692; SumSQ.u64 = 25744; Count.u64 = 19911; Min.u64 = 0; Max.u64 = 5; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 11460544; SumSQ.u64 = 6600749056; Count.u64 = 19911; Min.u64 = 64; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 61626670; SumSQ.u64 = 758097137268; Count.u64 = 8273; Min.u64 = 10; Max.u64 = 209366; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 20692; SumSQ.u64 = 25744; Count.u64 = 19911; Min.u64 = 0; Max.u64 = 5; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 11460544; SumSQ.u64 = 6600749056; Count.u64 = 19911; Min.u64 = 64; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 61626670; SumSQ.u64 = 758097137268; Count.u64 = 8273; Min.u64 = 10; Max.u64 = 209366; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 60; SumSQ.u64 = 120; Count.u64 = 30; Min.u64 = 2; Max.u64 = 2; directory0.get_request_latency : Accumulator : Sum.u64 = 1529478; SumSQ.u64 = 143767674; Count.u64 = 19881; Min.u64 = 21; Max.u64 = 255; @@ -3968,8 +4160,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3988,6 +4182,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 19881; SumSQ.u64 = 19881; Count.u64 = 19881; Min.u64 = 1; Max.u64 = 1; @@ -3998,6 +4193,8 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 1489716; SumSQ.u64 = 12587956; Count.u64 = 217831; Min.u64 = 0; Max.u64 = 14; @@ -4018,10 +4215,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t memory0.cycles_with_issue : Accumulator : Sum.u64 = 9102; SumSQ.u64 = 9102; Count.u64 = 9102; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 60235; SumSQ.u64 = 60235; Count.u64 = 60235; Min.u64 = 1; Max.u64 = 1; memory0.total_cycles : Accumulator : Sum.u64 = 77871; SumSQ.u64 = 6063892641; Count.u64 = 1; Min.u64 = 77871; Max.u64 = 77871; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 20983; SumSQ.u64 = 26165; Count.u64 = 20100; Min.u64 = 0; Max.u64 = 3; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 11567872; SumSQ.u64 = 6662471680; Count.u64 = 20100; Min.u64 = 64; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 62125726; SumSQ.u64 = 814233814196; Count.u64 = 8376; Min.u64 = 4; Max.u64 = 288568; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 20983; SumSQ.u64 = 26165; Count.u64 = 20100; Min.u64 = 0; Max.u64 = 3; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 11567872; SumSQ.u64 = 6662471680; Count.u64 = 20100; Min.u64 = 64; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 62125726; SumSQ.u64 = 814233814196; Count.u64 = 8376; Min.u64 = 4; Max.u64 = 288568; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 50; SumSQ.u64 = 100; Count.u64 = 25; Min.u64 = 2; Max.u64 = 2; directory1.get_request_latency : Accumulator : Sum.u64 = 1450574; SumSQ.u64 = 128080176; Count.u64 = 20075; Min.u64 = 21; Max.u64 = 217; @@ -4044,8 +4241,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4064,6 +4263,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 20075; SumSQ.u64 = 20075; Count.u64 = 20075; Min.u64 = 1; Max.u64 = 1; @@ -4074,6 +4274,8 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 1410424; SumSQ.u64 = 11467416; Count.u64 = 218114; Min.u64 = 0; Max.u64 = 14; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out index 8e217b0e71..1a8f178e08 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_Noninclusive_2.out @@ -72,13 +72,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3015; SumSQ.u64 = 3015; Count.u64 = 3015; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1985; SumSQ.u64 = 1985; Count.u64 = 1985; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -151,22 +155,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache0.Write_recv : Accumulator : Sum.u64 = 1985; SumSQ.u64 = 1985; Count.u64 = 1985; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 4972; SumSQ.u64 = 4972; Count.u64 = 4972; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 16439; SumSQ.u64 = 16439; Count.u64 = 16439; Min.u64 = 1; Max.u64 = 1; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 4758; SumSQ.u64 = 4758; Count.u64 = 4758; Min.u64 = 1; Max.u64 = 1; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 9833954; SumSQ.u64 = 156497206; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 17660; SumSQ.u64 = 23366; Count.u64 = 15611; Min.u64 = 0; Max.u64 = 5; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 5421568; SumSQ.u64 = 2894725120; Count.u64 = 15600; Min.u64 = 64; Max.u64 = 576; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 97365517; SumSQ.u64 = 3627728750711; Count.u64 = 14343; Min.u64 = 1; Max.u64 = 721569; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 17660; SumSQ.u64 = 23366; Count.u64 = 15611; Min.u64 = 0; Max.u64 = 5; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 5421568; SumSQ.u64 = 2894725120; Count.u64 = 15600; Min.u64 = 64; Max.u64 = 576; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 97365517; SumSQ.u64 = 3627728750711; Count.u64 = 14343; Min.u64 = 1; Max.u64 = 721569; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_I : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -258,6 +266,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; @@ -356,10 +369,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 4972; SumSQ.u64 = 4972; Count.u64 = 4972; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache0.PutM_recv : Accumulator : Sum.u64 = 1879; SumSQ.u64 = 1879; Count.u64 = 1879; Min.u64 = 1; Max.u64 = 1; l2cache0.PutE_recv : Accumulator : Sum.u64 = 2874; SumSQ.u64 = 2874; Count.u64 = 2874; Min.u64 = 1; Max.u64 = 1; @@ -371,6 +386,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 5694; SumSQ.u64 = 5694; Count.u64 = 5694; Min.u64 = 1; Max.u64 = 1; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 4344; SumSQ.u64 = 4344; Count.u64 = 4344; Min.u64 = 1; Max.u64 = 1; @@ -446,13 +464,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3055; SumSQ.u64 = 3055; Count.u64 = 3055; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1945; SumSQ.u64 = 1945; Count.u64 = 1945; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -479,6 +500,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -525,22 +547,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache1.Write_recv : Accumulator : Sum.u64 = 1945; SumSQ.u64 = 1945; Count.u64 = 1945; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 4978; SumSQ.u64 = 4978; Count.u64 = 4978; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 15745; SumSQ.u64 = 15745; Count.u64 = 15745; Min.u64 = 1; Max.u64 = 1; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 4779; SumSQ.u64 = 4779; Count.u64 = 4779; Min.u64 = 1; Max.u64 = 1; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 9758546; SumSQ.u64 = 155264906; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 17970; SumSQ.u64 = 23804; Count.u64 = 16054; Min.u64 = 0; Max.u64 = 6; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 5602176; SumSQ.u64 = 2993872896; Count.u64 = 16046; Min.u64 = 64; Max.u64 = 576; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 94955348; SumSQ.u64 = 5984990414992; Count.u64 = 14619; Min.u64 = 1; Max.u64 = 1808271; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 17970; SumSQ.u64 = 23804; Count.u64 = 16054; Min.u64 = 0; Max.u64 = 6; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 5602176; SumSQ.u64 = 2993872896; Count.u64 = 16046; Min.u64 = 64; Max.u64 = 576; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 94955348; SumSQ.u64 = 5984990414992; Count.u64 = 14619; Min.u64 = 1; Max.u64 = 1808271; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_I : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -632,6 +658,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; @@ -730,10 +761,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 4978; SumSQ.u64 = 4978; Count.u64 = 4978; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutS_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache1.PutM_recv : Accumulator : Sum.u64 = 1861; SumSQ.u64 = 1861; Count.u64 = 1861; Min.u64 = 1; Max.u64 = 1; l2cache1.PutE_recv : Accumulator : Sum.u64 = 2916; SumSQ.u64 = 2916; Count.u64 = 2916; Min.u64 = 1; Max.u64 = 1; @@ -745,6 +778,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NACK_recv : Accumulator : Sum.u64 = 6138; SumSQ.u64 = 6138; Count.u64 = 6138; Min.u64 = 1; Max.u64 = 1; l2cache1.AckInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 4425; SumSQ.u64 = 4425; Count.u64 = 4425; Min.u64 = 1; Max.u64 = 1; @@ -820,13 +856,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 3002; SumSQ.u64 = 3002; Count.u64 = 3002; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -853,6 +892,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -899,22 +939,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache2.Write_recv : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 4966; SumSQ.u64 = 4966; Count.u64 = 4966; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Inv_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NACK_recv : Accumulator : Sum.u64 = 16154; SumSQ.u64 = 16154; Count.u64 = 16154; Min.u64 = 1; Max.u64 = 1; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 4739; SumSQ.u64 = 4739; Count.u64 = 4739; Min.u64 = 1; Max.u64 = 1; l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 9760072; SumSQ.u64 = 155259842; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 17898; SumSQ.u64 = 23548; Count.u64 = 15984; Min.u64 = 0; Max.u64 = 5; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 5657664; SumSQ.u64 = 3031928832; Count.u64 = 15977; Min.u64 = 64; Max.u64 = 576; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 97136257; SumSQ.u64 = 5549977571987; Count.u64 = 14540; Min.u64 = 1; Max.u64 = 1555569; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 17898; SumSQ.u64 = 23548; Count.u64 = 15984; Min.u64 = 0; Max.u64 = 5; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 5657664; SumSQ.u64 = 3031928832; Count.u64 = 15977; Min.u64 = 64; Max.u64 = 576; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 97136257; SumSQ.u64 = 5549977571987; Count.u64 = 14540; Min.u64 = 1; Max.u64 = 1555569; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_I : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -1006,6 +1050,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; @@ -1104,10 +1153,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 4966; SumSQ.u64 = 4966; Count.u64 = 4966; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutS_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache2.PutM_recv : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; l2cache2.PutE_recv : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; @@ -1119,6 +1170,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NACK_recv : Accumulator : Sum.u64 = 6066; SumSQ.u64 = 6066; Count.u64 = 6066; Min.u64 = 1; Max.u64 = 1; l2cache2.AckInv_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 4368; SumSQ.u64 = 4368; Count.u64 = 4368; Min.u64 = 1; Max.u64 = 1; @@ -1194,13 +1248,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 3026; SumSQ.u64 = 3026; Count.u64 = 3026; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1227,6 +1284,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1273,22 +1331,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache3.Write_recv : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 4983; SumSQ.u64 = 4983; Count.u64 = 4983; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Inv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NACK_recv : Accumulator : Sum.u64 = 15905; SumSQ.u64 = 15905; Count.u64 = 15905; Min.u64 = 1; Max.u64 = 1; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 4803; SumSQ.u64 = 4803; Count.u64 = 4803; Min.u64 = 1; Max.u64 = 1; l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 9849364; SumSQ.u64 = 156763680; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 18216; SumSQ.u64 = 24070; Count.u64 = 16191; Min.u64 = 0; Max.u64 = 5; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 5693952; SumSQ.u64 = 3047522304; Count.u64 = 16184; Min.u64 = 64; Max.u64 = 576; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 95106303; SumSQ.u64 = 2794007110495; Count.u64 = 14858; Min.u64 = 1; Max.u64 = 212599; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 18216; SumSQ.u64 = 24070; Count.u64 = 16191; Min.u64 = 0; Max.u64 = 5; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 5693952; SumSQ.u64 = 3047522304; Count.u64 = 16184; Min.u64 = 64; Max.u64 = 576; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 95106303; SumSQ.u64 = 2794007110495; Count.u64 = 14858; Min.u64 = 1; Max.u64 = 212599; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_I : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1380,6 +1442,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; @@ -1478,10 +1545,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 4983; SumSQ.u64 = 4983; Count.u64 = 4983; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutS_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache3.PutM_recv : Accumulator : Sum.u64 = 1883; SumSQ.u64 = 1883; Count.u64 = 1883; Min.u64 = 1; Max.u64 = 1; l2cache3.PutE_recv : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 2919; Count.u64 = 2919; Min.u64 = 1; Max.u64 = 1; @@ -1493,6 +1562,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NACK_recv : Accumulator : Sum.u64 = 6279; SumSQ.u64 = 6279; Count.u64 = 6279; Min.u64 = 1; Max.u64 = 1; l2cache3.AckInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 4432; SumSQ.u64 = 4432; Count.u64 = 4432; Min.u64 = 1; Max.u64 = 1; @@ -1568,13 +1640,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 3035; SumSQ.u64 = 3035; Count.u64 = 3035; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1601,6 +1676,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1647,22 +1723,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache4.Write_recv : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 4979; SumSQ.u64 = 4979; Count.u64 = 4979; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NACK_recv : Accumulator : Sum.u64 = 16243; SumSQ.u64 = 16243; Count.u64 = 16243; Min.u64 = 1; Max.u64 = 1; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 4800; SumSQ.u64 = 4800; Count.u64 = 4800; Min.u64 = 1; Max.u64 = 1; l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 9840865; SumSQ.u64 = 156627969; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 18089; SumSQ.u64 = 23923; Count.u64 = 16018; Min.u64 = 0; Max.u64 = 5; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 5643584; SumSQ.u64 = 3021590528; Count.u64 = 16013; Min.u64 = 64; Max.u64 = 576; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 95546910; SumSQ.u64 = 3615337432564; Count.u64 = 14535; Min.u64 = 1; Max.u64 = 831058; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 18089; SumSQ.u64 = 23923; Count.u64 = 16018; Min.u64 = 0; Max.u64 = 5; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 5643584; SumSQ.u64 = 3021590528; Count.u64 = 16013; Min.u64 = 64; Max.u64 = 576; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 95546910; SumSQ.u64 = 3615337432564; Count.u64 = 14535; Min.u64 = 1; Max.u64 = 831058; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_I : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1754,6 +1834,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache4.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; @@ -1852,10 +1937,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 4979; SumSQ.u64 = 4979; Count.u64 = 4979; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutS_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.PutM_recv : Accumulator : Sum.u64 = 1885; SumSQ.u64 = 1885; Count.u64 = 1885; Min.u64 = 1; Max.u64 = 1; l2cache4.PutE_recv : Accumulator : Sum.u64 = 2914; SumSQ.u64 = 2914; Count.u64 = 2914; Min.u64 = 1; Max.u64 = 1; @@ -1867,6 +1954,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NACK_recv : Accumulator : Sum.u64 = 6106; SumSQ.u64 = 6106; Count.u64 = 6106; Min.u64 = 1; Max.u64 = 1; l2cache4.AckInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 4416; SumSQ.u64 = 4416; Count.u64 = 4416; Min.u64 = 1; Max.u64 = 1; @@ -1942,13 +2032,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 3048; SumSQ.u64 = 3048; Count.u64 = 3048; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 1952; SumSQ.u64 = 1952; Count.u64 = 1952; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1975,6 +2068,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2021,22 +2115,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache5.Write_recv : Accumulator : Sum.u64 = 1952; SumSQ.u64 = 1952; Count.u64 = 1952; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 4977; SumSQ.u64 = 4977; Count.u64 = 4977; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Inv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NACK_recv : Accumulator : Sum.u64 = 16185; SumSQ.u64 = 16185; Count.u64 = 16185; Min.u64 = 1; Max.u64 = 1; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 4746; SumSQ.u64 = 4746; Count.u64 = 4746; Min.u64 = 1; Max.u64 = 1; l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 9549334; SumSQ.u64 = 151864028; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 17408; SumSQ.u64 = 23114; Count.u64 = 15456; Min.u64 = 0; Max.u64 = 6; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 5375040; SumSQ.u64 = 2870513664; Count.u64 = 15449; Min.u64 = 64; Max.u64 = 576; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 104006546; SumSQ.u64 = 11161348544326; Count.u64 = 14146; Min.u64 = 1; Max.u64 = 1728624; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 17408; SumSQ.u64 = 23114; Count.u64 = 15456; Min.u64 = 0; Max.u64 = 6; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 5375040; SumSQ.u64 = 2870513664; Count.u64 = 15449; Min.u64 = 64; Max.u64 = 576; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 104006546; SumSQ.u64 = 11161348544326; Count.u64 = 14146; Min.u64 = 1; Max.u64 = 1728624; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_I : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -2128,6 +2226,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache5.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; @@ -2226,10 +2329,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 4977; SumSQ.u64 = 4977; Count.u64 = 4977; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.PutS_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache5.PutM_recv : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; l2cache5.PutE_recv : Accumulator : Sum.u64 = 2886; SumSQ.u64 = 2886; Count.u64 = 2886; Min.u64 = 1; Max.u64 = 1; @@ -2241,6 +2346,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NACK_recv : Accumulator : Sum.u64 = 5528; SumSQ.u64 = 5528; Count.u64 = 5528; Min.u64 = 1; Max.u64 = 1; l2cache5.AckInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 4345; SumSQ.u64 = 4345; Count.u64 = 4345; Min.u64 = 1; Max.u64 = 1; @@ -2316,13 +2424,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_FetchResp : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_AckInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_GetSResp : Accumulator : Sum.u64 = 2997; SumSQ.u64 = 2997; Count.u64 = 2997; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_WriteResp : Accumulator : Sum.u64 = 2003; SumSQ.u64 = 2003; Count.u64 = 2003; Min.u64 = 1; Max.u64 = 1; l1cache6.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2349,6 +2460,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2395,22 +2507,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache6.Write_recv : Accumulator : Sum.u64 = 2003; SumSQ.u64 = 2003; Count.u64 = 2003; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache6.GetXResp_recv : Accumulator : Sum.u64 = 4978; SumSQ.u64 = 4978; Count.u64 = 4978; Min.u64 = 1; Max.u64 = 1; l1cache6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.Inv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache6.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.FetchInv_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; l1cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.NACK_recv : Accumulator : Sum.u64 = 16307; SumSQ.u64 = 16307; Count.u64 = 16307; Min.u64 = 1; Max.u64 = 1; l1cache6.AckPut_recv : Accumulator : Sum.u64 = 4746; SumSQ.u64 = 4746; Count.u64 = 4746; Min.u64 = 1; Max.u64 = 1; l1cache6.MSHR_occupancy : Accumulator : Sum.u64 = 9729662; SumSQ.u64 = 154824596; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache6.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache6:memlink.packet_latency : Accumulator : Sum.u64 = 17792; SumSQ.u64 = 23680; Count.u64 = 15731; Min.u64 = 0; Max.u64 = 5; - l2cache6:memlink.send_bit_count : Accumulator : Sum.u64 = 5499840; SumSQ.u64 = 2940432384; Count.u64 = 15719; Min.u64 = 64; Max.u64 = 576; - l2cache6:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache6:memlink.idle_time : Accumulator : Sum.u64 = 99388174; SumSQ.u64 = 6321706285834; Count.u64 = 14411; Min.u64 = 1; Max.u64 = 1142739; + l2cache6:lowlink.packet_latency : Accumulator : Sum.u64 = 17792; SumSQ.u64 = 23680; Count.u64 = 15731; Min.u64 = 0; Max.u64 = 5; + l2cache6:lowlink.send_bit_count : Accumulator : Sum.u64 = 5499840; SumSQ.u64 = 2940432384; Count.u64 = 15719; Min.u64 = 64; Max.u64 = 576; + l2cache6:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6:lowlink.idle_time : Accumulator : Sum.u64 = 99388174; SumSQ.u64 = 6321706285834; Count.u64 = 14411; Min.u64 = 1; Max.u64 = 1142739; l2cache6.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.evict_I : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l2cache6.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2502,6 +2618,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache6.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_FetchResp : Accumulator : Sum.u64 = 536; SumSQ.u64 = 536; Count.u64 = 536; Min.u64 = 1; Max.u64 = 1; l2cache6.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.eventSent_AckInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; @@ -2600,10 +2721,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache6.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.GetSResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache6.GetXResp_recv : Accumulator : Sum.u64 = 4978; SumSQ.u64 = 4978; Count.u64 = 4978; Min.u64 = 1; Max.u64 = 1; l2cache6.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.PutS_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache6.PutM_recv : Accumulator : Sum.u64 = 1887; SumSQ.u64 = 1887; Count.u64 = 1887; Min.u64 = 1; Max.u64 = 1; l2cache6.PutE_recv : Accumulator : Sum.u64 = 2855; SumSQ.u64 = 2855; Count.u64 = 2855; Min.u64 = 1; Max.u64 = 1; @@ -2615,6 +2738,9 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache6.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.FetchResp_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; l2cache6.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache6.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache6.NACK_recv : Accumulator : Sum.u64 = 5806; SumSQ.u64 = 5806; Count.u64 = 5806; Min.u64 = 1; Max.u64 = 1; l2cache6.AckInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache6.AckPut_recv : Accumulator : Sum.u64 = 4355; SumSQ.u64 = 4355; Count.u64 = 4355; Min.u64 = 1; Max.u64 = 1; @@ -2690,13 +2816,16 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_FetchResp : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_AckInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_GetSResp : Accumulator : Sum.u64 = 3033; SumSQ.u64 = 3033; Count.u64 = 3033; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_WriteResp : Accumulator : Sum.u64 = 1967; SumSQ.u64 = 1967; Count.u64 = 1967; Min.u64 = 1; Max.u64 = 1; l1cache7.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2723,6 +2852,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2769,22 +2899,26 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l1cache7.Write_recv : Accumulator : Sum.u64 = 1967; SumSQ.u64 = 1967; Count.u64 = 1967; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache7.GetXResp_recv : Accumulator : Sum.u64 = 4987; SumSQ.u64 = 4987; Count.u64 = 4987; Min.u64 = 1; Max.u64 = 1; l1cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache7.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.FetchInv_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l1cache7.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.NACK_recv : Accumulator : Sum.u64 = 15620; SumSQ.u64 = 15620; Count.u64 = 15620; Min.u64 = 1; Max.u64 = 1; l1cache7.AckPut_recv : Accumulator : Sum.u64 = 4815; SumSQ.u64 = 4815; Count.u64 = 4815; Min.u64 = 1; Max.u64 = 1; l1cache7.MSHR_occupancy : Accumulator : Sum.u64 = 9878809; SumSQ.u64 = 157243919; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 16; l1cache7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache7:memlink.packet_latency : Accumulator : Sum.u64 = 17963; SumSQ.u64 = 23805; Count.u64 = 15997; Min.u64 = 0; Max.u64 = 4; - l2cache7:memlink.send_bit_count : Accumulator : Sum.u64 = 5599936; SumSQ.u64 = 2994614272; Count.u64 = 15987; Min.u64 = 64; Max.u64 = 576; - l2cache7:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache7:memlink.idle_time : Accumulator : Sum.u64 = 96129855; SumSQ.u64 = 3061762796723; Count.u64 = 14733; Min.u64 = 1; Max.u64 = 223840; + l2cache7:lowlink.packet_latency : Accumulator : Sum.u64 = 17963; SumSQ.u64 = 23805; Count.u64 = 15997; Min.u64 = 0; Max.u64 = 4; + l2cache7:lowlink.send_bit_count : Accumulator : Sum.u64 = 5599936; SumSQ.u64 = 2994614272; Count.u64 = 15987; Min.u64 = 64; Max.u64 = 576; + l2cache7:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7:lowlink.idle_time : Accumulator : Sum.u64 = 96129855; SumSQ.u64 = 3061762796723; Count.u64 = 14733; Min.u64 = 1; Max.u64 = 223840; l2cache7.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.evict_I : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; l2cache7.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2876,6 +3010,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache7.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_FetchResp : Accumulator : Sum.u64 = 501; SumSQ.u64 = 501; Count.u64 = 501; Min.u64 = 1; Max.u64 = 1; l2cache7.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.eventSent_AckInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; @@ -2974,10 +3113,12 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache7.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache7.GetXResp_recv : Accumulator : Sum.u64 = 4987; SumSQ.u64 = 4987; Count.u64 = 4987; Min.u64 = 1; Max.u64 = 1; l2cache7.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.PutS_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache7.PutM_recv : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; l2cache7.PutE_recv : Accumulator : Sum.u64 = 2924; SumSQ.u64 = 2924; Count.u64 = 2924; Min.u64 = 1; Max.u64 = 1; @@ -2989,17 +3130,20 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l2cache7.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.FetchResp_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l2cache7.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache7.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache7.NACK_recv : Accumulator : Sum.u64 = 6083; SumSQ.u64 = 6083; Count.u64 = 6083; Min.u64 = 1; Max.u64 = 1; l2cache7.AckInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache7.AckPut_recv : Accumulator : Sum.u64 = 4390; SumSQ.u64 = 4390; Count.u64 = 4390; Min.u64 = 1; Max.u64 = 1; l2cache7.MSHR_occupancy : Accumulator : Sum.u64 = 1688110; SumSQ.u64 = 4776984; Count.u64 = 621377; Min.u64 = 0; Max.u64 = 4; l2cache7.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 60748; SumSQ.u64 = 101300; Count.u64 = 51031; Min.u64 = 0; Max.u64 = 18; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 17576960; SumSQ.u64 = 9367715840; Count.u64 = 51040; Min.u64 = 64; Max.u64 = 576; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 111568304; SumSQ.u64 = 2077093006936; Count.u64 = 27574; Min.u64 = 4; Max.u64 = 343978; - l3cache0.default_stat : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l3cache0.evict_I : Accumulator : Sum.u64 = 7821; SumSQ.u64 = 7821; Count.u64 = 7821; Min.u64 = 1; Max.u64 = 1; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 60748; SumSQ.u64 = 101300; Count.u64 = 51031; Min.u64 = 0; Max.u64 = 18; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 17576960; SumSQ.u64 = 9367715840; Count.u64 = 51040; Min.u64 = 64; Max.u64 = 576; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 111568304; SumSQ.u64 = 2077093006936; Count.u64 = 27574; Min.u64 = 4; Max.u64 = 343978; + l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_I : Accumulator : Sum.u64 = 7822; SumSQ.u64 = 7822; Count.u64 = 7822; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IM : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3009,6 +3153,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_M : Accumulator : Sum.u64 = 1699; SumSQ.u64 = 1699; Count.u64 = 1699; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 6019; SumSQ.u64 = 6019; Count.u64 = 6019; Min.u64 = 1; Max.u64 = 1; @@ -3027,7 +3172,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3118,6 +3263,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 3709; SumSQ.u64 = 3709; Count.u64 = 3709; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3126,6 +3275,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 9940; SumSQ.u64 = 9940; Count.u64 = 9940; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 999; SumSQ.u64 = 999; Count.u64 = 999; Min.u64 = 1; Max.u64 = 1; @@ -3166,6 +3316,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.CacheHits : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l3cache0.CacheMisses : Accumulator : Sum.u64 = 9987; SumSQ.u64 = 9987; Count.u64 = 9987; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_E : Accumulator : Sum.u64 = 2565; SumSQ.u64 = 2565; Count.u64 = 2565; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -3226,9 +3377,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 9987; SumSQ.u64 = 9987; Count.u64 = 9987; Min.u64 = 1; Max.u64 = 1; l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutS_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache0.PutM_recv : Accumulator : Sum.u64 = 6582; SumSQ.u64 = 6582; Count.u64 = 6582; Min.u64 = 1; Max.u64 = 1; l3cache0.PutE_recv : Accumulator : Sum.u64 = 10109; SumSQ.u64 = 10109; Count.u64 = 10109; Min.u64 = 1; Max.u64 = 1; @@ -3240,17 +3393,20 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.AckInv_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 9329; SumSQ.u64 = 9329; Count.u64 = 9329; Min.u64 = 1; Max.u64 = 1; l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1564981; SumSQ.u64 = 8295923; Count.u64 = 362905; Min.u64 = 0; Max.u64 = 7; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 60876; SumSQ.u64 = 96962; Count.u64 = 51487; Min.u64 = 0; Max.u64 = 11; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 17769088; SumSQ.u64 = 9473499136; Count.u64 = 51506; Min.u64 = 64; Max.u64 = 576; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 113093640; SumSQ.u64 = 2246751269616; Count.u64 = 27732; Min.u64 = 4; Max.u64 = 266776; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 60876; SumSQ.u64 = 96962; Count.u64 = 51487; Min.u64 = 0; Max.u64 = 11; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 17769088; SumSQ.u64 = 9473499136; Count.u64 = 51506; Min.u64 = 64; Max.u64 = 576; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 113093640; SumSQ.u64 = 2246751269616; Count.u64 = 27732; Min.u64 = 4; Max.u64 = 266776; l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.evict_I : Accumulator : Sum.u64 = 7950; SumSQ.u64 = 7950; Count.u64 = 7950; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_I : Accumulator : Sum.u64 = 7952; SumSQ.u64 = 7952; Count.u64 = 7952; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IM : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3260,6 +3416,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_M : Accumulator : Sum.u64 = 1635; SumSQ.u64 = 1635; Count.u64 = 1635; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 6070; SumSQ.u64 = 6070; Count.u64 = 6070; Min.u64 = 1; Max.u64 = 1; @@ -3369,6 +3526,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 3721; SumSQ.u64 = 3721; Count.u64 = 3721; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3377,6 +3538,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 10033; SumSQ.u64 = 10033; Count.u64 = 10033; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; @@ -3417,6 +3579,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.CacheHits : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l3cache1.CacheMisses : Accumulator : Sum.u64 = 10070; SumSQ.u64 = 10070; Count.u64 = 10070; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_E : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -3477,9 +3640,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 10070; SumSQ.u64 = 10070; Count.u64 = 10070; Min.u64 = 1; Max.u64 = 1; l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutM_recv : Accumulator : Sum.u64 = 6672; SumSQ.u64 = 6672; Count.u64 = 6672; Min.u64 = 1; Max.u64 = 1; l3cache1.PutE_recv : Accumulator : Sum.u64 = 10299; SumSQ.u64 = 10299; Count.u64 = 10299; Min.u64 = 1; Max.u64 = 1; @@ -3491,17 +3656,20 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 985; SumSQ.u64 = 985; Count.u64 = 985; Min.u64 = 1; Max.u64 = 1; l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.AckInv_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 9406; SumSQ.u64 = 9406; Count.u64 = 9406; Min.u64 = 1; Max.u64 = 1; l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1500419; SumSQ.u64 = 7823699; Count.u64 = 362905; Min.u64 = 0; Max.u64 = 7; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 62399; SumSQ.u64 = 103095; Count.u64 = 52235; Min.u64 = 0; Max.u64 = 12; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 18047360; SumSQ.u64 = 9623724032; Count.u64 = 52262; Min.u64 = 64; Max.u64 = 576; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 111457212; SumSQ.u64 = 2095286689520; Count.u64 = 27888; Min.u64 = 4; Max.u64 = 329518; - l3cache2.default_stat : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l3cache2.evict_I : Accumulator : Sum.u64 = 7860; SumSQ.u64 = 7860; Count.u64 = 7860; Min.u64 = 1; Max.u64 = 1; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 62399; SumSQ.u64 = 103095; Count.u64 = 52235; Min.u64 = 0; Max.u64 = 12; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 18047360; SumSQ.u64 = 9623724032; Count.u64 = 52262; Min.u64 = 64; Max.u64 = 576; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 111457212; SumSQ.u64 = 2095286689520; Count.u64 = 27888; Min.u64 = 4; Max.u64 = 329518; + l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_I : Accumulator : Sum.u64 = 7866; SumSQ.u64 = 7866; Count.u64 = 7866; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IM : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3511,6 +3679,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_M : Accumulator : Sum.u64 = 1749; SumSQ.u64 = 1749; Count.u64 = 1749; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 6055; SumSQ.u64 = 6055; Count.u64 = 6055; Min.u64 = 1; Max.u64 = 1; @@ -3529,7 +3698,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3620,6 +3789,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 3683; SumSQ.u64 = 3683; Count.u64 = 3683; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3628,6 +3801,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 9952; SumSQ.u64 = 9952; Count.u64 = 9952; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Inv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 1050; SumSQ.u64 = 1050; Count.u64 = 1050; Min.u64 = 1; Max.u64 = 1; @@ -3668,6 +3842,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.CacheHits : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache2.CacheMisses : Accumulator : Sum.u64 = 9996; SumSQ.u64 = 9996; Count.u64 = 9996; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_E : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3728,9 +3903,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 9996; SumSQ.u64 = 9996; Count.u64 = 9996; Min.u64 = 1; Max.u64 = 1; l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutS_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l3cache2.PutM_recv : Accumulator : Sum.u64 = 6670; SumSQ.u64 = 6670; Count.u64 = 6670; Min.u64 = 1; Max.u64 = 1; l3cache2.PutE_recv : Accumulator : Sum.u64 = 10756; SumSQ.u64 = 10756; Count.u64 = 10756; Min.u64 = 1; Max.u64 = 1; @@ -3742,17 +3919,20 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.AckInv_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 9341; SumSQ.u64 = 9341; Count.u64 = 9341; Min.u64 = 1; Max.u64 = 1; l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 1567739; SumSQ.u64 = 8342677; Count.u64 = 362905; Min.u64 = 0; Max.u64 = 7; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache3:cpulink.packet_latency : Accumulator : Sum.u64 = 58299; SumSQ.u64 = 91651; Count.u64 = 49559; Min.u64 = 0; Max.u64 = 12; - l3cache3:cpulink.send_bit_count : Accumulator : Sum.u64 = 17035968; SumSQ.u64 = 9075634176; Count.u64 = 49571; Min.u64 = 64; Max.u64 = 576; - l3cache3:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache3:cpulink.idle_time : Accumulator : Sum.u64 = 113317574; SumSQ.u64 = 2141180390836; Count.u64 = 27164; Min.u64 = 4; Max.u64 = 231748; + l3cache3:highlink.packet_latency : Accumulator : Sum.u64 = 58299; SumSQ.u64 = 91651; Count.u64 = 49559; Min.u64 = 0; Max.u64 = 12; + l3cache3:highlink.send_bit_count : Accumulator : Sum.u64 = 17035968; SumSQ.u64 = 9075634176; Count.u64 = 49571; Min.u64 = 64; Max.u64 = 576; + l3cache3:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3:highlink.idle_time : Accumulator : Sum.u64 = 113317574; SumSQ.u64 = 2141180390836; Count.u64 = 27164; Min.u64 = 4; Max.u64 = 231748; l3cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache3.evict_I : Accumulator : Sum.u64 = 7843; SumSQ.u64 = 7843; Count.u64 = 7843; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_I : Accumulator : Sum.u64 = 7844; SumSQ.u64 = 7844; Count.u64 = 7844; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_IS : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_IM : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3762,6 +3942,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.evict_M : Accumulator : Sum.u64 = 1644; SumSQ.u64 = 1644; Count.u64 = 1644; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.evict_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 6060; SumSQ.u64 = 6060; Count.u64 = 6060; Min.u64 = 1; Max.u64 = 1; @@ -3871,6 +4052,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.eventSent_PutM : Accumulator : Sum.u64 = 3610; SumSQ.u64 = 3610; Count.u64 = 3610; Min.u64 = 1; Max.u64 = 1; l3cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3879,6 +4064,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 9895; SumSQ.u64 = 9895; Count.u64 = 9895; Min.u64 = 1; Max.u64 = 1; l3cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_Inv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l3cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; @@ -3919,6 +4105,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.CacheHits : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache3.CacheMisses : Accumulator : Sum.u64 = 9937; SumSQ.u64 = 9937; Count.u64 = 9937; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_E : Accumulator : Sum.u64 = 2607; SumSQ.u64 = 2607; Count.u64 = 2607; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.evict_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3cache3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3979,9 +4166,11 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.GetXResp_recv : Accumulator : Sum.u64 = 9937; SumSQ.u64 = 9937; Count.u64 = 9937; Min.u64 = 1; Max.u64 = 1; l3cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.PutM_recv : Accumulator : Sum.u64 = 6262; SumSQ.u64 = 6262; Count.u64 = 6262; Min.u64 = 1; Max.u64 = 1; l3cache3.PutE_recv : Accumulator : Sum.u64 = 9654; SumSQ.u64 = 9654; Count.u64 = 9654; Min.u64 = 1; Max.u64 = 1; @@ -3993,15 +4182,18 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t l3cache3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.FetchResp_recv : Accumulator : Sum.u64 = 1021; SumSQ.u64 = 1021; Count.u64 = 1021; Min.u64 = 1; Max.u64 = 1; l3cache3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache3.NACK_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache3.AckInv_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l3cache3.AckPut_recv : Accumulator : Sum.u64 = 9271; SumSQ.u64 = 9271; Count.u64 = 9271; Min.u64 = 1; Max.u64 = 1; l3cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1483568; SumSQ.u64 = 7675158; Count.u64 = 362905; Min.u64 = 0; Max.u64 = 7; l3cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 41150; SumSQ.u64 = 52690; Count.u64 = 38653; Min.u64 = 0; Max.u64 = 5; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 14013760; SumSQ.u64 = 7543902208; Count.u64 = 38653; Min.u64 = 64; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 155221602; SumSQ.u64 = 2115839078212; Count.u64 = 25519; Min.u64 = 4; Max.u64 = 289888; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 41150; SumSQ.u64 = 52690; Count.u64 = 38653; Min.u64 = 0; Max.u64 = 5; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 14013760; SumSQ.u64 = 7543902208; Count.u64 = 38653; Min.u64 = 64; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 155221602; SumSQ.u64 = 2115839078212; Count.u64 = 25519; Min.u64 = 4; Max.u64 = 289888; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 37340; SumSQ.u64 = 74680; Count.u64 = 18670; Min.u64 = 2; Max.u64 = 2; directory0.get_request_latency : Accumulator : Sum.u64 = 2833670; SumSQ.u64 = 488272728; Count.u64 = 19983; Min.u64 = 21; Max.u64 = 465; @@ -4024,8 +4216,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4044,6 +4238,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 19983; SumSQ.u64 = 19983; Count.u64 = 19983; Min.u64 = 1; Max.u64 = 1; @@ -4054,6 +4249,8 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 2793704; SumSQ.u64 = 25620956; Count.u64 = 362890; Min.u64 = 0; Max.u64 = 14; @@ -4074,10 +4271,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t memory0.cycles_with_issue : Accumulator : Sum.u64 = 11008; SumSQ.u64 = 11008; Count.u64 = 11008; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 113137; SumSQ.u64 = 113137; Count.u64 = 113137; Min.u64 = 1; Max.u64 = 1; memory0.total_cycles : Accumulator : Sum.u64 = 129557; SumSQ.u64 = 16785016249; Count.u64 = 1; Min.u64 = 129557; Max.u64 = 129557; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 41313; SumSQ.u64 = 53137; Count.u64 = 38684; Min.u64 = 0; Max.u64 = 5; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 13971200; SumSQ.u64 = 7515521024; Count.u64 = 38684; Min.u64 = 64; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 155470642; SumSQ.u64 = 2050812827068; Count.u64 = 25496; Min.u64 = 4; Max.u64 = 124908; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 41313; SumSQ.u64 = 53137; Count.u64 = 38684; Min.u64 = 0; Max.u64 = 5; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 13971200; SumSQ.u64 = 7515521024; Count.u64 = 38684; Min.u64 = 64; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 155470642; SumSQ.u64 = 2050812827068; Count.u64 = 25496; Min.u64 = 4; Max.u64 = 124908; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 37354; SumSQ.u64 = 74708; Count.u64 = 18677; Min.u64 = 2; Max.u64 = 2; directory1.get_request_latency : Accumulator : Sum.u64 = 2689743; SumSQ.u64 = 452194881; Count.u64 = 20007; Min.u64 = 21; Max.u64 = 414; @@ -4100,8 +4297,10 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -4120,6 +4319,7 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 20007; SumSQ.u64 = 20007; Count.u64 = 20007; Min.u64 = 1; Max.u64 = 1; @@ -4130,6 +4330,8 @@ l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated t directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 2649729; SumSQ.u64 = 23714551; Count.u64 = 362728; Min.u64 = 0; Max.u64 = 14; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out index ce547ea177..c68a18604b 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_PrefetchParams.out @@ -79,13 +79,16 @@ Completed @ 5088 ns l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1346; SumSQ.u64 = 1346; Count.u64 = 1346; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -112,6 +115,7 @@ Completed @ 5088 ns l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 377; SumSQ.u64 = 377; Count.u64 = 377; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -163,22 +167,26 @@ Completed @ 5088 ns l1cache0.Write_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 81804; SumSQ.u64 = 759806; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 12; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 641; SumSQ.u64 = 863; Count.u64 = 575; Min.u64 = 0; Max.u64 = 3; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 96192; SumSQ.u64 = 40366080; Count.u64 = 575; Min.u64 = 64; Max.u64 = 576; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 2826581; SumSQ.u64 = 66011908309; Count.u64 = 419; Min.u64 = 4; Max.u64 = 138607; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 641; SumSQ.u64 = 863; Count.u64 = 575; Min.u64 = 0; Max.u64 = 3; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 96192; SumSQ.u64 = 40366080; Count.u64 = 575; Min.u64 = 64; Max.u64 = 576; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 2826581; SumSQ.u64 = 66011908309; Count.u64 = 419; Min.u64 = 4; Max.u64 = 138607; l2cache0.Prefetch_requests : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l2cache0.Prefetch_drops : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -290,8 +298,11 @@ Completed @ 5088 ns l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; @@ -300,6 +311,9 @@ Completed @ 5088 ns l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -324,6 +338,7 @@ Completed @ 5088 ns l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -399,10 +414,12 @@ Completed @ 5088 ns l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -414,6 +431,9 @@ Completed @ 5088 ns l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -488,13 +508,16 @@ Completed @ 5088 ns l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1351; SumSQ.u64 = 1351; Count.u64 = 1351; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -521,6 +544,7 @@ Completed @ 5088 ns l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -572,22 +596,26 @@ Completed @ 5088 ns l1cache1.Write_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 92877; SumSQ.u64 = 879871; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 12; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 640; SumSQ.u64 = 870; Count.u64 = 574; Min.u64 = 0; Max.u64 = 3; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 94592; SumSQ.u64 = 39378944; Count.u64 = 574; Min.u64 = 64; Max.u64 = 576; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 2686823; SumSQ.u64 = 39736887183; Count.u64 = 420; Min.u64 = 10; Max.u64 = 94293; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 640; SumSQ.u64 = 870; Count.u64 = 574; Min.u64 = 0; Max.u64 = 3; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 94592; SumSQ.u64 = 39378944; Count.u64 = 574; Min.u64 = 64; Max.u64 = 576; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 2686823; SumSQ.u64 = 39736887183; Count.u64 = 420; Min.u64 = 10; Max.u64 = 94293; l2cache1.Prefetch_requests : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l2cache1.Prefetch_drops : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -699,8 +727,11 @@ Completed @ 5088 ns l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; @@ -709,6 +740,9 @@ Completed @ 5088 ns l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -733,6 +767,7 @@ Completed @ 5088 ns l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -808,10 +843,12 @@ Completed @ 5088 ns l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutS_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -823,6 +860,9 @@ Completed @ 5088 ns l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.AckInv_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -897,13 +937,16 @@ Completed @ 5088 ns l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1358; SumSQ.u64 = 1358; Count.u64 = 1358; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -930,6 +973,7 @@ Completed @ 5088 ns l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -981,22 +1025,26 @@ Completed @ 5088 ns l1cache2.Write_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Inv_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 96253; SumSQ.u64 = 910925; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 12; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 720; SumSQ.u64 = 992; Count.u64 = 630; Min.u64 = 0; Max.u64 = 3; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 94592; SumSQ.u64 = 37314560; Count.u64 = 630; Min.u64 = 64; Max.u64 = 576; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 2469595; SumSQ.u64 = 30020397345; Count.u64 = 454; Min.u64 = 16; Max.u64 = 55240; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 720; SumSQ.u64 = 992; Count.u64 = 630; Min.u64 = 0; Max.u64 = 3; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 94592; SumSQ.u64 = 37314560; Count.u64 = 630; Min.u64 = 64; Max.u64 = 576; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 2469595; SumSQ.u64 = 30020397345; Count.u64 = 454; Min.u64 = 16; Max.u64 = 55240; l2cache2.Prefetch_requests : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l2cache2.Prefetch_drops : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1108,8 +1156,11 @@ Completed @ 5088 ns l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; @@ -1118,6 +1169,9 @@ Completed @ 5088 ns l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1142,6 +1196,7 @@ Completed @ 5088 ns l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1217,10 +1272,12 @@ Completed @ 5088 ns l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutS_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1232,6 +1289,9 @@ Completed @ 5088 ns l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.AckInv_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1306,13 +1366,16 @@ Completed @ 5088 ns l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1332; SumSQ.u64 = 1332; Count.u64 = 1332; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1339,6 +1402,7 @@ Completed @ 5088 ns l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1390,22 +1454,26 @@ Completed @ 5088 ns l1cache3.Write_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Inv_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 97127; SumSQ.u64 = 930237; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 12; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 651; SumSQ.u64 = 893; Count.u64 = 576; Min.u64 = 0; Max.u64 = 3; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 94208; SumSQ.u64 = 39059456; Count.u64 = 576; Min.u64 = 64; Max.u64 = 576; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 2685151; SumSQ.u64 = 36964914855; Count.u64 = 416; Min.u64 = 46; Max.u64 = 59581; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 651; SumSQ.u64 = 893; Count.u64 = 576; Min.u64 = 0; Max.u64 = 3; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 94208; SumSQ.u64 = 39059456; Count.u64 = 576; Min.u64 = 64; Max.u64 = 576; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 2685151; SumSQ.u64 = 36964914855; Count.u64 = 416; Min.u64 = 46; Max.u64 = 59581; l2cache3.Prefetch_requests : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; l2cache3.Prefetch_drops : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1517,8 +1585,11 @@ Completed @ 5088 ns l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; @@ -1527,6 +1598,9 @@ Completed @ 5088 ns l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1551,6 +1625,7 @@ Completed @ 5088 ns l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1626,10 +1701,12 @@ Completed @ 5088 ns l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutS_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache3.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1641,6 +1718,9 @@ Completed @ 5088 ns l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.AckInv_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1715,13 +1795,16 @@ Completed @ 5088 ns l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 1339; SumSQ.u64 = 1339; Count.u64 = 1339; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1748,6 +1831,7 @@ Completed @ 5088 ns l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1799,22 +1883,26 @@ Completed @ 5088 ns l1cache4.Write_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Inv_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 88087; SumSQ.u64 = 823305; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 12; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 670; SumSQ.u64 = 926; Count.u64 = 595; Min.u64 = 0; Max.u64 = 3; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 94912; SumSQ.u64 = 38809600; Count.u64 = 595; Min.u64 = 64; Max.u64 = 576; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 2674195; SumSQ.u64 = 45488534365; Count.u64 = 440; Min.u64 = 22; Max.u64 = 92208; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 670; SumSQ.u64 = 926; Count.u64 = 595; Min.u64 = 0; Max.u64 = 3; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 94912; SumSQ.u64 = 38809600; Count.u64 = 595; Min.u64 = 64; Max.u64 = 576; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 2674195; SumSQ.u64 = 45488534365; Count.u64 = 440; Min.u64 = 22; Max.u64 = 92208; l2cache4.Prefetch_requests : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache4.Prefetch_drops : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1926,8 +2014,11 @@ Completed @ 5088 ns l2cache4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; @@ -1936,6 +2027,9 @@ Completed @ 5088 ns l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1960,6 +2054,7 @@ Completed @ 5088 ns l2cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2035,10 +2130,12 @@ Completed @ 5088 ns l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutS_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2050,6 +2147,9 @@ Completed @ 5088 ns l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.AckInv_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2124,13 +2224,16 @@ Completed @ 5088 ns l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 1344; SumSQ.u64 = 1344; Count.u64 = 1344; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2157,6 +2260,7 @@ Completed @ 5088 ns l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2208,22 +2312,26 @@ Completed @ 5088 ns l1cache5.Write_recv : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Inv_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 100707; SumSQ.u64 = 970349; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 12; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 634; SumSQ.u64 = 868; Count.u64 = 561; Min.u64 = 0; Max.u64 = 3; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 79936; SumSQ.u64 = 30478336; Count.u64 = 561; Min.u64 = 64; Max.u64 = 576; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 2722129; SumSQ.u64 = 46929031473; Count.u64 = 425; Min.u64 = 40; Max.u64 = 76981; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 634; SumSQ.u64 = 868; Count.u64 = 561; Min.u64 = 0; Max.u64 = 3; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 79936; SumSQ.u64 = 30478336; Count.u64 = 561; Min.u64 = 64; Max.u64 = 576; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 2722129; SumSQ.u64 = 46929031473; Count.u64 = 425; Min.u64 = 40; Max.u64 = 76981; l2cache5.Prefetch_requests : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l2cache5.Prefetch_drops : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2335,8 +2443,11 @@ Completed @ 5088 ns l2cache5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; @@ -2345,6 +2456,9 @@ Completed @ 5088 ns l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2369,6 +2483,7 @@ Completed @ 5088 ns l2cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2444,10 +2559,12 @@ Completed @ 5088 ns l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.PutS_recv : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l2cache5.PutM_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l2cache5.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2459,15 +2576,18 @@ Completed @ 5088 ns l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.AckInv_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 24776; SumSQ.u64 = 66270; Count.u64 = 12203; Min.u64 = 0; Max.u64 = 6; l2cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 1313; SumSQ.u64 = 1881; Count.u64 = 1175; Min.u64 = 0; Max.u64 = 5; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 376768; SumSQ.u64 = 197816320; Count.u64 = 1175; Min.u64 = 64; Max.u64 = 576; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 2170531; SumSQ.u64 = 12639290613; Count.u64 = 798; Min.u64 = 34; Max.u64 = 48100; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 1313; SumSQ.u64 = 1881; Count.u64 = 1175; Min.u64 = 0; Max.u64 = 5; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 376768; SumSQ.u64 = 197816320; Count.u64 = 1175; Min.u64 = 64; Max.u64 = 576; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 2170531; SumSQ.u64 = 12639290613; Count.u64 = 798; Min.u64 = 34; Max.u64 = 48100; l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2577,8 +2697,11 @@ Completed @ 5088 ns l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2587,6 +2710,9 @@ Completed @ 5088 ns l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2611,6 +2737,7 @@ Completed @ 5088 ns l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2681,10 +2808,12 @@ Completed @ 5088 ns l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2696,15 +2825,18 @@ Completed @ 5088 ns l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.AckInv_recv : Accumulator : Sum.u64 = 356; SumSQ.u64 = 356; Count.u64 = 356; Min.u64 = 1; Max.u64 = 1; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 11499; SumSQ.u64 = 28569; Count.u64 = 7126; Min.u64 = 0; Max.u64 = 6; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1992; Count.u64 = 1175; Min.u64 = 0; Max.u64 = 4; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 377792; SumSQ.u64 = 198471680; Count.u64 = 1175; Min.u64 = 64; Max.u64 = 576; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 2073551; SumSQ.u64 = 12084483177; Count.u64 = 783; Min.u64 = 10; Max.u64 = 56104; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1992; Count.u64 = 1175; Min.u64 = 0; Max.u64 = 4; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 377792; SumSQ.u64 = 198471680; Count.u64 = 1175; Min.u64 = 64; Max.u64 = 576; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 2073551; SumSQ.u64 = 12084483177; Count.u64 = 783; Min.u64 = 10; Max.u64 = 56104; l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2814,8 +2946,11 @@ Completed @ 5088 ns l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2824,6 +2959,9 @@ Completed @ 5088 ns l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2848,6 +2986,7 @@ Completed @ 5088 ns l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2918,10 +3057,12 @@ Completed @ 5088 ns l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2933,15 +3074,18 @@ Completed @ 5088 ns l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.AckInv_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 11423; SumSQ.u64 = 31021; Count.u64 = 7126; Min.u64 = 0; Max.u64 = 6; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 1395; SumSQ.u64 = 2091; Count.u64 = 1210; Min.u64 = 0; Max.u64 = 5; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 388224; SumSQ.u64 = 203857920; Count.u64 = 1210; Min.u64 = 64; Max.u64 = 576; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 2078823; SumSQ.u64 = 9025521257; Count.u64 = 816; Min.u64 = 4; Max.u64 = 17704; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 1395; SumSQ.u64 = 2091; Count.u64 = 1210; Min.u64 = 0; Max.u64 = 5; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 388224; SumSQ.u64 = 203857920; Count.u64 = 1210; Min.u64 = 64; Max.u64 = 576; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 2078823; SumSQ.u64 = 9025521257; Count.u64 = 816; Min.u64 = 4; Max.u64 = 17704; l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3051,8 +3195,11 @@ Completed @ 5088 ns l3cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3061,6 +3208,9 @@ Completed @ 5088 ns l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3085,6 +3235,7 @@ Completed @ 5088 ns l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3155,10 +3306,12 @@ Completed @ 5088 ns l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3170,15 +3323,18 @@ Completed @ 5088 ns l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.AckInv_recv : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 12075; SumSQ.u64 = 30363; Count.u64 = 7126; Min.u64 = 0; Max.u64 = 6; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 25; Min.u64 = 0; Max.u64 = 1; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 14400; SumSQ.u64 = 8294400; Count.u64 = 25; Min.u64 = 576; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 4643695; SumSQ.u64 = 13929654652177; Count.u64 = 26; Min.u64 = 10900; Max.u64 = 3727395; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 25; Min.u64 = 0; Max.u64 = 1; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 14400; SumSQ.u64 = 8294400; Count.u64 = 25; Min.u64 = 576; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 4643695; SumSQ.u64 = 13929654652177; Count.u64 = 26; Min.u64 = 10900; Max.u64 = 3727395; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.get_request_latency : Accumulator : Sum.u64 = 574; SumSQ.u64 = 13188; Count.u64 = 25; Min.u64 = 22; Max.u64 = 24; @@ -3201,8 +3357,10 @@ Completed @ 5088 ns directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3221,6 +3379,7 @@ Completed @ 5088 ns directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; @@ -3231,6 +3390,8 @@ Completed @ 5088 ns directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 1904; Min.u64 = 0; Max.u64 = 1; @@ -3251,10 +3412,10 @@ Completed @ 5088 ns memory0.cycles_with_issue : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.total_cycles : Accumulator : Sum.u64 = 2544; SumSQ.u64 = 6471936; Count.u64 = 1; Min.u64 = 2544; Max.u64 = 2544; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 27; SumSQ.u64 = 33; Count.u64 = 24; Min.u64 = 1; Max.u64 = 2; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 13824; SumSQ.u64 = 7962624; Count.u64 = 24; Min.u64 = 576; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 4659093; SumSQ.u64 = 13949261762169; Count.u64 = 25; Min.u64 = 11500; Max.u64 = 3729537; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 27; SumSQ.u64 = 33; Count.u64 = 24; Min.u64 = 1; Max.u64 = 2; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 13824; SumSQ.u64 = 7962624; Count.u64 = 24; Min.u64 = 576; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 4659093; SumSQ.u64 = 13949261762169; Count.u64 = 25; Min.u64 = 11500; Max.u64 = 3729537; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.get_request_latency : Accumulator : Sum.u64 = 552; SumSQ.u64 = 12710; Count.u64 = 24; Min.u64 = 22; Max.u64 = 24; @@ -3277,8 +3438,10 @@ Completed @ 5088 ns directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3297,6 +3460,7 @@ Completed @ 5088 ns directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; @@ -3307,6 +3471,8 @@ Completed @ 5088 ns directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 1901; Min.u64 = 0; Max.u64 = 1; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out index 7cb05265b6..f470a43668 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_1.out @@ -1,5 +1,9 @@ -ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 3837 cycles +memory0, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=0, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B +memory1, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=128, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 cycles +ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 3837 cycles l1_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; l1_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; @@ -67,13 +71,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FetchResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_AckInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_GetSResp : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_WriteResp : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_Put : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_Get : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_AckMove : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; @@ -81,7 +88,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1_0.evict_I : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1_0.evict_I : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; l1_0.evict_S : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1_0.evict_M : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -100,6 +107,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1_0.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -137,14 +145,18 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_0.Write_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetXResp_recv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.ForceInv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l1_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.AckPut_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; l1_0.MSHR_occupancy : Accumulator : Sum.u64 = 8385; SumSQ.u64 = 25943; Count.u64 = 3935; Min.u64 = 0; Max.u64 = 8; @@ -168,10 +180,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c scratch0.request_received_scratch_put : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_read : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_write : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; - scratch0:memlink.packet_latency : Accumulator : Sum.u64 = 837; SumSQ.u64 = 2379; Count.u64 = 343; Min.u64 = 0; Max.u64 = 6; - scratch0:memlink.send_bit_count : Accumulator : Sum.u64 = 117864; SumSQ.u64 = 59582144; Count.u64 = 684; Min.u64 = 64; Max.u64 = 1088; - scratch0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch0:memlink.idle_time : Accumulator : Sum.u64 = 600280; SumSQ.u64 = 2866318400; Count.u64 = 215; Min.u64 = 40; Max.u64 = 14460; + scratch0:lowlink.packet_latency : Accumulator : Sum.u64 = 837; SumSQ.u64 = 2379; Count.u64 = 343; Min.u64 = 0; Max.u64 = 6; + scratch0:lowlink.send_bit_count : Accumulator : Sum.u64 = 117864; SumSQ.u64 = 59582144; Count.u64 = 684; Min.u64 = 64; Max.u64 = 1088; + scratch0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch0:lowlink.idle_time : Accumulator : Sum.u64 = 600280; SumSQ.u64 = 2866318400; Count.u64 = 215; Min.u64 = 40; Max.u64 = 14460; l1_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; l1_1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -239,13 +251,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FetchResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_AckInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_GetSResp : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_WriteResp : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_Put : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_Get : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_AckMove : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; @@ -253,7 +268,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1_1.evict_I : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1_1.evict_I : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l1_1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.evict_M : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1_1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -272,6 +287,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1_1.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -318,14 +334,18 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c l1_1.Write_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetXResp_recv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.ForceInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l1_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.AckPut_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; l1_1.MSHR_occupancy : Accumulator : Sum.u64 = 8125; SumSQ.u64 = 23233; Count.u64 = 3935; Min.u64 = 0; Max.u64 = 7; @@ -349,10 +369,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c scratch1.request_received_scratch_put : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_read : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_write : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; - scratch1:memlink.packet_latency : Accumulator : Sum.u64 = 845; SumSQ.u64 = 2337; Count.u64 = 353; Min.u64 = 0; Max.u64 = 6; - scratch1:memlink.send_bit_count : Accumulator : Sum.u64 = 135256; SumSQ.u64 = 75597120; Count.u64 = 690; Min.u64 = 64; Max.u64 = 1088; - scratch1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch1:memlink.idle_time : Accumulator : Sum.u64 = 623000; SumSQ.u64 = 3174792800; Count.u64 = 224; Min.u64 = 80; Max.u64 = 22020; + scratch1:lowlink.packet_latency : Accumulator : Sum.u64 = 845; SumSQ.u64 = 2337; Count.u64 = 353; Min.u64 = 0; Max.u64 = 6; + scratch1:lowlink.send_bit_count : Accumulator : Sum.u64 = 135256; SumSQ.u64 = 75597120; Count.u64 = 690; Min.u64 = 64; Max.u64 = 1088; + scratch1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch1:lowlink.idle_time : Accumulator : Sum.u64 = 623000; SumSQ.u64 = 3174792800; Count.u64 = 224; Min.u64 = 80; Max.u64 = 22020; memory0.requests_received_GetS : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; memory0.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.requests_received_GetX : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; @@ -367,10 +387,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c memory0.cycles_with_issue : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.total_cycles : Accumulator : Sum.u64 = 1967; SumSQ.u64 = 3869089; Count.u64 = 1; Min.u64 = 1967; Max.u64 = 1967; - memory0:cpulink.packet_latency : Accumulator : Sum.u64 = 2900; SumSQ.u64 = 18176; Count.u64 = 665; Min.u64 = 0; Max.u64 = 17; - memory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 109544; SumSQ.u64 = 73174720; Count.u64 = 330; Min.u64 = 72; Max.u64 = 1088; - memory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:cpulink.idle_time : Accumulator : Sum.u64 = 497720; SumSQ.u64 = 2651620800; Count.u64 = 206; Min.u64 = 20; Max.u64 = 25560; + memory0:highlink.packet_latency : Accumulator : Sum.u64 = 2900; SumSQ.u64 = 18176; Count.u64 = 665; Min.u64 = 0; Max.u64 = 17; + memory0:highlink.send_bit_count : Accumulator : Sum.u64 = 109544; SumSQ.u64 = 73174720; Count.u64 = 330; Min.u64 = 72; Max.u64 = 1088; + memory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory0:highlink.idle_time : Accumulator : Sum.u64 = 497720; SumSQ.u64 = 2651620800; Count.u64 = 206; Min.u64 = 20; Max.u64 = 25560; memory1.requests_received_GetS : Accumulator : Sum.u64 = 366; SumSQ.u64 = 366; Count.u64 = 366; Min.u64 = 1; Max.u64 = 1; memory1.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.requests_received_GetX : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; @@ -385,8 +405,8 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3935 c memory1.cycles_with_issue : Accumulator : Sum.u64 = 796; SumSQ.u64 = 796; Count.u64 = 796; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.total_cycles : Accumulator : Sum.u64 = 1967; SumSQ.u64 = 3869089; Count.u64 = 1; Min.u64 = 1967; Max.u64 = 1967; - memory1:cpulink.packet_latency : Accumulator : Sum.u64 = 2975; SumSQ.u64 = 17651; Count.u64 = 709; Min.u64 = 0; Max.u64 = 18; - memory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 126024; SumSQ.u64 = 87254976; Count.u64 = 366; Min.u64 = 72; Max.u64 = 1088; - memory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:cpulink.idle_time : Accumulator : Sum.u64 = 554480; SumSQ.u64 = 2982011200; Count.u64 = 225; Min.u64 = 20; Max.u64 = 22560; + memory1:highlink.packet_latency : Accumulator : Sum.u64 = 2975; SumSQ.u64 = 17651; Count.u64 = 709; Min.u64 = 0; Max.u64 = 18; + memory1:highlink.send_bit_count : Accumulator : Sum.u64 = 126024; SumSQ.u64 = 87254976; Count.u64 = 366; Min.u64 = 72; Max.u64 = 1088; + memory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory1:highlink.idle_time : Accumulator : Sum.u64 = 554480; SumSQ.u64 = 2982011200; Count.u64 = 225; Min.u64 = 20; Max.u64 = 22560; Simulation is complete, simulated time: 1.9675 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out index e948ac10d4..59fcd21f83 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_2.out @@ -1,7 +1,11 @@ l2_0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. l2_1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. -ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 3773 cycles +memory0, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=0, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B +memory1, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=128, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 cycles +ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 3773 cycles l1_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l1_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -69,13 +73,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l1_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FetchResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_AckInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_GetSResp : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_WriteResp : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_Put : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_Get : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_AckMove : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; @@ -102,6 +109,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l1_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1_0.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -148,14 +156,18 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l1_0.Write_recv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetXResp_recv : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.ForceInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FetchInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.AckPut_recv : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l1_0.MSHR_occupancy : Accumulator : Sum.u64 = 10399; SumSQ.u64 = 37627; Count.u64 = 3963; Min.u64 = 0; Max.u64 = 8; @@ -251,6 +263,11 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l2_0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FetchResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_AckInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; @@ -349,10 +366,12 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l2_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.GetXResp_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l2_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.PutM_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; l2_0.PutE_recv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; @@ -364,6 +383,9 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l2_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FetchResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.AckInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2_0.AckPut_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; @@ -388,10 +410,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c scratch0.request_received_scratch_put : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_read : Accumulator : Sum.u64 = 473; SumSQ.u64 = 473; Count.u64 = 473; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_write : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; - scratch0:memlink.packet_latency : Accumulator : Sum.u64 = 737; SumSQ.u64 = 2053; Count.u64 = 309; Min.u64 = 0; Max.u64 = 8; - scratch0:memlink.send_bit_count : Accumulator : Sum.u64 = 123296; SumSQ.u64 = 64100608; Count.u64 = 655; Min.u64 = 64; Max.u64 = 1088; - scratch0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch0:memlink.idle_time : Accumulator : Sum.u64 = 607420; SumSQ.u64 = 2261936400; Count.u64 = 237; Min.u64 = 80; Max.u64 = 12000; + scratch0:lowlink.packet_latency : Accumulator : Sum.u64 = 737; SumSQ.u64 = 2053; Count.u64 = 309; Min.u64 = 0; Max.u64 = 8; + scratch0:lowlink.send_bit_count : Accumulator : Sum.u64 = 123296; SumSQ.u64 = 64100608; Count.u64 = 655; Min.u64 = 64; Max.u64 = 1088; + scratch0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch0:lowlink.idle_time : Accumulator : Sum.u64 = 607420; SumSQ.u64 = 2261936400; Count.u64 = 237; Min.u64 = 80; Max.u64 = 12000; l1_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l1_1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -459,13 +481,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l1_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FetchResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_AckInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_GetSResp : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_WriteResp : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_Put : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_Get : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_AckMove : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; @@ -492,6 +517,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l1_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1_1.GetXHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -538,14 +564,18 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l1_1.Write_recv : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetXResp_recv : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.ForceInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FetchInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.AckPut_recv : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l1_1.MSHR_occupancy : Accumulator : Sum.u64 = 11842; SumSQ.u64 = 46766; Count.u64 = 3963; Min.u64 = 0; Max.u64 = 8; @@ -641,6 +671,11 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l2_1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FetchResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_AckInv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; @@ -739,10 +774,12 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l2_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.GetXResp_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; l2_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.PutM_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2_1.PutE_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; @@ -754,6 +791,9 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c l2_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FetchResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.AckInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2_1.AckPut_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; @@ -778,10 +818,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c scratch1.request_received_scratch_put : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_read : Accumulator : Sum.u64 = 480; SumSQ.u64 = 480; Count.u64 = 480; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_write : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; - scratch1:memlink.packet_latency : Accumulator : Sum.u64 = 740; SumSQ.u64 = 2058; Count.u64 = 310; Min.u64 = 0; Max.u64 = 6; - scratch1:memlink.send_bit_count : Accumulator : Sum.u64 = 123672; SumSQ.u64 = 70887872; Count.u64 = 638; Min.u64 = 64; Max.u64 = 1088; - scratch1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch1:memlink.idle_time : Accumulator : Sum.u64 = 663060; SumSQ.u64 = 3110570800; Count.u64 = 228; Min.u64 = 80; Max.u64 = 16400; + scratch1:lowlink.packet_latency : Accumulator : Sum.u64 = 740; SumSQ.u64 = 2058; Count.u64 = 310; Min.u64 = 0; Max.u64 = 6; + scratch1:lowlink.send_bit_count : Accumulator : Sum.u64 = 123672; SumSQ.u64 = 70887872; Count.u64 = 638; Min.u64 = 64; Max.u64 = 1088; + scratch1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch1:lowlink.idle_time : Accumulator : Sum.u64 = 663060; SumSQ.u64 = 3110570800; Count.u64 = 228; Min.u64 = 80; Max.u64 = 16400; memory0.requests_received_GetS : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; memory0.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.requests_received_GetX : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; @@ -796,10 +836,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c memory0.cycles_with_issue : Accumulator : Sum.u64 = 743; SumSQ.u64 = 743; Count.u64 = 743; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.total_cycles : Accumulator : Sum.u64 = 1981; SumSQ.u64 = 3924361; Count.u64 = 1; Min.u64 = 1981; Max.u64 = 1981; - memory0:cpulink.packet_latency : Accumulator : Sum.u64 = 2195; SumSQ.u64 = 10131; Count.u64 = 662; Min.u64 = 0; Max.u64 = 14; - memory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 100176; SumSQ.u64 = 67532928; Count.u64 = 309; Min.u64 = 72; Max.u64 = 1088; - memory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:cpulink.idle_time : Accumulator : Sum.u64 = 503800; SumSQ.u64 = 2759550400; Count.u64 = 214; Min.u64 = 20; Max.u64 = 24120; + memory0:highlink.packet_latency : Accumulator : Sum.u64 = 2195; SumSQ.u64 = 10131; Count.u64 = 662; Min.u64 = 0; Max.u64 = 14; + memory0:highlink.send_bit_count : Accumulator : Sum.u64 = 100176; SumSQ.u64 = 67532928; Count.u64 = 309; Min.u64 = 72; Max.u64 = 1088; + memory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory0:highlink.idle_time : Accumulator : Sum.u64 = 503800; SumSQ.u64 = 2759550400; Count.u64 = 214; Min.u64 = 20; Max.u64 = 24120; memory1.requests_received_GetS : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; memory1.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.requests_received_GetX : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; @@ -814,8 +854,8 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 3963 c memory1.cycles_with_issue : Accumulator : Sum.u64 = 708; SumSQ.u64 = 708; Count.u64 = 708; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.total_cycles : Accumulator : Sum.u64 = 1981; SumSQ.u64 = 3924361; Count.u64 = 1; Min.u64 = 1981; Max.u64 = 1981; - memory1:cpulink.packet_latency : Accumulator : Sum.u64 = 2113; SumSQ.u64 = 10193; Count.u64 = 631; Min.u64 = 0; Max.u64 = 14; - memory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 106296; SumSQ.u64 = 72365760; Count.u64 = 310; Min.u64 = 72; Max.u64 = 1088; - memory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:cpulink.idle_time : Accumulator : Sum.u64 = 525920; SumSQ.u64 = 3265421600; Count.u64 = 219; Min.u64 = 20; Max.u64 = 36120; + memory1:highlink.packet_latency : Accumulator : Sum.u64 = 2113; SumSQ.u64 = 10193; Count.u64 = 631; Min.u64 = 0; Max.u64 = 14; + memory1:highlink.send_bit_count : Accumulator : Sum.u64 = 106296; SumSQ.u64 = 72365760; Count.u64 = 310; Min.u64 = 72; Max.u64 = 1088; + memory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory1:highlink.idle_time : Accumulator : Sum.u64 = 525920; SumSQ.u64 = 3265421600; Count.u64 = 219; Min.u64 = 20; Max.u64 = 36120; Simulation is complete, simulated time: 1.9815 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out index e9bdc05ac7..a19909f728 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_3.out @@ -2,8 +2,12 @@ l2_0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 l3_0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. l2_1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. l3_1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. -ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 65358 cycles +memory0, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=0, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B +memory1, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=128, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 cycles +ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 65358 cycles l1_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l1_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -71,13 +75,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l1_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FetchResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_AckInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_GetSResp : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_WriteResp : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_Put : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_Get : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_AckMove : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; @@ -104,6 +111,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l1_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1_0.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +158,18 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l1_0.Write_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetXResp_recv : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.ForceInv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FetchInv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.AckPut_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; l1_0.MSHR_occupancy : Accumulator : Sum.u64 = 26245; SumSQ.u64 = 40035; Count.u64 = 67763; Min.u64 = 0; Max.u64 = 7; @@ -253,6 +265,11 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l2_0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_AckInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; @@ -351,10 +368,12 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l2_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.GetXResp_recv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l2_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.PutM_recv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2_0.PutE_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; @@ -366,12 +385,15 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l2_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FetchResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.AckInv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2_0.AckPut_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2_0.MSHR_occupancy : Accumulator : Sum.u64 = 24757; SumSQ.u64 = 37129; Count.u64 = 67763; Min.u64 = 0; Max.u64 = 6; l2_0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3_0.default_stat : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.evict_I : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; l3_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -480,8 +502,11 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_0.eventSent_Write : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l3_0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.eventSent_AckPut : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l3_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.eventSent_FetchResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.eventSent_AckInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; @@ -490,6 +515,9 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_0.eventSent_GetXResp : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l3_0.eventSent_WriteResp : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l3_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.eventSent_FetchInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3_0.eventSent_ForceInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; @@ -514,6 +542,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -584,10 +613,12 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.GetXResp_recv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l3_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.PutM_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l3_0.PutE_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -599,6 +630,9 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.FetchResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_0.AckInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l3_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -623,10 +657,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 scratch0.request_received_scratch_put : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_read : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_write : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; - scratch0:memlink.packet_latency : Accumulator : Sum.u64 = 885; SumSQ.u64 = 2549; Count.u64 = 340; Min.u64 = 0; Max.u64 = 7; - scratch0:memlink.send_bit_count : Accumulator : Sum.u64 = 124360; SumSQ.u64 = 67159360; Count.u64 = 673; Min.u64 = 64; Max.u64 = 1088; - scratch0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch0:memlink.idle_time : Accumulator : Sum.u64 = 25944980; SumSQ.u64 = 4304673026000; Count.u64 = 597; Min.u64 = 200; Max.u64 = 805980; + scratch0:lowlink.packet_latency : Accumulator : Sum.u64 = 885; SumSQ.u64 = 2549; Count.u64 = 340; Min.u64 = 0; Max.u64 = 7; + scratch0:lowlink.send_bit_count : Accumulator : Sum.u64 = 124360; SumSQ.u64 = 67159360; Count.u64 = 673; Min.u64 = 64; Max.u64 = 1088; + scratch0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch0:lowlink.idle_time : Accumulator : Sum.u64 = 25944980; SumSQ.u64 = 4304673026000; Count.u64 = 597; Min.u64 = 200; Max.u64 = 805980; l1_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1_1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -694,13 +728,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l1_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FetchResp : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_AckInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_GetSResp : Accumulator : Sum.u64 = 340; SumSQ.u64 = 340; Count.u64 = 340; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_WriteResp : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_Put : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_Get : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_AckMove : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; @@ -727,6 +764,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l1_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1_1.GetXHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l1_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -773,14 +811,18 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l1_1.Write_recv : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1_1.GetXResp_recv : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1_1.ForceInv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FetchInv_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l1_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.AckPut_recv : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; l1_1.MSHR_occupancy : Accumulator : Sum.u64 = 17402; SumSQ.u64 = 26308; Count.u64 = 67763; Min.u64 = 0; Max.u64 = 7; @@ -876,6 +918,11 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l2_1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FetchResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_AckInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; @@ -974,10 +1021,12 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l2_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2_1.GetXResp_recv : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; l2_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.PutM_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; l2_1.PutE_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; @@ -989,13 +1038,16 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l2_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FetchResp_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; l2_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.AckInv_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2_1.AckPut_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2_1.MSHR_occupancy : Accumulator : Sum.u64 = 15374; SumSQ.u64 = 23204; Count.u64 = 67763; Min.u64 = 0; Max.u64 = 6; l2_1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3_1.evict_I : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + l3_1.evict_I : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; l3_1.evict_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3_1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1005,6 +1057,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_M : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l3_1.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.stateEvent_GetS_I : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; @@ -1114,6 +1167,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_1.eventSent_PutM : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; l3_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.eventSent_FetchResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l3_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.eventSent_AckInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; @@ -1122,6 +1179,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_1.eventSent_GetXResp : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; l3_1.eventSent_WriteResp : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; l3_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.eventSent_Inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3_1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.eventSent_FetchInv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; @@ -1162,6 +1220,7 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_1.CacheHits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.CacheMisses : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; l3_1.evict_E : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; + l3_1.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1222,9 +1281,11 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.GetXResp_recv : Accumulator : Sum.u64 = 310; SumSQ.u64 = 310; Count.u64 = 310; Min.u64 = 1; Max.u64 = 1; l3_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.PutM_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3_1.PutE_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -1236,6 +1297,9 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 l3_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.FetchResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l3_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3_1.AckInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3_1.AckPut_recv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; @@ -1260,10 +1324,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 scratch1.request_received_scratch_put : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_read : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_write : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; - scratch1:memlink.packet_latency : Accumulator : Sum.u64 = 855; SumSQ.u64 = 2351; Count.u64 = 336; Min.u64 = 0; Max.u64 = 6; - scratch1:memlink.send_bit_count : Accumulator : Sum.u64 = 121224; SumSQ.u64 = 64215744; Count.u64 = 654; Min.u64 = 64; Max.u64 = 1088; - scratch1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch1:memlink.idle_time : Accumulator : Sum.u64 = 27471200; SumSQ.u64 = 4717533934400; Count.u64 = 599; Min.u64 = 540; Max.u64 = 865380; + scratch1:lowlink.packet_latency : Accumulator : Sum.u64 = 855; SumSQ.u64 = 2351; Count.u64 = 336; Min.u64 = 0; Max.u64 = 6; + scratch1:lowlink.send_bit_count : Accumulator : Sum.u64 = 121224; SumSQ.u64 = 64215744; Count.u64 = 654; Min.u64 = 64; Max.u64 = 1088; + scratch1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch1:lowlink.idle_time : Accumulator : Sum.u64 = 27471200; SumSQ.u64 = 4717533934400; Count.u64 = 599; Min.u64 = 540; Max.u64 = 865380; memory0:backend.row_already_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0:backend.no_row_open : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; memory0:backend.wrong_row_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1281,10 +1345,10 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 memory0.cycles_with_issue : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 31110; SumSQ.u64 = 31110; Count.u64 = 31110; Min.u64 = 1; Max.u64 = 1; memory0.total_cycles : Accumulator : Sum.u64 = 33881; SumSQ.u64 = 1147922161; Count.u64 = 1; Min.u64 = 33881; Max.u64 = 33881; - memory0:cpulink.packet_latency : Accumulator : Sum.u64 = 1689; SumSQ.u64 = 4721; Count.u64 = 645; Min.u64 = 0; Max.u64 = 7; - memory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 109248; SumSQ.u64 = 77028864; Count.u64 = 339; Min.u64 = 72; Max.u64 = 1088; - memory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:cpulink.idle_time : Accumulator : Sum.u64 = 9442300; SumSQ.u64 = 1692110310000; Count.u64 = 225; Min.u64 = 540; Max.u64 = 974620; + memory0:highlink.packet_latency : Accumulator : Sum.u64 = 1689; SumSQ.u64 = 4721; Count.u64 = 645; Min.u64 = 0; Max.u64 = 7; + memory0:highlink.send_bit_count : Accumulator : Sum.u64 = 109248; SumSQ.u64 = 77028864; Count.u64 = 339; Min.u64 = 72; Max.u64 = 1088; + memory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory0:highlink.idle_time : Accumulator : Sum.u64 = 9442300; SumSQ.u64 = 1692110310000; Count.u64 = 225; Min.u64 = 540; Max.u64 = 974620; memory1:backend.row_already_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1:backend.no_row_open : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; memory1:backend.wrong_row_open : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1302,8 +1366,8 @@ ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 67763 memory1.cycles_with_issue : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 33788; SumSQ.u64 = 33788; Count.u64 = 33788; Min.u64 = 1; Max.u64 = 1; memory1.total_cycles : Accumulator : Sum.u64 = 33881; SumSQ.u64 = 1147922161; Count.u64 = 1; Min.u64 = 33881; Max.u64 = 33881; - memory1:cpulink.packet_latency : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 5363; Count.u64 = 682; Min.u64 = 0; Max.u64 = 8; - memory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 113840; SumSQ.u64 = 77270656; Count.u64 = 337; Min.u64 = 72; Max.u64 = 1088; - memory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:cpulink.idle_time : Accumulator : Sum.u64 = 8943560; SumSQ.u64 = 893352493600; Count.u64 = 234; Min.u64 = 740; Max.u64 = 325560; + memory1:highlink.packet_latency : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 5363; Count.u64 = 682; Min.u64 = 0; Max.u64 = 8; + memory1:highlink.send_bit_count : Accumulator : Sum.u64 = 113840; SumSQ.u64 = 77270656; Count.u64 = 337; Min.u64 = 72; Max.u64 = 1088; + memory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory1:highlink.idle_time : Accumulator : Sum.u64 = 8943560; SumSQ.u64 = 893352493600; Count.u64 = 234; Min.u64 = 740; Max.u64 = 325560; Simulation is complete, simulated time: 33.8815 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_4.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_4.out index 2efe395611..42cf06f0f4 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_4.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchCache_4.out @@ -1,9 +1,13 @@ l2_0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. l2_1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +memory0, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=0, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B +memory1, Notice: memory controller's region is larger than the backend's mem_size, controller is limiting accessible memory to mem_size +Region: start=128, end=18446744073709551615, interleaveStep=256, interleaveSize=128. MemSize: 536870912B +ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 cycles ScratchCPU core2 Finished after 1000 issued memory events, 1000 returned, 29375 cycles ScratchCPU core1 Finished after 1000 issued memory events, 1000 returned, 29430 cycles ScratchCPU core0 Finished after 1000 issued memory events, 1000 returned, 29453 cycles -ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 cycles l1_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.stateEvent_GetS_I : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1_0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -71,13 +75,16 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_FetchResp : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_AckInv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_GetSResp : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_WriteResp : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.eventSent_Put : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_Get : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l1_0.eventSent_AckMove : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; @@ -104,6 +111,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1_0.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -150,14 +158,18 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_0.Write_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.GetSResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; l1_0.GetXResp_recv : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l1_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.Inv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1_0.ForceInv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.FetchInv_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1_0.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_0.MSHR_occupancy : Accumulator : Sum.u64 = 91137; SumSQ.u64 = 349057; Count.u64 = 29453; Min.u64 = 0; Max.u64 = 7; @@ -229,13 +241,16 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_FetchResp : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_AckInv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_GetSResp : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_WriteResp : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.eventSent_Put : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_Get : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l1_1.eventSent_AckMove : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; @@ -262,6 +277,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l1_1.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -308,22 +324,26 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_1.Write_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.GetSResp_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l1_1.GetXResp_recv : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; l1_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.Inv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1_1.ForceInv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.FetchInv_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1_1.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_1.MSHR_occupancy : Accumulator : Sum.u64 = 90225; SumSQ.u64 = 343163; Count.u64 = 29453; Min.u64 = 0; Max.u64 = 8; l1_1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2_0:memlink.packet_latency : Accumulator : Sum.u64 = 12445; SumSQ.u64 = 96097; Count.u64 = 2267; Min.u64 = 0; Max.u64 = 19; - l2_0:memlink.send_bit_count : Accumulator : Sum.u64 = 324656; SumSQ.u64 = 133312256; Count.u64 = 2266; Min.u64 = 64; Max.u64 = 1088; - l2_0:memlink.output_port_stalls : Accumulator : Sum.u64 = 17760; SumSQ.u64 = 33408000; Count.u64 = 11; Min.u64 = 480; Max.u64 = 2880; - l2_0:memlink.idle_time : Accumulator : Sum.u64 = 7042600; SumSQ.u64 = 48613524000; Count.u64 = 1830; Min.u64 = 20; Max.u64 = 26900; + l2_0:lowlink.packet_latency : Accumulator : Sum.u64 = 12445; SumSQ.u64 = 96097; Count.u64 = 2267; Min.u64 = 0; Max.u64 = 19; + l2_0:lowlink.send_bit_count : Accumulator : Sum.u64 = 324656; SumSQ.u64 = 133312256; Count.u64 = 2266; Min.u64 = 64; Max.u64 = 1088; + l2_0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 17760; SumSQ.u64 = 33408000; Count.u64 = 11; Min.u64 = 480; Max.u64 = 2880; + l2_0:lowlink.idle_time : Accumulator : Sum.u64 = 7042600; SumSQ.u64 = 48613524000; Count.u64 = 1830; Min.u64 = 20; Max.u64 = 26900; l2_0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.evict_I : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; l2_0.evict_IS : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; @@ -433,8 +453,11 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_0.eventSent_Write : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_PutS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_PutM : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2_0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FetchResp : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_AckInv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; @@ -443,6 +466,9 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_0.eventSent_GetXResp : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_WriteResp : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.eventSent_FetchInv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l2_0.eventSent_ForceInv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; @@ -467,6 +493,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.GetSHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l2_0.GetXHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -537,10 +564,12 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.GetSResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; l2_0.GetXResp_recv : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; l2_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.PutS_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; l2_0.PutM_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; l2_0.PutE_recv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; @@ -552,6 +581,9 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_0.FetchInvX_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l2_0.FetchResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l2_0.FetchXResp_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_0.AckInv_recv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; l2_0.AckPut_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; @@ -624,13 +656,16 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.eventSent_FetchResp : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l1_2.eventSent_AckInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.eventSent_GetSResp : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; l1_2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.eventSent_WriteResp : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; l1_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.eventSent_Put : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1_2.eventSent_Get : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; l1_2.eventSent_AckMove : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; @@ -657,6 +692,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1_2.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -703,14 +739,18 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_2.Write_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; l1_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.GetSResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1_2.GetXResp_recv : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; l1_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.Inv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1_2.ForceInv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l1_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.FetchInv_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1_2.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_2.MSHR_occupancy : Accumulator : Sum.u64 = 98459; SumSQ.u64 = 427359; Count.u64 = 29453; Min.u64 = 0; Max.u64 = 9; @@ -782,13 +822,16 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.eventSent_FetchResp : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l1_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l1_3.eventSent_AckInv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.eventSent_GetSResp : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l1_3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.eventSent_WriteResp : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; l1_3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.eventSent_Put : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l1_3.eventSent_Get : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1_3.eventSent_AckMove : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; @@ -815,6 +858,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.GetSHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1_3.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l1_3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -861,22 +905,26 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l1_3.Write_recv : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; l1_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.GetSResp_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l1_3.GetXResp_recv : Accumulator : Sum.u64 = 296; SumSQ.u64 = 296; Count.u64 = 296; Min.u64 = 1; Max.u64 = 1; l1_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.Inv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1_3.ForceInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l1_3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.FetchInv_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l1_3.FetchInvX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1_3.MSHR_occupancy : Accumulator : Sum.u64 = 98408; SumSQ.u64 = 406628; Count.u64 = 29453; Min.u64 = 0; Max.u64 = 8; l1_3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2_1:memlink.packet_latency : Accumulator : Sum.u64 = 12745; SumSQ.u64 = 98419; Count.u64 = 2323; Min.u64 = 0; Max.u64 = 18; - l2_1:memlink.send_bit_count : Accumulator : Sum.u64 = 356080; SumSQ.u64 = 152722304; Count.u64 = 2323; Min.u64 = 64; Max.u64 = 1088; - l2_1:memlink.output_port_stalls : Accumulator : Sum.u64 = 20140; SumSQ.u64 = 45562000; Count.u64 = 10; Min.u64 = 1420; Max.u64 = 2880; - l2_1:memlink.idle_time : Accumulator : Sum.u64 = 6772840; SumSQ.u64 = 44047380000; Count.u64 = 1809; Min.u64 = 20; Max.u64 = 31100; + l2_1:lowlink.packet_latency : Accumulator : Sum.u64 = 12745; SumSQ.u64 = 98419; Count.u64 = 2323; Min.u64 = 0; Max.u64 = 18; + l2_1:lowlink.send_bit_count : Accumulator : Sum.u64 = 356080; SumSQ.u64 = 152722304; Count.u64 = 2323; Min.u64 = 64; Max.u64 = 1088; + l2_1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 20140; SumSQ.u64 = 45562000; Count.u64 = 10; Min.u64 = 1420; Max.u64 = 2880; + l2_1:lowlink.idle_time : Accumulator : Sum.u64 = 6772840; SumSQ.u64 = 44047380000; Count.u64 = 1809; Min.u64 = 20; Max.u64 = 31100; l2_1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.evict_I : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; l2_1.evict_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -986,8 +1034,11 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_1.eventSent_Write : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_PutS : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_PutM : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2_1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FetchResp : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_AckInv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; @@ -996,6 +1047,9 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_1.eventSent_GetXResp : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_WriteResp : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.eventSent_FetchInv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l2_1.eventSent_ForceInv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; @@ -1020,6 +1074,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.GetSHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l2_1.GetXHit_Arrival : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1090,10 +1145,12 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.GetSResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2_1.GetXResp_recv : Accumulator : Sum.u64 = 546; SumSQ.u64 = 546; Count.u64 = 546; Min.u64 = 1; Max.u64 = 1; l2_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.PutS_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l2_1.PutM_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; l2_1.PutE_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; @@ -1105,15 +1162,18 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 l2_1.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l2_1.FetchResp_recv : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; l2_1.FetchXResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2_1.AckInv_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l2_1.AckPut_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l2_1.MSHR_occupancy : Accumulator : Sum.u64 = 192596; SumSQ.u64 = 1436936; Count.u64 = 29453; Min.u64 = 0; Max.u64 = 15; l2_1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dir:cpulink.packet_latency : Accumulator : Sum.u64 = 142501; SumSQ.u64 = 3806915; Count.u64 = 8920; Min.u64 = 0; Max.u64 = 64; - dir:cpulink.send_bit_count : Accumulator : Sum.u64 = 1829792; SumSQ.u64 = 908203392; Count.u64 = 8921; Min.u64 = 64; Max.u64 = 1088; - dir:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - dir:cpulink.idle_time : Accumulator : Sum.u64 = 850720; SumSQ.u64 = 1509216000; Count.u64 = 724; Min.u64 = 20; Max.u64 = 16900; + dir:highlink.packet_latency : Accumulator : Sum.u64 = 142501; SumSQ.u64 = 3806915; Count.u64 = 8920; Min.u64 = 0; Max.u64 = 64; + dir:highlink.send_bit_count : Accumulator : Sum.u64 = 1829792; SumSQ.u64 = 908203392; Count.u64 = 8921; Min.u64 = 64; Max.u64 = 1088; + dir:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dir:highlink.idle_time : Accumulator : Sum.u64 = 850720; SumSQ.u64 = 1509216000; Count.u64 = 724; Min.u64 = 20; Max.u64 = 16900; dir.default_stat : Accumulator : Sum.u64 = 5651; SumSQ.u64 = 5651; Count.u64 = 5651; Min.u64 = 1; Max.u64 = 1; dir.replacement_request_latency : Accumulator : Sum.u64 = 336; SumSQ.u64 = 672; Count.u64 = 168; Min.u64 = 2; Max.u64 = 2; dir.get_request_latency : Accumulator : Sum.u64 = 158148; SumSQ.u64 = 25717868; Count.u64 = 1133; Min.u64 = 12; Max.u64 = 341; @@ -1136,8 +1196,10 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 dir.ForceInv_recv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; dir.FetchInv_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; dir.AckInv_recv : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; + dir.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dir.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.GetS_uncache_recv : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; dir.Write_uncache_recv : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; @@ -1156,6 +1218,7 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 dir.eventSent_FetchInv : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; dir.eventSent_FetchInvX : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; dir.eventSent_ForceInv : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; + dir.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.eventSent_GetSResp : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; dir.eventSent_GetXResp : Accumulator : Sum.u64 = 1050; SumSQ.u64 = 1050; Count.u64 = 1050; Min.u64 = 1; Max.u64 = 1; @@ -1166,6 +1229,8 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 dir.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dir.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + dir.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; dir.MSHR_occupancy : Accumulator : Sum.u64 = 164615; SumSQ.u64 = 1989237; Count.u64 = 14720; Min.u64 = 0; Max.u64 = 22; @@ -1188,10 +1253,10 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 scratch.request_received_scratch_put : Accumulator : Sum.u64 = 696; SumSQ.u64 = 696; Count.u64 = 696; Min.u64 = 1; Max.u64 = 1; scratch.request_issued_scratch_read : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; scratch.request_issued_scratch_write : Accumulator : Sum.u64 = 1052; SumSQ.u64 = 1052; Count.u64 = 1052; Min.u64 = 1; Max.u64 = 1; - scratch:cpulink.packet_latency : Accumulator : Sum.u64 = 26249; SumSQ.u64 = 189859; Count.u64 = 5643; Min.u64 = 0; Max.u64 = 19; - scratch:cpulink.send_bit_count : Accumulator : Sum.u64 = 1729128; SumSQ.u64 = 939170368; Count.u64 = 6988; Min.u64 = 64; Max.u64 = 1088; - scratch:cpulink.output_port_stalls : Accumulator : Sum.u64 = 2306420; SumSQ.u64 = 4675603600; Count.u64 = 1303; Min.u64 = 1440; Max.u64 = 4320; - scratch:cpulink.idle_time : Accumulator : Sum.u64 = 54060; SumSQ.u64 = 836036400; Count.u64 = 6; Min.u64 = 1060; Max.u64 = 24480; + scratch:highlink.packet_latency : Accumulator : Sum.u64 = 26249; SumSQ.u64 = 189859; Count.u64 = 5643; Min.u64 = 0; Max.u64 = 19; + scratch:highlink.send_bit_count : Accumulator : Sum.u64 = 1729128; SumSQ.u64 = 939170368; Count.u64 = 6988; Min.u64 = 64; Max.u64 = 1088; + scratch:highlink.output_port_stalls : Accumulator : Sum.u64 = 2306420; SumSQ.u64 = 4675603600; Count.u64 = 1303; Min.u64 = 1440; Max.u64 = 4320; + scratch:highlink.idle_time : Accumulator : Sum.u64 = 54060; SumSQ.u64 = 836036400; Count.u64 = 6; Min.u64 = 1060; Max.u64 = 24480; memory0.requests_received_GetS : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; memory0.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.requests_received_GetX : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; @@ -1206,10 +1271,10 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 memory0.cycles_with_issue : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.total_cycles : Accumulator : Sum.u64 = 14726; SumSQ.u64 = 216855076; Count.u64 = 1; Min.u64 = 14726; Max.u64 = 14726; - memory0:cpulink.packet_latency : Accumulator : Sum.u64 = 36443; SumSQ.u64 = 1040127; Count.u64 = 1306; Min.u64 = 2; Max.u64 = 46; - memory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 213440; SumSQ.u64 = 147547264; Count.u64 = 663; Min.u64 = 72; Max.u64 = 1088; - memory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:cpulink.idle_time : Accumulator : Sum.u64 = 4823640; SumSQ.u64 = 71238940000; Count.u64 = 610; Min.u64 = 20; Max.u64 = 48820; + memory0:highlink.packet_latency : Accumulator : Sum.u64 = 36443; SumSQ.u64 = 1040127; Count.u64 = 1306; Min.u64 = 2; Max.u64 = 46; + memory0:highlink.send_bit_count : Accumulator : Sum.u64 = 213440; SumSQ.u64 = 147547264; Count.u64 = 663; Min.u64 = 72; Max.u64 = 1088; + memory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory0:highlink.idle_time : Accumulator : Sum.u64 = 4823640; SumSQ.u64 = 71238940000; Count.u64 = 610; Min.u64 = 20; Max.u64 = 48820; memory1.requests_received_GetS : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; memory1.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.requests_received_GetX : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; @@ -1224,8 +1289,8 @@ ScratchCPU core3 Finished after 1000 issued memory events, 1000 returned, 28969 memory1.cycles_with_issue : Accumulator : Sum.u64 = 1513; SumSQ.u64 = 1513; Count.u64 = 1513; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.total_cycles : Accumulator : Sum.u64 = 14726; SumSQ.u64 = 216855076; Count.u64 = 1; Min.u64 = 14726; Max.u64 = 14726; - memory1:cpulink.packet_latency : Accumulator : Sum.u64 = 37635; SumSQ.u64 = 1072703; Count.u64 = 1351; Min.u64 = 3; Max.u64 = 43; - memory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 222632; SumSQ.u64 = 150767296; Count.u64 = 649; Min.u64 = 72; Max.u64 = 1088; - memory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:cpulink.idle_time : Accumulator : Sum.u64 = 4509160; SumSQ.u64 = 63981261600; Count.u64 = 614; Min.u64 = 20; Max.u64 = 64800; + memory1:highlink.packet_latency : Accumulator : Sum.u64 = 37635; SumSQ.u64 = 1072703; Count.u64 = 1351; Min.u64 = 3; Max.u64 = 43; + memory1:highlink.send_bit_count : Accumulator : Sum.u64 = 222632; SumSQ.u64 = 150767296; Count.u64 = 649; Min.u64 = 72; Max.u64 = 1088; + memory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory1:highlink.idle_time : Accumulator : Sum.u64 = 4509160; SumSQ.u64 = 63981261600; Count.u64 = 614; Min.u64 = 20; Max.u64 = 64800; Simulation is complete, simulated time: 14.7265 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchNetwork.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchNetwork.out index 608b947fcd..a07adee575 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchNetwork.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ScratchNetwork.out @@ -1,5 +1,5 @@ -ScratchCPU core0 Finished after 500 issued memory events, 500 returned, 1268 cycles ScratchCPU core1 Finished after 500 issued memory events, 500 returned, 1282 cycles +ScratchCPU core0 Finished after 500 issued memory events, 500 returned, 1268 cycles scratch0:backendConvertor.cycles_with_issue : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; scratch0:backendConvertor.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; scratch0:backendConvertor.total_cycles : Accumulator : Sum.u64 = 2564; SumSQ.u64 = 2564; Count.u64 = 2564; Min.u64 = 1; Max.u64 = 1; @@ -19,10 +19,10 @@ ScratchCPU core1 Finished after 500 issued memory events, 500 returned, 1282 cyc scratch0.request_received_scratch_put : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_read : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; scratch0.request_issued_scratch_write : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; - scratch0:memlink.packet_latency : Accumulator : Sum.u64 = 376; SumSQ.u64 = 1032; Count.u64 = 166; Min.u64 = 0; Max.u64 = 7; - scratch0:memlink.send_bit_count : Accumulator : Sum.u64 = 59776; SumSQ.u64 = 30706816; Count.u64 = 336; Min.u64 = 64; Max.u64 = 1088; - scratch0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch0:memlink.idle_time : Accumulator : Sum.u64 = 494580; SumSQ.u64 = 4870959600; Count.u64 = 129; Min.u64 = 40; Max.u64 = 45200; + scratch0:lowlink.packet_latency : Accumulator : Sum.u64 = 376; SumSQ.u64 = 1032; Count.u64 = 166; Min.u64 = 0; Max.u64 = 7; + scratch0:lowlink.send_bit_count : Accumulator : Sum.u64 = 59776; SumSQ.u64 = 30706816; Count.u64 = 336; Min.u64 = 64; Max.u64 = 1088; + scratch0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch0:lowlink.idle_time : Accumulator : Sum.u64 = 494580; SumSQ.u64 = 4870959600; Count.u64 = 129; Min.u64 = 40; Max.u64 = 45200; scratch1:backendConvertor.cycles_with_issue : Accumulator : Sum.u64 = 351; SumSQ.u64 = 351; Count.u64 = 351; Min.u64 = 1; Max.u64 = 1; scratch1:backendConvertor.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; scratch1:backendConvertor.total_cycles : Accumulator : Sum.u64 = 2564; SumSQ.u64 = 2564; Count.u64 = 2564; Min.u64 = 1; Max.u64 = 1; @@ -42,10 +42,10 @@ ScratchCPU core1 Finished after 500 issued memory events, 500 returned, 1282 cyc scratch1.request_received_scratch_put : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_read : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; scratch1.request_issued_scratch_write : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; - scratch1:memlink.packet_latency : Accumulator : Sum.u64 = 361; SumSQ.u64 = 991; Count.u64 = 163; Min.u64 = 0; Max.u64 = 7; - scratch1:memlink.send_bit_count : Accumulator : Sum.u64 = 68696; SumSQ.u64 = 39192768; Count.u64 = 350; Min.u64 = 64; Max.u64 = 1088; - scratch1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - scratch1:memlink.idle_time : Accumulator : Sum.u64 = 491780; SumSQ.u64 = 3546770000; Count.u64 = 129; Min.u64 = 320; Max.u64 = 25920; + scratch1:lowlink.packet_latency : Accumulator : Sum.u64 = 361; SumSQ.u64 = 991; Count.u64 = 163; Min.u64 = 0; Max.u64 = 7; + scratch1:lowlink.send_bit_count : Accumulator : Sum.u64 = 68696; SumSQ.u64 = 39192768; Count.u64 = 350; Min.u64 = 64; Max.u64 = 1088; + scratch1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + scratch1:lowlink.idle_time : Accumulator : Sum.u64 = 491780; SumSQ.u64 = 3546770000; Count.u64 = 129; Min.u64 = 320; Max.u64 = 25920; memory0.requests_received_GetS : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; memory0.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.requests_received_GetX : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; @@ -60,10 +60,10 @@ ScratchCPU core1 Finished after 500 issued memory events, 500 returned, 1282 cyc memory0.cycles_with_issue : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.total_cycles : Accumulator : Sum.u64 = 1282; SumSQ.u64 = 1643524; Count.u64 = 1; Min.u64 = 1282; Max.u64 = 1282; - memory0:cpulink.packet_latency : Accumulator : Sum.u64 = 1011; SumSQ.u64 = 4729; Count.u64 = 307; Min.u64 = 0; Max.u64 = 16; - memory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 44792; SumSQ.u64 = 30420544; Count.u64 = 148; Min.u64 = 72; Max.u64 = 1088; - memory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0:cpulink.idle_time : Accumulator : Sum.u64 = 310800; SumSQ.u64 = 1968024800; Count.u64 = 94; Min.u64 = 180; Max.u64 = 18240; + memory0:highlink.packet_latency : Accumulator : Sum.u64 = 1011; SumSQ.u64 = 4729; Count.u64 = 307; Min.u64 = 0; Max.u64 = 16; + memory0:highlink.send_bit_count : Accumulator : Sum.u64 = 44792; SumSQ.u64 = 30420544; Count.u64 = 148; Min.u64 = 72; Max.u64 = 1088; + memory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory0:highlink.idle_time : Accumulator : Sum.u64 = 310800; SumSQ.u64 = 1968024800; Count.u64 = 94; Min.u64 = 180; Max.u64 = 18240; memory1.requests_received_GetS : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; memory1.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.requests_received_GetX : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; @@ -78,8 +78,8 @@ ScratchCPU core1 Finished after 500 issued memory events, 500 returned, 1282 cyc memory1.cycles_with_issue : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.total_cycles : Accumulator : Sum.u64 = 1282; SumSQ.u64 = 1643524; Count.u64 = 1; Min.u64 = 1282; Max.u64 = 1282; - memory1:cpulink.packet_latency : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 7540; Count.u64 = 379; Min.u64 = 0; Max.u64 = 16; - memory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 57536; SumSQ.u64 = 37369984; Count.u64 = 181; Min.u64 = 72; Max.u64 = 1088; - memory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1:cpulink.idle_time : Accumulator : Sum.u64 = 329980; SumSQ.u64 = 1895143600; Count.u64 = 110; Min.u64 = 140; Max.u64 = 14560; + memory1:highlink.packet_latency : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 7540; Count.u64 = 379; Min.u64 = 0; Max.u64 = 16; + memory1:highlink.send_bit_count : Accumulator : Sum.u64 = 57536; SumSQ.u64 = 37369984; Count.u64 = 181; Min.u64 = 72; Max.u64 = 1088; + memory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory1:highlink.idle_time : Accumulator : Sum.u64 = 329980; SumSQ.u64 = 1895143600; Count.u64 = 110; Min.u64 = 140; Max.u64 = 14560; Simulation is complete, simulated time: 1.282 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem.out index e0fee38527..ce5de53c28 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem.out @@ -69,13 +69,16 @@ StandardCPU: Test Completed Successfuly l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -102,6 +105,7 @@ StandardCPU: Test Completed Successfuly l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -139,14 +143,18 @@ StandardCPU: Test Completed Successfuly l1cache.Write_recv : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 2010100; SumSQ.u64 = 16325984; Count.u64 = 262626; Min.u64 = 0; Max.u64 = 10; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_flush.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_flush.out index f3f1e08c24..78cc51354a 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_flush.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_flush.out @@ -144,13 +144,16 @@ StandardCPU: Test Completed Successfuly l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -158,7 +161,7 @@ StandardCPU: Test Completed Successfuly l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.evict_I : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_I : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_S : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_M : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_IS : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; @@ -177,6 +180,7 @@ StandardCPU: Test Completed Successfuly l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 25348; SumSQ.u64 = 26695048; Count.u64 = 70; Min.u64 = 67; Max.u64 = 2543; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -223,22 +227,26 @@ StandardCPU: Test Completed Successfuly l1cache0.Write_recv : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 1385; SumSQ.u64 = 1385; Count.u64 = 1385; Min.u64 = 1; Max.u64 = 1; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 283645; SumSQ.u64 = 4141411; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 16; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 3046; SumSQ.u64 = 6024; Count.u64 = 2196; Min.u64 = 0; Max.u64 = 7; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 301696; SumSQ.u64 = 111972352; Count.u64 = 2192; Min.u64 = 64; Max.u64 = 576; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 4023382; SumSQ.u64 = 20516307416; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 40951; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 3046; SumSQ.u64 = 6024; Count.u64 = 2196; Min.u64 = 0; Max.u64 = 7; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 301696; SumSQ.u64 = 111972352; Count.u64 = 2192; Min.u64 = 64; Max.u64 = 576; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 4023382; SumSQ.u64 = 20516307416; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 40951; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_I : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -348,8 +356,11 @@ StandardCPU: Test Completed Successfuly l2cache0.eventSent_Write : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; @@ -358,6 +369,9 @@ StandardCPU: Test Completed Successfuly l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -382,6 +396,7 @@ StandardCPU: Test Completed Successfuly l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 14098; SumSQ.u64 = 3063030; Count.u64 = 224; Min.u64 = 3; Max.u64 = 526; l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 20983; SumSQ.u64 = 19350937; Count.u64 = 162; Min.u64 = 3; Max.u64 = 2453; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -452,10 +467,12 @@ StandardCPU: Test Completed Successfuly l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 490; SumSQ.u64 = 490; Count.u64 = 490; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.PutS_recv : Accumulator : Sum.u64 = 254; SumSQ.u64 = 254; Count.u64 = 254; Min.u64 = 1; Max.u64 = 1; l2cache0.PutM_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l2cache0.PutE_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; @@ -467,6 +484,9 @@ StandardCPU: Test Completed Successfuly l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NACK_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; l2cache0.AckInv_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -546,13 +566,16 @@ StandardCPU: Test Completed Successfuly l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1098; SumSQ.u64 = 1098; Count.u64 = 1098; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -560,7 +583,7 @@ StandardCPU: Test Completed Successfuly l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.evict_I : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_I : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_S : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_M : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_IS : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; @@ -579,6 +602,7 @@ StandardCPU: Test Completed Successfuly l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 22804; SumSQ.u64 = 22188830; Count.u64 = 54; Min.u64 = 74; Max.u64 = 2475; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -625,22 +649,26 @@ StandardCPU: Test Completed Successfuly l1cache1.Write_recv : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 1549; SumSQ.u64 = 1549; Count.u64 = 1549; Min.u64 = 1; Max.u64 = 1; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 259883; SumSQ.u64 = 3757437; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 16; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 3044; SumSQ.u64 = 6090; Count.u64 = 2197; Min.u64 = 0; Max.u64 = 7; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 300928; SumSQ.u64 = 111609856; Count.u64 = 2191; Min.u64 = 64; Max.u64 = 576; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 4204768; SumSQ.u64 = 144149555800; Count.u64 = 1751; Min.u64 = 1; Max.u64 = 327813; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 3044; SumSQ.u64 = 6090; Count.u64 = 2197; Min.u64 = 0; Max.u64 = 7; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 300928; SumSQ.u64 = 111609856; Count.u64 = 2191; Min.u64 = 64; Max.u64 = 576; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 4204768; SumSQ.u64 = 144149555800; Count.u64 = 1751; Min.u64 = 1; Max.u64 = 327813; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_I : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -750,8 +778,11 @@ StandardCPU: Test Completed Successfuly l2cache1.eventSent_Write : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; @@ -760,6 +791,9 @@ StandardCPU: Test Completed Successfuly l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -784,6 +818,7 @@ StandardCPU: Test Completed Successfuly l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 11285; SumSQ.u64 = 2454511; Count.u64 = 171; Min.u64 = 3; Max.u64 = 484; l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 16099; SumSQ.u64 = 11128341; Count.u64 = 178; Min.u64 = 3; Max.u64 = 2285; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -854,10 +889,12 @@ StandardCPU: Test Completed Successfuly l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.PutS_recv : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; l2cache1.PutM_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l2cache1.PutE_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; @@ -869,6 +906,9 @@ StandardCPU: Test Completed Successfuly l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NACK_recv : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; l2cache1.AckInv_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -948,13 +988,16 @@ StandardCPU: Test Completed Successfuly l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1097; SumSQ.u64 = 1097; Count.u64 = 1097; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 251; SumSQ.u64 = 251; Count.u64 = 251; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -962,7 +1005,7 @@ StandardCPU: Test Completed Successfuly l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.evict_I : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_I : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_S : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_M : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_IS : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; @@ -981,6 +1024,7 @@ StandardCPU: Test Completed Successfuly l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 26125; SumSQ.u64 = 21192971; Count.u64 = 73; Min.u64 = 81; Max.u64 = 2352; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1027,22 +1071,26 @@ StandardCPU: Test Completed Successfuly l1cache2.Write_recv : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 608; SumSQ.u64 = 608; Count.u64 = 608; Min.u64 = 1; Max.u64 = 1; l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Inv_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NACK_recv : Accumulator : Sum.u64 = 1478; SumSQ.u64 = 1478; Count.u64 = 1478; Min.u64 = 1; Max.u64 = 1; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 262024; SumSQ.u64 = 3780686; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 16; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 3051; SumSQ.u64 = 6209; Count.u64 = 2171; Min.u64 = 0; Max.u64 = 7; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 288288; SumSQ.u64 = 104340480; Count.u64 = 2165; Min.u64 = 64; Max.u64 = 576; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 4205955; SumSQ.u64 = 114152642797; Count.u64 = 1791; Min.u64 = 1; Max.u64 = 276522; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 3051; SumSQ.u64 = 6209; Count.u64 = 2171; Min.u64 = 0; Max.u64 = 7; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 288288; SumSQ.u64 = 104340480; Count.u64 = 2165; Min.u64 = 64; Max.u64 = 576; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 4205955; SumSQ.u64 = 114152642797; Count.u64 = 1791; Min.u64 = 1; Max.u64 = 276522; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_I : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1152,8 +1200,11 @@ StandardCPU: Test Completed Successfuly l2cache2.eventSent_Write : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 549; SumSQ.u64 = 549; Count.u64 = 549; Min.u64 = 1; Max.u64 = 1; @@ -1162,6 +1213,9 @@ StandardCPU: Test Completed Successfuly l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 242; SumSQ.u64 = 242; Count.u64 = 242; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1186,6 +1240,7 @@ StandardCPU: Test Completed Successfuly l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 13986; SumSQ.u64 = 2945394; Count.u64 = 216; Min.u64 = 3; Max.u64 = 395; l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 17237; SumSQ.u64 = 6885671; Count.u64 = 192; Min.u64 = 3; Max.u64 = 1780; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1256,10 +1311,12 @@ StandardCPU: Test Completed Successfuly l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.PutS_recv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l2cache2.PutM_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; l2cache2.PutE_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; @@ -1271,6 +1328,9 @@ StandardCPU: Test Completed Successfuly l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NACK_recv : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; l2cache2.AckInv_recv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1350,13 +1410,16 @@ StandardCPU: Test Completed Successfuly l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1126; SumSQ.u64 = 1126; Count.u64 = 1126; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1364,7 +1427,7 @@ StandardCPU: Test Completed Successfuly l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.evict_I : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_I : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_S : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_M : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_IS : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; @@ -1383,6 +1446,7 @@ StandardCPU: Test Completed Successfuly l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 19896; SumSQ.u64 = 29197692; Count.u64 = 55; Min.u64 = 92; Max.u64 = 4457; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1429,22 +1493,26 @@ StandardCPU: Test Completed Successfuly l1cache3.Write_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Inv_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NACK_recv : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 259042; SumSQ.u64 = 3778088; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 16; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 3170; SumSQ.u64 = 6640; Count.u64 = 2216; Min.u64 = 0; Max.u64 = 7; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 286560; SumSQ.u64 = 101569536; Count.u64 = 2211; Min.u64 = 64; Max.u64 = 576; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 4247923; SumSQ.u64 = 103032259273; Count.u64 = 1756; Min.u64 = 1; Max.u64 = 226482; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 3170; SumSQ.u64 = 6640; Count.u64 = 2216; Min.u64 = 0; Max.u64 = 7; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 286560; SumSQ.u64 = 101569536; Count.u64 = 2211; Min.u64 = 64; Max.u64 = 576; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 4247923; SumSQ.u64 = 103032259273; Count.u64 = 1756; Min.u64 = 1; Max.u64 = 226482; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_I : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1554,8 +1622,11 @@ StandardCPU: Test Completed Successfuly l2cache3.eventSent_Write : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 559; SumSQ.u64 = 559; Count.u64 = 559; Min.u64 = 1; Max.u64 = 1; @@ -1564,6 +1635,9 @@ StandardCPU: Test Completed Successfuly l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1588,6 +1662,7 @@ StandardCPU: Test Completed Successfuly l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 13287; SumSQ.u64 = 4060375; Count.u64 = 182; Min.u64 = 3; Max.u64 = 1239; l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 12020; SumSQ.u64 = 3097438; Count.u64 = 114; Min.u64 = 3; Max.u64 = 638; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1658,10 +1733,12 @@ StandardCPU: Test Completed Successfuly l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 482; SumSQ.u64 = 482; Count.u64 = 482; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.PutS_recv : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; l2cache3.PutM_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; l2cache3.PutE_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; @@ -1673,6 +1750,9 @@ StandardCPU: Test Completed Successfuly l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NACK_recv : Accumulator : Sum.u64 = 431; SumSQ.u64 = 431; Count.u64 = 431; Min.u64 = 1; Max.u64 = 1; l2cache3.AckInv_recv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1752,13 +1832,16 @@ StandardCPU: Test Completed Successfuly l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 1084; SumSQ.u64 = 1084; Count.u64 = 1084; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1785,6 +1868,7 @@ StandardCPU: Test Completed Successfuly l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 27985; SumSQ.u64 = 45934375; Count.u64 = 66; Min.u64 = 74; Max.u64 = 5067; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1831,22 +1915,26 @@ StandardCPU: Test Completed Successfuly l1cache4.Write_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 587; SumSQ.u64 = 587; Count.u64 = 587; Min.u64 = 1; Max.u64 = 1; l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Inv_recv : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NACK_recv : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 269760; SumSQ.u64 = 3936572; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 16; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 3168; SumSQ.u64 = 6482; Count.u64 = 2213; Min.u64 = 0; Max.u64 = 7; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 311904; SumSQ.u64 = 117943296; Count.u64 = 2206; Min.u64 = 64; Max.u64 = 576; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 4165943; SumSQ.u64 = 52595004515; Count.u64 = 1826; Min.u64 = 1; Max.u64 = 175608; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 3168; SumSQ.u64 = 6482; Count.u64 = 2213; Min.u64 = 0; Max.u64 = 7; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 311904; SumSQ.u64 = 117943296; Count.u64 = 2206; Min.u64 = 64; Max.u64 = 576; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 4165943; SumSQ.u64 = 52595004515; Count.u64 = 1826; Min.u64 = 1; Max.u64 = 175608; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_I : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1956,8 +2044,11 @@ StandardCPU: Test Completed Successfuly l2cache4.eventSent_Write : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; @@ -1966,6 +2057,9 @@ StandardCPU: Test Completed Successfuly l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1990,6 +2084,7 @@ StandardCPU: Test Completed Successfuly l2cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_FlushLine : Accumulator : Sum.u64 = 19991; SumSQ.u64 = 20181261; Count.u64 = 224; Min.u64 = 3; Max.u64 = 2414; l2cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 14265; SumSQ.u64 = 4058703; Count.u64 = 175; Min.u64 = 3; Max.u64 = 896; + l2cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2060,10 +2155,12 @@ StandardCPU: Test Completed Successfuly l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.PutS_recv : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; l2cache4.PutM_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2cache4.PutE_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; @@ -2075,6 +2172,9 @@ StandardCPU: Test Completed Successfuly l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NACK_recv : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; l2cache4.AckInv_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2154,13 +2254,16 @@ StandardCPU: Test Completed Successfuly l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 266; SumSQ.u64 = 266; Count.u64 = 266; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2168,7 +2271,7 @@ StandardCPU: Test Completed Successfuly l1cache5.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.evict_I : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_I : Accumulator : Sum.u64 = 375; SumSQ.u64 = 375; Count.u64 = 375; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_S : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_M : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_IS : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; @@ -2187,6 +2290,7 @@ StandardCPU: Test Completed Successfuly l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 22357; SumSQ.u64 = 14897423; Count.u64 = 74; Min.u64 = 87; Max.u64 = 2591; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2233,22 +2337,26 @@ StandardCPU: Test Completed Successfuly l1cache5.Write_recv : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Inv_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NACK_recv : Accumulator : Sum.u64 = 1420; SumSQ.u64 = 1420; Count.u64 = 1420; Min.u64 = 1; Max.u64 = 1; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 290064; SumSQ.u64 = 4307272; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 16; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 2968; SumSQ.u64 = 6052; Count.u64 = 2077; Min.u64 = 0; Max.u64 = 7; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 276928; SumSQ.u64 = 100366336; Count.u64 = 2076; Min.u64 = 64; Max.u64 = 576; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 3914914; SumSQ.u64 = 23274751654; Count.u64 = 1701; Min.u64 = 1; Max.u64 = 72082; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 2968; SumSQ.u64 = 6052; Count.u64 = 2077; Min.u64 = 0; Max.u64 = 7; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 276928; SumSQ.u64 = 100366336; Count.u64 = 2076; Min.u64 = 64; Max.u64 = 576; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 3914914; SumSQ.u64 = 23274751654; Count.u64 = 1701; Min.u64 = 1; Max.u64 = 72082; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_I : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2358,8 +2466,11 @@ StandardCPU: Test Completed Successfuly l2cache5.eventSent_Write : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; @@ -2368,6 +2479,9 @@ StandardCPU: Test Completed Successfuly l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2392,6 +2506,7 @@ StandardCPU: Test Completed Successfuly l2cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_FlushLine : Accumulator : Sum.u64 = 18674; SumSQ.u64 = 15897826; Count.u64 = 215; Min.u64 = 3; Max.u64 = 2783; l2cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 15872; SumSQ.u64 = 4306784; Count.u64 = 184; Min.u64 = 3; Max.u64 = 792; + l2cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2462,10 +2577,12 @@ StandardCPU: Test Completed Successfuly l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.PutS_recv : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; l2cache5.PutM_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; l2cache5.PutE_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; @@ -2477,15 +2594,18 @@ StandardCPU: Test Completed Successfuly l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NACK_recv : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; l2cache5.AckInv_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 120465; SumSQ.u64 = 774593; Count.u64 = 19982; Min.u64 = 0; Max.u64 = 8; l2cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 7593; SumSQ.u64 = 17043; Count.u64 = 5459; Min.u64 = 0; Max.u64 = 13; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 1307296; SumSQ.u64 = 629976064; Count.u64 = 5469; Min.u64 = 64; Max.u64 = 576; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 2011358; SumSQ.u64 = 5935237452; Count.u64 = 1764; Min.u64 = 4; Max.u64 = 35328; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 7593; SumSQ.u64 = 17043; Count.u64 = 5459; Min.u64 = 0; Max.u64 = 13; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 1307296; SumSQ.u64 = 629976064; Count.u64 = 5469; Min.u64 = 64; Max.u64 = 576; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 2011358; SumSQ.u64 = 5935237452; Count.u64 = 1764; Min.u64 = 4; Max.u64 = 35328; l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2595,8 +2715,11 @@ StandardCPU: Test Completed Successfuly l3cache0.eventSent_Write : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2605,6 +2728,9 @@ StandardCPU: Test Completed Successfuly l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2629,6 +2755,7 @@ StandardCPU: Test Completed Successfuly l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 12373; SumSQ.u64 = 1131419; Count.u64 = 277; Min.u64 = 7; Max.u64 = 194; l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 13810; SumSQ.u64 = 1569712; Count.u64 = 270; Min.u64 = 7; Max.u64 = 419; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 483; SumSQ.u64 = 483; Count.u64 = 483; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2699,10 +2826,12 @@ StandardCPU: Test Completed Successfuly l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2714,15 +2843,18 @@ StandardCPU: Test Completed Successfuly l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NACK_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l3cache0.AckInv_recv : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 62110; SumSQ.u64 = 370202; Count.u64 = 11670; Min.u64 = 0; Max.u64 = 7; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 7133; SumSQ.u64 = 16153; Count.u64 = 5000; Min.u64 = 0; Max.u64 = 12; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 1252096; SumSQ.u64 = 614410240; Count.u64 = 5005; Min.u64 = 64; Max.u64 = 576; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 2215352; SumSQ.u64 = 10129413768; Count.u64 = 1781; Min.u64 = 4; Max.u64 = 72022; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 7133; SumSQ.u64 = 16153; Count.u64 = 5000; Min.u64 = 0; Max.u64 = 12; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 1252096; SumSQ.u64 = 614410240; Count.u64 = 5005; Min.u64 = 64; Max.u64 = 576; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 2215352; SumSQ.u64 = 10129413768; Count.u64 = 1781; Min.u64 = 4; Max.u64 = 72022; l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2832,8 +2964,11 @@ StandardCPU: Test Completed Successfuly l3cache1.eventSent_Write : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2842,6 +2977,9 @@ StandardCPU: Test Completed Successfuly l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 507; SumSQ.u64 = 507; Count.u64 = 507; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2866,6 +3004,7 @@ StandardCPU: Test Completed Successfuly l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 10850; SumSQ.u64 = 955004; Count.u64 = 222; Min.u64 = 7; Max.u64 = 233; l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 12244; SumSQ.u64 = 1429088; Count.u64 = 202; Min.u64 = 7; Max.u64 = 340; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 778; SumSQ.u64 = 778; Count.u64 = 778; Min.u64 = 1; Max.u64 = 1; l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2936,10 +3075,12 @@ StandardCPU: Test Completed Successfuly l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2951,15 +3092,18 @@ StandardCPU: Test Completed Successfuly l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 379; SumSQ.u64 = 379; Count.u64 = 379; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NACK_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l3cache1.AckInv_recv : Accumulator : Sum.u64 = 1119; SumSQ.u64 = 1119; Count.u64 = 1119; Min.u64 = 1; Max.u64 = 1; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 60060; SumSQ.u64 = 346898; Count.u64 = 11670; Min.u64 = 0; Max.u64 = 7; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 6449; SumSQ.u64 = 14425; Count.u64 = 4617; Min.u64 = 0; Max.u64 = 14; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 1223008; SumSQ.u64 = 609350656; Count.u64 = 4631; Min.u64 = 64; Max.u64 = 576; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 2361322; SumSQ.u64 = 16823803636; Count.u64 = 1789; Min.u64 = 4; Max.u64 = 105414; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 6449; SumSQ.u64 = 14425; Count.u64 = 4617; Min.u64 = 0; Max.u64 = 14; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 1223008; SumSQ.u64 = 609350656; Count.u64 = 4631; Min.u64 = 64; Max.u64 = 576; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 2361322; SumSQ.u64 = 16823803636; Count.u64 = 1789; Min.u64 = 4; Max.u64 = 105414; l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3069,8 +3213,11 @@ StandardCPU: Test Completed Successfuly l3cache2.eventSent_Write : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3079,6 +3226,9 @@ StandardCPU: Test Completed Successfuly l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 520; SumSQ.u64 = 520; Count.u64 = 520; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3103,6 +3253,7 @@ StandardCPU: Test Completed Successfuly l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 11521; SumSQ.u64 = 1141845; Count.u64 = 216; Min.u64 = 7; Max.u64 = 221; l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 12287; SumSQ.u64 = 1241683; Count.u64 = 184; Min.u64 = 7; Max.u64 = 323; + l3cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 372; SumSQ.u64 = 372; Count.u64 = 372; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3173,10 +3324,12 @@ StandardCPU: Test Completed Successfuly l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 221; SumSQ.u64 = 221; Count.u64 = 221; Min.u64 = 1; Max.u64 = 1; l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3188,15 +3341,18 @@ StandardCPU: Test Completed Successfuly l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NACK_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; l3cache2.AckInv_recv : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 57366; SumSQ.u64 = 326314; Count.u64 = 11670; Min.u64 = 0; Max.u64 = 7; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 2747; Count.u64 = 999; Min.u64 = 0; Max.u64 = 6; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 353856; SumSQ.u64 = 185401344; Count.u64 = 999; Min.u64 = 64; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 3988272; SumSQ.u64 = 65827075680; Count.u64 = 714; Min.u64 = 28; Max.u64 = 125044; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 1409; SumSQ.u64 = 2747; Count.u64 = 999; Min.u64 = 0; Max.u64 = 6; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 353856; SumSQ.u64 = 185401344; Count.u64 = 999; Min.u64 = 64; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 3988272; SumSQ.u64 = 65827075680; Count.u64 = 714; Min.u64 = 28; Max.u64 = 125044; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 11522; SumSQ.u64 = 719240; Count.u64 = 401; Min.u64 = 5; Max.u64 = 152; directory0.get_request_latency : Accumulator : Sum.u64 = 8819; SumSQ.u64 = 486919; Count.u64 = 322; Min.u64 = 2; Max.u64 = 162; @@ -3219,8 +3375,10 @@ StandardCPU: Test Completed Successfuly directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; @@ -3239,6 +3397,7 @@ StandardCPU: Test Completed Successfuly directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; @@ -3249,6 +3408,8 @@ StandardCPU: Test Completed Successfuly directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 202; SumSQ.u64 = 202; Count.u64 = 202; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 18895; SumSQ.u64 = 63495; Count.u64 = 11517; Min.u64 = 0; Max.u64 = 10; @@ -3269,10 +3430,10 @@ StandardCPU: Test Completed Successfuly memory0.cycles_with_issue : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; memory0.total_cycles : Accumulator : Sum.u64 = 4166; SumSQ.u64 = 17355556; Count.u64 = 1; Min.u64 = 4166; Max.u64 = 4166; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 1415; SumSQ.u64 = 2667; Count.u64 = 1036; Min.u64 = 0; Max.u64 = 7; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 360416; SumSQ.u64 = 188435456; Count.u64 = 1036; Min.u64 = 64; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 4205274; SumSQ.u64 = 48391567812; Count.u64 = 782; Min.u64 = 10; Max.u64 = 56800; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 1415; SumSQ.u64 = 2667; Count.u64 = 1036; Min.u64 = 0; Max.u64 = 7; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 360416; SumSQ.u64 = 188435456; Count.u64 = 1036; Min.u64 = 64; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 4205274; SumSQ.u64 = 48391567812; Count.u64 = 782; Min.u64 = 10; Max.u64 = 56800; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 11724; SumSQ.u64 = 694568; Count.u64 = 436; Min.u64 = 5; Max.u64 = 151; directory1.get_request_latency : Accumulator : Sum.u64 = 10275; SumSQ.u64 = 683341; Count.u64 = 337; Min.u64 = 2; Max.u64 = 174; @@ -3295,8 +3456,10 @@ StandardCPU: Test Completed Successfuly directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 436; SumSQ.u64 = 436; Count.u64 = 436; Min.u64 = 1; Max.u64 = 1; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; @@ -3315,6 +3478,7 @@ StandardCPU: Test Completed Successfuly directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; @@ -3325,6 +3489,8 @@ StandardCPU: Test Completed Successfuly directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 436; SumSQ.u64 = 436; Count.u64 = 436; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 20453; SumSQ.u64 = 70257; Count.u64 = 11641; Min.u64 = 0; Max.u64 = 11; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio.out index d51615ddc7..ded2eef65b 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio.out @@ -1139,17 +1139,17 @@ core: 1 Issued MMIO Write for address 0x400 with payload -31081 Handle Read. Returning 816130624 Handle Write. Squared is 966028561 StandardCPU: Test Completed Successfuly - core:memory:memlink.packet_latency : Accumulator : Sum.u64 = 142568; SumSQ.u64 = 24100456; Count.u64 = 956; Min.u64 = 71; Max.u64 = 359; - core:memory:memlink.send_bit_count : Accumulator : Sum.u64 = 87168; SumSQ.u64 = 7802880; Count.u64 = 1000; Min.u64 = 64; Max.u64 = 96; - core:memory:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core:memory:memlink.idle_time : Accumulator : Sum.u64 = 789000; SumSQ.u64 = 76906500000; Count.u64 = 9; Min.u64 = 71000; Max.u64 = 144000; + core:memory:lowlink.packet_latency : Accumulator : Sum.u64 = 142568; SumSQ.u64 = 24100456; Count.u64 = 956; Min.u64 = 71; Max.u64 = 359; + core:memory:lowlink.send_bit_count : Accumulator : Sum.u64 = 87168; SumSQ.u64 = 7802880; Count.u64 = 1000; Min.u64 = 64; Max.u64 = 96; + core:memory:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + core:memory:lowlink.idle_time : Accumulator : Sum.u64 = 789000; SumSQ.u64 = 76906500000; Count.u64 = 9; Min.u64 = 71000; Max.u64 = 144000; core.pendCycle : Accumulator : Sum.u64 = 1454681; SumSQ.u64 = 14480683; Count.u64 = 146739; Min.u64 = 0; Max.u64 = 10; core.reads : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; core.writes : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; - l1cache:cpulink.packet_latency : Accumulator : Sum.u64 = 340763; SumSQ.u64 = 135350911; Count.u64 = 876; Min.u64 = 43; Max.u64 = 573; - l1cache:cpulink.send_bit_count : Accumulator : Sum.u64 = 83584; SumSQ.u64 = 7991296; Count.u64 = 876; Min.u64 = 64; Max.u64 = 96; - l1cache:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache:cpulink.idle_time : Accumulator : Sum.u64 = 5860500; SumSQ.u64 = 583843250000; Count.u64 = 69; Min.u64 = 70500; Max.u64 = 217000; + l1cache:highlink.packet_latency : Accumulator : Sum.u64 = 340763; SumSQ.u64 = 135350911; Count.u64 = 876; Min.u64 = 43; Max.u64 = 573; + l1cache:highlink.send_bit_count : Accumulator : Sum.u64 = 83584; SumSQ.u64 = 7991296; Count.u64 = 876; Min.u64 = 64; Max.u64 = 96; + l1cache:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache:highlink.idle_time : Accumulator : Sum.u64 = 5860500; SumSQ.u64 = 583843250000; Count.u64 = 69; Min.u64 = 70500; Max.u64 = 217000; l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -1217,13 +1217,16 @@ StandardCPU: Test Completed Successfuly l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1231,7 +1234,7 @@ StandardCPU: Test Completed Successfuly l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1250,6 +1253,7 @@ StandardCPU: Test Completed Successfuly l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1287,22 +1291,26 @@ StandardCPU: Test Completed Successfuly l1cache.Write_recv : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 17714; SumSQ.u64 = 49976; Count.u64 = 146739; Min.u64 = 0; Max.u64 = 5; l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - mmio:iface:memlink.packet_latency : Accumulator : Sum.u64 = 57331; SumSQ.u64 = 23982447; Count.u64 = 140; Min.u64 = 144; Max.u64 = 644; - mmio:iface:memlink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 884736; Count.u64 = 96; Min.u64 = 96; Max.u64 = 96; - mmio:iface:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - mmio:iface:memlink.idle_time : Accumulator : Sum.u64 = 41904500; SumSQ.u64 = 38341152250000; Count.u64 = 83; Min.u64 = 72000; Max.u64 = 2160000; + mmio:iface:lowlink.packet_latency : Accumulator : Sum.u64 = 57331; SumSQ.u64 = 23982447; Count.u64 = 140; Min.u64 = 144; Max.u64 = 644; + mmio:iface:lowlink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 884736; Count.u64 = 96; Min.u64 = 96; Max.u64 = 96; + mmio:iface:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio:iface:lowlink.idle_time : Accumulator : Sum.u64 = 41904500; SumSQ.u64 = 38341152250000; Count.u64 = 83; Min.u64 = 72000; Max.u64 = 2160000; memory.requests_received_GetS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; memory.requests_received_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.requests_received_GetX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -1317,8 +1325,8 @@ StandardCPU: Test Completed Successfuly memory.cycles_with_issue : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.total_cycles : Accumulator : Sum.u64 = 73369; SumSQ.u64 = 5383010161; Count.u64 = 1; Min.u64 = 73369; Max.u64 = 73369; - memory:cpulink.packet_latency : Accumulator : Sum.u64 = 2649; SumSQ.u64 = 497967; Count.u64 = 16; Min.u64 = 71; Max.u64 = 287; - memory:cpulink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 5308416; Count.u64 = 16; Min.u64 = 576; Max.u64 = 576; - memory:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory:cpulink.idle_time : Accumulator : Sum.u64 = 70891500; SumSQ.u64 = 4569827188250000; Count.u64 = 12; Min.u64 = 43000; Max.u64 = 67579500; + memory:highlink.packet_latency : Accumulator : Sum.u64 = 2649; SumSQ.u64 = 497967; Count.u64 = 16; Min.u64 = 71; Max.u64 = 287; + memory:highlink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 5308416; Count.u64 = 16; Min.u64 = 576; Max.u64 = 576; + memory:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory:highlink.idle_time : Accumulator : Sum.u64 = 70891500; SumSQ.u64 = 4569827188250000; Count.u64 = 12; Min.u64 = 43000; Max.u64 = 67579500; Simulation is complete, simulated time: 73.3695 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio2.out index fc430266e2..e130dfe90c 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio2.out @@ -1511,10 +1511,10 @@ StandardCPU: Test Completed Successfuly core.pendCycle : Accumulator : Sum.u64 = 880761; SumSQ.u64 = 8741651; Count.u64 = 89575; Min.u64 = 0; Max.u64 = 10; core.reads : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; core.writes : Accumulator : Sum.u64 = 658; SumSQ.u64 = 658; Count.u64 = 658; Min.u64 = 1; Max.u64 = 1; - l1cache:memlink.packet_latency : Accumulator : Sum.u64 = 41688; SumSQ.u64 = 19100008; Count.u64 = 194; Min.u64 = 38; Max.u64 = 1153; - l1cache:memlink.send_bit_count : Accumulator : Sum.u64 = 32992; SumSQ.u64 = 12000256; Count.u64 = 226; Min.u64 = 64; Max.u64 = 576; - l1cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache:memlink.idle_time : Accumulator : Sum.u64 = 25411000; SumSQ.u64 = 80564581500000; Count.u64 = 58; Min.u64 = 59000; Max.u64 = 7342500; + l1cache:lowlink.packet_latency : Accumulator : Sum.u64 = 41688; SumSQ.u64 = 19100008; Count.u64 = 194; Min.u64 = 38; Max.u64 = 1153; + l1cache:lowlink.send_bit_count : Accumulator : Sum.u64 = 32992; SumSQ.u64 = 12000256; Count.u64 = 226; Min.u64 = 64; Max.u64 = 576; + l1cache:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache:lowlink.idle_time : Accumulator : Sum.u64 = 25411000; SumSQ.u64 = 80564581500000; Count.u64 = 58; Min.u64 = 59000; Max.u64 = 7342500; l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -1582,13 +1582,16 @@ StandardCPU: Test Completed Successfuly l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1596,7 +1599,7 @@ StandardCPU: Test Completed Successfuly l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1615,6 +1618,7 @@ StandardCPU: Test Completed Successfuly l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 590; SumSQ.u64 = 590; Count.u64 = 590; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1652,26 +1656,30 @@ StandardCPU: Test Completed Successfuly l1cache.Write_recv : Accumulator : Sum.u64 = 658; SumSQ.u64 = 658; Count.u64 = 658; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 127058; SumSQ.u64 = 632840; Count.u64 = 89575; Min.u64 = 0; Max.u64 = 10; l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - mmio:iface:memlink.packet_latency : Accumulator : Sum.u64 = 118712; SumSQ.u64 = 35013530; Count.u64 = 509; Min.u64 = 37; Max.u64 = 646; - mmio:iface:memlink.send_bit_count : Accumulator : Sum.u64 = 129760; SumSQ.u64 = 64279552; Count.u64 = 477; Min.u64 = 64; Max.u64 = 576; - mmio:iface:memlink.output_port_stalls : Accumulator : Sum.u64 = 3023000; SumSQ.u64 = 217585000000; Count.u64 = 42; Min.u64 = 71000; Max.u64 = 72000; - mmio:iface:memlink.idle_time : Accumulator : Sum.u64 = 1513500; SumSQ.u64 = 140186250000; Count.u64 = 19; Min.u64 = 72000; Max.u64 = 216000; - directory:cpulink.packet_latency : Accumulator : Sum.u64 = 518010; SumSQ.u64 = 636018966; Count.u64 = 517; Min.u64 = 70; Max.u64 = 2089; - directory:cpulink.send_bit_count : Accumulator : Sum.u64 = 266048; SumSQ.u64 = 151212032; Count.u64 = 517; Min.u64 = 64; Max.u64 = 576; - directory:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory:cpulink.idle_time : Accumulator : Sum.u64 = 6852500; SumSQ.u64 = 36310363250000; Count.u64 = 11; Min.u64 = 38000; Max.u64 = 6017500; + mmio:iface:lowlink.packet_latency : Accumulator : Sum.u64 = 118712; SumSQ.u64 = 35013530; Count.u64 = 509; Min.u64 = 37; Max.u64 = 646; + mmio:iface:lowlink.send_bit_count : Accumulator : Sum.u64 = 129760; SumSQ.u64 = 64279552; Count.u64 = 477; Min.u64 = 64; Max.u64 = 576; + mmio:iface:lowlink.output_port_stalls : Accumulator : Sum.u64 = 3023000; SumSQ.u64 = 217585000000; Count.u64 = 42; Min.u64 = 71000; Max.u64 = 72000; + mmio:iface:lowlink.idle_time : Accumulator : Sum.u64 = 1513500; SumSQ.u64 = 140186250000; Count.u64 = 19; Min.u64 = 72000; Max.u64 = 216000; + directory:highlink.packet_latency : Accumulator : Sum.u64 = 518010; SumSQ.u64 = 636018966; Count.u64 = 517; Min.u64 = 70; Max.u64 = 2089; + directory:highlink.send_bit_count : Accumulator : Sum.u64 = 266048; SumSQ.u64 = 151212032; Count.u64 = 517; Min.u64 = 64; Max.u64 = 576; + directory:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory:highlink.idle_time : Accumulator : Sum.u64 = 6852500; SumSQ.u64 = 36310363250000; Count.u64 = 11; Min.u64 = 38000; Max.u64 = 6017500; directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.replacement_request_latency : Accumulator : Sum.u64 = 130984; SumSQ.u64 = 220224840; Count.u64 = 189; Min.u64 = 210; Max.u64 = 4098; directory.get_request_latency : Accumulator : Sum.u64 = 100505; SumSQ.u64 = 90578849; Count.u64 = 273; Min.u64 = 2; Max.u64 = 2212; @@ -1694,8 +1702,10 @@ StandardCPU: Test Completed Successfuly directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.AckInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + directory.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1714,6 +1724,7 @@ StandardCPU: Test Completed Successfuly directory.eventSent_FetchInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_GetSResp : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; directory.eventSent_GetXResp : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; @@ -1724,6 +1735,8 @@ StandardCPU: Test Completed Successfuly directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.MSHR_occupancy : Accumulator : Sum.u64 = 230565; SumSQ.u64 = 997821; Count.u64 = 77252; Min.u64 = 0; Max.u64 = 10; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio3.out index a658c9ce73..108713758e 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_mmio3.out @@ -1136,10 +1136,10 @@ StandardCPU: Test Completed Successfuly core.pendCycle : Accumulator : Sum.u64 = 258668; SumSQ.u64 = 2502048; Count.u64 = 27655; Min.u64 = 0; Max.u64 = 10; core.reads : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; core.writes : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; - cpu_l1cache:memlink.packet_latency : Accumulator : Sum.u64 = 17943; SumSQ.u64 = 2905293; Count.u64 = 120; Min.u64 = 71; Max.u64 = 360; - cpu_l1cache:memlink.send_bit_count : Accumulator : Sum.u64 = 15296; SumSQ.u64 = 2945024; Count.u64 = 159; Min.u64 = 64; Max.u64 = 576; - cpu_l1cache:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu_l1cache:memlink.idle_time : Accumulator : Sum.u64 = 1534000; SumSQ.u64 = 262631000000; Count.u64 = 12; Min.u64 = 62500; Max.u64 = 286000; + cpu_l1cache:lowlink.packet_latency : Accumulator : Sum.u64 = 17943; SumSQ.u64 = 2905293; Count.u64 = 120; Min.u64 = 71; Max.u64 = 360; + cpu_l1cache:lowlink.send_bit_count : Accumulator : Sum.u64 = 15296; SumSQ.u64 = 2945024; Count.u64 = 159; Min.u64 = 64; Max.u64 = 576; + cpu_l1cache:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache:lowlink.idle_time : Accumulator : Sum.u64 = 1534000; SumSQ.u64 = 262631000000; Count.u64 = 12; Min.u64 = 62500; Max.u64 = 286000; cpu_l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -1207,13 +1207,16 @@ StandardCPU: Test Completed Successfuly cpu_l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1221,7 +1224,7 @@ StandardCPU: Test Completed Successfuly cpu_l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu_l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + cpu_l1cache.evict_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1240,6 +1243,7 @@ StandardCPU: Test Completed Successfuly cpu_l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 611; SumSQ.u64 = 611; Count.u64 = 611; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1277,22 +1281,26 @@ StandardCPU: Test Completed Successfuly cpu_l1cache.Write_recv : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.GetSResp_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.GetXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.FetchInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; cpu_l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + cpu_l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu_l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 91071; SumSQ.u64 = 770319; Count.u64 = 27655; Min.u64 = 0; Max.u64 = 10; cpu_l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - mmio_l1:memlink.packet_latency : Accumulator : Sum.u64 = 17430; SumSQ.u64 = 2392126; Count.u64 = 139; Min.u64 = 64; Max.u64 = 359; - mmio_l1:memlink.send_bit_count : Accumulator : Sum.u64 = 11360; SumSQ.u64 = 2186240; Count.u64 = 100; Min.u64 = 64; Max.u64 = 576; - mmio_l1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - mmio_l1:memlink.idle_time : Accumulator : Sum.u64 = 4175000; SumSQ.u64 = 1066267000000; Count.u64 = 32; Min.u64 = 69000; Max.u64 = 574500; + mmio_l1:lowlink.packet_latency : Accumulator : Sum.u64 = 17430; SumSQ.u64 = 2392126; Count.u64 = 139; Min.u64 = 64; Max.u64 = 359; + mmio_l1:lowlink.send_bit_count : Accumulator : Sum.u64 = 11360; SumSQ.u64 = 2186240; Count.u64 = 100; Min.u64 = 64; Max.u64 = 576; + mmio_l1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1:lowlink.idle_time : Accumulator : Sum.u64 = 4175000; SumSQ.u64 = 1066267000000; Count.u64 = 32; Min.u64 = 69000; Max.u64 = 574500; mmio_l1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; mmio_l1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1360,13 +1368,16 @@ StandardCPU: Test Completed Successfuly mmio_l1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_FetchResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; mmio_l1.eventSent_FetchXResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; mmio_l1.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + mmio_l1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_GetSResp : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; mmio_l1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_WriteResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; mmio_l1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1393,6 +1404,7 @@ StandardCPU: Test Completed Successfuly mmio_l1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1430,22 +1442,26 @@ StandardCPU: Test Completed Successfuly mmio_l1.Write_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; mmio_l1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.GetXResp_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; mmio_l1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; mmio_l1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.FetchInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; mmio_l1.FetchInvX_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + mmio_l1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + mmio_l1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmio_l1.MSHR_occupancy : Accumulator : Sum.u64 = 10768; SumSQ.u64 = 38570; Count.u64 = 27655; Min.u64 = 0; Max.u64 = 4; mmio_l1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory:cpulink.packet_latency : Accumulator : Sum.u64 = 13083; SumSQ.u64 = 4205925; Count.u64 = 54; Min.u64 = 65; Max.u64 = 648; - directory:cpulink.send_bit_count : Accumulator : Sum.u64 = 19072; SumSQ.u64 = 10067968; Count.u64 = 58; Min.u64 = 64; Max.u64 = 576; - directory:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory:cpulink.idle_time : Accumulator : Sum.u64 = 9214500; SumSQ.u64 = 68766414250000; Count.u64 = 7; Min.u64 = 70500; Max.u64 = 8281000; + directory:highlink.packet_latency : Accumulator : Sum.u64 = 13083; SumSQ.u64 = 4205925; Count.u64 = 54; Min.u64 = 65; Max.u64 = 648; + directory:highlink.send_bit_count : Accumulator : Sum.u64 = 19072; SumSQ.u64 = 10067968; Count.u64 = 58; Min.u64 = 64; Max.u64 = 576; + directory:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory:highlink.idle_time : Accumulator : Sum.u64 = 9214500; SumSQ.u64 = 68766414250000; Count.u64 = 7; Min.u64 = 70500; Max.u64 = 8281000; directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.get_request_latency : Accumulator : Sum.u64 = 35057; SumSQ.u64 = 48710179; Count.u64 = 27; Min.u64 = 867; Max.u64 = 2451; @@ -1468,8 +1484,10 @@ StandardCPU: Test Completed Successfuly directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.AckInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + directory.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1488,6 +1506,7 @@ StandardCPU: Test Completed Successfuly directory.eventSent_FetchInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_GetSResp : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; directory.eventSent_GetXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; @@ -1498,6 +1517,8 @@ StandardCPU: Test Completed Successfuly directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.MSHR_occupancy : Accumulator : Sum.u64 = 35003; SumSQ.u64 = 158317; Count.u64 = 10805; Min.u64 = 0; Max.u64 = 7; @@ -1515,8 +1536,8 @@ StandardCPU: Test Completed Successfuly memory.cycles_with_issue : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.total_cycles : Accumulator : Sum.u64 = 13827; SumSQ.u64 = 191185929; Count.u64 = 1; Min.u64 = 13827; Max.u64 = 13827; - memory:cpulink.packet_latency : Accumulator : Sum.u64 = 2792; SumSQ.u64 = 436048; Count.u64 = 20; Min.u64 = 71; Max.u64 = 287; - memory:cpulink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 5308416; Count.u64 = 16; Min.u64 = 576; Max.u64 = 576; - memory:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory:cpulink.idle_time : Accumulator : Sum.u64 = 2448000; SumSQ.u64 = 750656000000; Count.u64 = 11; Min.u64 = 43000; Max.u64 = 433000; + memory:highlink.packet_latency : Accumulator : Sum.u64 = 2792; SumSQ.u64 = 436048; Count.u64 = 20; Min.u64 = 71; Max.u64 = 287; + memory:highlink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 5308416; Count.u64 = 16; Min.u64 = 576; Max.u64 = 576; + memory:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory:highlink.idle_time : Accumulator : Sum.u64 = 2448000; SumSQ.u64 = 750656000000; Count.u64 = 11; Min.u64 = 43000; Max.u64 = 433000; Simulation is complete, simulated time: 13.8275 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_nic.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_nic.out index 22f0bcc658..7ebe854fb5 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_nic.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_nic.out @@ -1,17 +1,17 @@ StandardCPU: Test Completed Successfuly - core:memory:memlink.packet_latency : Accumulator : Sum.u64 = 138768; SumSQ.u64 = 19412280; Count.u64 = 1000; Min.u64 = 69; Max.u64 = 141; - core:memory:memlink.send_bit_count : Accumulator : Sum.u64 = 86240; SumSQ.u64 = 7654400; Count.u64 = 1000; Min.u64 = 64; Max.u64 = 96; - core:memory:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core:memory:memlink.idle_time : Accumulator : Sum.u64 = 933000; SumSQ.u64 = 170657000000; Count.u64 = 9; Min.u64 = 68000; Max.u64 = 360000; + core:memory:lowlink.packet_latency : Accumulator : Sum.u64 = 138768; SumSQ.u64 = 19412280; Count.u64 = 1000; Min.u64 = 69; Max.u64 = 141; + core:memory:lowlink.send_bit_count : Accumulator : Sum.u64 = 86240; SumSQ.u64 = 7654400; Count.u64 = 1000; Min.u64 = 64; Max.u64 = 96; + core:memory:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + core:memory:lowlink.idle_time : Accumulator : Sum.u64 = 933000; SumSQ.u64 = 170657000000; Count.u64 = 9; Min.u64 = 68000; Max.u64 = 360000; core.pendCycle : Accumulator : Sum.u64 = 725240; SumSQ.u64 = 7169682; Count.u64 = 73658; Min.u64 = 0; Max.u64 = 10; core.reads : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; core.writes : Accumulator : Sum.u64 = 601; SumSQ.u64 = 601; Count.u64 = 601; Min.u64 = 1; Max.u64 = 1; core.llsc : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; core.llsc_success : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; - c0.l1cache:cpulink.packet_latency : Accumulator : Sum.u64 = 295622; SumSQ.u64 = 87493070; Count.u64 = 1016; Min.u64 = 115; Max.u64 = 720; - c0.l1cache:cpulink.send_bit_count : Accumulator : Sum.u64 = 97024; SumSQ.u64 = 9281536; Count.u64 = 1016; Min.u64 = 64; Max.u64 = 96; - c0.l1cache:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - c0.l1cache:cpulink.idle_time : Accumulator : Sum.u64 = 356000; SumSQ.u64 = 56750000000; Count.u64 = 3; Min.u64 = 69000; Max.u64 = 217000; + c0.l1cache:highlink.packet_latency : Accumulator : Sum.u64 = 295622; SumSQ.u64 = 87493070; Count.u64 = 1016; Min.u64 = 115; Max.u64 = 720; + c0.l1cache:highlink.send_bit_count : Accumulator : Sum.u64 = 97024; SumSQ.u64 = 9281536; Count.u64 = 1016; Min.u64 = 64; Max.u64 = 96; + c0.l1cache:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache:highlink.idle_time : Accumulator : Sum.u64 = 356000; SumSQ.u64 = 56750000000; Count.u64 = 3; Min.u64 = 69000; Max.u64 = 217000; c0.l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; c0.l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -79,13 +79,16 @@ StandardCPU: Test Completed Successfuly c0.l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; c0.l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -93,7 +96,7 @@ StandardCPU: Test Completed Successfuly c0.l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - c0.l1cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + c0.l1cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; c0.l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -112,6 +115,7 @@ StandardCPU: Test Completed Successfuly c0.l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; c0.l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; c0.l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; @@ -149,14 +153,18 @@ StandardCPU: Test Completed Successfuly c0.l1cache.Write_recv : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; c0.l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + c0.l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; c0.l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 27658; SumSQ.u64 = 114676; Count.u64 = 147316; Min.u64 = 0; Max.u64 = 7; @@ -175,8 +183,8 @@ StandardCPU: Test Completed Successfuly memory.cycles_with_issue : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory.total_cycles : Accumulator : Sum.u64 = 73658; SumSQ.u64 = 5425500964; Count.u64 = 1; Min.u64 = 73658; Max.u64 = 73658; - memory:cpulink.packet_latency : Accumulator : Sum.u64 = 2184; SumSQ.u64 = 302976; Count.u64 = 16; Min.u64 = 69; Max.u64 = 141; - memory:cpulink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 5308416; Count.u64 = 16; Min.u64 = 576; Max.u64 = 576; - memory:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory:cpulink.idle_time : Accumulator : Sum.u64 = 71641000; SumSQ.u64 = 4687031637000000; Count.u64 = 8; Min.u64 = 43000; Max.u64 = 68444000; + memory:highlink.packet_latency : Accumulator : Sum.u64 = 2184; SumSQ.u64 = 302976; Count.u64 = 16; Min.u64 = 69; Max.u64 = 141; + memory:highlink.send_bit_count : Accumulator : Sum.u64 = 9216; SumSQ.u64 = 5308416; Count.u64 = 16; Min.u64 = 576; Max.u64 = 576; + memory:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory:highlink.idle_time : Accumulator : Sum.u64 = 71641000; SumSQ.u64 = 4687031637000000; Count.u64 = 8; Min.u64 = 43000; Max.u64 = 68444000; Simulation is complete, simulated time: 73.658 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_noninclusive.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_noninclusive.out index 73969c9e96..7ac0d70f74 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_noninclusive.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_StdMem_noninclusive.out @@ -73,13 +73,16 @@ StandardCPU: Test Completed Successfuly l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 6727; SumSQ.u64 = 6727; Count.u64 = 6727; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 3273; SumSQ.u64 = 3273; Count.u64 = 3273; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -106,6 +109,7 @@ StandardCPU: Test Completed Successfuly l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -143,14 +147,18 @@ StandardCPU: Test Completed Successfuly l1cache.Write_recv : Accumulator : Sum.u64 = 3256; SumSQ.u64 = 3256; Count.u64 = 3256; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 6676; SumSQ.u64 = 6676; Count.u64 = 6676; Min.u64 = 1; Max.u64 = 1; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 3254; SumSQ.u64 = 3254; Count.u64 = 3254; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 4680296; SumSQ.u64 = 15519432; Count.u64 = 2009996; Min.u64 = 0; Max.u64 = 10; @@ -264,8 +272,11 @@ StandardCPU: Test Completed Successfuly l2cache.eventSent_Write : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache.eventSent_PutS : Accumulator : Sum.u64 = 6082; SumSQ.u64 = 6082; Count.u64 = 6082; Min.u64 = 1; Max.u64 = 1; l2cache.eventSent_PutM : Accumulator : Sum.u64 = 3065; SumSQ.u64 = 3065; Count.u64 = 3065; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -274,6 +285,9 @@ StandardCPU: Test Completed Successfuly l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 3254; SumSQ.u64 = 3254; Count.u64 = 3254; Min.u64 = 1; Max.u64 = 1; l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -298,6 +312,7 @@ StandardCPU: Test Completed Successfuly l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -333,10 +348,12 @@ StandardCPU: Test Completed Successfuly l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.GetSResp_recv : Accumulator : Sum.u64 = 6503; SumSQ.u64 = 6503; Count.u64 = 6503; Min.u64 = 1; Max.u64 = 1; l2cache.GetXResp_recv : Accumulator : Sum.u64 = 3225; SumSQ.u64 = 3225; Count.u64 = 3225; Min.u64 = 1; Max.u64 = 1; l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.PutS_recv : Accumulator : Sum.u64 = 6619; SumSQ.u64 = 6619; Count.u64 = 6619; Min.u64 = 1; Max.u64 = 1; l2cache.PutM_recv : Accumulator : Sum.u64 = 3239; SumSQ.u64 = 3239; Count.u64 = 3239; Min.u64 = 1; Max.u64 = 1; l2cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -348,6 +365,9 @@ StandardCPU: Test Completed Successfuly l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -462,8 +482,11 @@ StandardCPU: Test Completed Successfuly l3cache.eventSent_Write : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_PutS : Accumulator : Sum.u64 = 5511; SumSQ.u64 = 5511; Count.u64 = 5511; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2843; SumSQ.u64 = 2843; Count.u64 = 2843; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -472,6 +495,9 @@ StandardCPU: Test Completed Successfuly l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 3225; SumSQ.u64 = 3225; Count.u64 = 3225; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -496,6 +522,7 @@ StandardCPU: Test Completed Successfuly l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -531,10 +558,12 @@ StandardCPU: Test Completed Successfuly l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetXResp_recv : Accumulator : Sum.u64 = 9378; SumSQ.u64 = 9378; Count.u64 = 9378; Min.u64 = 1; Max.u64 = 1; l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutS_recv : Accumulator : Sum.u64 = 6082; SumSQ.u64 = 6082; Count.u64 = 6082; Min.u64 = 1; Max.u64 = 1; l3cache.PutM_recv : Accumulator : Sum.u64 = 3065; SumSQ.u64 = 3065; Count.u64 = 3065; Min.u64 = 1; Max.u64 = 1; l3cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -546,6 +575,9 @@ StandardCPU: Test Completed Successfuly l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out index ae39533d0f..a8bf0e68d4 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHA_ThroughputThrottling.out @@ -1,32 +1,32 @@ - core0.pendCycle : Accumulator : Sum.u64 = 892449; SumSQ.u64 = 13943525; Count.u64 = 57340; Min.u64 = 0; Max.u64 = 16; - core0.reads : Accumulator : Sum.u64 = 3026; SumSQ.u64 = 3026; Count.u64 = 3026; Min.u64 = 1; Max.u64 = 1; - core0.writes : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; - l1cache0.Prefetch_requests : Accumulator : Sum.u64 = 3553; SumSQ.u64 = 3553; Count.u64 = 3553; Min.u64 = 1; Max.u64 = 1; - l1cache0.Prefetch_drops : Accumulator : Sum.u64 = 2335; SumSQ.u64 = 2335; Count.u64 = 2335; Min.u64 = 1; Max.u64 = 1; + core0.pendCycle : Accumulator : Sum.u64 = 922896; SumSQ.u64 = 14435324; Count.u64 = 59261; Min.u64 = 0; Max.u64 = 16; + core0.reads : Accumulator : Sum.u64 = 3004; SumSQ.u64 = 3004; Count.u64 = 3004; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; + l1cache0.Prefetch_requests : Accumulator : Sum.u64 = 3620; SumSQ.u64 = 3620; Count.u64 = 3620; Min.u64 = 1; Max.u64 = 1; + l1cache0.Prefetch_drops : Accumulator : Sum.u64 = 2268; SumSQ.u64 = 2268; Count.u64 = 2268; Min.u64 = 1; Max.u64 = 1; l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 2299; SumSQ.u64 = 2299; Count.u64 = 2299; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1302; SumSQ.u64 = 1302; Count.u64 = 1302; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 621; SumSQ.u64 = 621; Count.u64 = 621; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1248; SumSQ.u64 = 1248; Count.u64 = 1248; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 432; SumSQ.u64 = 432; Count.u64 = 432; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 2403; SumSQ.u64 = 2403; Count.u64 = 2403; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 517; SumSQ.u64 = 517; Count.u64 = 517; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1329; SumSQ.u64 = 1329; Count.u64 = 1329; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 411; SumSQ.u64 = 411; Count.u64 = 411; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2210; SumSQ.u64 = 2210; Count.u64 = 2210; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1336; SumSQ.u64 = 1336; Count.u64 = 1336; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2340; SumSQ.u64 = 2340; Count.u64 = 2340; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1448; SumSQ.u64 = 1448; Count.u64 = 1448; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 1480; SumSQ.u64 = 1480; Count.u64 = 1480; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 667; SumSQ.u64 = 667; Count.u64 = 667; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -37,11 +37,11 @@ l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 555; SumSQ.u64 = 555; Count.u64 = 555; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -62,21 +62,24 @@ l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 5151; SumSQ.u64 = 5151; Count.u64 = 5151; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 4151; SumSQ.u64 = 4151; Count.u64 = 4151; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 5509; SumSQ.u64 = 5509; Count.u64 = 5509; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 4320; SumSQ.u64 = 4320; Count.u64 = 4320; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 569; SumSQ.u64 = 569; Count.u64 = 569; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 754; SumSQ.u64 = 754; Count.u64 = 754; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 1495; SumSQ.u64 = 1495; Count.u64 = 1495; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3026; SumSQ.u64 = 3026; Count.u64 = 3026; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 654; SumSQ.u64 = 654; Count.u64 = 654; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 701; SumSQ.u64 = 701; Count.u64 = 701; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 1599; SumSQ.u64 = 1599; Count.u64 = 1599; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3004; SumSQ.u64 = 3004; Count.u64 = 3004; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -84,18 +87,18 @@ l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.evict_I : Accumulator : Sum.u64 = 1607; SumSQ.u64 = 1607; Count.u64 = 1607; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_S : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_M : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_IS : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_IM : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_SM : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_I : Accumulator : Sum.u64 = 1772; SumSQ.u64 = 1772; Count.u64 = 1772; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 273147; SumSQ.u64 = 636002427; Count.u64 = 1945; Min.u64 = 1; Max.u64 = 7142; - l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 427359; SumSQ.u64 = 592013499; Count.u64 = 2299; Min.u64 = 13; Max.u64 = 8104; - l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 83672; SumSQ.u64 = 209443758; Count.u64 = 294; Min.u64 = 2; Max.u64 = 8243; - l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 286501; SumSQ.u64 = 311156431; Count.u64 = 1248; Min.u64 = 16; Max.u64 = 8496; - l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 120291; SumSQ.u64 = 112249587; Count.u64 = 432; Min.u64 = 68; Max.u64 = 3287; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 237792; SumSQ.u64 = 363218618; Count.u64 = 1953; Min.u64 = 1; Max.u64 = 4375; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 443833; SumSQ.u64 = 424686693; Count.u64 = 2403; Min.u64 = 13; Max.u64 = 4228; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 86250; SumSQ.u64 = 156190500; Count.u64 = 256; Min.u64 = 2; Max.u64 = 4440; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 316127; SumSQ.u64 = 272293473; Count.u64 = 1329; Min.u64 = 16; Max.u64 = 4294; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 144712; SumSQ.u64 = 174359924; Count.u64 = 411; Min.u64 = 72; Max.u64 = 4450; l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -103,39 +106,40 @@ l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1434; SumSQ.u64 = 1434; Count.u64 = 1434; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1438; SumSQ.u64 = 1438; Count.u64 = 1438; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1994; SumSQ.u64 = 1994; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 2089; SumSQ.u64 = 2089; Count.u64 = 2089; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1424; SumSQ.u64 = 1424; Count.u64 = 1424; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.CacheHits : Accumulator : Sum.u64 = 2239; SumSQ.u64 = 2239; Count.u64 = 2239; Min.u64 = 1; Max.u64 = 1; - l1cache0.CacheMisses : Accumulator : Sum.u64 = 3979; SumSQ.u64 = 3979; Count.u64 = 3979; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 2209; SumSQ.u64 = 2209; Count.u64 = 2209; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 4143; SumSQ.u64 = 4143; Count.u64 = 4143; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; - l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l1cache0.prefetch_evict : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; - l1cache0.prefetch_inv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; - l1cache0.prefetch_useful : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; - l1cache0.prefetch_coherence_miss : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; - l1cache0.prefetch_redundant : Accumulator : Sum.u64 = 792; SumSQ.u64 = 792; Count.u64 = 792; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; - l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.prefetch_evict : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l1cache0.prefetch_inv : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; + l1cache0.prefetch_useful : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache0.prefetch_coherence_miss : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.prefetch_redundant : Accumulator : Sum.u64 = 829; SumSQ.u64 = 829; Count.u64 = 829; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; - l1cache0.evict_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; - l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 17153; SumSQ.u64 = 17153; Count.u64 = 17153; Min.u64 = 1; Max.u64 = 1; - l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1766; SumSQ.u64 = 1766; Count.u64 = 1766; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 17827; SumSQ.u64 = 17827; Count.u64 = 17827; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1792; SumSQ.u64 = 1792; Count.u64 = 1792; Min.u64 = 1; Max.u64 = 1; l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -148,35 +152,39 @@ l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetS_recv : Accumulator : Sum.u64 = 6579; SumSQ.u64 = 6579; Count.u64 = 6579; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 6624; SumSQ.u64 = 6624; Count.u64 = 6624; Min.u64 = 1; Max.u64 = 1; l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.Write_recv : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 2210; SumSQ.u64 = 2210; Count.u64 = 2210; Min.u64 = 1; Max.u64 = 1; - l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 2340; SumSQ.u64 = 2340; Count.u64 = 2340; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1803; SumSQ.u64 = 1803; Count.u64 = 1803; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.Inv_recv : Accumulator : Sum.u64 = 1503; SumSQ.u64 = 1503; Count.u64 = 1503; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 1610; SumSQ.u64 = 1610; Count.u64 = 1610; Min.u64 = 1; Max.u64 = 1; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 581; SumSQ.u64 = 581; Count.u64 = 581; Min.u64 = 1; Max.u64 = 1; - l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; - l1cache0.NACK_recv : Accumulator : Sum.u64 = 5323; SumSQ.u64 = 5323; Count.u64 = 5323; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 5686; SumSQ.u64 = 5686; Count.u64 = 5686; Min.u64 = 1; Max.u64 = 1; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1169149; SumSQ.u64 = 20002689; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 18; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1206699; SumSQ.u64 = 20626233; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 18; l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.packet_latency : Accumulator : Sum.u64 = 12889; SumSQ.u64 = 27835; Count.u64 = 8766; Min.u64 = 0; Max.u64 = 9; - l2cache0:memlink.send_bit_count : Accumulator : Sum.u64 = 1544208; SumSQ.u64 = 621839616; Count.u64 = 8781; Min.u64 = 80; Max.u64 = 592; - l2cache0:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0:memlink.idle_time : Accumulator : Sum.u64 = 12692012; SumSQ.u64 = 123348851730; Count.u64 = 6399; Min.u64 = 1; Max.u64 = 201228; - l2cache0.Prefetch_requests : Accumulator : Sum.u64 = 3099; SumSQ.u64 = 3099; Count.u64 = 3099; Min.u64 = 1; Max.u64 = 1; - l2cache0.Prefetch_drops : Accumulator : Sum.u64 = 2440; SumSQ.u64 = 2440; Count.u64 = 2440; Min.u64 = 1; Max.u64 = 1; + l2cache0:lowlink.packet_latency : Accumulator : Sum.u64 = 13045; SumSQ.u64 = 27233; Count.u64 = 9094; Min.u64 = 0; Max.u64 = 9; + l2cache0:lowlink.send_bit_count : Accumulator : Sum.u64 = 1597104; SumSQ.u64 = 642135808; Count.u64 = 9103; Min.u64 = 80; Max.u64 = 592; + l2cache0:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0:lowlink.idle_time : Accumulator : Sum.u64 = 12866994; SumSQ.u64 = 53363947134; Count.u64 = 6702; Min.u64 = 1; Max.u64 = 37654; + l2cache0.Prefetch_requests : Accumulator : Sum.u64 = 3192; SumSQ.u64 = 3192; Count.u64 = 3192; Min.u64 = 1; Max.u64 = 1; + l2cache0.Prefetch_drops : Accumulator : Sum.u64 = 2514; SumSQ.u64 = 2514; Count.u64 = 2514; Min.u64 = 1; Max.u64 = 1; l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.evict_I : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_I : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.evict_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; @@ -186,42 +194,42 @@ l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1841; SumSQ.u64 = 1841; Count.u64 = 1841; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 939; SumSQ.u64 = 939; Count.u64 = 939; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1103; SumSQ.u64 = 1103; Count.u64 = 1103; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 544; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1218; SumSQ.u64 = 1218; Count.u64 = 1218; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1172; SumSQ.u64 = 1172; Count.u64 = 1172; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1308; SumSQ.u64 = 1308; Count.u64 = 1308; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 1099; SumSQ.u64 = 1099; Count.u64 = 1099; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 1123; SumSQ.u64 = 1123; Count.u64 = 1123; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 2341; SumSQ.u64 = 2341; Count.u64 = 2341; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 2423; SumSQ.u64 = 2423; Count.u64 = 2423; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1582; SumSQ.u64 = 1582; Count.u64 = 1582; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -239,7 +247,7 @@ l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 736; SumSQ.u64 = 736; Count.u64 = 736; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -260,11 +268,11 @@ l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 751; SumSQ.u64 = 751; Count.u64 = 751; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 697; SumSQ.u64 = 697; Count.u64 = 697; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1445; SumSQ.u64 = 1445; Count.u64 = 1445; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1522; SumSQ.u64 = 1522; Count.u64 = 1522; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -275,77 +283,84 @@ l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 2275; SumSQ.u64 = 2275; Count.u64 = 2275; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 2293; SumSQ.u64 = 2293; Count.u64 = 2293; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 2333; SumSQ.u64 = 2333; Count.u64 = 2333; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 2417; SumSQ.u64 = 2417; Count.u64 = 2417; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 962; SumSQ.u64 = 962; Count.u64 = 962; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 2276; SumSQ.u64 = 2276; Count.u64 = 2276; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 5603; SumSQ.u64 = 5603; Count.u64 = 5603; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 2210; SumSQ.u64 = 2210; Count.u64 = 2210; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 873; SumSQ.u64 = 873; Count.u64 = 873; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 2366; SumSQ.u64 = 2366; Count.u64 = 2366; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 5969; SumSQ.u64 = 5969; Count.u64 = 5969; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 2340; SumSQ.u64 = 2340; Count.u64 = 2340; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1803; SumSQ.u64 = 1803; Count.u64 = 1803; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 581; SumSQ.u64 = 581; Count.u64 = 581; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; - l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 1503; SumSQ.u64 = 1503; Count.u64 = 1503; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 1610; SumSQ.u64 = 1610; Count.u64 = 1610; Min.u64 = 1; Max.u64 = 1; l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 8134; SumSQ.u64 = 1023632; Count.u64 = 1117; Min.u64 = 1; Max.u64 = 892; - l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 184154; SumSQ.u64 = 61077682; Count.u64 = 1776; Min.u64 = 36; Max.u64 = 4231; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 9308; SumSQ.u64 = 3271790; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1602; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 182580; SumSQ.u64 = 46284952; Count.u64 = 1878; Min.u64 = 36; Max.u64 = 2690; l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 387; SumSQ.u64 = 4643; Count.u64 = 33; Min.u64 = 10; Max.u64 = 19; - l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 153085; SumSQ.u64 = 57148791; Count.u64 = 1103; Min.u64 = 63; Max.u64 = 3358; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 245; SumSQ.u64 = 2745; Count.u64 = 22; Min.u64 = 10; Max.u64 = 13; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 180841; SumSQ.u64 = 66531699; Count.u64 = 1218; Min.u64 = 65; Max.u64 = 3218; l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 65855; SumSQ.u64 = 37570597; Count.u64 = 544; Min.u64 = 59; Max.u64 = 5340; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 61055; SumSQ.u64 = 15873561; Count.u64 = 500; Min.u64 = 59; Max.u64 = 2414; l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1110; SumSQ.u64 = 1110; Count.u64 = 1110; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1126; SumSQ.u64 = 1126; Count.u64 = 1126; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1840; SumSQ.u64 = 1840; Count.u64 = 1840; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1635; SumSQ.u64 = 1635; Count.u64 = 1635; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1946; SumSQ.u64 = 1946; Count.u64 = 1946; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1713; SumSQ.u64 = 1713; Count.u64 = 1713; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.CacheHits : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; - l2cache0.CacheMisses : Accumulator : Sum.u64 = 3488; SumSQ.u64 = 3488; Count.u64 = 3488; Min.u64 = 1; Max.u64 = 1; - l2cache0.prefetch_evict : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache0.prefetch_inv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; - l2cache0.prefetch_useful : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; - l2cache0.prefetch_coherence_miss : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache0.prefetch_redundant : Accumulator : Sum.u64 = 594; SumSQ.u64 = 594; Count.u64 = 594; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheHits : Accumulator : Sum.u64 = 1156; SumSQ.u64 = 1156; Count.u64 = 1156; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 3665; SumSQ.u64 = 3665; Count.u64 = 3665; Min.u64 = 1; Max.u64 = 1; + l2cache0.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.prefetch_inv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache0.prefetch_useful : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.prefetch_coherence_miss : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.prefetch_redundant : Accumulator : Sum.u64 = 609; SumSQ.u64 = 609; Count.u64 = 609; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -355,23 +370,23 @@ l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 22434; SumSQ.u64 = 22434; Count.u64 = 22434; Min.u64 = 1; Max.u64 = 1; - l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2871; SumSQ.u64 = 2871; Count.u64 = 2871; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 23444; SumSQ.u64 = 23444; Count.u64 = 23444; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 3012; SumSQ.u64 = 3012; Count.u64 = 3012; Min.u64 = 1; Max.u64 = 1; l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -384,62 +399,67 @@ l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetS_recv : Accumulator : Sum.u64 = 8250; SumSQ.u64 = 8250; Count.u64 = 8250; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetX_recv : Accumulator : Sum.u64 = 4151; SumSQ.u64 = 4151; Count.u64 = 4151; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 8701; SumSQ.u64 = 8701; Count.u64 = 8701; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 4320; SumSQ.u64 = 4320; Count.u64 = 4320; Min.u64 = 1; Max.u64 = 1; l2cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; - l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 1653; SumSQ.u64 = 1653; Count.u64 = 1653; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 1724; SumSQ.u64 = 1724; Count.u64 = 1724; Min.u64 = 1; Max.u64 = 1; l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.PutS_recv : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; - l2cache0.PutM_recv : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; - l2cache0.PutE_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 1134; SumSQ.u64 = 1134; Count.u64 = 1134; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.Inv_recv : Accumulator : Sum.u64 = 2417; SumSQ.u64 = 2417; Count.u64 = 2417; Min.u64 = 1; Max.u64 = 1; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 2521; SumSQ.u64 = 2521; Count.u64 = 2521; Min.u64 = 1; Max.u64 = 1; l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; - l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 1043; SumSQ.u64 = 1043; Count.u64 = 1043; Min.u64 = 1; Max.u64 = 1; - l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 569; SumSQ.u64 = 569; Count.u64 = 569; Min.u64 = 1; Max.u64 = 1; - l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 754; SumSQ.u64 = 754; Count.u64 = 754; Min.u64 = 1; Max.u64 = 1; - l2cache0.NACK_recv : Accumulator : Sum.u64 = 1080; SumSQ.u64 = 1080; Count.u64 = 1080; Min.u64 = 1; Max.u64 = 1; - l2cache0.AckInv_recv : Accumulator : Sum.u64 = 1495; SumSQ.u64 = 1495; Count.u64 = 1495; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 887; SumSQ.u64 = 887; Count.u64 = 887; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 654; SumSQ.u64 = 654; Count.u64 = 654; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 701; SumSQ.u64 = 701; Count.u64 = 701; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 1085; SumSQ.u64 = 1085; Count.u64 = 1085; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 1599; SumSQ.u64 = 1599; Count.u64 = 1599; Min.u64 = 1; Max.u64 = 1; l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 412085; SumSQ.u64 = 2623005; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 8; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 438555; SumSQ.u64 = 2839307; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 8; l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core1.pendCycle : Accumulator : Sum.u64 = 863499; SumSQ.u64 = 13465919; Count.u64 = 55636; Min.u64 = 0; Max.u64 = 16; - core1.reads : Accumulator : Sum.u64 = 3022; SumSQ.u64 = 3022; Count.u64 = 3022; Min.u64 = 1; Max.u64 = 1; - core1.writes : Accumulator : Sum.u64 = 1978; SumSQ.u64 = 1978; Count.u64 = 1978; Min.u64 = 1; Max.u64 = 1; - l1cache1.Prefetch_requests : Accumulator : Sum.u64 = 3628; SumSQ.u64 = 3628; Count.u64 = 3628; Min.u64 = 1; Max.u64 = 1; - l1cache1.Prefetch_drops : Accumulator : Sum.u64 = 2412; SumSQ.u64 = 2412; Count.u64 = 2412; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 911424; SumSQ.u64 = 14243278; Count.u64 = 58555; Min.u64 = 0; Max.u64 = 16; + core1.reads : Accumulator : Sum.u64 = 2985; SumSQ.u64 = 2985; Count.u64 = 2985; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; + l1cache1.Prefetch_requests : Accumulator : Sum.u64 = 3641; SumSQ.u64 = 3641; Count.u64 = 3641; Min.u64 = 1; Max.u64 = 1; + l1cache1.Prefetch_drops : Accumulator : Sum.u64 = 2382; SumSQ.u64 = 2382; Count.u64 = 2382; Min.u64 = 1; Max.u64 = 1; l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 2312; SumSQ.u64 = 2312; Count.u64 = 2312; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 1371; SumSQ.u64 = 1371; Count.u64 = 1371; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 1273; SumSQ.u64 = 1273; Count.u64 = 1273; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 253; SumSQ.u64 = 253; Count.u64 = 253; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 2348; SumSQ.u64 = 2348; Count.u64 = 2348; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 1366; SumSQ.u64 = 1366; Count.u64 = 1366; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 1316; SumSQ.u64 = 1316; Count.u64 = 1316; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 429; SumSQ.u64 = 429; Count.u64 = 429; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2250; SumSQ.u64 = 2250; Count.u64 = 2250; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1361; SumSQ.u64 = 1361; Count.u64 = 1361; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 1502; SumSQ.u64 = 1502; Count.u64 = 1502; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2293; SumSQ.u64 = 2293; Count.u64 = 2293; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1421; SumSQ.u64 = 1421; Count.u64 = 1421; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 1445; SumSQ.u64 = 1445; Count.u64 = 1445; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 706; SumSQ.u64 = 706; Count.u64 = 706; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -449,10 +469,10 @@ l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 602; SumSQ.u64 = 602; Count.u64 = 602; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -474,21 +494,24 @@ l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 5378; SumSQ.u64 = 5378; Count.u64 = 5378; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 4259; SumSQ.u64 = 4259; Count.u64 = 4259; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 5381; SumSQ.u64 = 5381; Count.u64 = 5381; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 4418; SumSQ.u64 = 4418; Count.u64 = 4418; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 1590; SumSQ.u64 = 1590; Count.u64 = 1590; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3022; SumSQ.u64 = 3022; Count.u64 = 3022; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 1550; SumSQ.u64 = 1550; Count.u64 = 1550; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 2985; SumSQ.u64 = 2985; Count.u64 = 2985; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1978; SumSQ.u64 = 1978; Count.u64 = 1978; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -496,18 +519,18 @@ l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.evict_I : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 1729; Count.u64 = 1729; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_S : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_M : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_IS : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_IM : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_SM : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_I : Accumulator : Sum.u64 = 1815; SumSQ.u64 = 1815; Count.u64 = 1815; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 1080; SumSQ.u64 = 1080; Count.u64 = 1080; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 240500; SumSQ.u64 = 381590922; Count.u64 = 1926; Min.u64 = 1; Max.u64 = 4200; - l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 414965; SumSQ.u64 = 375728381; Count.u64 = 2312; Min.u64 = 13; Max.u64 = 4280; - l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 60843; SumSQ.u64 = 76855927; Count.u64 = 260; Min.u64 = 2; Max.u64 = 4167; - l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 299506; SumSQ.u64 = 272534874; Count.u64 = 1273; Min.u64 = 16; Max.u64 = 5281; - l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 135823; SumSQ.u64 = 150293617; Count.u64 = 445; Min.u64 = 70; Max.u64 = 4316; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 220939; SumSQ.u64 = 294090827; Count.u64 = 1896; Min.u64 = 1; Max.u64 = 4098; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 445313; SumSQ.u64 = 466292629; Count.u64 = 2348; Min.u64 = 13; Max.u64 = 5134; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 73803; SumSQ.u64 = 99751185; Count.u64 = 270; Min.u64 = 2; Max.u64 = 3978; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 329558; SumSQ.u64 = 349793596; Count.u64 = 1316; Min.u64 = 16; Max.u64 = 4398; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 145597; SumSQ.u64 = 191551811; Count.u64 = 429; Min.u64 = 69; Max.u64 = 5625; l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -515,39 +538,40 @@ l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 1375; SumSQ.u64 = 1375; Count.u64 = 1375; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 1361; SumSQ.u64 = 1361; Count.u64 = 1361; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 551; SumSQ.u64 = 551; Count.u64 = 551; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 1393; SumSQ.u64 = 1393; Count.u64 = 1393; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 1416; SumSQ.u64 = 1416; Count.u64 = 1416; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.CacheHits : Accumulator : Sum.u64 = 2186; SumSQ.u64 = 2186; Count.u64 = 2186; Min.u64 = 1; Max.u64 = 1; - l1cache1.CacheMisses : Accumulator : Sum.u64 = 4030; SumSQ.u64 = 4030; Count.u64 = 4030; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 2166; SumSQ.u64 = 2166; Count.u64 = 2166; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 4093; SumSQ.u64 = 4093; Count.u64 = 4093; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; - l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l1cache1.prefetch_evict : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; - l1cache1.prefetch_inv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; - l1cache1.prefetch_useful : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; - l1cache1.prefetch_coherence_miss : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; - l1cache1.prefetch_redundant : Accumulator : Sum.u64 = 814; SumSQ.u64 = 814; Count.u64 = 814; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; - l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 1079; SumSQ.u64 = 1079; Count.u64 = 1079; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.prefetch_evict : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l1cache1.prefetch_inv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l1cache1.prefetch_useful : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache1.prefetch_coherence_miss : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache1.prefetch_redundant : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l1cache1.evict_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 17615; SumSQ.u64 = 17615; Count.u64 = 17615; Min.u64 = 1; Max.u64 = 1; - l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1847; SumSQ.u64 = 1847; Count.u64 = 1847; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 17802; SumSQ.u64 = 17802; Count.u64 = 17802; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1937; SumSQ.u64 = 1937; Count.u64 = 1937; Min.u64 = 1; Max.u64 = 1; l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -560,80 +584,84 @@ l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetS_recv : Accumulator : Sum.u64 = 6650; SumSQ.u64 = 6650; Count.u64 = 6650; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 6626; SumSQ.u64 = 6626; Count.u64 = 6626; Min.u64 = 1; Max.u64 = 1; l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.Write_recv : Accumulator : Sum.u64 = 1978; SumSQ.u64 = 1978; Count.u64 = 1978; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 2250; SumSQ.u64 = 2250; Count.u64 = 2250; Min.u64 = 1; Max.u64 = 1; - l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 2293; SumSQ.u64 = 2293; Count.u64 = 2293; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 1800; SumSQ.u64 = 1800; Count.u64 = 1800; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.Inv_recv : Accumulator : Sum.u64 = 1601; SumSQ.u64 = 1601; Count.u64 = 1601; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 1562; SumSQ.u64 = 1562; Count.u64 = 1562; Min.u64 = 1; Max.u64 = 1; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; - l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; - l1cache1.NACK_recv : Accumulator : Sum.u64 = 5607; SumSQ.u64 = 5607; Count.u64 = 5607; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 752; SumSQ.u64 = 752; Count.u64 = 752; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 689; SumSQ.u64 = 689; Count.u64 = 689; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 5706; SumSQ.u64 = 5706; Count.u64 = 5706; Min.u64 = 1; Max.u64 = 1; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1129734; SumSQ.u64 = 19265946; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 18; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1193232; SumSQ.u64 = 20401604; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 18; l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.packet_latency : Accumulator : Sum.u64 = 13439; SumSQ.u64 = 29067; Count.u64 = 9168; Min.u64 = 0; Max.u64 = 8; - l2cache1:memlink.send_bit_count : Accumulator : Sum.u64 = 1607008; SumSQ.u64 = 645049856; Count.u64 = 9182; Min.u64 = 80; Max.u64 = 592; - l2cache1:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1:memlink.idle_time : Accumulator : Sum.u64 = 12950426; SumSQ.u64 = 351685801930; Count.u64 = 6657; Min.u64 = 1; Max.u64 = 523413; - l2cache1.Prefetch_requests : Accumulator : Sum.u64 = 3253; SumSQ.u64 = 3253; Count.u64 = 3253; Min.u64 = 1; Max.u64 = 1; - l2cache1.Prefetch_drops : Accumulator : Sum.u64 = 2628; SumSQ.u64 = 2628; Count.u64 = 2628; Min.u64 = 1; Max.u64 = 1; + l2cache1:lowlink.packet_latency : Accumulator : Sum.u64 = 13269; SumSQ.u64 = 27835; Count.u64 = 9217; Min.u64 = 0; Max.u64 = 8; + l2cache1:lowlink.send_bit_count : Accumulator : Sum.u64 = 1624800; SumSQ.u64 = 654353920; Count.u64 = 9238; Min.u64 = 80; Max.u64 = 592; + l2cache1:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1:lowlink.idle_time : Accumulator : Sum.u64 = 13450776; SumSQ.u64 = 127911846280; Count.u64 = 6766; Min.u64 = 1; Max.u64 = 232981; + l2cache1.Prefetch_requests : Accumulator : Sum.u64 = 3240; SumSQ.u64 = 3240; Count.u64 = 3240; Min.u64 = 1; Max.u64 = 1; + l2cache1.Prefetch_drops : Accumulator : Sum.u64 = 2571; SumSQ.u64 = 2571; Count.u64 = 2571; Min.u64 = 1; Max.u64 = 1; l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.evict_I : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_I : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.evict_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_S : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.evict_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 1143; SumSQ.u64 = 1143; Count.u64 = 1143; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1943; SumSQ.u64 = 1943; Count.u64 = 1943; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 1200; SumSQ.u64 = 1200; Count.u64 = 1200; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1940; SumSQ.u64 = 1940; Count.u64 = 1940; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1213; SumSQ.u64 = 1213; Count.u64 = 1213; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1936; SumSQ.u64 = 1936; Count.u64 = 1936; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1284; SumSQ.u64 = 1284; Count.u64 = 1284; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 1020; SumSQ.u64 = 1020; Count.u64 = 1020; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 1067; SumSQ.u64 = 1067; Count.u64 = 1067; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 2467; SumSQ.u64 = 2467; Count.u64 = 2467; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 2407; SumSQ.u64 = 2407; Count.u64 = 2407; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1659; SumSQ.u64 = 1659; Count.u64 = 1659; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1512; SumSQ.u64 = 1512; Count.u64 = 1512; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -651,7 +679,7 @@ l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 844; SumSQ.u64 = 844; Count.u64 = 844; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -672,11 +700,11 @@ l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 616; SumSQ.u64 = 616; Count.u64 = 616; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 726; SumSQ.u64 = 726; Count.u64 = 726; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 666; SumSQ.u64 = 666; Count.u64 = 666; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1534; SumSQ.u64 = 1534; Count.u64 = 1534; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1477; SumSQ.u64 = 1477; Count.u64 = 1477; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -687,65 +715,72 @@ l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 2415; SumSQ.u64 = 2415; Count.u64 = 2415; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 2347; SumSQ.u64 = 2347; Count.u64 = 2347; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 2391; SumSQ.u64 = 2391; Count.u64 = 2391; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 2408; SumSQ.u64 = 2408; Count.u64 = 2408; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 775; SumSQ.u64 = 775; Count.u64 = 775; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 927; SumSQ.u64 = 927; Count.u64 = 927; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 2369; SumSQ.u64 = 2369; Count.u64 = 2369; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 5940; SumSQ.u64 = 5940; Count.u64 = 5940; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 2250; SumSQ.u64 = 2250; Count.u64 = 2250; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 828; SumSQ.u64 = 828; Count.u64 = 828; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 2291; Count.u64 = 2291; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 6103; SumSQ.u64 = 6103; Count.u64 = 6103; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 2293; SumSQ.u64 = 2293; Count.u64 = 2293; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1800; SumSQ.u64 = 1800; Count.u64 = 1800; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 752; SumSQ.u64 = 752; Count.u64 = 752; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 738; SumSQ.u64 = 738; Count.u64 = 738; Min.u64 = 1; Max.u64 = 1; - l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 1601; SumSQ.u64 = 1601; Count.u64 = 1601; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 689; SumSQ.u64 = 689; Count.u64 = 689; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 1562; SumSQ.u64 = 1562; Count.u64 = 1562; Min.u64 = 1; Max.u64 = 1; l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 5503; SumSQ.u64 = 78133; Count.u64 = 989; Min.u64 = 1; Max.u64 = 128; - l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 178897; SumSQ.u64 = 28499011; Count.u64 = 1895; Min.u64 = 36; Max.u64 = 1275; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 6407; SumSQ.u64 = 178261; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 324; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 179802; SumSQ.u64 = 42119728; Count.u64 = 1878; Min.u64 = 37; Max.u64 = 2861; l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 260; SumSQ.u64 = 3504; Count.u64 = 21; Min.u64 = 10; Max.u64 = 28; - l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 158323; SumSQ.u64 = 48478551; Count.u64 = 1143; Min.u64 = 62; Max.u64 = 2749; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 232; SumSQ.u64 = 2730; Count.u64 = 20; Min.u64 = 10; Max.u64 = 14; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 172645; SumSQ.u64 = 68602545; Count.u64 = 1200; Min.u64 = 47; Max.u64 = 4220; l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 71055; SumSQ.u64 = 21482051; Count.u64 = 554; Min.u64 = 61; Max.u64 = 2308; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 66011; SumSQ.u64 = 16922311; Count.u64 = 525; Min.u64 = 59; Max.u64 = 2131; l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 987; SumSQ.u64 = 987; Count.u64 = 987; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 1068; SumSQ.u64 = 1068; Count.u64 = 1068; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 1691; SumSQ.u64 = 1691; Count.u64 = 1691; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1939; SumSQ.u64 = 1939; Count.u64 = 1939; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 1720; SumSQ.u64 = 1720; Count.u64 = 1720; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.CacheHits : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; - l2cache1.CacheMisses : Accumulator : Sum.u64 = 3645; SumSQ.u64 = 3645; Count.u64 = 3645; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheHits : Accumulator : Sum.u64 = 1094; SumSQ.u64 = 1094; Count.u64 = 1094; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 3668; SumSQ.u64 = 3668; Count.u64 = 3668; Min.u64 = 1; Max.u64 = 1; l2cache1.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.prefetch_inv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; - l2cache1.prefetch_useful : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l2cache1.prefetch_coherence_miss : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache1.prefetch_redundant : Accumulator : Sum.u64 = 572; SumSQ.u64 = 572; Count.u64 = 572; Min.u64 = 1; Max.u64 = 1; + l2cache1.prefetch_inv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.prefetch_useful : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.prefetch_coherence_miss : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.prefetch_redundant : Accumulator : Sum.u64 = 604; SumSQ.u64 = 604; Count.u64 = 604; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.evict_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -755,8 +790,8 @@ l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -767,7 +802,7 @@ l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; @@ -782,8 +817,8 @@ l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 23206; SumSQ.u64 = 23206; Count.u64 = 23206; Min.u64 = 1; Max.u64 = 1; - l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2987; SumSQ.u64 = 2987; Count.u64 = 2987; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 23445; SumSQ.u64 = 23445; Count.u64 = 23445; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 3018; SumSQ.u64 = 3018; Count.u64 = 3018; Min.u64 = 1; Max.u64 = 1; l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -796,61 +831,66 @@ l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetS_recv : Accumulator : Sum.u64 = 8631; SumSQ.u64 = 8631; Count.u64 = 8631; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetX_recv : Accumulator : Sum.u64 = 4259; SumSQ.u64 = 4259; Count.u64 = 4259; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 8621; SumSQ.u64 = 8621; Count.u64 = 8621; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 4418; SumSQ.u64 = 4418; Count.u64 = 4418; Min.u64 = 1; Max.u64 = 1; l2cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 1940; SumSQ.u64 = 1940; Count.u64 = 1940; Min.u64 = 1; Max.u64 = 1; - l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 1936; SumSQ.u64 = 1936; Count.u64 = 1936; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 1732; SumSQ.u64 = 1732; Count.u64 = 1732; Min.u64 = 1; Max.u64 = 1; l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.PutS_recv : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; - l2cache1.PutM_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; - l2cache1.PutE_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 1079; SumSQ.u64 = 1079; Count.u64 = 1079; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.Inv_recv : Accumulator : Sum.u64 = 2547; SumSQ.u64 = 2547; Count.u64 = 2547; Min.u64 = 1; Max.u64 = 1; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 2505; SumSQ.u64 = 2505; Count.u64 = 2505; Min.u64 = 1; Max.u64 = 1; l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 847; SumSQ.u64 = 847; Count.u64 = 847; Min.u64 = 1; Max.u64 = 1; - l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 1012; SumSQ.u64 = 1012; Count.u64 = 1012; Min.u64 = 1; Max.u64 = 1; - l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 620; SumSQ.u64 = 620; Count.u64 = 620; Min.u64 = 1; Max.u64 = 1; - l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; - l2cache1.NACK_recv : Accumulator : Sum.u64 = 1117; SumSQ.u64 = 1117; Count.u64 = 1117; Min.u64 = 1; Max.u64 = 1; - l2cache1.AckInv_recv : Accumulator : Sum.u64 = 1590; SumSQ.u64 = 1590; Count.u64 = 1590; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 1007; Count.u64 = 1007; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 1550; SumSQ.u64 = 1550; Count.u64 = 1550; Min.u64 = 1; Max.u64 = 1; l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 418534; SumSQ.u64 = 2732556; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 8; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 439266; SumSQ.u64 = 2871970; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 8; l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core2.pendCycle : Accumulator : Sum.u64 = 896350; SumSQ.u64 = 14003930; Count.u64 = 57687; Min.u64 = 0; Max.u64 = 16; - core2.reads : Accumulator : Sum.u64 = 2958; SumSQ.u64 = 2958; Count.u64 = 2958; Min.u64 = 1; Max.u64 = 1; - core2.writes : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; - l1cache2.Prefetch_requests : Accumulator : Sum.u64 = 3615; SumSQ.u64 = 3615; Count.u64 = 3615; Min.u64 = 1; Max.u64 = 1; - l1cache2.Prefetch_drops : Accumulator : Sum.u64 = 2441; SumSQ.u64 = 2441; Count.u64 = 2441; Min.u64 = 1; Max.u64 = 1; + core2.pendCycle : Accumulator : Sum.u64 = 926510; SumSQ.u64 = 14447892; Count.u64 = 59741; Min.u64 = 0; Max.u64 = 16; + core2.reads : Accumulator : Sum.u64 = 2983; SumSQ.u64 = 2983; Count.u64 = 2983; Min.u64 = 1; Max.u64 = 1; + core2.writes : Accumulator : Sum.u64 = 2017; SumSQ.u64 = 2017; Count.u64 = 2017; Min.u64 = 1; Max.u64 = 1; + l1cache2.Prefetch_requests : Accumulator : Sum.u64 = 3595; SumSQ.u64 = 3595; Count.u64 = 3595; Min.u64 = 1; Max.u64 = 1; + l1cache2.Prefetch_drops : Accumulator : Sum.u64 = 2308; SumSQ.u64 = 2308; Count.u64 = 2308; Min.u64 = 1; Max.u64 = 1; l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 2233; SumSQ.u64 = 2233; Count.u64 = 2233; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 1327; SumSQ.u64 = 1327; Count.u64 = 1327; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 561; SumSQ.u64 = 561; Count.u64 = 561; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 2288; SumSQ.u64 = 2288; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 1396; SumSQ.u64 = 1396; Count.u64 = 1396; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 1340; SumSQ.u64 = 1340; Count.u64 = 1340; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2183; SumSQ.u64 = 2183; Count.u64 = 2183; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1477; SumSQ.u64 = 1477; Count.u64 = 1477; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 1475; SumSQ.u64 = 1475; Count.u64 = 1475; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1450; SumSQ.u64 = 1450; Count.u64 = 1450; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 1423; SumSQ.u64 = 1423; Count.u64 = 1423; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -861,10 +901,10 @@ l1cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 616; SumSQ.u64 = 616; Count.u64 = 616; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 549; SumSQ.u64 = 549; Count.u64 = 549; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -886,21 +926,24 @@ l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 5229; SumSQ.u64 = 5229; Count.u64 = 5229; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 4770; SumSQ.u64 = 4770; Count.u64 = 4770; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 5063; SumSQ.u64 = 5063; Count.u64 = 5063; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 4802; SumSQ.u64 = 4802; Count.u64 = 4802; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 629; SumSQ.u64 = 629; Count.u64 = 629; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 1590; SumSQ.u64 = 1590; Count.u64 = 1590; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 2958; SumSQ.u64 = 2958; Count.u64 = 2958; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 570; SumSQ.u64 = 570; Count.u64 = 570; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 1533; SumSQ.u64 = 1533; Count.u64 = 1533; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 2983; SumSQ.u64 = 2983; Count.u64 = 2983; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 2017; SumSQ.u64 = 2017; Count.u64 = 2017; Min.u64 = 1; Max.u64 = 1; l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -908,18 +951,18 @@ l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.evict_I : Accumulator : Sum.u64 = 1655; SumSQ.u64 = 1655; Count.u64 = 1655; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_S : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_M : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_IS : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_IM : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_SM : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_I : Accumulator : Sum.u64 = 1700; SumSQ.u64 = 1700; Count.u64 = 1700; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_S : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_M : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IS : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IM : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SM : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; l1cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 232127; SumSQ.u64 = 365964883; Count.u64 = 1899; Min.u64 = 1; Max.u64 = 5052; - l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 421743; SumSQ.u64 = 427414143; Count.u64 = 2233; Min.u64 = 13; Max.u64 = 4323; - l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 72507; SumSQ.u64 = 109990267; Count.u64 = 253; Min.u64 = 2; Max.u64 = 4126; - l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 319159; SumSQ.u64 = 289062445; Count.u64 = 1362; Min.u64 = 16; Max.u64 = 5175; - l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 150036; SumSQ.u64 = 166792564; Count.u64 = 427; Min.u64 = 65; Max.u64 = 3297; + l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 230378; SumSQ.u64 = 347676996; Count.u64 = 1982; Min.u64 = 1; Max.u64 = 4206; + l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 394698; SumSQ.u64 = 373655378; Count.u64 = 2288; Min.u64 = 13; Max.u64 = 5507; + l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 97260; SumSQ.u64 = 143106898; Count.u64 = 262; Min.u64 = 2; Max.u64 = 3830; + l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 357644; SumSQ.u64 = 382415716; Count.u64 = 1340; Min.u64 = 16; Max.u64 = 4700; + l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 151905; SumSQ.u64 = 183709627; Count.u64 = 415; Min.u64 = 67; Max.u64 = 4520; l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -927,39 +970,40 @@ l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1365; SumSQ.u64 = 1365; Count.u64 = 1365; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1454; SumSQ.u64 = 1454; Count.u64 = 1454; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 534; SumSQ.u64 = 534; Count.u64 = 534; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1947; SumSQ.u64 = 1947; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 1474; SumSQ.u64 = 1474; Count.u64 = 1474; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1972; SumSQ.u64 = 1972; Count.u64 = 1972; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 1364; SumSQ.u64 = 1364; Count.u64 = 1364; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 391; SumSQ.u64 = 391; Count.u64 = 391; Min.u64 = 1; Max.u64 = 1; l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.CacheHits : Accumulator : Sum.u64 = 2152; SumSQ.u64 = 2152; Count.u64 = 2152; Min.u64 = 1; Max.u64 = 1; - l1cache2.CacheMisses : Accumulator : Sum.u64 = 4022; SumSQ.u64 = 4022; Count.u64 = 4022; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheHits : Accumulator : Sum.u64 = 2244; SumSQ.u64 = 2244; Count.u64 = 2244; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheMisses : Accumulator : Sum.u64 = 4043; SumSQ.u64 = 4043; Count.u64 = 4043; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 1059; SumSQ.u64 = 1059; Count.u64 = 1059; Min.u64 = 1; Max.u64 = 1; - l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache2.prefetch_evict : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; - l1cache2.prefetch_inv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; - l1cache2.prefetch_useful : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; - l1cache2.prefetch_coherence_miss : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; - l1cache2.prefetch_redundant : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.prefetch_evict : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache2.prefetch_inv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache2.prefetch_useful : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache2.prefetch_coherence_miss : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache2.prefetch_redundant : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l1cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; - l1cache2.evict_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 18054; SumSQ.u64 = 18054; Count.u64 = 18054; Min.u64 = 1; Max.u64 = 1; - l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1760; SumSQ.u64 = 1760; Count.u64 = 1760; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 17776; SumSQ.u64 = 17776; Count.u64 = 17776; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1946; SumSQ.u64 = 1946; Count.u64 = 1946; Min.u64 = 1; Max.u64 = 1; l1cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -972,80 +1016,84 @@ l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetS_recv : Accumulator : Sum.u64 = 6573; SumSQ.u64 = 6573; Count.u64 = 6573; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetS_recv : Accumulator : Sum.u64 = 6578; SumSQ.u64 = 6578; Count.u64 = 6578; Min.u64 = 1; Max.u64 = 1; l1cache2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.Write_recv : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_recv : Accumulator : Sum.u64 = 2017; SumSQ.u64 = 2017; Count.u64 = 2017; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 2183; SumSQ.u64 = 2183; Count.u64 = 2183; Min.u64 = 1; Max.u64 = 1; - l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 1839; Count.u64 = 1839; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1838; SumSQ.u64 = 1838; Count.u64 = 1838; Min.u64 = 1; Max.u64 = 1; l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.Inv_recv : Accumulator : Sum.u64 = 1603; SumSQ.u64 = 1603; Count.u64 = 1603; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Inv_recv : Accumulator : Sum.u64 = 1547; SumSQ.u64 = 1547; Count.u64 = 1547; Min.u64 = 1; Max.u64 = 1; l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; - l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; - l1cache2.NACK_recv : Accumulator : Sum.u64 = 5977; SumSQ.u64 = 5977; Count.u64 = 5977; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.NACK_recv : Accumulator : Sum.u64 = 5822; SumSQ.u64 = 5822; Count.u64 = 5822; Min.u64 = 1; Max.u64 = 1; l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 1173711; SumSQ.u64 = 20062605; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 18; + l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 1209853; SumSQ.u64 = 20606315; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 18; l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.packet_latency : Accumulator : Sum.u64 = 13417; SumSQ.u64 = 28701; Count.u64 = 9184; Min.u64 = 0; Max.u64 = 8; - l2cache2:memlink.send_bit_count : Accumulator : Sum.u64 = 1629952; SumSQ.u64 = 659615744; Count.u64 = 9200; Min.u64 = 80; Max.u64 = 592; - l2cache2:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2:memlink.idle_time : Accumulator : Sum.u64 = 12604710; SumSQ.u64 = 47939625990; Count.u64 = 6731; Min.u64 = 1; Max.u64 = 29007; - l2cache2.Prefetch_requests : Accumulator : Sum.u64 = 3255; SumSQ.u64 = 3255; Count.u64 = 3255; Min.u64 = 1; Max.u64 = 1; - l2cache2.Prefetch_drops : Accumulator : Sum.u64 = 2614; SumSQ.u64 = 2614; Count.u64 = 2614; Min.u64 = 1; Max.u64 = 1; + l2cache2:lowlink.packet_latency : Accumulator : Sum.u64 = 13085; SumSQ.u64 = 27645; Count.u64 = 9010; Min.u64 = 0; Max.u64 = 9; + l2cache2:lowlink.send_bit_count : Accumulator : Sum.u64 = 1606816; SumSQ.u64 = 652308992; Count.u64 = 9026; Min.u64 = 80; Max.u64 = 592; + l2cache2:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2:lowlink.idle_time : Accumulator : Sum.u64 = 13377875; SumSQ.u64 = 112503915017; Count.u64 = 6655; Min.u64 = 1; Max.u64 = 204981; + l2cache2.Prefetch_requests : Accumulator : Sum.u64 = 3147; SumSQ.u64 = 3147; Count.u64 = 3147; Min.u64 = 1; Max.u64 = 1; + l2cache2.Prefetch_drops : Accumulator : Sum.u64 = 2492; SumSQ.u64 = 2492; Count.u64 = 2492; Min.u64 = 1; Max.u64 = 1; l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.evict_I : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_I : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.evict_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.evict_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache2.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1869; SumSQ.u64 = 1869; Count.u64 = 1869; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 863; SumSQ.u64 = 863; Count.u64 = 863; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 1254; SumSQ.u64 = 1254; Count.u64 = 1254; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 984; SumSQ.u64 = 984; Count.u64 = 984; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 1243; SumSQ.u64 = 1243; Count.u64 = 1243; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1864; SumSQ.u64 = 1864; Count.u64 = 1864; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1785; SumSQ.u64 = 1785; Count.u64 = 1785; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1341; SumSQ.u64 = 1341; Count.u64 = 1341; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1321; SumSQ.u64 = 1321; Count.u64 = 1321; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 1094; SumSQ.u64 = 1094; Count.u64 = 1094; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 2474; SumSQ.u64 = 2474; Count.u64 = 2474; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 2375; SumSQ.u64 = 2375; Count.u64 = 2375; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1767; SumSQ.u64 = 1767; Count.u64 = 1767; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1063,7 +1111,7 @@ l2cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 840; SumSQ.u64 = 840; Count.u64 = 840; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1084,11 +1132,11 @@ l2cache2.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1518; SumSQ.u64 = 1518; Count.u64 = 1518; Min.u64 = 1; Max.u64 = 1; - l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1467; SumSQ.u64 = 1467; Count.u64 = 1467; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1099,65 +1147,72 @@ l2cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 2206; SumSQ.u64 = 2206; Count.u64 = 2206; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 2499; SumSQ.u64 = 2499; Count.u64 = 2499; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 2236; SumSQ.u64 = 2236; Count.u64 = 2236; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 2462; SumSQ.u64 = 2462; Count.u64 = 2462; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 759; SumSQ.u64 = 759; Count.u64 = 759; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 986; SumSQ.u64 = 986; Count.u64 = 986; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 2381; SumSQ.u64 = 2381; Count.u64 = 2381; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 6330; SumSQ.u64 = 6330; Count.u64 = 6330; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 2183; SumSQ.u64 = 2183; Count.u64 = 2183; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 1839; Count.u64 = 1839; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 995; SumSQ.u64 = 995; Count.u64 = 995; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 2328; SumSQ.u64 = 2328; Count.u64 = 2328; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 6080; SumSQ.u64 = 6080; Count.u64 = 6080; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1838; SumSQ.u64 = 1838; Count.u64 = 1838; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 645; SumSQ.u64 = 645; Count.u64 = 645; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; - l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 1603; SumSQ.u64 = 1603; Count.u64 = 1603; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 1547; SumSQ.u64 = 1547; Count.u64 = 1547; Min.u64 = 1; Max.u64 = 1; l2cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 6480; SumSQ.u64 = 1160734; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1045; - l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 170528; SumSQ.u64 = 29121114; Count.u64 = 1817; Min.u64 = 36; Max.u64 = 1129; + l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 7267; SumSQ.u64 = 116911; Count.u64 = 1153; Min.u64 = 1; Max.u64 = 142; + l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 180670; SumSQ.u64 = 54293010; Count.u64 = 1738; Min.u64 = 37; Max.u64 = 2239; l2cache2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 279; SumSQ.u64 = 3133; Count.u64 = 25; Min.u64 = 10; Max.u64 = 13; - l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 184544; SumSQ.u64 = 78712226; Count.u64 = 1254; Min.u64 = 65; Max.u64 = 3260; + l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 297; SumSQ.u64 = 3411; Count.u64 = 26; Min.u64 = 10; Max.u64 = 13; + l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 187666; SumSQ.u64 = 85472674; Count.u64 = 1243; Min.u64 = 64; Max.u64 = 3489; l2cache2.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 67150; SumSQ.u64 = 21664602; Count.u64 = 510; Min.u64 = 56; Max.u64 = 2533; + l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 65401; SumSQ.u64 = 20774661; Count.u64 = 486; Min.u64 = 58; Max.u64 = 1708; l2cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1868; SumSQ.u64 = 1868; Count.u64 = 1868; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 1756; SumSQ.u64 = 1756; Count.u64 = 1756; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1787; SumSQ.u64 = 1787; Count.u64 = 1787; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 1722; SumSQ.u64 = 1722; Count.u64 = 1722; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.CacheHits : Accumulator : Sum.u64 = 1030; SumSQ.u64 = 1030; Count.u64 = 1030; Min.u64 = 1; Max.u64 = 1; - l2cache2.CacheMisses : Accumulator : Sum.u64 = 3633; SumSQ.u64 = 3633; Count.u64 = 3633; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheHits : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheMisses : Accumulator : Sum.u64 = 3519; SumSQ.u64 = 3519; Count.u64 = 3519; Min.u64 = 1; Max.u64 = 1; l2cache2.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.prefetch_inv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; - l2cache2.prefetch_useful : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l2cache2.prefetch_coherence_miss : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l2cache2.prefetch_redundant : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; + l2cache2.prefetch_inv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache2.prefetch_useful : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache2.prefetch_coherence_miss : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.prefetch_redundant : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1167,10 +1222,10 @@ l2cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1179,23 +1234,23 @@ l2cache2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 23655; SumSQ.u64 = 23655; Count.u64 = 23655; Min.u64 = 1; Max.u64 = 1; - l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 3069; SumSQ.u64 = 3069; Count.u64 = 3069; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 23350; SumSQ.u64 = 23350; Count.u64 = 23350; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 2927; SumSQ.u64 = 2927; Count.u64 = 2927; Min.u64 = 1; Max.u64 = 1; l2cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1208,60 +1263,65 @@ l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetS_recv : Accumulator : Sum.u64 = 8484; SumSQ.u64 = 8484; Count.u64 = 8484; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetX_recv : Accumulator : Sum.u64 = 4770; SumSQ.u64 = 4770; Count.u64 = 4770; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetS_recv : Accumulator : Sum.u64 = 8210; SumSQ.u64 = 8210; Count.u64 = 8210; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetX_recv : Accumulator : Sum.u64 = 4802; SumSQ.u64 = 4802; Count.u64 = 4802; Min.u64 = 1; Max.u64 = 1; l2cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 1864; SumSQ.u64 = 1864; Count.u64 = 1864; Min.u64 = 1; Max.u64 = 1; - l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 1785; SumSQ.u64 = 1785; Count.u64 = 1785; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 1734; SumSQ.u64 = 1734; Count.u64 = 1734; Min.u64 = 1; Max.u64 = 1; l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.PutS_recv : Accumulator : Sum.u64 = 1059; SumSQ.u64 = 1059; Count.u64 = 1059; Min.u64 = 1; Max.u64 = 1; - l2cache2.PutM_recv : Accumulator : Sum.u64 = 392; SumSQ.u64 = 392; Count.u64 = 392; Min.u64 = 1; Max.u64 = 1; - l2cache2.PutE_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.PutS_recv : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutM_recv : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutE_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.Inv_recv : Accumulator : Sum.u64 = 2568; SumSQ.u64 = 2568; Count.u64 = 2568; Min.u64 = 1; Max.u64 = 1; + l2cache2.Inv_recv : Accumulator : Sum.u64 = 2464; SumSQ.u64 = 2464; Count.u64 = 2464; Min.u64 = 1; Max.u64 = 1; l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; - l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 1068; SumSQ.u64 = 1068; Count.u64 = 1068; Min.u64 = 1; Max.u64 = 1; - l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 629; SumSQ.u64 = 629; Count.u64 = 629; Min.u64 = 1; Max.u64 = 1; - l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; - l2cache2.NACK_recv : Accumulator : Sum.u64 = 1072; SumSQ.u64 = 1072; Count.u64 = 1072; Min.u64 = 1; Max.u64 = 1; - l2cache2.AckInv_recv : Accumulator : Sum.u64 = 1590; SumSQ.u64 = 1590; Count.u64 = 1590; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 778; SumSQ.u64 = 778; Count.u64 = 778; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 570; SumSQ.u64 = 570; Count.u64 = 570; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.NACK_recv : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckInv_recv : Accumulator : Sum.u64 = 1533; SumSQ.u64 = 1533; Count.u64 = 1533; Min.u64 = 1; Max.u64 = 1; l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 434359; SumSQ.u64 = 2842445; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 8; + l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 441806; SumSQ.u64 = 2876802; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 8; l2cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core3.pendCycle : Accumulator : Sum.u64 = 850966; SumSQ.u64 = 13280508; Count.u64 = 54714; Min.u64 = 0; Max.u64 = 16; - core3.reads : Accumulator : Sum.u64 = 3026; SumSQ.u64 = 3026; Count.u64 = 3026; Min.u64 = 1; Max.u64 = 1; - core3.writes : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; - l1cache3.Prefetch_requests : Accumulator : Sum.u64 = 3638; SumSQ.u64 = 3638; Count.u64 = 3638; Min.u64 = 1; Max.u64 = 1; - l1cache3.Prefetch_drops : Accumulator : Sum.u64 = 2493; SumSQ.u64 = 2493; Count.u64 = 2493; Min.u64 = 1; Max.u64 = 1; + core3.pendCycle : Accumulator : Sum.u64 = 907436; SumSQ.u64 = 14179798; Count.u64 = 58276; Min.u64 = 0; Max.u64 = 16; + core3.reads : Accumulator : Sum.u64 = 2993; SumSQ.u64 = 2993; Count.u64 = 2993; Min.u64 = 1; Max.u64 = 1; + core3.writes : Accumulator : Sum.u64 = 2007; SumSQ.u64 = 2007; Count.u64 = 2007; Min.u64 = 1; Max.u64 = 1; + l1cache3.Prefetch_requests : Accumulator : Sum.u64 = 3618; SumSQ.u64 = 3618; Count.u64 = 3618; Min.u64 = 1; Max.u64 = 1; + l1cache3.Prefetch_drops : Accumulator : Sum.u64 = 2355; SumSQ.u64 = 2355; Count.u64 = 2355; Min.u64 = 1; Max.u64 = 1; l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 2282; SumSQ.u64 = 2282; Count.u64 = 2282; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 1308; SumSQ.u64 = 1308; Count.u64 = 1308; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 1275; SumSQ.u64 = 1275; Count.u64 = 1275; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 243; SumSQ.u64 = 243; Count.u64 = 243; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 2309; SumSQ.u64 = 2309; Count.u64 = 2309; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 1363; SumSQ.u64 = 1363; Count.u64 = 1363; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 571; SumSQ.u64 = 571; Count.u64 = 571; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 1339; SumSQ.u64 = 1339; Count.u64 = 1339; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2212; SumSQ.u64 = 2212; Count.u64 = 2212; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1364; SumSQ.u64 = 1364; Count.u64 = 1364; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 359; SumSQ.u64 = 359; Count.u64 = 359; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 1449; SumSQ.u64 = 1449; Count.u64 = 1449; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2243; SumSQ.u64 = 2243; Count.u64 = 2243; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 689; SumSQ.u64 = 689; Count.u64 = 689; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 655; SumSQ.u64 = 655; Count.u64 = 655; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1275,8 +1335,8 @@ l1cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 602; SumSQ.u64 = 602; Count.u64 = 602; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 704; SumSQ.u64 = 704; Count.u64 = 704; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1298,21 +1358,24 @@ l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 5215; SumSQ.u64 = 5215; Count.u64 = 5215; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 4574; SumSQ.u64 = 4574; Count.u64 = 4574; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 5358; SumSQ.u64 = 5358; Count.u64 = 5358; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 4644; SumSQ.u64 = 4644; Count.u64 = 4644; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 440; SumSQ.u64 = 440; Count.u64 = 440; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 621; SumSQ.u64 = 621; Count.u64 = 621; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 1538; SumSQ.u64 = 1538; Count.u64 = 1538; Min.u64 = 1; Max.u64 = 1; - l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 3026; SumSQ.u64 = 3026; Count.u64 = 3026; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 723; SumSQ.u64 = 723; Count.u64 = 723; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 1572; SumSQ.u64 = 1572; Count.u64 = 1572; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 2993; SumSQ.u64 = 2993; Count.u64 = 2993; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 2007; SumSQ.u64 = 2007; Count.u64 = 2007; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1320,18 +1383,18 @@ l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.evict_I : Accumulator : Sum.u64 = 1763; SumSQ.u64 = 1763; Count.u64 = 1763; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_S : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_M : Accumulator : Sum.u64 = 440; SumSQ.u64 = 440; Count.u64 = 440; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_IS : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_IM : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; - l1cache3.evict_SM : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_I : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_S : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_M : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IS : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IM : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_SM : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 201100; SumSQ.u64 = 284402590; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 5007; - l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 421324; SumSQ.u64 = 409437910; Count.u64 = 2282; Min.u64 = 13; Max.u64 = 5296; - l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 73003; SumSQ.u64 = 95756007; Count.u64 = 251; Min.u64 = 2; Max.u64 = 3473; - l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 304659; SumSQ.u64 = 259087621; Count.u64 = 1275; Min.u64 = 16; Max.u64 = 5414; - l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 136795; SumSQ.u64 = 147897825; Count.u64 = 448; Min.u64 = 68; Max.u64 = 4084; + l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 213954; SumSQ.u64 = 297356950; Count.u64 = 1947; Min.u64 = 1; Max.u64 = 4320; + l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 424874; SumSQ.u64 = 418106444; Count.u64 = 2309; Min.u64 = 13; Max.u64 = 5272; + l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 69400; SumSQ.u64 = 96115062; Count.u64 = 268; Min.u64 = 2; Max.u64 = 3332; + l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 365598; SumSQ.u64 = 395166812; Count.u64 = 1339; Min.u64 = 16; Max.u64 = 5299; + l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 135126; SumSQ.u64 = 153192374; Count.u64 = 400; Min.u64 = 72; Max.u64 = 4459; l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1339,39 +1402,40 @@ l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 1362; SumSQ.u64 = 1362; Count.u64 = 1362; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 1374; SumSQ.u64 = 1374; Count.u64 = 1374; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 1410; SumSQ.u64 = 1410; Count.u64 = 1410; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1983; SumSQ.u64 = 1983; Count.u64 = 1983; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.CacheHits : Accumulator : Sum.u64 = 2140; SumSQ.u64 = 2140; Count.u64 = 2140; Min.u64 = 1; Max.u64 = 1; - l1cache3.CacheMisses : Accumulator : Sum.u64 = 4005; SumSQ.u64 = 4005; Count.u64 = 4005; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheHits : Accumulator : Sum.u64 = 2215; SumSQ.u64 = 2215; Count.u64 = 2215; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheMisses : Accumulator : Sum.u64 = 4048; SumSQ.u64 = 4048; Count.u64 = 4048; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache3.prefetch_evict : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; - l1cache3.prefetch_inv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; - l1cache3.prefetch_useful : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; + l1cache3.prefetch_evict : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; + l1cache3.prefetch_inv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache3.prefetch_useful : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; l1cache3.prefetch_coherence_miss : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; - l1cache3.prefetch_redundant : Accumulator : Sum.u64 = 778; SumSQ.u64 = 778; Count.u64 = 778; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.prefetch_redundant : Accumulator : Sum.u64 = 833; SumSQ.u64 = 833; Count.u64 = 833; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l1cache3.evict_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 17716; SumSQ.u64 = 17716; Count.u64 = 17716; Min.u64 = 1; Max.u64 = 1; - l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1870; SumSQ.u64 = 1870; Count.u64 = 1870; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 18027; SumSQ.u64 = 18027; Count.u64 = 18027; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1929; SumSQ.u64 = 1929; Count.u64 = 1929; Min.u64 = 1; Max.u64 = 1; l1cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1384,80 +1448,84 @@ l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetS_recv : Accumulator : Sum.u64 = 6664; SumSQ.u64 = 6664; Count.u64 = 6664; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetS_recv : Accumulator : Sum.u64 = 6611; SumSQ.u64 = 6611; Count.u64 = 6611; Min.u64 = 1; Max.u64 = 1; l1cache3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.Write_recv : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_recv : Accumulator : Sum.u64 = 2007; SumSQ.u64 = 2007; Count.u64 = 2007; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 2212; SumSQ.u64 = 2212; Count.u64 = 2212; Min.u64 = 1; Max.u64 = 1; - l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 2243; SumSQ.u64 = 2243; Count.u64 = 2243; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.Inv_recv : Accumulator : Sum.u64 = 1550; SumSQ.u64 = 1550; Count.u64 = 1550; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Inv_recv : Accumulator : Sum.u64 = 1583; SumSQ.u64 = 1583; Count.u64 = 1583; Min.u64 = 1; Max.u64 = 1; l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; - l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; - l1cache3.NACK_recv : Accumulator : Sum.u64 = 5784; SumSQ.u64 = 5784; Count.u64 = 5784; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.NACK_recv : Accumulator : Sum.u64 = 5954; SumSQ.u64 = 5954; Count.u64 = 5954; Min.u64 = 1; Max.u64 = 1; l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1115095; SumSQ.u64 = 19054203; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 18; + l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1187012; SumSQ.u64 = 20275464; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 18; l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.packet_latency : Accumulator : Sum.u64 = 13307; SumSQ.u64 = 29181; Count.u64 = 8858; Min.u64 = 0; Max.u64 = 9; - l2cache3:memlink.send_bit_count : Accumulator : Sum.u64 = 1575584; SumSQ.u64 = 638898688; Count.u64 = 8866; Min.u64 = 80; Max.u64 = 592; - l2cache3:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3:memlink.idle_time : Accumulator : Sum.u64 = 13251317; SumSQ.u64 = 650041535835; Count.u64 = 6582; Min.u64 = 1; Max.u64 = 732747; - l2cache3.Prefetch_requests : Accumulator : Sum.u64 = 3194; SumSQ.u64 = 3194; Count.u64 = 3194; Min.u64 = 1; Max.u64 = 1; - l2cache3.Prefetch_drops : Accumulator : Sum.u64 = 2563; SumSQ.u64 = 2563; Count.u64 = 2563; Min.u64 = 1; Max.u64 = 1; + l2cache3:lowlink.packet_latency : Accumulator : Sum.u64 = 13545; SumSQ.u64 = 28947; Count.u64 = 9170; Min.u64 = 0; Max.u64 = 9; + l2cache3:lowlink.send_bit_count : Accumulator : Sum.u64 = 1607120; SumSQ.u64 = 645361920; Count.u64 = 9177; Min.u64 = 80; Max.u64 = 592; + l2cache3:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3:lowlink.idle_time : Accumulator : Sum.u64 = 13508168; SumSQ.u64 = 128295549292; Count.u64 = 6781; Min.u64 = 1; Max.u64 = 232330; + l2cache3.Prefetch_requests : Accumulator : Sum.u64 = 3239; SumSQ.u64 = 3239; Count.u64 = 3239; Min.u64 = 1; Max.u64 = 1; + l2cache3.Prefetch_drops : Accumulator : Sum.u64 = 2625; SumSQ.u64 = 2625; Count.u64 = 2625; Min.u64 = 1; Max.u64 = 1; l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.evict_I : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_I : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.evict_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l2cache3.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 1839; Count.u64 = 1839; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 914; SumSQ.u64 = 914; Count.u64 = 914; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 1101; SumSQ.u64 = 1101; Count.u64 = 1101; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 587; SumSQ.u64 = 587; Count.u64 = 587; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1913; SumSQ.u64 = 1913; Count.u64 = 1913; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 868; SumSQ.u64 = 868; Count.u64 = 868; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 1202; SumSQ.u64 = 1202; Count.u64 = 1202; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 500; SumSQ.u64 = 500; Count.u64 = 500; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1180; SumSQ.u64 = 1180; Count.u64 = 1180; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1910; SumSQ.u64 = 1910; Count.u64 = 1910; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1295; SumSQ.u64 = 1295; Count.u64 = 1295; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 1019; SumSQ.u64 = 1019; Count.u64 = 1019; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 2307; SumSQ.u64 = 2307; Count.u64 = 2307; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1641; SumSQ.u64 = 1641; Count.u64 = 1641; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1531; SumSQ.u64 = 1531; Count.u64 = 1531; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1475,7 +1543,7 @@ l2cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1496,11 +1564,11 @@ l2cache3.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 621; SumSQ.u64 = 621; Count.u64 = 621; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 713; SumSQ.u64 = 713; Count.u64 = 713; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 723; SumSQ.u64 = 723; Count.u64 = 723; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1484; SumSQ.u64 = 1484; Count.u64 = 1484; Min.u64 = 1; Max.u64 = 1; - l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1499; SumSQ.u64 = 1499; Count.u64 = 1499; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1511,65 +1579,72 @@ l2cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 2227; SumSQ.u64 = 2227; Count.u64 = 2227; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 2390; SumSQ.u64 = 2390; Count.u64 = 2390; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 2369; SumSQ.u64 = 2369; Count.u64 = 2369; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 2461; SumSQ.u64 = 2461; Count.u64 = 2461; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 2233; SumSQ.u64 = 2233; Count.u64 = 2233; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 6102; SumSQ.u64 = 6102; Count.u64 = 6102; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 2212; SumSQ.u64 = 2212; Count.u64 = 2212; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 867; SumSQ.u64 = 867; Count.u64 = 867; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 2322; SumSQ.u64 = 2322; Count.u64 = 2322; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 6268; SumSQ.u64 = 6268; Count.u64 = 6268; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 2243; SumSQ.u64 = 2243; Count.u64 = 2243; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; - l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 1550; SumSQ.u64 = 1550; Count.u64 = 1550; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 1583; SumSQ.u64 = 1583; Count.u64 = 1583; Min.u64 = 1; Max.u64 = 1; l2cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 6267; SumSQ.u64 = 78043; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 81; - l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 174303; SumSQ.u64 = 33080253; Count.u64 = 1800; Min.u64 = 37; Max.u64 = 2158; + l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 6361; SumSQ.u64 = 597299; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 728; + l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 182262; SumSQ.u64 = 36002488; Count.u64 = 1874; Min.u64 = 37; Max.u64 = 1188; l2cache3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 411; SumSQ.u64 = 4929; Count.u64 = 35; Min.u64 = 10; Max.u64 = 18; - l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 161085; SumSQ.u64 = 51661667; Count.u64 = 1101; Min.u64 = 62; Max.u64 = 2259; + l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 424; SumSQ.u64 = 4910; Count.u64 = 37; Min.u64 = 10; Max.u64 = 15; + l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 181386; SumSQ.u64 = 60561808; Count.u64 = 1202; Min.u64 = 46; Max.u64 = 2155; l2cache3.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 70387; SumSQ.u64 = 13011037; Count.u64 = 587; Min.u64 = 59; Max.u64 = 1085; + l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 70305; SumSQ.u64 = 32870951; Count.u64 = 500; Min.u64 = 62; Max.u64 = 3411; l2cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1837; SumSQ.u64 = 1837; Count.u64 = 1837; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 1682; SumSQ.u64 = 1682; Count.u64 = 1682; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1913; SumSQ.u64 = 1913; Count.u64 = 1913; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 1693; SumSQ.u64 = 1693; Count.u64 = 1693; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.CacheHits : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; - l2cache3.CacheMisses : Accumulator : Sum.u64 = 3527; SumSQ.u64 = 3527; Count.u64 = 3527; Min.u64 = 1; Max.u64 = 1; - l2cache3.prefetch_evict : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache3.prefetch_inv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; - l2cache3.prefetch_useful : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l2cache3.prefetch_coherence_miss : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l2cache3.prefetch_redundant : Accumulator : Sum.u64 = 592; SumSQ.u64 = 592; Count.u64 = 592; Min.u64 = 1; Max.u64 = 1; + l2cache3.CacheHits : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l2cache3.CacheMisses : Accumulator : Sum.u64 = 3615; SumSQ.u64 = 3615; Count.u64 = 3615; Min.u64 = 1; Max.u64 = 1; + l2cache3.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.prefetch_inv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache3.prefetch_useful : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.prefetch_coherence_miss : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache3.prefetch_redundant : Accumulator : Sum.u64 = 575; SumSQ.u64 = 575; Count.u64 = 575; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1591,7 +1666,7 @@ l2cache3.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1601,13 +1676,13 @@ l2cache3.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l2cache3.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 23009; SumSQ.u64 = 23009; Count.u64 = 23009; Min.u64 = 1; Max.u64 = 1; - l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 2943; SumSQ.u64 = 2943; Count.u64 = 2943; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 23609; SumSQ.u64 = 23609; Count.u64 = 23609; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 3040; SumSQ.u64 = 3040; Count.u64 = 3040; Min.u64 = 1; Max.u64 = 1; l2cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1620,60 +1695,65 @@ l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetS_recv : Accumulator : Sum.u64 = 8409; SumSQ.u64 = 8409; Count.u64 = 8409; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetX_recv : Accumulator : Sum.u64 = 4574; SumSQ.u64 = 4574; Count.u64 = 4574; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetS_recv : Accumulator : Sum.u64 = 8597; SumSQ.u64 = 8597; Count.u64 = 8597; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetX_recv : Accumulator : Sum.u64 = 4644; SumSQ.u64 = 4644; Count.u64 = 4644; Min.u64 = 1; Max.u64 = 1; l2cache3.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 1835; SumSQ.u64 = 1835; Count.u64 = 1835; Min.u64 = 1; Max.u64 = 1; - l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 1692; SumSQ.u64 = 1692; Count.u64 = 1692; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 1910; SumSQ.u64 = 1910; Count.u64 = 1910; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.PutS_recv : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; - l2cache3.PutM_recv : Accumulator : Sum.u64 = 440; SumSQ.u64 = 440; Count.u64 = 440; Min.u64 = 1; Max.u64 = 1; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.PutS_recv : Accumulator : Sum.u64 = 1060; SumSQ.u64 = 1060; Count.u64 = 1060; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutM_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; l2cache3.PutE_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.Inv_recv : Accumulator : Sum.u64 = 2397; SumSQ.u64 = 2397; Count.u64 = 2397; Min.u64 = 1; Max.u64 = 1; + l2cache3.Inv_recv : Accumulator : Sum.u64 = 2483; SumSQ.u64 = 2483; Count.u64 = 2483; Min.u64 = 1; Max.u64 = 1; l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 853; SumSQ.u64 = 853; Count.u64 = 853; Min.u64 = 1; Max.u64 = 1; - l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 991; SumSQ.u64 = 991; Count.u64 = 991; Min.u64 = 1; Max.u64 = 1; - l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 621; SumSQ.u64 = 621; Count.u64 = 621; Min.u64 = 1; Max.u64 = 1; - l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; - l2cache3.NACK_recv : Accumulator : Sum.u64 = 1090; SumSQ.u64 = 1090; Count.u64 = 1090; Min.u64 = 1; Max.u64 = 1; - l2cache3.AckInv_recv : Accumulator : Sum.u64 = 1538; SumSQ.u64 = 1538; Count.u64 = 1538; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 898; SumSQ.u64 = 898; Count.u64 = 898; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 723; SumSQ.u64 = 723; Count.u64 = 723; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.NACK_recv : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckInv_recv : Accumulator : Sum.u64 = 1572; SumSQ.u64 = 1572; Count.u64 = 1572; Min.u64 = 1; Max.u64 = 1; l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 411956; SumSQ.u64 = 2704070; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 8; + l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 442334; SumSQ.u64 = 2896546; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 8; l2cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core4.pendCycle : Accumulator : Sum.u64 = 871323; SumSQ.u64 = 13585211; Count.u64 = 56225; Min.u64 = 0; Max.u64 = 16; - core4.reads : Accumulator : Sum.u64 = 3003; SumSQ.u64 = 3003; Count.u64 = 3003; Min.u64 = 1; Max.u64 = 1; - core4.writes : Accumulator : Sum.u64 = 1997; SumSQ.u64 = 1997; Count.u64 = 1997; Min.u64 = 1; Max.u64 = 1; - l1cache4.Prefetch_requests : Accumulator : Sum.u64 = 3636; SumSQ.u64 = 3636; Count.u64 = 3636; Min.u64 = 1; Max.u64 = 1; - l1cache4.Prefetch_drops : Accumulator : Sum.u64 = 2349; SumSQ.u64 = 2349; Count.u64 = 2349; Min.u64 = 1; Max.u64 = 1; + core4.pendCycle : Accumulator : Sum.u64 = 895238; SumSQ.u64 = 13977546; Count.u64 = 57637; Min.u64 = 0; Max.u64 = 16; + core4.reads : Accumulator : Sum.u64 = 2988; SumSQ.u64 = 2988; Count.u64 = 2988; Min.u64 = 1; Max.u64 = 1; + core4.writes : Accumulator : Sum.u64 = 2012; SumSQ.u64 = 2012; Count.u64 = 2012; Min.u64 = 1; Max.u64 = 1; + l1cache4.Prefetch_requests : Accumulator : Sum.u64 = 3596; SumSQ.u64 = 3596; Count.u64 = 3596; Min.u64 = 1; Max.u64 = 1; + l1cache4.Prefetch_drops : Accumulator : Sum.u64 = 2389; SumSQ.u64 = 2389; Count.u64 = 2389; Min.u64 = 1; Max.u64 = 1; l1cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 2372; SumSQ.u64 = 2372; Count.u64 = 2372; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 1319; SumSQ.u64 = 1319; Count.u64 = 1319; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 1284; SumSQ.u64 = 1284; Count.u64 = 1284; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 472; SumSQ.u64 = 472; Count.u64 = 472; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 2201; SumSQ.u64 = 2201; Count.u64 = 2201; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 1380; SumSQ.u64 = 1380; Count.u64 = 1380; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 1350; SumSQ.u64 = 1350; Count.u64 = 1350; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 2319; Count.u64 = 2319; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1401; SumSQ.u64 = 1401; Count.u64 = 1401; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_Inv_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 1482; SumSQ.u64 = 1482; Count.u64 = 1482; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2139; SumSQ.u64 = 2139; Count.u64 = 2139; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1473; SumSQ.u64 = 1473; Count.u64 = 1473; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 1357; SumSQ.u64 = 1357; Count.u64 = 1357; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 667; SumSQ.u64 = 667; Count.u64 = 667; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1685,10 +1765,10 @@ l1cache4.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 710; SumSQ.u64 = 710; Count.u64 = 710; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1710,21 +1790,24 @@ l1cache4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_GetS : Accumulator : Sum.u64 = 5492; SumSQ.u64 = 5492; Count.u64 = 5492; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_GetX : Accumulator : Sum.u64 = 4762; SumSQ.u64 = 4762; Count.u64 = 4762; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_GetS : Accumulator : Sum.u64 = 5190; SumSQ.u64 = 5190; Count.u64 = 5190; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_GetX : Accumulator : Sum.u64 = 4494; SumSQ.u64 = 4494; Count.u64 = 4494; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_PutM : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_PutM : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 1599; SumSQ.u64 = 1599; Count.u64 = 1599; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 3003; SumSQ.u64 = 3003; Count.u64 = 3003; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 726; SumSQ.u64 = 726; Count.u64 = 726; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 694; SumSQ.u64 = 694; Count.u64 = 694; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckInv : Accumulator : Sum.u64 = 1480; SumSQ.u64 = 1480; Count.u64 = 1480; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 2988; SumSQ.u64 = 2988; Count.u64 = 2988; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 1997; SumSQ.u64 = 1997; Count.u64 = 1997; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 2012; SumSQ.u64 = 2012; Count.u64 = 2012; Min.u64 = 1; Max.u64 = 1; l1cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1732,18 +1815,18 @@ l1cache4.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.evict_I : Accumulator : Sum.u64 = 1714; SumSQ.u64 = 1714; Count.u64 = 1714; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_S : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_M : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_IS : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_IM : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_SM : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_I : Accumulator : Sum.u64 = 1744; SumSQ.u64 = 1744; Count.u64 = 1744; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_S : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_M : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_IS : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_IM : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_SM : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l1cache4.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.latency_GetS_hit : Accumulator : Sum.u64 = 217418; SumSQ.u64 = 316672538; Count.u64 = 1918; Min.u64 = 1; Max.u64 = 4992; - l1cache4.latency_GetS_miss : Accumulator : Sum.u64 = 432471; SumSQ.u64 = 365543811; Count.u64 = 2372; Min.u64 = 13; Max.u64 = 3697; - l1cache4.latency_GetX_hit : Accumulator : Sum.u64 = 67052; SumSQ.u64 = 96556012; Count.u64 = 241; Min.u64 = 2; Max.u64 = 4469; - l1cache4.latency_GetX_miss : Accumulator : Sum.u64 = 307757; SumSQ.u64 = 273068733; Count.u64 = 1284; Min.u64 = 16; Max.u64 = 5352; - l1cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 135424; SumSQ.u64 = 128151860; Count.u64 = 472; Min.u64 = 68; Max.u64 = 3625; + l1cache4.latency_GetS_hit : Accumulator : Sum.u64 = 244392; SumSQ.u64 = 360172608; Count.u64 = 1994; Min.u64 = 1; Max.u64 = 4123; + l1cache4.latency_GetS_miss : Accumulator : Sum.u64 = 402028; SumSQ.u64 = 405904326; Count.u64 = 2201; Min.u64 = 13; Max.u64 = 5386; + l1cache4.latency_GetX_hit : Accumulator : Sum.u64 = 77783; SumSQ.u64 = 115640667; Count.u64 = 227; Min.u64 = 2; Max.u64 = 3015; + l1cache4.latency_GetX_miss : Accumulator : Sum.u64 = 346592; SumSQ.u64 = 385353320; Count.u64 = 1350; Min.u64 = 16; Max.u64 = 4333; + l1cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 123684; SumSQ.u64 = 115594588; Count.u64 = 435; Min.u64 = 68; Max.u64 = 4318; l1cache4.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1751,39 +1834,40 @@ l1cache4.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 1352; SumSQ.u64 = 1352; Count.u64 = 1352; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 1416; SumSQ.u64 = 1416; Count.u64 = 1416; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 566; SumSQ.u64 = 566; Count.u64 = 566; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXHit_Blocked : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 578; SumSQ.u64 = 578; Count.u64 = 578; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXHit_Blocked : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 2053; SumSQ.u64 = 2053; Count.u64 = 2053; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 1451; SumSQ.u64 = 1451; Count.u64 = 1451; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 1897; SumSQ.u64 = 1897; Count.u64 = 1897; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 1460; SumSQ.u64 = 1460; Count.u64 = 1460; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l1cache4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.CacheHits : Accumulator : Sum.u64 = 2159; SumSQ.u64 = 2159; Count.u64 = 2159; Min.u64 = 1; Max.u64 = 1; - l1cache4.CacheMisses : Accumulator : Sum.u64 = 4128; SumSQ.u64 = 4128; Count.u64 = 4128; Min.u64 = 1; Max.u64 = 1; + l1cache4.CacheHits : Accumulator : Sum.u64 = 2221; SumSQ.u64 = 2221; Count.u64 = 2221; Min.u64 = 1; Max.u64 = 1; + l1cache4.CacheMisses : Accumulator : Sum.u64 = 3986; SumSQ.u64 = 3986; Count.u64 = 3986; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.eventSent_PutS : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; - l1cache4.eventSent_PutE : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache4.prefetch_evict : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; - l1cache4.prefetch_inv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; - l1cache4.prefetch_useful : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; - l1cache4.prefetch_coherence_miss : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; - l1cache4.prefetch_redundant : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetS_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l1cache4.stateEvent_GetX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_PutS : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; + l1cache4.eventSent_PutE : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache4.prefetch_evict : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache4.prefetch_inv : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; + l1cache4.prefetch_useful : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache4.prefetch_coherence_miss : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache4.prefetch_redundant : Accumulator : Sum.u64 = 817; SumSQ.u64 = 817; Count.u64 = 817; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetS_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_GetX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache4.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l1cache4.evict_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l1cache4.TotalEventsReceived : Accumulator : Sum.u64 = 18269; SumSQ.u64 = 18269; Count.u64 = 18269; Min.u64 = 1; Max.u64 = 1; - l1cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 1806; SumSQ.u64 = 1806; Count.u64 = 1806; Min.u64 = 1; Max.u64 = 1; + l1cache4.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache4.evict_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache4.TotalEventsReceived : Accumulator : Sum.u64 = 17626; SumSQ.u64 = 17626; Count.u64 = 17626; Min.u64 = 1; Max.u64 = 1; + l1cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 1863; SumSQ.u64 = 1863; Count.u64 = 1863; Min.u64 = 1; Max.u64 = 1; l1cache4.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1796,80 +1880,84 @@ l1cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetS_recv : Accumulator : Sum.u64 = 6639; SumSQ.u64 = 6639; Count.u64 = 6639; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetS_recv : Accumulator : Sum.u64 = 6584; SumSQ.u64 = 6584; Count.u64 = 6584; Min.u64 = 1; Max.u64 = 1; l1cache4.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.Write_recv : Accumulator : Sum.u64 = 1997; SumSQ.u64 = 1997; Count.u64 = 1997; Min.u64 = 1; Max.u64 = 1; + l1cache4.Write_recv : Accumulator : Sum.u64 = 2012; SumSQ.u64 = 2012; Count.u64 = 2012; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 2319; Count.u64 = 2319; Min.u64 = 1; Max.u64 = 1; - l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.GetSResp_recv : Accumulator : Sum.u64 = 2139; SumSQ.u64 = 2139; Count.u64 = 2139; Min.u64 = 1; Max.u64 = 1; + l1cache4.GetXResp_recv : Accumulator : Sum.u64 = 1847; SumSQ.u64 = 1847; Count.u64 = 1847; Min.u64 = 1; Max.u64 = 1; l1cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.Inv_recv : Accumulator : Sum.u64 = 1611; SumSQ.u64 = 1611; Count.u64 = 1611; Min.u64 = 1; Max.u64 = 1; + l1cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.Inv_recv : Accumulator : Sum.u64 = 1486; SumSQ.u64 = 1486; Count.u64 = 1486; Min.u64 = 1; Max.u64 = 1; l1cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; - l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; - l1cache4.NACK_recv : Accumulator : Sum.u64 = 6126; SumSQ.u64 = 6126; Count.u64 = 6126; Min.u64 = 1; Max.u64 = 1; + l1cache4.FetchInv_recv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; + l1cache4.FetchInvX_recv : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; + l1cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.NACK_recv : Accumulator : Sum.u64 = 5698; SumSQ.u64 = 5698; Count.u64 = 5698; Min.u64 = 1; Max.u64 = 1; l1cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 1138146; SumSQ.u64 = 19369810; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 18; + l1cache4.MSHR_occupancy : Accumulator : Sum.u64 = 1172505; SumSQ.u64 = 20032699; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 18; l1cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.packet_latency : Accumulator : Sum.u64 = 14293; SumSQ.u64 = 32101; Count.u64 = 9345; Min.u64 = 0; Max.u64 = 8; - l2cache4:memlink.send_bit_count : Accumulator : Sum.u64 = 1634752; SumSQ.u64 = 655453184; Count.u64 = 9356; Min.u64 = 80; Max.u64 = 592; - l2cache4:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4:memlink.idle_time : Accumulator : Sum.u64 = 12623559; SumSQ.u64 = 128834257451; Count.u64 = 6799; Min.u64 = 1; Max.u64 = 238602; - l2cache4.Prefetch_requests : Accumulator : Sum.u64 = 3254; SumSQ.u64 = 3254; Count.u64 = 3254; Min.u64 = 1; Max.u64 = 1; - l2cache4.Prefetch_drops : Accumulator : Sum.u64 = 2616; SumSQ.u64 = 2616; Count.u64 = 2616; Min.u64 = 1; Max.u64 = 1; + l2cache4:lowlink.packet_latency : Accumulator : Sum.u64 = 13220; SumSQ.u64 = 28662; Count.u64 = 8948; Min.u64 = 0; Max.u64 = 9; + l2cache4:lowlink.send_bit_count : Accumulator : Sum.u64 = 1620800; SumSQ.u64 = 664642560; Count.u64 = 8964; Min.u64 = 80; Max.u64 = 592; + l2cache4:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4:lowlink.idle_time : Accumulator : Sum.u64 = 13518049; SumSQ.u64 = 247622723555; Count.u64 = 6493; Min.u64 = 1; Max.u64 = 255211; + l2cache4.Prefetch_requests : Accumulator : Sum.u64 = 3218; SumSQ.u64 = 3218; Count.u64 = 3218; Min.u64 = 1; Max.u64 = 1; + l2cache4.Prefetch_drops : Accumulator : Sum.u64 = 2560; SumSQ.u64 = 2560; Count.u64 = 2560; Min.u64 = 1; Max.u64 = 1; l2cache4.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.evict_I : Accumulator : Sum.u64 = 177; SumSQ.u64 = 177; Count.u64 = 177; Min.u64 = 1; Max.u64 = 1; + l2cache4.evict_I : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_S : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.evict_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache4.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.evict_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 1978; SumSQ.u64 = 1978; Count.u64 = 1978; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 884; SumSQ.u64 = 884; Count.u64 = 884; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 1161; SumSQ.u64 = 1161; Count.u64 = 1161; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 565; SumSQ.u64 = 565; Count.u64 = 565; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetS_I : Accumulator : Sum.u64 = 1842; SumSQ.u64 = 1842; Count.u64 = 1842; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetS_S : Accumulator : Sum.u64 = 861; SumSQ.u64 = 861; Count.u64 = 861; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetS_M : Accumulator : Sum.u64 = 156; SumSQ.u64 = 156; Count.u64 = 156; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetX_I : Accumulator : Sum.u64 = 1212; SumSQ.u64 = 1212; Count.u64 = 1212; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetX_S : Accumulator : Sum.u64 = 548; SumSQ.u64 = 548; Count.u64 = 548; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetX_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1973; SumSQ.u64 = 1973; Count.u64 = 1973; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1837; SumSQ.u64 = 1837; Count.u64 = 1837; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1250; SumSQ.u64 = 1250; Count.u64 = 1250; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1313; SumSQ.u64 = 1313; Count.u64 = 1313; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 447; SumSQ.u64 = 447; Count.u64 = 447; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutS_S : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutS_S : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_PutM_M : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutM_M : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 2505; SumSQ.u64 = 2505; Count.u64 = 2505; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_Inv_S : Accumulator : Sum.u64 = 2284; SumSQ.u64 = 2284; Count.u64 = 2284; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_Inv_SM : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1650; SumSQ.u64 = 1650; Count.u64 = 1650; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1581; SumSQ.u64 = 1581; Count.u64 = 1581; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1887,7 +1975,7 @@ l2cache4.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 906; SumSQ.u64 = 906; Count.u64 = 906; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 961; SumSQ.u64 = 961; Count.u64 = 961; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1908,11 +1996,11 @@ l2cache4.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 724; SumSQ.u64 = 724; Count.u64 = 724; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 692; SumSQ.u64 = 692; Count.u64 = 692; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1526; SumSQ.u64 = 1526; Count.u64 = 1526; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1400; SumSQ.u64 = 1400; Count.u64 = 1400; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1923,65 +2011,72 @@ l2cache4.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_GetS : Accumulator : Sum.u64 = 2447; SumSQ.u64 = 2447; Count.u64 = 2447; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetX : Accumulator : Sum.u64 = 2370; SumSQ.u64 = 2370; Count.u64 = 2370; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetS : Accumulator : Sum.u64 = 2262; SumSQ.u64 = 2262; Count.u64 = 2262; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetX : Accumulator : Sum.u64 = 2384; SumSQ.u64 = 2384; Count.u64 = 2384; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_PutS : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_PutS : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_PutM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 921; SumSQ.u64 = 921; Count.u64 = 921; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 2403; SumSQ.u64 = 2403; Count.u64 = 2403; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_NACK : Accumulator : Sum.u64 = 6519; SumSQ.u64 = 6519; Count.u64 = 6519; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 2319; SumSQ.u64 = 2319; Count.u64 = 2319; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FetchResp : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FetchXResp : Accumulator : Sum.u64 = 875; SumSQ.u64 = 875; Count.u64 = 875; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_AckInv : Accumulator : Sum.u64 = 2247; SumSQ.u64 = 2247; Count.u64 = 2247; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_NACK : Accumulator : Sum.u64 = 5990; SumSQ.u64 = 5990; Count.u64 = 5990; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetSResp : Accumulator : Sum.u64 = 2139; SumSQ.u64 = 2139; Count.u64 = 2139; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_GetXResp : Accumulator : Sum.u64 = 1847; SumSQ.u64 = 1847; Count.u64 = 1847; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FetchInv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.eventSent_FetchInvX : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; - l2cache4.eventSent_Inv : Accumulator : Sum.u64 = 1611; SumSQ.u64 = 1611; Count.u64 = 1611; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_FetchInvX : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; + l2cache4.eventSent_Inv : Accumulator : Sum.u64 = 1486; SumSQ.u64 = 1486; Count.u64 = 1486; Min.u64 = 1; Max.u64 = 1; l2cache4.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetS_hit : Accumulator : Sum.u64 = 5748; SumSQ.u64 = 64550; Count.u64 = 1032; Min.u64 = 1; Max.u64 = 65; - l2cache4.latency_GetS_miss : Accumulator : Sum.u64 = 184395; SumSQ.u64 = 33339517; Count.u64 = 1926; Min.u64 = 37; Max.u64 = 1852; + l2cache4.latency_GetS_hit : Accumulator : Sum.u64 = 5775; SumSQ.u64 = 83523; Count.u64 = 1017; Min.u64 = 1; Max.u64 = 107; + l2cache4.latency_GetS_miss : Accumulator : Sum.u64 = 167383; SumSQ.u64 = 27549071; Count.u64 = 1775; Min.u64 = 37; Max.u64 = 1293; l2cache4.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetX_hit : Accumulator : Sum.u64 = 339; SumSQ.u64 = 3855; Count.u64 = 30; Min.u64 = 10; Max.u64 = 13; - l2cache4.latency_GetX_miss : Accumulator : Sum.u64 = 162335; SumSQ.u64 = 53819299; Count.u64 = 1161; Min.u64 = 61; Max.u64 = 2737; + l2cache4.latency_GetX_hit : Accumulator : Sum.u64 = 279; SumSQ.u64 = 3127; Count.u64 = 25; Min.u64 = 10; Max.u64 = 13; + l2cache4.latency_GetX_miss : Accumulator : Sum.u64 = 180425; SumSQ.u64 = 87261727; Count.u64 = 1212; Min.u64 = 41; Max.u64 = 3304; l2cache4.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 70161; SumSQ.u64 = 13437253; Count.u64 = 565; Min.u64 = 57; Max.u64 = 896; + l2cache4.latency_GetX_upgrade : Accumulator : Sum.u64 = 72964; SumSQ.u64 = 20665964; Count.u64 = 548; Min.u64 = 60; Max.u64 = 2182; l2cache4.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache4.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.GetSHit_Arrival : Accumulator : Sum.u64 = 1008; SumSQ.u64 = 1008; Count.u64 = 1008; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSHit_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache4.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 1977; SumSQ.u64 = 1977; Count.u64 = 1977; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSMiss_Arrival : Accumulator : Sum.u64 = 1840; SumSQ.u64 = 1840; Count.u64 = 1840; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXMiss_Arrival : Accumulator : Sum.u64 = 1747; SumSQ.u64 = 1747; Count.u64 = 1747; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetSMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXMiss_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.CacheHits : Accumulator : Sum.u64 = 1062; SumSQ.u64 = 1062; Count.u64 = 1062; Min.u64 = 1; Max.u64 = 1; - l2cache4.CacheMisses : Accumulator : Sum.u64 = 3704; SumSQ.u64 = 3704; Count.u64 = 3704; Min.u64 = 1; Max.u64 = 1; - l2cache4.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.prefetch_inv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache4.CacheHits : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l2cache4.CacheMisses : Accumulator : Sum.u64 = 3602; SumSQ.u64 = 3602; Count.u64 = 3602; Min.u64 = 1; Max.u64 = 1; + l2cache4.prefetch_evict : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache4.prefetch_inv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; l2cache4.prefetch_useful : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - l2cache4.prefetch_coherence_miss : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; - l2cache4.prefetch_redundant : Accumulator : Sum.u64 = 586; SumSQ.u64 = 586; Count.u64 = 586; Min.u64 = 1; Max.u64 = 1; + l2cache4.prefetch_coherence_miss : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache4.prefetch_redundant : Accumulator : Sum.u64 = 591; SumSQ.u64 = 591; Count.u64 = 591; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1992,8 +2087,8 @@ l2cache4.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutE_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_PutE_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; - l2cache4.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.stateEvent_PutE_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache4.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache4.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2018,8 +2113,8 @@ l2cache4.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.TotalEventsReceived : Accumulator : Sum.u64 = 24089; SumSQ.u64 = 24089; Count.u64 = 24089; Min.u64 = 1; Max.u64 = 1; - l2cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 3029; SumSQ.u64 = 3029; Count.u64 = 3029; Min.u64 = 1; Max.u64 = 1; + l2cache4.TotalEventsReceived : Accumulator : Sum.u64 = 22999; SumSQ.u64 = 22999; Count.u64 = 22999; Min.u64 = 1; Max.u64 = 1; + l2cache4.TotalEventsReplayed : Accumulator : Sum.u64 = 2966; SumSQ.u64 = 2966; Count.u64 = 2966; Min.u64 = 1; Max.u64 = 1; l2cache4.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2032,61 +2127,66 @@ l2cache4.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetS_recv : Accumulator : Sum.u64 = 8746; SumSQ.u64 = 8746; Count.u64 = 8746; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetX_recv : Accumulator : Sum.u64 = 4762; SumSQ.u64 = 4762; Count.u64 = 4762; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetS_recv : Accumulator : Sum.u64 = 8408; SumSQ.u64 = 8408; Count.u64 = 8408; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetX_recv : Accumulator : Sum.u64 = 4494; SumSQ.u64 = 4494; Count.u64 = 4494; Min.u64 = 1; Max.u64 = 1; l2cache4.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 1973; SumSQ.u64 = 1973; Count.u64 = 1973; Min.u64 = 1; Max.u64 = 1; - l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 1731; SumSQ.u64 = 1731; Count.u64 = 1731; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.GetSResp_recv : Accumulator : Sum.u64 = 1837; SumSQ.u64 = 1837; Count.u64 = 1837; Min.u64 = 1; Max.u64 = 1; + l2cache4.GetXResp_recv : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; l2cache4.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.PutS_recv : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; - l2cache4.PutM_recv : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; - l2cache4.PutE_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache4.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.PutS_recv : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; + l2cache4.PutM_recv : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l2cache4.PutE_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache4.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.Inv_recv : Accumulator : Sum.u64 = 2601; SumSQ.u64 = 2601; Count.u64 = 2601; Min.u64 = 1; Max.u64 = 1; + l2cache4.Inv_recv : Accumulator : Sum.u64 = 2393; SumSQ.u64 = 2393; Count.u64 = 2393; Min.u64 = 1; Max.u64 = 1; l2cache4.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache4.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 908; SumSQ.u64 = 908; Count.u64 = 908; Min.u64 = 1; Max.u64 = 1; - l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 1019; SumSQ.u64 = 1019; Count.u64 = 1019; Min.u64 = 1; Max.u64 = 1; - l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; - l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; - l2cache4.NACK_recv : Accumulator : Sum.u64 = 1113; SumSQ.u64 = 1113; Count.u64 = 1113; Min.u64 = 1; Max.u64 = 1; - l2cache4.AckInv_recv : Accumulator : Sum.u64 = 1599; SumSQ.u64 = 1599; Count.u64 = 1599; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchInv_recv : Accumulator : Sum.u64 = 963; SumSQ.u64 = 963; Count.u64 = 963; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchInvX_recv : Accumulator : Sum.u64 = 946; SumSQ.u64 = 946; Count.u64 = 946; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchResp_recv : Accumulator : Sum.u64 = 726; SumSQ.u64 = 726; Count.u64 = 726; Min.u64 = 1; Max.u64 = 1; + l2cache4.FetchXResp_recv : Accumulator : Sum.u64 = 694; SumSQ.u64 = 694; Count.u64 = 694; Min.u64 = 1; Max.u64 = 1; + l2cache4.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache4.NACK_recv : Accumulator : Sum.u64 = 1044; SumSQ.u64 = 1044; Count.u64 = 1044; Min.u64 = 1; Max.u64 = 1; + l2cache4.AckInv_recv : Accumulator : Sum.u64 = 1480; SumSQ.u64 = 1480; Count.u64 = 1480; Min.u64 = 1; Max.u64 = 1; l2cache4.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache4.MSHR_occupancy : Accumulator : Sum.u64 = 426214; SumSQ.u64 = 2797534; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 8; + l2cache4.MSHR_occupancy : Accumulator : Sum.u64 = 430195; SumSQ.u64 = 2798949; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 8; l2cache4.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - core5.pendCycle : Accumulator : Sum.u64 = 881301; SumSQ.u64 = 13757295; Count.u64 = 56796; Min.u64 = 0; Max.u64 = 16; - core5.reads : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 2992; Count.u64 = 2992; Min.u64 = 1; Max.u64 = 1; - core5.writes : Accumulator : Sum.u64 = 2008; SumSQ.u64 = 2008; Count.u64 = 2008; Min.u64 = 1; Max.u64 = 1; - l1cache5.Prefetch_requests : Accumulator : Sum.u64 = 3573; SumSQ.u64 = 3573; Count.u64 = 3573; Min.u64 = 1; Max.u64 = 1; - l1cache5.Prefetch_drops : Accumulator : Sum.u64 = 2327; SumSQ.u64 = 2327; Count.u64 = 2327; Min.u64 = 1; Max.u64 = 1; + core5.pendCycle : Accumulator : Sum.u64 = 887267; SumSQ.u64 = 13848701; Count.u64 = 57148; Min.u64 = 0; Max.u64 = 16; + core5.reads : Accumulator : Sum.u64 = 3004; SumSQ.u64 = 3004; Count.u64 = 3004; Min.u64 = 1; Max.u64 = 1; + core5.writes : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; + l1cache5.Prefetch_requests : Accumulator : Sum.u64 = 3590; SumSQ.u64 = 3590; Count.u64 = 3590; Min.u64 = 1; Max.u64 = 1; + l1cache5.Prefetch_drops : Accumulator : Sum.u64 = 2348; SumSQ.u64 = 2348; Count.u64 = 2348; Min.u64 = 1; Max.u64 = 1; l1cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 2301; SumSQ.u64 = 2301; Count.u64 = 2301; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 1348; SumSQ.u64 = 1348; Count.u64 = 1348; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 577; SumSQ.u64 = 577; Count.u64 = 577; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 1297; SumSQ.u64 = 1297; Count.u64 = 1297; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 2284; SumSQ.u64 = 2284; Count.u64 = 2284; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 1334; SumSQ.u64 = 1334; Count.u64 = 1334; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 606; SumSQ.u64 = 606; Count.u64 = 606; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 1235; SumSQ.u64 = 1235; Count.u64 = 1235; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 463; SumSQ.u64 = 463; Count.u64 = 463; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2247; SumSQ.u64 = 2247; Count.u64 = 2247; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1405; SumSQ.u64 = 1405; Count.u64 = 1405; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_Inv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 1499; SumSQ.u64 = 1499; Count.u64 = 1499; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 2202; SumSQ.u64 = 2202; Count.u64 = 2202; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1327; SumSQ.u64 = 1327; Count.u64 = 1327; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 1364; SumSQ.u64 = 1364; Count.u64 = 1364; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 697; SumSQ.u64 = 697; Count.u64 = 697; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2097,10 +2197,10 @@ l1cache5.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 611; SumSQ.u64 = 611; Count.u64 = 611; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2122,21 +2222,24 @@ l1cache5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_GetS : Accumulator : Sum.u64 = 5276; SumSQ.u64 = 5276; Count.u64 = 5276; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetX : Accumulator : Sum.u64 = 4500; SumSQ.u64 = 4500; Count.u64 = 4500; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_GetS : Accumulator : Sum.u64 = 5190; SumSQ.u64 = 5190; Count.u64 = 5190; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_GetX : Accumulator : Sum.u64 = 4441; SumSQ.u64 = 4441; Count.u64 = 4441; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_PutM : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_PutM : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 627; SumSQ.u64 = 627; Count.u64 = 627; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 740; SumSQ.u64 = 740; Count.u64 = 740; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 1607; SumSQ.u64 = 1607; Count.u64 = 1607; Min.u64 = 1; Max.u64 = 1; - l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 2992; Count.u64 = 2992; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckInv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 3004; SumSQ.u64 = 3004; Count.u64 = 3004; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 2008; SumSQ.u64 = 2008; Count.u64 = 2008; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2144,18 +2247,18 @@ l1cache5.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.evict_I : Accumulator : Sum.u64 = 1745; SumSQ.u64 = 1745; Count.u64 = 1745; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_S : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_M : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_IS : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_IM : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; - l1cache5.evict_SM : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_I : Accumulator : Sum.u64 = 1690; SumSQ.u64 = 1690; Count.u64 = 1690; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_S : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_M : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_IS : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_IM : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache5.evict_SM : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.latency_GetS_hit : Accumulator : Sum.u64 = 224967; SumSQ.u64 = 344406973; Count.u64 = 1937; Min.u64 = 1; Max.u64 = 4271; - l1cache5.latency_GetS_miss : Accumulator : Sum.u64 = 401226; SumSQ.u64 = 384669926; Count.u64 = 2301; Min.u64 = 13; Max.u64 = 5284; - l1cache5.latency_GetX_hit : Accumulator : Sum.u64 = 87794; SumSQ.u64 = 168618486; Count.u64 = 291; Min.u64 = 2; Max.u64 = 4596; - l1cache5.latency_GetX_miss : Accumulator : Sum.u64 = 327420; SumSQ.u64 = 369007448; Count.u64 = 1297; Min.u64 = 16; Max.u64 = 5374; - l1cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 131853; SumSQ.u64 = 186213665; Count.u64 = 420; Min.u64 = 71; Max.u64 = 6482; + l1cache5.latency_GetS_hit : Accumulator : Sum.u64 = 213759; SumSQ.u64 = 292431541; Count.u64 = 1962; Min.u64 = 1; Max.u64 = 4283; + l1cache5.latency_GetS_miss : Accumulator : Sum.u64 = 414838; SumSQ.u64 = 393945304; Count.u64 = 2284; Min.u64 = 13; Max.u64 = 4257; + l1cache5.latency_GetX_hit : Accumulator : Sum.u64 = 83609; SumSQ.u64 = 131902809; Count.u64 = 298; Min.u64 = 2; Max.u64 = 4739; + l1cache5.latency_GetX_miss : Accumulator : Sum.u64 = 317742; SumSQ.u64 = 327068866; Count.u64 = 1235; Min.u64 = 16; Max.u64 = 5350; + l1cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 154404; SumSQ.u64 = 199737032; Count.u64 = 463; Min.u64 = 64; Max.u64 = 4315; l1cache5.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2163,39 +2266,40 @@ l1cache5.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 1394; SumSQ.u64 = 1394; Count.u64 = 1394; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l1cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 1449; SumSQ.u64 = 1449; Count.u64 = 1449; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 543; SumSQ.u64 = 543; Count.u64 = 543; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXHit_Blocked : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 513; SumSQ.u64 = 513; Count.u64 = 513; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXHit_Blocked : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 1997; SumSQ.u64 = 1997; Count.u64 = 1997; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 1408; SumSQ.u64 = 1408; Count.u64 = 1408; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 1972; SumSQ.u64 = 1972; Count.u64 = 1972; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 1385; SumSQ.u64 = 1385; Count.u64 = 1385; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; l1cache5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.CacheHits : Accumulator : Sum.u64 = 2228; SumSQ.u64 = 2228; Count.u64 = 2228; Min.u64 = 1; Max.u64 = 1; - l1cache5.CacheMisses : Accumulator : Sum.u64 = 4018; SumSQ.u64 = 4018; Count.u64 = 4018; Min.u64 = 1; Max.u64 = 1; + l1cache5.CacheHits : Accumulator : Sum.u64 = 2260; SumSQ.u64 = 2260; Count.u64 = 2260; Min.u64 = 1; Max.u64 = 1; + l1cache5.CacheMisses : Accumulator : Sum.u64 = 3982; SumSQ.u64 = 3982; Count.u64 = 3982; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.eventSent_PutS : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; + l1cache5.eventSent_PutS : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; l1cache5.eventSent_PutE : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache5.prefetch_evict : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; - l1cache5.prefetch_inv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; - l1cache5.prefetch_useful : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; - l1cache5.prefetch_coherence_miss : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; - l1cache5.prefetch_redundant : Accumulator : Sum.u64 = 801; SumSQ.u64 = 801; Count.u64 = 801; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetS_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l1cache5.stateEvent_GetX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache5.prefetch_evict : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; + l1cache5.prefetch_inv : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l1cache5.prefetch_useful : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache5.prefetch_coherence_miss : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache5.prefetch_redundant : Accumulator : Sum.u64 = 850; SumSQ.u64 = 850; Count.u64 = 850; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetS_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_GetX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l1cache5.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l1cache5.evict_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; - l1cache5.TotalEventsReceived : Accumulator : Sum.u64 = 17779; SumSQ.u64 = 17779; Count.u64 = 17779; Min.u64 = 1; Max.u64 = 1; - l1cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 1829; SumSQ.u64 = 1829; Count.u64 = 1829; Min.u64 = 1; Max.u64 = 1; + l1cache5.TotalEventsReceived : Accumulator : Sum.u64 = 17434; SumSQ.u64 = 17434; Count.u64 = 17434; Min.u64 = 1; Max.u64 = 1; + l1cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 1828; SumSQ.u64 = 1828; Count.u64 = 1828; Min.u64 = 1; Max.u64 = 1; l1cache5.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2208,80 +2312,84 @@ l1cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetS_recv : Accumulator : Sum.u64 = 6565; SumSQ.u64 = 6565; Count.u64 = 6565; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetS_recv : Accumulator : Sum.u64 = 6594; SumSQ.u64 = 6594; Count.u64 = 6594; Min.u64 = 1; Max.u64 = 1; l1cache5.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.Write_recv : Accumulator : Sum.u64 = 2008; SumSQ.u64 = 2008; Count.u64 = 2008; Min.u64 = 1; Max.u64 = 1; + l1cache5.Write_recv : Accumulator : Sum.u64 = 1996; SumSQ.u64 = 1996; Count.u64 = 1996; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 2247; SumSQ.u64 = 2247; Count.u64 = 2247; Min.u64 = 1; Max.u64 = 1; - l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.GetSResp_recv : Accumulator : Sum.u64 = 2202; SumSQ.u64 = 2202; Count.u64 = 2202; Min.u64 = 1; Max.u64 = 1; + l1cache5.GetXResp_recv : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; l1cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.Inv_recv : Accumulator : Sum.u64 = 1612; SumSQ.u64 = 1612; Count.u64 = 1612; Min.u64 = 1; Max.u64 = 1; + l1cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.Inv_recv : Accumulator : Sum.u64 = 1468; SumSQ.u64 = 1468; Count.u64 = 1468; Min.u64 = 1; Max.u64 = 1; l1cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; - l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; - l1cache5.NACK_recv : Accumulator : Sum.u64 = 5758; SumSQ.u64 = 5758; Count.u64 = 5758; Min.u64 = 1; Max.u64 = 1; + l1cache5.FetchInv_recv : Accumulator : Sum.u64 = 587; SumSQ.u64 = 587; Count.u64 = 587; Min.u64 = 1; Max.u64 = 1; + l1cache5.FetchInvX_recv : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; + l1cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.NACK_recv : Accumulator : Sum.u64 = 5649; SumSQ.u64 = 5649; Count.u64 = 5649; Min.u64 = 1; Max.u64 = 1; l1cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 1151354; SumSQ.u64 = 19628242; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 18; + l1cache5.MSHR_occupancy : Accumulator : Sum.u64 = 1162567; SumSQ.u64 = 19868937; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 18; l1cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.packet_latency : Accumulator : Sum.u64 = 13887; SumSQ.u64 = 31159; Count.u64 = 9042; Min.u64 = 0; Max.u64 = 8; - l2cache5:memlink.send_bit_count : Accumulator : Sum.u64 = 1586448; SumSQ.u64 = 637342976; Count.u64 = 9053; Min.u64 = 80; Max.u64 = 592; - l2cache5:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5:memlink.idle_time : Accumulator : Sum.u64 = 12837187; SumSQ.u64 = 69522003985; Count.u64 = 6587; Min.u64 = 1; Max.u64 = 77866; - l2cache5.Prefetch_requests : Accumulator : Sum.u64 = 3165; SumSQ.u64 = 3165; Count.u64 = 3165; Min.u64 = 1; Max.u64 = 1; - l2cache5.Prefetch_drops : Accumulator : Sum.u64 = 2590; SumSQ.u64 = 2590; Count.u64 = 2590; Min.u64 = 1; Max.u64 = 1; + l2cache5:lowlink.packet_latency : Accumulator : Sum.u64 = 13251; SumSQ.u64 = 29223; Count.u64 = 8791; Min.u64 = 0; Max.u64 = 9; + l2cache5:lowlink.send_bit_count : Accumulator : Sum.u64 = 1561488; SumSQ.u64 = 632315136; Count.u64 = 8805; Min.u64 = 80; Max.u64 = 592; + l2cache5:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5:lowlink.idle_time : Accumulator : Sum.u64 = 13810571; SumSQ.u64 = 685772338049; Count.u64 = 6514; Min.u64 = 1; Max.u64 = 704737; + l2cache5.Prefetch_requests : Accumulator : Sum.u64 = 3141; SumSQ.u64 = 3141; Count.u64 = 3141; Min.u64 = 1; Max.u64 = 1; + l2cache5.Prefetch_drops : Accumulator : Sum.u64 = 2497; SumSQ.u64 = 2497; Count.u64 = 2497; Min.u64 = 1; Max.u64 = 1; l2cache5.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.evict_I : Accumulator : Sum.u64 = 180; SumSQ.u64 = 180; Count.u64 = 180; Min.u64 = 1; Max.u64 = 1; + l2cache5.evict_I : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.evict_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache5.evict_S : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache5.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.evict_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache5.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 1916; SumSQ.u64 = 1916; Count.u64 = 1916; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 1188; SumSQ.u64 = 1188; Count.u64 = 1188; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 492; SumSQ.u64 = 492; Count.u64 = 492; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetS_I : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetS_S : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetS_M : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_I : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_S : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetX_M : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1266; SumSQ.u64 = 1266; Count.u64 = 1266; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1798; SumSQ.u64 = 1798; Count.u64 = 1798; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutS_S : Accumulator : Sum.u64 = 1061; SumSQ.u64 = 1061; Count.u64 = 1061; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutS_S : Accumulator : Sum.u64 = 1095; SumSQ.u64 = 1095; Count.u64 = 1095; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_PutM_M : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutM_M : Accumulator : Sum.u64 = 434; SumSQ.u64 = 434; Count.u64 = 434; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 2459; SumSQ.u64 = 2459; Count.u64 = 2459; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_Inv_S : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 2291; Count.u64 = 2291; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_Inv_SM : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1645; SumSQ.u64 = 1645; Count.u64 = 1645; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1679; SumSQ.u64 = 1679; Count.u64 = 1679; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2299,7 +2407,7 @@ l2cache5.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 861; SumSQ.u64 = 861; Count.u64 = 861; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2320,11 +2428,11 @@ l2cache5.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 627; SumSQ.u64 = 627; Count.u64 = 627; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 736; SumSQ.u64 = 736; Count.u64 = 736; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 578; SumSQ.u64 = 578; Count.u64 = 578; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1541; SumSQ.u64 = 1541; Count.u64 = 1541; Min.u64 = 1; Max.u64 = 1; - l2cache5.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1401; SumSQ.u64 = 1401; Count.u64 = 1401; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2335,65 +2443,72 @@ l2cache5.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_GetS : Accumulator : Sum.u64 = 2359; SumSQ.u64 = 2359; Count.u64 = 2359; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetX : Accumulator : Sum.u64 = 2265; SumSQ.u64 = 2265; Count.u64 = 2265; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetS : Accumulator : Sum.u64 = 2210; SumSQ.u64 = 2210; Count.u64 = 2210; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetX : Accumulator : Sum.u64 = 2345; SumSQ.u64 = 2345; Count.u64 = 2345; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_PutS : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_PutM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_PutS : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 780; SumSQ.u64 = 780; Count.u64 = 780; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 903; SumSQ.u64 = 903; Count.u64 = 903; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 2387; SumSQ.u64 = 2387; Count.u64 = 2387; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_NACK : Accumulator : Sum.u64 = 6106; SumSQ.u64 = 6106; Count.u64 = 6106; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 2247; SumSQ.u64 = 2247; Count.u64 = 2247; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FetchResp : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FetchXResp : Accumulator : Sum.u64 = 941; SumSQ.u64 = 941; Count.u64 = 941; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_AckInv : Accumulator : Sum.u64 = 2182; SumSQ.u64 = 2182; Count.u64 = 2182; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_NACK : Accumulator : Sum.u64 = 6029; SumSQ.u64 = 6029; Count.u64 = 6029; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetSResp : Accumulator : Sum.u64 = 2202; SumSQ.u64 = 2202; Count.u64 = 2202; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_GetXResp : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FetchInv : Accumulator : Sum.u64 = 587; SumSQ.u64 = 587; Count.u64 = 587; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.eventSent_FetchInvX : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; - l2cache5.eventSent_Inv : Accumulator : Sum.u64 = 1612; SumSQ.u64 = 1612; Count.u64 = 1612; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_FetchInvX : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; + l2cache5.eventSent_Inv : Accumulator : Sum.u64 = 1468; SumSQ.u64 = 1468; Count.u64 = 1468; Min.u64 = 1; Max.u64 = 1; l2cache5.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetS_hit : Accumulator : Sum.u64 = 6339; SumSQ.u64 = 195869; Count.u64 = 960; Min.u64 = 1; Max.u64 = 325; - l2cache5.latency_GetS_miss : Accumulator : Sum.u64 = 175965; SumSQ.u64 = 32716705; Count.u64 = 1849; Min.u64 = 37; Max.u64 = 1989; + l2cache5.latency_GetS_hit : Accumulator : Sum.u64 = 6637; SumSQ.u64 = 93361; Count.u64 = 1124; Min.u64 = 1; Max.u64 = 138; + l2cache5.latency_GetS_miss : Accumulator : Sum.u64 = 175457; SumSQ.u64 = 36010255; Count.u64 = 1771; Min.u64 = 37; Max.u64 = 1764; l2cache5.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetX_hit : Accumulator : Sum.u64 = 417; SumSQ.u64 = 4731; Count.u64 = 37; Min.u64 = 10; Max.u64 = 13; - l2cache5.latency_GetX_miss : Accumulator : Sum.u64 = 166637; SumSQ.u64 = 58994501; Count.u64 = 1188; Min.u64 = 45; Max.u64 = 3242; + l2cache5.latency_GetX_hit : Accumulator : Sum.u64 = 343; SumSQ.u64 = 3995; Count.u64 = 30; Min.u64 = 10; Max.u64 = 17; + l2cache5.latency_GetX_miss : Accumulator : Sum.u64 = 154034; SumSQ.u64 = 61394972; Count.u64 = 1049; Min.u64 = 63; Max.u64 = 3246; l2cache5.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 58887; SumSQ.u64 = 11476461; Count.u64 = 492; Min.u64 = 58; Max.u64 = 1367; + l2cache5.latency_GetX_upgrade : Accumulator : Sum.u64 = 90217; SumSQ.u64 = 48379993; Count.u64 = 619; Min.u64 = 57; Max.u64 = 2718; l2cache5.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 953; SumSQ.u64 = 953; Count.u64 = 953; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache5.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.GetSHit_Arrival : Accumulator : Sum.u64 = 1120; SumSQ.u64 = 1120; Count.u64 = 1120; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSHit_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l2cache5.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 1915; SumSQ.u64 = 1915; Count.u64 = 1915; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 1667; SumSQ.u64 = 1667; Count.u64 = 1667; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSMiss_Arrival : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXMiss_Arrival : Accumulator : Sum.u64 = 1660; SumSQ.u64 = 1660; Count.u64 = 1660; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.GetXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.CacheHits : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; - l2cache5.CacheMisses : Accumulator : Sum.u64 = 3596; SumSQ.u64 = 3596; Count.u64 = 3596; Min.u64 = 1; Max.u64 = 1; - l2cache5.prefetch_evict : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; - l2cache5.prefetch_inv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; - l2cache5.prefetch_useful : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; - l2cache5.prefetch_coherence_miss : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; - l2cache5.prefetch_redundant : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; + l2cache5.CacheHits : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; + l2cache5.CacheMisses : Accumulator : Sum.u64 = 3472; SumSQ.u64 = 3472; Count.u64 = 3472; Min.u64 = 1; Max.u64 = 1; + l2cache5.prefetch_evict : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.prefetch_inv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache5.prefetch_useful : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache5.prefetch_coherence_miss : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache5.prefetch_redundant : Accumulator : Sum.u64 = 611; SumSQ.u64 = 611; Count.u64 = 611; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2415,23 +2530,23 @@ l2cache5.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache5.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l2cache5.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.TotalEventsReceived : Accumulator : Sum.u64 = 23262; SumSQ.u64 = 23262; Count.u64 = 23262; Min.u64 = 1; Max.u64 = 1; - l2cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 3024; SumSQ.u64 = 3024; Count.u64 = 3024; Min.u64 = 1; Max.u64 = 1; + l2cache5.TotalEventsReceived : Accumulator : Sum.u64 = 22765; SumSQ.u64 = 22765; Count.u64 = 22765; Min.u64 = 1; Max.u64 = 1; + l2cache5.TotalEventsReplayed : Accumulator : Sum.u64 = 2815; SumSQ.u64 = 2815; Count.u64 = 2815; Min.u64 = 1; Max.u64 = 1; l2cache5.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2444,38 +2559,43 @@ l2cache5.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetS_recv : Accumulator : Sum.u64 = 8441; SumSQ.u64 = 8441; Count.u64 = 8441; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetX_recv : Accumulator : Sum.u64 = 4500; SumSQ.u64 = 4500; Count.u64 = 4500; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetS_recv : Accumulator : Sum.u64 = 8331; SumSQ.u64 = 8331; Count.u64 = 8331; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetX_recv : Accumulator : Sum.u64 = 4441; SumSQ.u64 = 4441; Count.u64 = 4441; Min.u64 = 1; Max.u64 = 1; l2cache5.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; - l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.GetSResp_recv : Accumulator : Sum.u64 = 1798; SumSQ.u64 = 1798; Count.u64 = 1798; Min.u64 = 1; Max.u64 = 1; + l2cache5.GetXResp_recv : Accumulator : Sum.u64 = 1674; SumSQ.u64 = 1674; Count.u64 = 1674; Min.u64 = 1; Max.u64 = 1; l2cache5.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.PutS_recv : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; - l2cache5.PutM_recv : Accumulator : Sum.u64 = 393; SumSQ.u64 = 393; Count.u64 = 393; Min.u64 = 1; Max.u64 = 1; + l2cache5.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.PutS_recv : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; + l2cache5.PutM_recv : Accumulator : Sum.u64 = 456; SumSQ.u64 = 456; Count.u64 = 456; Min.u64 = 1; Max.u64 = 1; l2cache5.PutE_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l2cache5.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.Inv_recv : Accumulator : Sum.u64 = 2551; SumSQ.u64 = 2551; Count.u64 = 2551; Min.u64 = 1; Max.u64 = 1; + l2cache5.Inv_recv : Accumulator : Sum.u64 = 2382; SumSQ.u64 = 2382; Count.u64 = 2382; Min.u64 = 1; Max.u64 = 1; l2cache5.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache5.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 861; SumSQ.u64 = 861; Count.u64 = 861; Min.u64 = 1; Max.u64 = 1; - l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 1006; SumSQ.u64 = 1006; Count.u64 = 1006; Min.u64 = 1; Max.u64 = 1; - l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 627; SumSQ.u64 = 627; Count.u64 = 627; Min.u64 = 1; Max.u64 = 1; - l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 740; SumSQ.u64 = 740; Count.u64 = 740; Min.u64 = 1; Max.u64 = 1; - l2cache5.NACK_recv : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; - l2cache5.AckInv_recv : Accumulator : Sum.u64 = 1607; SumSQ.u64 = 1607; Count.u64 = 1607; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchInv_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchInvX_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchResp_recv : Accumulator : Sum.u64 = 579; SumSQ.u64 = 579; Count.u64 = 579; Min.u64 = 1; Max.u64 = 1; + l2cache5.FetchXResp_recv : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l2cache5.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache5.NACK_recv : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l2cache5.AckInv_recv : Accumulator : Sum.u64 = 1456; SumSQ.u64 = 1456; Count.u64 = 1456; Min.u64 = 1; Max.u64 = 1; l2cache5.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 417468; SumSQ.u64 = 2700986; Count.u64 = 69169; Min.u64 = 0; Max.u64 = 8; + l2cache5.MSHR_occupancy : Accumulator : Sum.u64 = 434338; SumSQ.u64 = 2861702; Count.u64 = 71631; Min.u64 = 0; Max.u64 = 8; l2cache5.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.packet_latency : Accumulator : Sum.u64 = 36631; SumSQ.u64 = 119019; Count.u64 = 19213; Min.u64 = 0; Max.u64 = 15; - l3cache0:cpulink.send_bit_count : Accumulator : Sum.u64 = 4423744; SumSQ.u64 = 2214086656; Count.u64 = 19186; Min.u64 = 32; Max.u64 = 544; - l3cache0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0:cpulink.idle_time : Accumulator : Sum.u64 = 6581164; SumSQ.u64 = 23877711592; Count.u64 = 6302; Min.u64 = 4; Max.u64 = 109626; + l3cache0:highlink.packet_latency : Accumulator : Sum.u64 = 36348; SumSQ.u64 = 118820; Count.u64 = 18984; Min.u64 = 0; Max.u64 = 14; + l3cache0:highlink.send_bit_count : Accumulator : Sum.u64 = 4381152; SumSQ.u64 = 2193505280; Count.u64 = 18959; Min.u64 = 32; Max.u64 = 544; + l3cache0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0:highlink.idle_time : Accumulator : Sum.u64 = 7099030; SumSQ.u64 = 53509883780; Count.u64 = 6281; Min.u64 = 4; Max.u64 = 191326; l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.evict_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_I : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2490,10 +2610,10 @@ l3cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 3876; SumSQ.u64 = 3876; Count.u64 = 3876; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 3777; SumSQ.u64 = 3777; Count.u64 = 3777; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 4672; SumSQ.u64 = 4672; Count.u64 = 4672; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 4720; SumSQ.u64 = 4720; Count.u64 = 4720; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2503,13 +2623,13 @@ l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2562,9 +2682,9 @@ l3cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1547; SumSQ.u64 = 1547; Count.u64 = 1547; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1941; SumSQ.u64 = 1941; Count.u64 = 1941; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 4804; SumSQ.u64 = 4804; Count.u64 = 4804; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1720; SumSQ.u64 = 1720; Count.u64 = 1720; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1795; SumSQ.u64 = 1795; Count.u64 = 1795; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 4646; SumSQ.u64 = 4646; Count.u64 = 4646; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2583,33 +2703,39 @@ l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 2687; SumSQ.u64 = 2687; Count.u64 = 2687; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3914; SumSQ.u64 = 3914; Count.u64 = 3914; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 3527; SumSQ.u64 = 3527; Count.u64 = 3527; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 2668; SumSQ.u64 = 2668; Count.u64 = 2668; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 3818; SumSQ.u64 = 3818; Count.u64 = 3818; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 3554; SumSQ.u64 = 3554; Count.u64 = 3554; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 1711; SumSQ.u64 = 1711; Count.u64 = 1711; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 1905; SumSQ.u64 = 1905; Count.u64 = 1905; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 2129; SumSQ.u64 = 2129; Count.u64 = 2129; Min.u64 = 1; Max.u64 = 1; - l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 5196; SumSQ.u64 = 5196; Count.u64 = 5196; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 1951; SumSQ.u64 = 1951; Count.u64 = 1951; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 5041; SumSQ.u64 = 5041; Count.u64 = 5041; Min.u64 = 1; Max.u64 = 1; l3cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 42090; SumSQ.u64 = 1330506; Count.u64 = 1961; Min.u64 = 15; Max.u64 = 243; + l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 44721; SumSQ.u64 = 1688179; Count.u64 = 2009; Min.u64 = 15; Max.u64 = 381; l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 682; SumSQ.u64 = 33488; Count.u64 = 14; Min.u64 = 45; Max.u64 = 63; - l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 96940; SumSQ.u64 = 6118776; Count.u64 = 1955; Min.u64 = 28; Max.u64 = 487; - l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 15; SumSQ.u64 = 225; Count.u64 = 1; Min.u64 = 15; Max.u64 = 15; + l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 91927; SumSQ.u64 = 6486841; Count.u64 = 1809; Min.u64 = 28; Max.u64 = 535; + l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 30; SumSQ.u64 = 450; Count.u64 = 2; Min.u64 = 15; Max.u64 = 15; l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 470; SumSQ.u64 = 30258; Count.u64 = 8; Min.u64 = 46; Max.u64 = 92; - l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 177949; SumSQ.u64 = 12778917; Count.u64 = 3502; Min.u64 = 24; Max.u64 = 476; + l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 190360; SumSQ.u64 = 19182798; Count.u64 = 3530; Min.u64 = 25; Max.u64 = 766; l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2617,11 +2743,12 @@ l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 3240; SumSQ.u64 = 3240; Count.u64 = 3240; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 4069; SumSQ.u64 = 4069; Count.u64 = 4069; Min.u64 = 1; Max.u64 = 1; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 3137; SumSQ.u64 = 3137; Count.u64 = 3137; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 4021; SumSQ.u64 = 4021; Count.u64 = 4021; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; @@ -2629,13 +2756,13 @@ l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.CacheHits : Accumulator : Sum.u64 = 8624; SumSQ.u64 = 8624; Count.u64 = 8624; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheHits : Accumulator : Sum.u64 = 8574; SumSQ.u64 = 8574; Count.u64 = 8574; Min.u64 = 1; Max.u64 = 1; l3cache0.CacheMisses : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -2663,12 +2790,12 @@ l3cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 19213; SumSQ.u64 = 19213; Count.u64 = 19213; Min.u64 = 1; Max.u64 = 1; - l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 6772; SumSQ.u64 = 6772; Count.u64 = 6772; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 18984; SumSQ.u64 = 18984; Count.u64 = 18984; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 6755; SumSQ.u64 = 6755; Count.u64 = 6755; Min.u64 = 1; Max.u64 = 1; l3cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2681,18 +2808,20 @@ l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.GetS_recv : Accumulator : Sum.u64 = 4969; SumSQ.u64 = 4969; Count.u64 = 4969; Min.u64 = 1; Max.u64 = 1; - l3cache0.GetX_recv : Accumulator : Sum.u64 = 5159; SumSQ.u64 = 5159; Count.u64 = 5159; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetS_recv : Accumulator : Sum.u64 = 4858; SumSQ.u64 = 4858; Count.u64 = 4858; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetX_recv : Accumulator : Sum.u64 = 5182; SumSQ.u64 = 5182; Count.u64 = 5182; Min.u64 = 1; Max.u64 = 1; l3cache0.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.PutS_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; - l3cache0.PutM_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.PutS_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutM_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; l3cache0.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2700,17 +2829,20 @@ l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 1556; SumSQ.u64 = 1556; Count.u64 = 1556; Min.u64 = 1; Max.u64 = 1; - l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 1954; SumSQ.u64 = 1954; Count.u64 = 1954; Min.u64 = 1; Max.u64 = 1; - l3cache0.NACK_recv : Accumulator : Sum.u64 = 684; SumSQ.u64 = 684; Count.u64 = 684; Min.u64 = 1; Max.u64 = 1; - l3cache0.AckInv_recv : Accumulator : Sum.u64 = 4840; SumSQ.u64 = 4840; Count.u64 = 4840; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 1729; Count.u64 = 1729; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 1808; SumSQ.u64 = 1808; Count.u64 = 1808; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NACK_recv : Accumulator : Sum.u64 = 675; SumSQ.u64 = 675; Count.u64 = 675; Min.u64 = 1; Max.u64 = 1; + l3cache0.AckInv_recv : Accumulator : Sum.u64 = 4683; SumSQ.u64 = 4683; Count.u64 = 4683; Min.u64 = 1; Max.u64 = 1; l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 211585; SumSQ.u64 = 1225957; Count.u64 = 40397; Min.u64 = 0; Max.u64 = 7; + l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 221553; SumSQ.u64 = 1298411; Count.u64 = 41835; Min.u64 = 0; Max.u64 = 7; l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.packet_latency : Accumulator : Sum.u64 = 32962; SumSQ.u64 = 107004; Count.u64 = 17333; Min.u64 = 0; Max.u64 = 15; - l3cache1:cpulink.send_bit_count : Accumulator : Sum.u64 = 4157984; SumSQ.u64 = 2093892608; Count.u64 = 17297; Min.u64 = 32; Max.u64 = 544; - l3cache1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1:cpulink.idle_time : Accumulator : Sum.u64 = 7218334; SumSQ.u64 = 18158397684; Count.u64 = 6303; Min.u64 = 4; Max.u64 = 39862; + l3cache1:highlink.packet_latency : Accumulator : Sum.u64 = 32593; SumSQ.u64 = 102937; Count.u64 = 17446; Min.u64 = 0; Max.u64 = 14; + l3cache1:highlink.send_bit_count : Accumulator : Sum.u64 = 4162016; SumSQ.u64 = 2094300160; Count.u64 = 17407; Min.u64 = 32; Max.u64 = 544; + l3cache1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1:highlink.idle_time : Accumulator : Sum.u64 = 7770204; SumSQ.u64 = 109991031048; Count.u64 = 6383; Min.u64 = 4; Max.u64 = 292678; l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_I : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2727,10 +2859,10 @@ l3cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 3689; SumSQ.u64 = 3689; Count.u64 = 3689; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 3632; SumSQ.u64 = 3632; Count.u64 = 3632; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 3998; SumSQ.u64 = 3998; Count.u64 = 3998; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 4178; SumSQ.u64 = 4178; Count.u64 = 4178; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2741,14 +2873,14 @@ l3cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2799,9 +2931,9 @@ l3cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1459; SumSQ.u64 = 1459; Count.u64 = 1459; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1821; SumSQ.u64 = 1821; Count.u64 = 1821; Min.u64 = 1; Max.u64 = 1; - l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 4578; SumSQ.u64 = 4578; Count.u64 = 4578; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1592; SumSQ.u64 = 1592; Count.u64 = 1592; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1742; SumSQ.u64 = 1742; Count.u64 = 1742; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 4469; SumSQ.u64 = 4469; Count.u64 = 4469; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2820,33 +2952,39 @@ l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 1647; SumSQ.u64 = 1647; Count.u64 = 1647; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3732; SumSQ.u64 = 3732; Count.u64 = 3732; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 3308; SumSQ.u64 = 3308; Count.u64 = 3308; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 1908; SumSQ.u64 = 1908; Count.u64 = 1908; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 3681; SumSQ.u64 = 3681; Count.u64 = 3681; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 3360; SumSQ.u64 = 3360; Count.u64 = 3360; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 1625; SumSQ.u64 = 1625; Count.u64 = 1625; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 1732; SumSQ.u64 = 1732; Count.u64 = 1732; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 2012; SumSQ.u64 = 2012; Count.u64 = 2012; Min.u64 = 1; Max.u64 = 1; - l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 4951; SumSQ.u64 = 4951; Count.u64 = 4951; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 1907; SumSQ.u64 = 1907; Count.u64 = 1907; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 4797; SumSQ.u64 = 4797; Count.u64 = 4797; Min.u64 = 1; Max.u64 = 1; l3cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 40890; SumSQ.u64 = 1497438; Count.u64 = 1900; Min.u64 = 15; Max.u64 = 268; + l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 41682; SumSQ.u64 = 1686376; Count.u64 = 1928; Min.u64 = 15; Max.u64 = 515; l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 450; SumSQ.u64 = 23060; Count.u64 = 9; Min.u64 = 45; Max.u64 = 72; - l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 91052; SumSQ.u64 = 5951326; Count.u64 = 1832; Min.u64 = 21; Max.u64 = 350; - l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 30; SumSQ.u64 = 450; Count.u64 = 2; Min.u64 = 15; Max.u64 = 15; + l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 90567; SumSQ.u64 = 7594297; Count.u64 = 1752; Min.u64 = 29; Max.u64 = 1015; + l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 15; SumSQ.u64 = 225; Count.u64 = 1; Min.u64 = 15; Max.u64 = 15; l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 652; SumSQ.u64 = 33334; Count.u64 = 13; Min.u64 = 46; Max.u64 = 70; - l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 162997; SumSQ.u64 = 10342761; Count.u64 = 3284; Min.u64 = 25; Max.u64 = 376; + l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 177233; SumSQ.u64 = 17641605; Count.u64 = 3338; Min.u64 = 26; Max.u64 = 1237; l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2854,11 +2992,12 @@ l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 3125; SumSQ.u64 = 3125; Count.u64 = 3125; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3391; SumSQ.u64 = 3391; Count.u64 = 3391; Min.u64 = 1; Max.u64 = 1; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 3052; SumSQ.u64 = 3052; Count.u64 = 3052; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3489; SumSQ.u64 = 3489; Count.u64 = 3489; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 618; SumSQ.u64 = 618; Count.u64 = 618; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 628; SumSQ.u64 = 628; Count.u64 = 628; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; @@ -2866,16 +3005,16 @@ l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.CacheHits : Accumulator : Sum.u64 = 7741; SumSQ.u64 = 7741; Count.u64 = 7741; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheHits : Accumulator : Sum.u64 = 7869; SumSQ.u64 = 7869; Count.u64 = 7869; Min.u64 = 1; Max.u64 = 1; l3cache1.CacheMisses : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2904,8 +3043,8 @@ l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 17333; SumSQ.u64 = 17333; Count.u64 = 17333; Min.u64 = 1; Max.u64 = 1; - l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 6341; SumSQ.u64 = 6341; Count.u64 = 6341; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 17446; SumSQ.u64 = 17446; Count.u64 = 17446; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 6418; SumSQ.u64 = 6418; Count.u64 = 6418; Min.u64 = 1; Max.u64 = 1; l3cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2918,18 +3057,20 @@ l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.GetS_recv : Accumulator : Sum.u64 = 4396; SumSQ.u64 = 4396; Count.u64 = 4396; Min.u64 = 1; Max.u64 = 1; - l3cache1.GetX_recv : Accumulator : Sum.u64 = 4291; SumSQ.u64 = 4291; Count.u64 = 4291; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetS_recv : Accumulator : Sum.u64 = 4397; SumSQ.u64 = 4397; Count.u64 = 4397; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetX_recv : Accumulator : Sum.u64 = 4552; SumSQ.u64 = 4552; Count.u64 = 4552; Min.u64 = 1; Max.u64 = 1; l3cache1.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.PutS_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; - l3cache1.PutM_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.PutS_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutM_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache1.PutE_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2937,17 +3078,20 @@ l3cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 1464; SumSQ.u64 = 1464; Count.u64 = 1464; Min.u64 = 1; Max.u64 = 1; - l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; - l3cache1.NACK_recv : Accumulator : Sum.u64 = 697; SumSQ.u64 = 697; Count.u64 = 697; Min.u64 = 1; Max.u64 = 1; - l3cache1.AckInv_recv : Accumulator : Sum.u64 = 4594; SumSQ.u64 = 4594; Count.u64 = 4594; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 1597; SumSQ.u64 = 1597; Count.u64 = 1597; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 1752; SumSQ.u64 = 1752; Count.u64 = 1752; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NACK_recv : Accumulator : Sum.u64 = 602; SumSQ.u64 = 602; Count.u64 = 602; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckInv_recv : Accumulator : Sum.u64 = 4485; SumSQ.u64 = 4485; Count.u64 = 4485; Min.u64 = 1; Max.u64 = 1; l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 195581; SumSQ.u64 = 1078941; Count.u64 = 40397; Min.u64 = 0; Max.u64 = 7; + l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 209488; SumSQ.u64 = 1188596; Count.u64 = 41835; Min.u64 = 0; Max.u64 = 7; l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.packet_latency : Accumulator : Sum.u64 = 34110; SumSQ.u64 = 110858; Count.u64 = 17957; Min.u64 = 0; Max.u64 = 15; - l3cache2:cpulink.send_bit_count : Accumulator : Sum.u64 = 4215584; SumSQ.u64 = 2115789824; Count.u64 = 17945; Min.u64 = 32; Max.u64 = 544; - l3cache2:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2:cpulink.idle_time : Accumulator : Sum.u64 = 7030656; SumSQ.u64 = 26304965784; Count.u64 = 6372; Min.u64 = 4; Max.u64 = 113910; + l3cache2:highlink.packet_latency : Accumulator : Sum.u64 = 34007; SumSQ.u64 = 109189; Count.u64 = 17948; Min.u64 = 0; Max.u64 = 15; + l3cache2:highlink.send_bit_count : Accumulator : Sum.u64 = 4223264; SumSQ.u64 = 2120492032; Count.u64 = 17929; Min.u64 = 32; Max.u64 = 544; + l3cache2:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2:highlink.idle_time : Accumulator : Sum.u64 = 7390198; SumSQ.u64 = 101825902044; Count.u64 = 6340; Min.u64 = 4; Max.u64 = 286966; l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l3cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2964,10 +3108,10 @@ l3cache2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 3667; SumSQ.u64 = 3667; Count.u64 = 3667; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 3665; SumSQ.u64 = 3665; Count.u64 = 3665; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 4333; SumSQ.u64 = 4333; Count.u64 = 4333; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 4322; SumSQ.u64 = 4322; Count.u64 = 4322; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -2977,15 +3121,15 @@ l3cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3036,9 +3180,9 @@ l3cache2.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1550; SumSQ.u64 = 1550; Count.u64 = 1550; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1819; SumSQ.u64 = 1819; Count.u64 = 1819; Min.u64 = 1; Max.u64 = 1; - l3cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 4577; SumSQ.u64 = 4577; Count.u64 = 4577; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1605; SumSQ.u64 = 1605; Count.u64 = 1605; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1780; SumSQ.u64 = 1780; Count.u64 = 1780; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 4530; SumSQ.u64 = 4530; Count.u64 = 4530; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3057,33 +3201,39 @@ l3cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_NACK : Accumulator : Sum.u64 = 2166; SumSQ.u64 = 2166; Count.u64 = 2166; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 3713; SumSQ.u64 = 3713; Count.u64 = 3713; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 3399; SumSQ.u64 = 3399; Count.u64 = 3399; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_NACK : Accumulator : Sum.u64 = 2161; SumSQ.u64 = 2161; Count.u64 = 2161; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 3708; SumSQ.u64 = 3708; Count.u64 = 3708; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 3420; SumSQ.u64 = 3420; Count.u64 = 3420; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 1714; SumSQ.u64 = 1714; Count.u64 = 1714; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; - l3cache2.eventSent_Inv : Accumulator : Sum.u64 = 4934; SumSQ.u64 = 4934; Count.u64 = 4934; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 1944; SumSQ.u64 = 1944; Count.u64 = 1944; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_Inv : Accumulator : Sum.u64 = 4910; SumSQ.u64 = 4910; Count.u64 = 4910; Min.u64 = 1; Max.u64 = 1; l3cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.latency_GetS_hit : Accumulator : Sum.u64 = 41476; SumSQ.u64 = 1436332; Count.u64 = 1881; Min.u64 = 15; Max.u64 = 325; + l3cache2.latency_GetS_hit : Accumulator : Sum.u64 = 41573; SumSQ.u64 = 1459889; Count.u64 = 1917; Min.u64 = 15; Max.u64 = 385; l3cache2.latency_GetS_miss : Accumulator : Sum.u64 = 599; SumSQ.u64 = 30617; Count.u64 = 12; Min.u64 = 45; Max.u64 = 75; - l3cache2.latency_GetS_inv : Accumulator : Sum.u64 = 92058; SumSQ.u64 = 6137360; Count.u64 = 1827; Min.u64 = 29; Max.u64 = 432; - l3cache2.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetS_inv : Accumulator : Sum.u64 = 92427; SumSQ.u64 = 7245863; Count.u64 = 1789; Min.u64 = 29; Max.u64 = 583; + l3cache2.latency_GetX_hit : Accumulator : Sum.u64 = 30; SumSQ.u64 = 450; Count.u64 = 2; Min.u64 = 15; Max.u64 = 15; l3cache2.latency_GetX_miss : Accumulator : Sum.u64 = 464; SumSQ.u64 = 24586; Count.u64 = 9; Min.u64 = 45; Max.u64 = 75; - l3cache2.latency_GetX_inv : Accumulator : Sum.u64 = 168298; SumSQ.u64 = 11200224; Count.u64 = 3383; Min.u64 = 25; Max.u64 = 453; + l3cache2.latency_GetX_inv : Accumulator : Sum.u64 = 174948; SumSQ.u64 = 13326308; Count.u64 = 3399; Min.u64 = 25; Max.u64 = 551; l3cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3091,11 +3241,12 @@ l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 3023; SumSQ.u64 = 3023; Count.u64 = 3023; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 3723; SumSQ.u64 = 3723; Count.u64 = 3723; Min.u64 = 1; Max.u64 = 1; + l3cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 3062; SumSQ.u64 = 3062; Count.u64 = 3062; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 3669; SumSQ.u64 = 3669; Count.u64 = 3669; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 685; SumSQ.u64 = 685; Count.u64 = 685; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; l3cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; @@ -3103,7 +3254,7 @@ l3cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.CacheHits : Accumulator : Sum.u64 = 8061; SumSQ.u64 = 8061; Count.u64 = 8061; Min.u64 = 1; Max.u64 = 1; + l3cache2.CacheHits : Accumulator : Sum.u64 = 8048; SumSQ.u64 = 8048; Count.u64 = 8048; Min.u64 = 1; Max.u64 = 1; l3cache2.CacheMisses : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l3cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.evict_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3141,8 +3292,8 @@ l3cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.eventSent_PutE : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.TotalEventsReceived : Accumulator : Sum.u64 = 17957; SumSQ.u64 = 17957; Count.u64 = 17957; Min.u64 = 1; Max.u64 = 1; - l3cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 6525; SumSQ.u64 = 6525; Count.u64 = 6525; Min.u64 = 1; Max.u64 = 1; + l3cache2.TotalEventsReceived : Accumulator : Sum.u64 = 17948; SumSQ.u64 = 17948; Count.u64 = 17948; Min.u64 = 1; Max.u64 = 1; + l3cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 6505; SumSQ.u64 = 6505; Count.u64 = 6505; Min.u64 = 1; Max.u64 = 1; l3cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3155,18 +3306,20 @@ l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.GetS_recv : Accumulator : Sum.u64 = 4564; SumSQ.u64 = 4564; Count.u64 = 4564; Min.u64 = 1; Max.u64 = 1; - l3cache2.GetX_recv : Accumulator : Sum.u64 = 4714; SumSQ.u64 = 4714; Count.u64 = 4714; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetS_recv : Accumulator : Sum.u64 = 4546; SumSQ.u64 = 4546; Count.u64 = 4546; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetX_recv : Accumulator : Sum.u64 = 4743; SumSQ.u64 = 4743; Count.u64 = 4743; Min.u64 = 1; Max.u64 = 1; l3cache2.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.PutS_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; - l3cache2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.PutS_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache2.PutM_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; l3cache2.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3174,17 +3327,20 @@ l3cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 1560; SumSQ.u64 = 1560; Count.u64 = 1560; Min.u64 = 1; Max.u64 = 1; - l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 1827; SumSQ.u64 = 1827; Count.u64 = 1827; Min.u64 = 1; Max.u64 = 1; - l3cache2.NACK_recv : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; - l3cache2.AckInv_recv : Accumulator : Sum.u64 = 4615; SumSQ.u64 = 4615; Count.u64 = 4615; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 1615; SumSQ.u64 = 1615; Count.u64 = 1615; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.NACK_recv : Accumulator : Sum.u64 = 647; SumSQ.u64 = 647; Count.u64 = 647; Min.u64 = 1; Max.u64 = 1; + l3cache2.AckInv_recv : Accumulator : Sum.u64 = 4568; SumSQ.u64 = 4568; Count.u64 = 4568; Min.u64 = 1; Max.u64 = 1; l3cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 200881; SumSQ.u64 = 1130101; Count.u64 = 40397; Min.u64 = 0; Max.u64 = 7; + l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 207784; SumSQ.u64 = 1172836; Count.u64 = 41835; Min.u64 = 0; Max.u64 = 7; l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.packet_latency : Accumulator : Sum.u64 = 43; SumSQ.u64 = 79; Count.u64 = 33; Min.u64 = 1; Max.u64 = 5; - directory0:cpulink.send_bit_count : Accumulator : Sum.u64 = 19008; SumSQ.u64 = 10948608; Count.u64 = 33; Min.u64 = 576; Max.u64 = 576; - directory0:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory0:cpulink.idle_time : Accumulator : Sum.u64 = 28605294; SumSQ.u64 = 804078598506996; Count.u64 = 30; Min.u64 = 130; Max.u64 = 28356180; + directory0:highlink.packet_latency : Accumulator : Sum.u64 = 43; SumSQ.u64 = 79; Count.u64 = 33; Min.u64 = 1; Max.u64 = 5; + directory0:highlink.send_bit_count : Accumulator : Sum.u64 = 19008; SumSQ.u64 = 10948608; Count.u64 = 33; Min.u64 = 576; Max.u64 = 576; + directory0:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0:highlink.idle_time : Accumulator : Sum.u64 = 29632294; SumSQ.u64 = 863376921226996; Count.u64 = 30; Min.u64 = 130; Max.u64 = 29383180; directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.get_request_latency : Accumulator : Sum.u64 = 848; SumSQ.u64 = 23614; Count.u64 = 33; Min.u64 = 21; Max.u64 = 51; @@ -3207,8 +3363,10 @@ directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3227,6 +3385,7 @@ directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; @@ -3237,6 +3396,8 @@ directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory0.MSHR_occupancy : Accumulator : Sum.u64 = 782; SumSQ.u64 = 1756; Count.u64 = 680; Min.u64 = 0; Max.u64 = 4; @@ -3248,7 +3409,7 @@ memory0.requests_received_GetX : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; memory0.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.requests_received_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory0.outstanding_requests : Accumulator : Sum.u64 = 265; SumSQ.u64 = 577; Count.u64 = 14421; Min.u64 = 0; Max.u64 = 4; + memory0.outstanding_requests : Accumulator : Sum.u64 = 265; SumSQ.u64 = 577; Count.u64 = 14935; Min.u64 = 0; Max.u64 = 4; memory0.latency_GetS : Accumulator : Sum.u64 = 174; SumSQ.u64 = 1626; Count.u64 = 21; Min.u64 = 7; Max.u64 = 17; memory0.latency_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.latency_GetX : Accumulator : Sum.u64 = 91; SumSQ.u64 = 735; Count.u64 = 12; Min.u64 = 7; Max.u64 = 14; @@ -3256,11 +3417,11 @@ memory0.latency_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory0.cycles_with_issue : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; memory0.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - memory0.total_cycles : Accumulator : Sum.u64 = 14421; SumSQ.u64 = 207965241; Count.u64 = 1; Min.u64 = 14421; Max.u64 = 14421; - directory1:cpulink.packet_latency : Accumulator : Sum.u64 = 32; SumSQ.u64 = 38; Count.u64 = 32; Min.u64 = 0; Max.u64 = 2; - directory1:cpulink.send_bit_count : Accumulator : Sum.u64 = 18432; SumSQ.u64 = 10616832; Count.u64 = 32; Min.u64 = 576; Max.u64 = 576; - directory1:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory1:cpulink.idle_time : Accumulator : Sum.u64 = 28590182; SumSQ.u64 = 799896375409732; Count.u64 = 28; Min.u64 = 142; Max.u64 = 28281924; + memory0.total_cycles : Accumulator : Sum.u64 = 14935; SumSQ.u64 = 223054225; Count.u64 = 1; Min.u64 = 14935; Max.u64 = 14935; + directory1:highlink.packet_latency : Accumulator : Sum.u64 = 32; SumSQ.u64 = 38; Count.u64 = 32; Min.u64 = 0; Max.u64 = 2; + directory1:highlink.send_bit_count : Accumulator : Sum.u64 = 18432; SumSQ.u64 = 10616832; Count.u64 = 32; Min.u64 = 576; Max.u64 = 576; + directory1:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1:highlink.idle_time : Accumulator : Sum.u64 = 29617182; SumSQ.u64 = 859042176305732; Count.u64 = 28; Min.u64 = 142; Max.u64 = 29308924; directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.get_request_latency : Accumulator : Sum.u64 = 866; SumSQ.u64 = 27448; Count.u64 = 32; Min.u64 = 22; Max.u64 = 68; @@ -3283,8 +3444,10 @@ directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -3303,6 +3466,7 @@ directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; @@ -3313,6 +3477,8 @@ directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory1.MSHR_occupancy : Accumulator : Sum.u64 = 802; SumSQ.u64 = 1914; Count.u64 = 784; Min.u64 = 0; Max.u64 = 5; @@ -3324,7 +3490,7 @@ memory1.requests_received_GetX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; memory1.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.requests_received_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - memory1.outstanding_requests : Accumulator : Sum.u64 = 271; SumSQ.u64 = 633; Count.u64 = 14421; Min.u64 = 0; Max.u64 = 4; + memory1.outstanding_requests : Accumulator : Sum.u64 = 271; SumSQ.u64 = 633; Count.u64 = 14935; Min.u64 = 0; Max.u64 = 4; memory1.latency_GetS : Accumulator : Sum.u64 = 99; SumSQ.u64 = 701; Count.u64 = 14; Min.u64 = 7; Max.u64 = 8; memory1.latency_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.latency_GetX : Accumulator : Sum.u64 = 172; SumSQ.u64 = 2114; Count.u64 = 18; Min.u64 = 7; Max.u64 = 23; @@ -3332,5 +3498,5 @@ memory1.latency_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; memory1.cycles_with_issue : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; memory1.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; - memory1.total_cycles : Accumulator : Sum.u64 = 14421; SumSQ.u64 = 207965241; Count.u64 = 1; Min.u64 = 14421; Max.u64 = 14421; -Simulation is complete, simulated time: 28.8435 us + memory1.total_cycles : Accumulator : Sum.u64 = 14935; SumSQ.u64 = 223054225; Count.u64 = 1; Min.u64 = 14935; Max.u64 = 14935; +Simulation is complete, simulated time: 29.8705 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case0_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case0_mesi.out new file mode 100644 index 0000000000..10a9b152eb --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case0_mesi.out @@ -0,0 +1,187 @@ + core.pendCycle : Accumulator : Sum.u64 = 9135300; SumSQ.u64 = 145949392; Count.u64 = 571981; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1459; SumSQ.u64 = 1459; Count.u64 = 1459; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1112; SumSQ.u64 = 1112; Count.u64 = 1112; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1112; SumSQ.u64 = 1112; Count.u64 = 1112; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 720; SumSQ.u64 = 720; Count.u64 = 720; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 1112; SumSQ.u64 = 1112; Count.u64 = 1112; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 803; SumSQ.u64 = 803; Count.u64 = 803; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1459; SumSQ.u64 = 1459; Count.u64 = 1459; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 925; SumSQ.u64 = 925; Count.u64 = 925; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_I : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_M : Accumulator : Sum.u64 = 803; SumSQ.u64 = 803; Count.u64 = 803; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 478908; SumSQ.u64 = 1992588502; Count.u64 = 347; Min.u64 = 4; Max.u64 = 7057; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 4861010; SumSQ.u64 = 23901672844; Count.u64 = 1112; Min.u64 = 3504; Max.u64 = 10665; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 362441; SumSQ.u64 = 1390677465; Count.u64 = 238; Min.u64 = 4; Max.u64 = 7048; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 2930756; SumSQ.u64 = 14430687216; Count.u64 = 672; Min.u64 = 3504; Max.u64 = 10571; + l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 14073; SumSQ.u64 = 74012337; Count.u64 = 11; Min.u64 = 4; Max.u64 = 7032; + l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 219022; SumSQ.u64 = 1122433578; Count.u64 = 48; Min.u64 = 3504; Max.u64 = 7107; + l1cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1062; SumSQ.u64 = 1062; Count.u64 = 1062; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 596; SumSQ.u64 = 596; Count.u64 = 596; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 1832; SumSQ.u64 = 1832; Count.u64 = 1832; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 1005; SumSQ.u64 = 1005; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_E : Accumulator : Sum.u64 = 1005; SumSQ.u64 = 1005; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 4332; SumSQ.u64 = 4332; Count.u64 = 4332; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 1860; SumSQ.u64 = 1860; Count.u64 = 1860; Min.u64 = 1; Max.u64 = 1; + l1cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_recv : Accumulator : Sum.u64 = 1459; SumSQ.u64 = 1459; Count.u64 = 1459; Min.u64 = 1; Max.u64 = 1; + l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.Write_recv : Accumulator : Sum.u64 = 925; SumSQ.u64 = 925; Count.u64 = 925; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1832; SumSQ.u64 = 1832; Count.u64 = 1832; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 7605225; SumSQ.u64 = 113147667; Count.u64 = 571981; Min.u64 = 0; Max.u64 = 16; + l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 1112; SumSQ.u64 = 1112; Count.u64 = 1112; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 672; SumSQ.u64 = 672; Count.u64 = 672; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 803; SumSQ.u64 = 803; Count.u64 = 803; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 2654844; SumSQ.u64 = 53323906; Count.u64 = 163586; Min.u64 = 0; Max.u64 = 36; + memory.latency_GetS : Accumulator : Sum.u64 = 1121459; SumSQ.u64 = 1131073469; Count.u64 = 1112; Min.u64 = 1001; Max.u64 = 1034; + memory.latency_GetSX : Accumulator : Sum.u64 = 48489; SumSQ.u64 = 48987087; Count.u64 = 48; Min.u64 = 1001; Max.u64 = 1028; + memory.latency_GetX : Accumulator : Sum.u64 = 677626; SumSQ.u64 = 683346856; Count.u64 = 672; Min.u64 = 1001; Max.u64 = 1033; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 807270; SumSQ.u64 = 811577472; Count.u64 = 803; Min.u64 = 1001; Max.u64 = 1020; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2635; SumSQ.u64 = 2635; Count.u64 = 2635; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 163586; SumSQ.u64 = 26760379396; Count.u64 = 1; Min.u64 = 163586; Max.u64 = 163586; +Simulation is complete, simulated time: 163.587 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case1_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case1_mesi.out new file mode 100644 index 0000000000..a990c1d5bc --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case1_mesi.out @@ -0,0 +1,433 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core.pendCycle : Accumulator : Sum.u64 = 9409958; SumSQ.u64 = 150253358; Count.u64 = 590495; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1395; SumSQ.u64 = 1395; Count.u64 = 1395; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 705; SumSQ.u64 = 705; Count.u64 = 705; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1002; SumSQ.u64 = 1002; Count.u64 = 1002; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 708; SumSQ.u64 = 708; Count.u64 = 708; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1395; SumSQ.u64 = 1395; Count.u64 = 1395; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_I : Accumulator : Sum.u64 = 1442; SumSQ.u64 = 1442; Count.u64 = 1442; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_M : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 486969; SumSQ.u64 = 2188718027; Count.u64 = 346; Min.u64 = 4; Max.u64 = 10620; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 4764108; SumSQ.u64 = 25526506520; Count.u64 = 1049; Min.u64 = 24; Max.u64 = 10655; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 375607; SumSQ.u64 = 1696112693; Count.u64 = 240; Min.u64 = 4; Max.u64 = 7151; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 3230725; SumSQ.u64 = 17642890443; Count.u64 = 705; Min.u64 = 24; Max.u64 = 10641; + l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 21200; SumSQ.u64 = 149819494; Count.u64 = 3; Min.u64 = 7011; Max.u64 = 7122; + l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 21289; SumSQ.u64 = 99864451; Count.u64 = 17; Min.u64 = 4; Max.u64 = 7106; + l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 263091; SumSQ.u64 = 1488828349; Count.u64 = 59; Min.u64 = 24; Max.u64 = 10644; + l1cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 1816; SumSQ.u64 = 1816; Count.u64 = 1816; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_E : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 4859; SumSQ.u64 = 4859; Count.u64 = 4859; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 1706; SumSQ.u64 = 1706; Count.u64 = 1706; Min.u64 = 1; Max.u64 = 1; + l1cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_recv : Accumulator : Sum.u64 = 1395; SumSQ.u64 = 1395; Count.u64 = 1395; Min.u64 = 1; Max.u64 = 1; + l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_recv : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache.Write_recv : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.Inv_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInv_recv : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 7734416; SumSQ.u64 = 113237034; Count.u64 = 590495; Min.u64 = 0; Max.u64 = 17; + l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 860; SumSQ.u64 = 860; Count.u64 = 860; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 2621298; SumSQ.u64 = 52536572; Count.u64 = 168881; Min.u64 = 0; Max.u64 = 36; + memory.latency_GetS : Accumulator : Sum.u64 = 1017284; SumSQ.u64 = 1024676662; Count.u64 = 1010; Min.u64 = 1001; Max.u64 = 1032; + memory.latency_GetSX : Accumulator : Sum.u64 = 53425; SumSQ.u64 = 53856687; Count.u64 = 53; Min.u64 = 1001; Max.u64 = 1029; + memory.latency_GetX : Accumulator : Sum.u64 = 686007; SumSQ.u64 = 691090141; Count.u64 = 681; Min.u64 = 1001; Max.u64 = 1032; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 864582; SumSQ.u64 = 869206934; Count.u64 = 860; Min.u64 = 1001; Max.u64 = 1022; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2604; SumSQ.u64 = 2604; Count.u64 = 2604; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 168881; SumSQ.u64 = 28520792161; Count.u64 = 1; Min.u64 = 168881; Max.u64 = 168881; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 1619; SumSQ.u64 = 1619; Count.u64 = 1619; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IS : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IM : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 581; SumSQ.u64 = 581; Count.u64 = 581; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 860; SumSQ.u64 = 860; Count.u64 = 860; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 469; SumSQ.u64 = 5641; Count.u64 = 39; Min.u64 = 12; Max.u64 = 13; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 2514449; SumSQ.u64 = 6393535611; Count.u64 = 1010; Min.u64 = 2413; Max.u64 = 4843; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 324; SumSQ.u64 = 3888; Count.u64 = 27; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 1700067; SumSQ.u64 = 4344132245; Count.u64 = 681; Min.u64 = 2413; Max.u64 = 4880; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 72; SumSQ.u64 = 864; Count.u64 = 6; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 131394; SumSQ.u64 = 331387624; Count.u64 = 53; Min.u64 = 2414; Max.u64 = 4829; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 540; SumSQ.u64 = 540; Count.u64 = 540; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheHits : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 1744; SumSQ.u64 = 1744; Count.u64 = 1744; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_E : Accumulator : Sum.u64 = 1097; SumSQ.u64 = 1097; Count.u64 = 1097; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 753; SumSQ.u64 = 753; Count.u64 = 753; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 5489; SumSQ.u64 = 5489; Count.u64 = 5489; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 2234; SumSQ.u64 = 2234; Count.u64 = 2234; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 708; SumSQ.u64 = 708; Count.u64 = 708; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 1744; SumSQ.u64 = 1744; Count.u64 = 1744; Min.u64 = 1; Max.u64 = 1; + l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.PutS_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.PutM_recv : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 4489234; SumSQ.u64 = 56935498; Count.u64 = 404991; Min.u64 = 0; Max.u64 = 16; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 168.882 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case2_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case2_mesi.out new file mode 100644 index 0000000000..f5ca8f03ef --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case2_mesi.out @@ -0,0 +1,407 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core.pendCycle : Accumulator : Sum.u64 = 9175642; SumSQ.u64 = 146534960; Count.u64 = 576265; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1092; SumSQ.u64 = 1092; Count.u64 = 1092; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1092; SumSQ.u64 = 1092; Count.u64 = 1092; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 719; SumSQ.u64 = 719; Count.u64 = 719; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 1092; SumSQ.u64 = 1092; Count.u64 = 1092; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 911; SumSQ.u64 = 911; Count.u64 = 911; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_I : Accumulator : Sum.u64 = 1410; SumSQ.u64 = 1410; Count.u64 = 1410; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_M : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 441202; SumSQ.u64 = 1955424936; Count.u64 = 351; Min.u64 = 4; Max.u64 = 7161; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 4800828; SumSQ.u64 = 25041473776; Count.u64 = 1092; Min.u64 = 24; Max.u64 = 10675; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 364954; SumSQ.u64 = 1409376198; Count.u64 = 232; Min.u64 = 4; Max.u64 = 7083; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 3005314; SumSQ.u64 = 16467112590; Count.u64 = 662; Min.u64 = 24; Max.u64 = 10677; + l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 25002; SumSQ.u64 = 114075228; Count.u64 = 20; Min.u64 = 4; Max.u64 = 7153; + l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 255478; SumSQ.u64 = 1310017504; Count.u64 = 57; Min.u64 = 44; Max.u64 = 7149; + l1cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 585; SumSQ.u64 = 585; Count.u64 = 585; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 603; SumSQ.u64 = 603; Count.u64 = 603; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 1811; SumSQ.u64 = 1811; Count.u64 = 1811; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_E : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 6311; SumSQ.u64 = 6311; Count.u64 = 6311; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 2080; SumSQ.u64 = 2080; Count.u64 = 2080; Min.u64 = 1; Max.u64 = 1; + l1cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_recv : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache.Write_recv : Accumulator : Sum.u64 = 911; SumSQ.u64 = 911; Count.u64 = 911; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1811; SumSQ.u64 = 1811; Count.u64 = 1811; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckPut_recv : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 7546966; SumSQ.u64 = 109673154; Count.u64 = 576265; Min.u64 = 0; Max.u64 = 17; + l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 634; SumSQ.u64 = 634; Count.u64 = 634; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 780; SumSQ.u64 = 780; Count.u64 = 780; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 2527806; SumSQ.u64 = 53263142; Count.u64 = 164811; Min.u64 = 0; Max.u64 = 47; + memory.latency_GetS : Accumulator : Sum.u64 = 1048769; SumSQ.u64 = 1056665411; Count.u64 = 1041; Min.u64 = 1001; Max.u64 = 1041; + memory.latency_GetSX : Accumulator : Sum.u64 = 54400; SumSQ.u64 = 54806466; Count.u64 = 54; Min.u64 = 1001; Max.u64 = 1026; + memory.latency_GetX : Accumulator : Sum.u64 = 638574; SumSQ.u64 = 643222432; Count.u64 = 634; Min.u64 = 1001; Max.u64 = 1040; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 786063; SumSQ.u64 = 792203119; Count.u64 = 780; Min.u64 = 1001; Max.u64 = 1031; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2509; SumSQ.u64 = 2509; Count.u64 = 2509; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 164811; SumSQ.u64 = 27162665721; Count.u64 = 1; Min.u64 = 164811; Max.u64 = 164811; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 888; SumSQ.u64 = 888; Count.u64 = 888; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 821; SumSQ.u64 = 821; Count.u64 = 821; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 634; SumSQ.u64 = 634; Count.u64 = 634; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 1729; Count.u64 = 1729; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_I : Accumulator : Sum.u64 = 804; SumSQ.u64 = 804; Count.u64 = 804; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 634; SumSQ.u64 = 634; Count.u64 = 634; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 780; SumSQ.u64 = 780; Count.u64 = 780; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1811; SumSQ.u64 = 1811; Count.u64 = 1811; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 612; SumSQ.u64 = 7344; Count.u64 = 51; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 2529158; SumSQ.u64 = 6145105722; Count.u64 = 1041; Min.u64 = 2413; Max.u64 = 2510; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 336; SumSQ.u64 = 4032; Count.u64 = 28; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 1539933; SumSQ.u64 = 3740606967; Count.u64 = 634; Min.u64 = 2413; Max.u64 = 2508; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 36; SumSQ.u64 = 432; Count.u64 = 3; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 131184; SumSQ.u64 = 318709836; Count.u64 = 54; Min.u64 = 2413; Max.u64 = 2473; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 634; SumSQ.u64 = 634; Count.u64 = 634; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CacheHits : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 1729; Count.u64 = 1729; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_E : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_I : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 929; SumSQ.u64 = 929; Count.u64 = 929; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 5471; SumSQ.u64 = 5471; Count.u64 = 5471; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 1092; SumSQ.u64 = 1092; Count.u64 = 1092; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 1729; Count.u64 = 1729; Min.u64 = 1; Max.u64 = 1; + l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.PutM_recv : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 4358059; SumSQ.u64 = 54506263; Count.u64 = 395232; Min.u64 = 0; Max.u64 = 16; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 164.812 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case3_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case3_mesi.out new file mode 100644 index 0000000000..05297d7bc9 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case3_mesi.out @@ -0,0 +1,447 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core.pendCycle : Accumulator : Sum.u64 = 20232237; SumSQ.u64 = 322894561; Count.u64 = 1272386; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1403; SumSQ.u64 = 1403; Count.u64 = 1403; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 850; SumSQ.u64 = 850; Count.u64 = 850; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1178; SumSQ.u64 = 1178; Count.u64 = 1178; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 705; SumSQ.u64 = 705; Count.u64 = 705; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 843; SumSQ.u64 = 843; Count.u64 = 843; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 566; SumSQ.u64 = 566; Count.u64 = 566; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 615; SumSQ.u64 = 615; Count.u64 = 615; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 1178; SumSQ.u64 = 1178; Count.u64 = 1178; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1403; SumSQ.u64 = 1403; Count.u64 = 1403; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 944; SumSQ.u64 = 944; Count.u64 = 944; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_I : Accumulator : Sum.u64 = 1535; SumSQ.u64 = 1535; Count.u64 = 1535; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_S : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_M : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 924237; SumSQ.u64 = 7620649661; Count.u64 = 225; Min.u64 = 4; Max.u64 = 17733; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 10118393; SumSQ.u64 = 113440753183; Count.u64 = 1178; Min.u64 = 25; Max.u64 = 28322; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 786356; SumSQ.u64 = 6811366500; Count.u64 = 164; Min.u64 = 4; Max.u64 = 17706; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 6141505; SumSQ.u64 = 69573940683; Count.u64 = 705; Min.u64 = 25; Max.u64 = 35442; + l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 785999; SumSQ.u64 = 13011536599; Count.u64 = 53; Min.u64 = 7080; Max.u64 = 35400; + l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 56626; SumSQ.u64 = 574726680; Count.u64 = 9; Min.u64 = 4; Max.u64 = 10641; + l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 655556; SumSQ.u64 = 7288678494; Count.u64 = 79; Min.u64 = 3525; Max.u64 = 21255; + l1cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 70755; SumSQ.u64 = 875604733; Count.u64 = 6; Min.u64 = 7117; Max.u64 = 14169; + l1cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1105; SumSQ.u64 = 1105; Count.u64 = 1105; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 666; SumSQ.u64 = 666; Count.u64 = 666; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 2021; SumSQ.u64 = 2021; Count.u64 = 2021; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutS : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 224; SumSQ.u64 = 224; Count.u64 = 224; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_E : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 6782; SumSQ.u64 = 6782; Count.u64 = 6782; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 1124; SumSQ.u64 = 1124; Count.u64 = 1124; Min.u64 = 1; Max.u64 = 1; + l1cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_recv : Accumulator : Sum.u64 = 1403; SumSQ.u64 = 1403; Count.u64 = 1403; Min.u64 = 1; Max.u64 = 1; + l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache.Write_recv : Accumulator : Sum.u64 = 944; SumSQ.u64 = 944; Count.u64 = 944; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSResp_recv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1358; SumSQ.u64 = 1358; Count.u64 = 1358; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.Inv_recv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInv_recv : Accumulator : Sum.u64 = 869; SumSQ.u64 = 869; Count.u64 = 869; Min.u64 = 1; Max.u64 = 1; + l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckPut_recv : Accumulator : Sum.u64 = 552; SumSQ.u64 = 552; Count.u64 = 552; Min.u64 = 1; Max.u64 = 1; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 15567562; SumSQ.u64 = 223308974; Count.u64 = 1272386; Min.u64 = 0; Max.u64 = 17; + l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 1176; SumSQ.u64 = 1176; Count.u64 = 1176; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 845; SumSQ.u64 = 845; Count.u64 = 845; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 2869132; SumSQ.u64 = 28446418; Count.u64 = 363902; Min.u64 = 0; Max.u64 = 17; + memory.latency_GetS : Accumulator : Sum.u64 = 1178783; SumSQ.u64 = 1181576857; Count.u64 = 1176; Min.u64 = 1001; Max.u64 = 1012; + memory.latency_GetSX : Accumulator : Sum.u64 = 85173; SumSQ.u64 = 85346553; Count.u64 = 85; Min.u64 = 1001; Max.u64 = 1008; + memory.latency_GetX : Accumulator : Sum.u64 = 758715; SumSQ.u64 = 760436391; Count.u64 = 757; Min.u64 = 1001; Max.u64 = 1011; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 846461; SumSQ.u64 = 847925551; Count.u64 = 845; Min.u64 = 1001; Max.u64 = 1007; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2863; SumSQ.u64 = 2863; Count.u64 = 2863; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 363902; SumSQ.u64 = 132424665604; Count.u64 = 1; Min.u64 = 363902; Max.u64 = 363902; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 2801; SumSQ.u64 = 2801; Count.u64 = 2801; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IS : Accumulator : Sum.u64 = 999; SumSQ.u64 = 999; Count.u64 = 999; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IM : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 1282; SumSQ.u64 = 1282; Count.u64 = 1282; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInv : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1176; SumSQ.u64 = 1176; Count.u64 = 1176; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1176; SumSQ.u64 = 1176; Count.u64 = 1176; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 842; SumSQ.u64 = 842; Count.u64 = 842; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 610; SumSQ.u64 = 610; Count.u64 = 610; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 1176; SumSQ.u64 = 1176; Count.u64 = 1176; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 849; SumSQ.u64 = 849; Count.u64 = 849; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1358; SumSQ.u64 = 1358; Count.u64 = 1358; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 869; SumSQ.u64 = 869; Count.u64 = 869; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 24; SumSQ.u64 = 288; Count.u64 = 2; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 4871276; SumSQ.u64 = 25339981652; Count.u64 = 1176; Min.u64 = 2413; Max.u64 = 12178; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 3303886; SumSQ.u64 = 18388619372; Count.u64 = 757; Min.u64 = 2413; Max.u64 = 14564; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 366484; SumSQ.u64 = 1937165924; Count.u64 = 85; Min.u64 = 2413; Max.u64 = 12118; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 302; SumSQ.u64 = 302; Count.u64 = 302; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheHits : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_E : Accumulator : Sum.u64 = 1805; SumSQ.u64 = 1805; Count.u64 = 1805; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_EInv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 1169; SumSQ.u64 = 1169; Count.u64 = 1169; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 6178; SumSQ.u64 = 6178; Count.u64 = 6178; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 6683; SumSQ.u64 = 6683; Count.u64 = 6683; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 1178; SumSQ.u64 = 1178; Count.u64 = 1178; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.PutS_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache.PutM_recv : Accumulator : Sum.u64 = 233; SumSQ.u64 = 233; Count.u64 = 233; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 625; SumSQ.u64 = 625; Count.u64 = 625; Min.u64 = 1; Max.u64 = 1; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 8926654; SumSQ.u64 = 110192784; Count.u64 = 872667; Min.u64 = 0; Max.u64 = 16; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 363.902 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case4_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case4_mesi.out new file mode 100644 index 0000000000..7efdbde3ea --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case4_mesi.out @@ -0,0 +1,247 @@ + core.pendCycle : Accumulator : Sum.u64 = 18593371; SumSQ.u64 = 297029301; Count.u64 = 1167106; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1445; SumSQ.u64 = 1445; Count.u64 = 1445; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 823; SumSQ.u64 = 823; Count.u64 = 823; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 6436; SumSQ.u64 = 6436; Count.u64 = 6436; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 3923; SumSQ.u64 = 3923; Count.u64 = 3923; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1445; SumSQ.u64 = 1445; Count.u64 = 1445; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_I : Accumulator : Sum.u64 = 1548; SumSQ.u64 = 1548; Count.u64 = 1548; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_M : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 1051453; SumSQ.u64 = 11834410241; Count.u64 = 314; Min.u64 = 4; Max.u64 = 35834; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 9642388; SumSQ.u64 = 114578829718; Count.u64 = 1131; Min.u64 = 3510; Max.u64 = 49894; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 845320; SumSQ.u64 = 8554743354; Count.u64 = 228; Min.u64 = 4; Max.u64 = 25794; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 5740842; SumSQ.u64 = 69231033800; Count.u64 = 649; Min.u64 = 3510; Max.u64 = 29315; + l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 53768; SumSQ.u64 = 626496022; Count.u64 = 11; Min.u64 = 4; Max.u64 = 14326; + l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 590868; SumSQ.u64 = 6830590688; Count.u64 = 68; Min.u64 = 3510; Max.u64 = 26255; + l1cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 553; SumSQ.u64 = 553; Count.u64 = 553; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 1848; SumSQ.u64 = 1848; Count.u64 = 1848; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1816; SumSQ.u64 = 1816; Count.u64 = 1816; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_E : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 15510; SumSQ.u64 = 15510; Count.u64 = 15510; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 2135; SumSQ.u64 = 2135; Count.u64 = 2135; Min.u64 = 1; Max.u64 = 1; + l1cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_recv : Accumulator : Sum.u64 = 1445; SumSQ.u64 = 1445; Count.u64 = 1445; Min.u64 = 1; Max.u64 = 1; + l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache.Write_recv : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1848; SumSQ.u64 = 1848; Count.u64 = 1848; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache.NACK_recv : Accumulator : Sum.u64 = 9124; SumSQ.u64 = 9124; Count.u64 = 9124; Min.u64 = 1; Max.u64 = 1; + l1cache.AckPut_recv : Accumulator : Sum.u64 = 1816; SumSQ.u64 = 1816; Count.u64 = 1816; Min.u64 = 1; Max.u64 = 1; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 14631544; SumSQ.u64 = 207741624; Count.u64 = 1167106; Min.u64 = 0; Max.u64 = 17; + l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 2640677; SumSQ.u64 = 29135391; Count.u64 = 333792; Min.u64 = 0; Max.u64 = 26; + memory.latency_GetS : Accumulator : Sum.u64 = 1134010; SumSQ.u64 = 1137035350; Count.u64 = 1131; Min.u64 = 1001; Max.u64 = 1016; + memory.latency_GetSX : Accumulator : Sum.u64 = 68185; SumSQ.u64 = 68370899; Count.u64 = 68; Min.u64 = 1001; Max.u64 = 1011; + memory.latency_GetX : Accumulator : Sum.u64 = 650719; SumSQ.u64 = 652446535; Count.u64 = 649; Min.u64 = 1001; Max.u64 = 1015; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 787763; SumSQ.u64 = 790541841; Count.u64 = 785; Min.u64 = 1001; Max.u64 = 1014; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2633; SumSQ.u64 = 2633; Count.u64 = 2633; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 333792; SumSQ.u64 = 111417099264; Count.u64 = 1; Min.u64 = 333792; Max.u64 = 333792; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 395769; SumSQ.u64 = 1911481293; Count.u64 = 11014; Min.u64 = 3; Max.u64 = 8109; + directory.get_request_latency : Accumulator : Sum.u64 = 4450521; SumSQ.u64 = 10718227781; Count.u64 = 1848; Min.u64 = 2403; Max.u64 = 2443; + directory.directory_cache_hits : Accumulator : Sum.u64 = 12645; SumSQ.u64 = 12645; Count.u64 = 12645; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 3923; SumSQ.u64 = 3923; Count.u64 = 3923; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 6436; SumSQ.u64 = 6436; Count.u64 = 6436; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 470; SumSQ.u64 = 470; Count.u64 = 470; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 1848; SumSQ.u64 = 1848; Count.u64 = 1848; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckFlush_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 217; SumSQ.u64 = 217; Count.u64 = 217; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 785; SumSQ.u64 = 785; Count.u64 = 785; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 9124; SumSQ.u64 = 9124; Count.u64 = 9124; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 1848; SumSQ.u64 = 1848; Count.u64 = 1848; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 1816; SumSQ.u64 = 1816; Count.u64 = 1816; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 4799109; SumSQ.u64 = 31131223; Count.u64 = 800457; Min.u64 = 0; Max.u64 = 7; +Simulation is complete, simulated time: 333.792 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case5_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case5_mesi.out new file mode 100644 index 0000000000..dc5548d4c7 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case5_mesi.out @@ -0,0 +1,627 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core.pendCycle : Accumulator : Sum.u64 = 8904976; SumSQ.u64 = 142261106; Count.u64 = 559768; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 852; SumSQ.u64 = 852; Count.u64 = 852; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 735; SumSQ.u64 = 735; Count.u64 = 735; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 938; SumSQ.u64 = 938; Count.u64 = 938; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_I : Accumulator : Sum.u64 = 1389; SumSQ.u64 = 1389; Count.u64 = 1389; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_M : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 418803; SumSQ.u64 = 1815521933; Count.u64 = 331; Min.u64 = 4; Max.u64 = 7234; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 4623224; SumSQ.u64 = 25285444880; Count.u64 = 1075; Min.u64 = 24; Max.u64 = 14359; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 331599; SumSQ.u64 = 1452901273; Count.u64 = 247; Min.u64 = 4; Max.u64 = 10779; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 2892412; SumSQ.u64 = 15799284958; Count.u64 = 668; Min.u64 = 24; Max.u64 = 10893; + l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 25005; SumSQ.u64 = 114496041; Count.u64 = 19; Min.u64 = 4; Max.u64 = 7206; + l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 290794; SumSQ.u64 = 1656897558; Count.u64 = 67; Min.u64 = 25; Max.u64 = 10793; + l1cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1015; SumSQ.u64 = 1015; Count.u64 = 1015; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 597; SumSQ.u64 = 597; Count.u64 = 597; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 1810; SumSQ.u64 = 1810; Count.u64 = 1810; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 946; SumSQ.u64 = 946; Count.u64 = 946; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.evict_E : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 6298; SumSQ.u64 = 6298; Count.u64 = 6298; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 1918; SumSQ.u64 = 1918; Count.u64 = 1918; Min.u64 = 1; Max.u64 = 1; + l1cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetS_recv : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSX_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache.Write_recv : Accumulator : Sum.u64 = 938; SumSQ.u64 = 938; Count.u64 = 938; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1810; SumSQ.u64 = 1810; Count.u64 = 1810; Min.u64 = 1; Max.u64 = 1; + l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.AckPut_recv : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 7292750; SumSQ.u64 = 106636526; Count.u64 = 559768; Min.u64 = 0; Max.u64 = 17; + l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 2444029; SumSQ.u64 = 54338727; Count.u64 = 160093; Min.u64 = 0; Max.u64 = 48; + memory.latency_GetS : Accumulator : Sum.u64 = 995800; SumSQ.u64 = 1001682288; Count.u64 = 990; Min.u64 = 1001; Max.u64 = 1036; + memory.latency_GetSX : Accumulator : Sum.u64 = 61407; SumSQ.u64 = 61820433; Count.u64 = 61; Min.u64 = 1001; Max.u64 = 1032; + memory.latency_GetX : Accumulator : Sum.u64 = 622606; SumSQ.u64 = 626260968; Count.u64 = 619; Min.u64 = 1001; Max.u64 = 1036; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 764216; SumSQ.u64 = 771547380; Count.u64 = 757; Min.u64 = 1001; Max.u64 = 1037; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2427; SumSQ.u64 = 2427; Count.u64 = 2427; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 160093; SumSQ.u64 = 25629768649; Count.u64 = 1; Min.u64 = 160093; Max.u64 = 160093; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 814; SumSQ.u64 = 814; Count.u64 = 814; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 824; SumSQ.u64 = 824; Count.u64 = 824; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1712; SumSQ.u64 = 1712; Count.u64 = 1712; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_I : Accumulator : Sum.u64 = 813; SumSQ.u64 = 813; Count.u64 = 813; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 782; SumSQ.u64 = 782; Count.u64 = 782; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1810; SumSQ.u64 = 1810; Count.u64 = 1810; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 780; SumSQ.u64 = 9360; Count.u64 = 65; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 2416934; SumSQ.u64 = 5897518806; Count.u64 = 1010; Min.u64 = 27; Max.u64 = 2512; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 360; SumSQ.u64 = 4320; Count.u64 = 30; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 1511362; SumSQ.u64 = 3687199048; Count.u64 = 638; Min.u64 = 27; Max.u64 = 2512; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 36; SumSQ.u64 = 432; Count.u64 = 3; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 149099; SumSQ.u64 = 363942319; Count.u64 = 64; Min.u64 = 27; Max.u64 = 2503; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 631; SumSQ.u64 = 631; Count.u64 = 631; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheHits : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 1712; SumSQ.u64 = 1712; Count.u64 = 1712; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1668; SumSQ.u64 = 1668; Count.u64 = 1668; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_E : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_I : Accumulator : Sum.u64 = 933; SumSQ.u64 = 933; Count.u64 = 933; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 7318; SumSQ.u64 = 7318; Count.u64 = 7318; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 951; SumSQ.u64 = 951; Count.u64 = 951; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 1712; SumSQ.u64 = 1712; Count.u64 = 1712; Min.u64 = 1; Max.u64 = 1; + l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.PutM_recv : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 946; SumSQ.u64 = 946; Count.u64 = 946; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 1668; SumSQ.u64 = 1668; Count.u64 = 1668; Min.u64 = 1; Max.u64 = 1; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 4401250; SumSQ.u64 = 56522624; Count.u64 = 383917; Min.u64 = 0; Max.u64 = 16; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 790; SumSQ.u64 = 790; Count.u64 = 790; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1670; SumSQ.u64 = 1670; Count.u64 = 1670; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_I : Accumulator : Sum.u64 = 779; SumSQ.u64 = 779; Count.u64 = 779; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1712; SumSQ.u64 = 1712; Count.u64 = 1712; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 1668; SumSQ.u64 = 1668; Count.u64 = 1668; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 240; SumSQ.u64 = 2880; Count.u64 = 20; Min.u64 = 12; Max.u64 = 12; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 2401396; SumSQ.u64 = 5825228364; Count.u64 = 990; Min.u64 = 2413; Max.u64 = 2497; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 228; SumSQ.u64 = 2736; Count.u64 = 19; Min.u64 = 12; Max.u64 = 12; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 1501431; SumSQ.u64 = 3641992995; Count.u64 = 619; Min.u64 = 2413; Max.u64 = 2497; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 36; SumSQ.u64 = 432; Count.u64 = 3; Min.u64 = 12; Max.u64 = 12; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 148078; SumSQ.u64 = 359482092; Count.u64 = 61; Min.u64 = 2413; Max.u64 = 2488; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CacheHits : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 1670; SumSQ.u64 = 1670; Count.u64 = 1670; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_E : Accumulator : Sum.u64 = 872; SumSQ.u64 = 872; Count.u64 = 872; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_I : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 867; SumSQ.u64 = 867; Count.u64 = 867; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 5190; SumSQ.u64 = 5190; Count.u64 = 5190; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 1670; SumSQ.u64 = 1670; Count.u64 = 1670; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutM_recv : Accumulator : Sum.u64 = 782; SumSQ.u64 = 782; Count.u64 = 782; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 4210723; SumSQ.u64 = 53401773; Count.u64 = 383917; Min.u64 = 0; Max.u64 = 16; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 160.094 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case6_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case6_mesi.out new file mode 100644 index 0000000000..52e8de58ef --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_1core_case6_mesi.out @@ -0,0 +1,21 @@ + core.pendCycle : Accumulator : Sum.u64 = 8497068; SumSQ.u64 = 135686772; Count.u64 = 532512; Min.u64 = 0; Max.u64 = 16; + core.reads : Accumulator : Sum.u64 = 1430; SumSQ.u64 = 1430; Count.u64 = 1430; Min.u64 = 1; Max.u64 = 1; + core.writes : Accumulator : Sum.u64 = 833; SumSQ.u64 = 833; Count.u64 = 833; Min.u64 = 1; Max.u64 = 1; + core.flushcaches : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + core.llsc : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + core.llsc_success : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetS : Accumulator : Sum.u64 = 1430; SumSQ.u64 = 1430; Count.u64 = 1430; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_Write : Accumulator : Sum.u64 = 915; SumSQ.u64 = 915; Count.u64 = 915; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.outstanding_requests : Accumulator : Sum.u64 = 2429863; SumSQ.u64 = 38797151; Count.u64 = 152298; Min.u64 = 1; Max.u64 = 16; + memory.latency_GetS : Accumulator : Sum.u64 = 1431691; SumSQ.u64 = 1433384637; Count.u64 = 1430; Min.u64 = 1001; Max.u64 = 1013; + memory.latency_GetSX : Accumulator : Sum.u64 = 82092; SumSQ.u64 = 82184112; Count.u64 = 82; Min.u64 = 1001; Max.u64 = 1002; + memory.latency_GetX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_Write : Accumulator : Sum.u64 = 916080; SumSQ.u64 = 917161788; Count.u64 = 915; Min.u64 = 1001; Max.u64 = 1013; + memory.latency_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.cycles_with_issue : Accumulator : Sum.u64 = 2427; SumSQ.u64 = 2427; Count.u64 = 2427; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 152298; SumSQ.u64 = 23194680804; Count.u64 = 1; Min.u64 = 152298; Max.u64 = 152298; +Simulation is complete, simulated time: 152.298 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case0_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case0_mesi.out new file mode 100644 index 0000000000..e632944783 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case0_mesi.out @@ -0,0 +1,1097 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1232707; SumSQ.u64 = 9835033; Count.u64 = 154613; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1724; SumSQ.u64 = 1724; Count.u64 = 1724; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1276678; SumSQ.u64 = 10189014; Count.u64 = 160040; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 974; SumSQ.u64 = 974; Count.u64 = 974; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1662; SumSQ.u64 = 1662; Count.u64 = 1662; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1076; SumSQ.u64 = 1076; Count.u64 = 1076; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1559; SumSQ.u64 = 1559; Count.u64 = 1559; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1121; SumSQ.u64 = 1121; Count.u64 = 1121; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1662; SumSQ.u64 = 1662; Count.u64 = 1662; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 1085; SumSQ.u64 = 1085; Count.u64 = 1085; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1724; SumSQ.u64 = 1724; Count.u64 = 1724; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1170; SumSQ.u64 = 1170; Count.u64 = 1170; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1729; SumSQ.u64 = 1729; Count.u64 = 1729; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 1085; SumSQ.u64 = 1085; Count.u64 = 1085; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 7615; SumSQ.u64 = 2613559; Count.u64 = 62; Min.u64 = 3; Max.u64 = 729; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 699460; SumSQ.u64 = 372900828; Count.u64 = 1662; Min.u64 = 18; Max.u64 = 1840; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 13860; SumSQ.u64 = 4457116; Count.u64 = 79; Min.u64 = 3; Max.u64 = 654; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 455028; SumSQ.u64 = 248188076; Count.u64 = 1076; Min.u64 = 18; Max.u64 = 1840; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 177; SumSQ.u64 = 17069; Count.u64 = 2; Min.u64 = 62; Max.u64 = 115; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 18734; SumSQ.u64 = 9752826; Count.u64 = 45; Min.u64 = 77; Max.u64 = 1240; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1618; SumSQ.u64 = 1618; Count.u64 = 1618; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2785; SumSQ.u64 = 2785; Count.u64 = 2785; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1527; SumSQ.u64 = 1527; Count.u64 = 1527; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1527; SumSQ.u64 = 1527; Count.u64 = 1527; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6251; SumSQ.u64 = 6251; Count.u64 = 6251; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2174; SumSQ.u64 = 2174; Count.u64 = 2174; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1724; SumSQ.u64 = 1724; Count.u64 = 1724; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1170; SumSQ.u64 = 1170; Count.u64 = 1170; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 859833; SumSQ.u64 = 5636547; Count.u64 = 160040; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 927; SumSQ.u64 = 927; Count.u64 = 927; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1674; SumSQ.u64 = 1674; Count.u64 = 1674; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1011; SumSQ.u64 = 1011; Count.u64 = 1011; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1711; SumSQ.u64 = 1711; Count.u64 = 1711; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 6867; SumSQ.u64 = 2636841; Count.u64 = 65; Min.u64 = 3; Max.u64 = 611; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 777354; SumSQ.u64 = 433970634; Count.u64 = 1789; Min.u64 = 18; Max.u64 = 1606; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 11105; SumSQ.u64 = 3446603; Count.u64 = 71; Min.u64 = 3; Max.u64 = 602; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 406411; SumSQ.u64 = 228633859; Count.u64 = 927; Min.u64 = 18; Max.u64 = 1606; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 681; SumSQ.u64 = 263129; Count.u64 = 3; Min.u64 = 92; Max.u64 = 496; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 14969; SumSQ.u64 = 8912485; Count.u64 = 36; Min.u64 = 21; Max.u64 = 1572; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1736; SumSQ.u64 = 1736; Count.u64 = 1736; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2755; SumSQ.u64 = 2755; Count.u64 = 2755; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1633; SumSQ.u64 = 1633; Count.u64 = 1633; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1633; SumSQ.u64 = 1633; Count.u64 = 1633; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6231; SumSQ.u64 = 6231; Count.u64 = 6231; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2144; SumSQ.u64 = 2144; Count.u64 = 2144; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1011; SumSQ.u64 = 1011; Count.u64 = 1011; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2640; SumSQ.u64 = 2640; Count.u64 = 2640; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 880751; SumSQ.u64 = 5724927; Count.u64 = 160040; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2050; SumSQ.u64 = 2050; Count.u64 = 2050; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 620247; SumSQ.u64 = 12837125; Count.u64 = 53293; Min.u64 = 0; Max.u64 = 65; + memory.latency_GetS : Accumulator : Sum.u64 = 271131; SumSQ.u64 = 23251305; Count.u64 = 3188; Min.u64 = 81; Max.u64 = 134; + memory.latency_GetSX : Accumulator : Sum.u64 = 6163; SumSQ.u64 = 524597; Count.u64 = 73; Min.u64 = 81; Max.u64 = 125; + memory.latency_GetX : Accumulator : Sum.u64 = 156557; SumSQ.u64 = 13471893; Count.u64 = 1836; Min.u64 = 81; Max.u64 = 132; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 186396; SumSQ.u64 = 17131756; Count.u64 = 2050; Min.u64 = 81; Max.u64 = 131; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7147; SumSQ.u64 = 7147; Count.u64 = 7147; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 53293; SumSQ.u64 = 2840143849; Count.u64 = 1; Min.u64 = 53293; Max.u64 = 53293; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2285; SumSQ.u64 = 2285; Count.u64 = 2285; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 1064; SumSQ.u64 = 1064; Count.u64 = 1064; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1637; SumSQ.u64 = 1637; Count.u64 = 1637; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1534; SumSQ.u64 = 1534; Count.u64 = 1534; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1092; SumSQ.u64 = 1092; Count.u64 = 1092; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 1045; SumSQ.u64 = 1045; Count.u64 = 1045; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1637; SumSQ.u64 = 1637; Count.u64 = 1637; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1050; SumSQ.u64 = 1050; Count.u64 = 1050; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 1064; SumSQ.u64 = 1064; Count.u64 = 1064; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2682; SumSQ.u64 = 2682; Count.u64 = 2682; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 300; SumSQ.u64 = 3600; Count.u64 = 25; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 461217; SumSQ.u64 = 135721257; Count.u64 = 1637; Min.u64 = 29; Max.u64 = 427; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 336; SumSQ.u64 = 4032; Count.u64 = 28; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 294761; SumSQ.u64 = 87200391; Count.u64 = 1047; Min.u64 = 34; Max.u64 = 425; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 179; SumSQ.u64 = 10845; Count.u64 = 3; Min.u64 = 53; Max.u64 = 70; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 12729; SumSQ.u64 = 3736999; Count.u64 = 45; Min.u64 = 36; Max.u64 = 419; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1637; SumSQ.u64 = 1637; Count.u64 = 1637; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1050; SumSQ.u64 = 1050; Count.u64 = 1050; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2732; SumSQ.u64 = 2732; Count.u64 = 2732; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_E : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1499; SumSQ.u64 = 1499; Count.u64 = 1499; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 9081; SumSQ.u64 = 9081; Count.u64 = 9081; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2622; SumSQ.u64 = 2622; Count.u64 = 2622; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1662; SumSQ.u64 = 1662; Count.u64 = 1662; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2629; SumSQ.u64 = 2629; Count.u64 = 2629; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 1085; SumSQ.u64 = 1085; Count.u64 = 1085; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1527; SumSQ.u64 = 1527; Count.u64 = 1527; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 841251; SumSQ.u64 = 5467909; Count.u64 = 160040; Min.u64 = 0; Max.u64 = 9; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2291; SumSQ.u64 = 2291; Count.u64 = 2291; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 925; SumSQ.u64 = 925; Count.u64 = 925; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1653; SumSQ.u64 = 1653; Count.u64 = 1653; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 960; SumSQ.u64 = 960; Count.u64 = 960; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 927; SumSQ.u64 = 927; Count.u64 = 927; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2640; SumSQ.u64 = 2640; Count.u64 = 2640; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 289; SumSQ.u64 = 3481; Count.u64 = 24; Min.u64 = 12; Max.u64 = 13; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 501193; SumSQ.u64 = 148155905; Count.u64 = 1765; Min.u64 = 28; Max.u64 = 448; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 36; SumSQ.u64 = 432; Count.u64 = 3; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 261991; SumSQ.u64 = 77499585; Count.u64 = 925; Min.u64 = 34; Max.u64 = 441; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 140; SumSQ.u64 = 9800; Count.u64 = 2; Min.u64 = 70; Max.u64 = 70; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 9552; SumSQ.u64 = 2790500; Count.u64 = 35; Min.u64 = 35; Max.u64 = 387; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 926; SumSQ.u64 = 926; Count.u64 = 926; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2727; SumSQ.u64 = 2727; Count.u64 = 2727; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_E : Accumulator : Sum.u64 = 1554; SumSQ.u64 = 1554; Count.u64 = 1554; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1613; SumSQ.u64 = 1613; Count.u64 = 1613; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1554; SumSQ.u64 = 1554; Count.u64 = 1554; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 9033; SumSQ.u64 = 9033; Count.u64 = 9033; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2584; SumSQ.u64 = 2584; Count.u64 = 2584; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2615; SumSQ.u64 = 2615; Count.u64 = 2615; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1633; SumSQ.u64 = 1633; Count.u64 = 1633; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 857490; SumSQ.u64 = 5489144; Count.u64 = 160040; Min.u64 = 0; Max.u64 = 9; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 4876; SumSQ.u64 = 4876; Count.u64 = 4876; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 2050; SumSQ.u64 = 2050; Count.u64 = 2050; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1909; SumSQ.u64 = 1909; Count.u64 = 1909; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1843; SumSQ.u64 = 1843; Count.u64 = 1843; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2050; SumSQ.u64 = 2050; Count.u64 = 2050; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5244; SumSQ.u64 = 5244; Count.u64 = 5244; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 6419; SumSQ.u64 = 1414435; Count.u64 = 70; Min.u64 = 12; Max.u64 = 294; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 889161; SumSQ.u64 = 249734565; Count.u64 = 3188; Min.u64 = 265; Max.u64 = 426; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 10696; SumSQ.u64 = 1703216; Count.u64 = 144; Min.u64 = 24; Max.u64 = 381; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 589; SumSQ.u64 = 11191; Count.u64 = 31; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 513363; SumSQ.u64 = 144645711; Count.u64 = 1836; Min.u64 = 265; Max.u64 = 421; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 10511; SumSQ.u64 = 2114883; Count.u64 = 110; Min.u64 = 24; Max.u64 = 370; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 38; SumSQ.u64 = 722; Count.u64 = 2; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 20230; SumSQ.u64 = 5645022; Count.u64 = 73; Min.u64 = 265; Max.u64 = 399; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 697; SumSQ.u64 = 166141; Count.u64 = 5; Min.u64 = 38; Max.u64 = 288; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 3188; SumSQ.u64 = 3188; Count.u64 = 3188; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CacheHits : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 5097; SumSQ.u64 = 5097; Count.u64 = 5097; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_E : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 3020; Count.u64 = 3020; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 2973; SumSQ.u64 = 2973; Count.u64 = 2973; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 3020; SumSQ.u64 = 3020; Count.u64 = 3020; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 16601; SumSQ.u64 = 16601; Count.u64 = 16601; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 5521; SumSQ.u64 = 5521; Count.u64 = 5521; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 3402; SumSQ.u64 = 3402; Count.u64 = 3402; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 1977; SumSQ.u64 = 1977; Count.u64 = 1977; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 5097; SumSQ.u64 = 5097; Count.u64 = 5097; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 328; SumSQ.u64 = 328; Count.u64 = 328; Min.u64 = 1; Max.u64 = 1; + l3cache.PutM_recv : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 2997; SumSQ.u64 = 2997; Count.u64 = 2997; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1488858; SumSQ.u64 = 17404126; Count.u64 = 160040; Min.u64 = 0; Max.u64 = 14; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 53.2933 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case10_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case10_mesi.out new file mode 100644 index 0000000000..b6f086d76e --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case10_mesi.out @@ -0,0 +1,1139 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1536979; SumSQ.u64 = 12268833; Count.u64 = 192627; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1708; SumSQ.u64 = 1708; Count.u64 = 1708; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1074; SumSQ.u64 = 1074; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1642250; SumSQ.u64 = 13112610; Count.u64 = 205809; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1890; SumSQ.u64 = 1890; Count.u64 = 1890; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 963; SumSQ.u64 = 963; Count.u64 = 963; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1648; SumSQ.u64 = 1648; Count.u64 = 1648; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 432; SumSQ.u64 = 432; Count.u64 = 432; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1216; SumSQ.u64 = 1216; Count.u64 = 1216; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1116; SumSQ.u64 = 1116; Count.u64 = 1116; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1648; SumSQ.u64 = 1648; Count.u64 = 1648; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1708; SumSQ.u64 = 1708; Count.u64 = 1708; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2218; SumSQ.u64 = 2218; Count.u64 = 2218; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 9513; SumSQ.u64 = 3946185; Count.u64 = 60; Min.u64 = 3; Max.u64 = 661; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 865998; SumSQ.u64 = 581514256; Count.u64 = 1648; Min.u64 = 20; Max.u64 = 1837; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 28815; SumSQ.u64 = 12679737; Count.u64 = 96; Min.u64 = 3; Max.u64 = 1240; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 542863; SumSQ.u64 = 357452001; Count.u64 = 1037; Min.u64 = 22; Max.u64 = 1744; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 2417; SumSQ.u64 = 1956285; Count.u64 = 4; Min.u64 = 26; Max.u64 = 908; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 67; SumSQ.u64 = 3649; Count.u64 = 2; Min.u64 = 7; Max.u64 = 60; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 38184; SumSQ.u64 = 24329364; Count.u64 = 76; Min.u64 = 26; Max.u64 = 1491; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1600; Count.u64 = 1600; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2765; SumSQ.u64 = 2765; Count.u64 = 2765; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1718; SumSQ.u64 = 1718; Count.u64 = 1718; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 933; SumSQ.u64 = 933; Count.u64 = 933; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 933; SumSQ.u64 = 933; Count.u64 = 933; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 9014; SumSQ.u64 = 9014; Count.u64 = 9014; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1676; SumSQ.u64 = 1676; Count.u64 = 1676; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1708; SumSQ.u64 = 1708; Count.u64 = 1708; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 432; SumSQ.u64 = 432; Count.u64 = 432; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2333; SumSQ.u64 = 2333; Count.u64 = 2333; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 1718; SumSQ.u64 = 1718; Count.u64 = 1718; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1063047; SumSQ.u64 = 6883975; Count.u64 = 205809; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1824; SumSQ.u64 = 1824; Count.u64 = 1824; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 434; SumSQ.u64 = 434; Count.u64 = 434; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1390; SumSQ.u64 = 1390; Count.u64 = 1390; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 311; SumSQ.u64 = 311; Count.u64 = 311; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1824; SumSQ.u64 = 1824; Count.u64 = 1824; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 940; SumSQ.u64 = 940; Count.u64 = 940; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 313; SumSQ.u64 = 313; Count.u64 = 313; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1890; SumSQ.u64 = 1890; Count.u64 = 1890; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 998; SumSQ.u64 = 998; Count.u64 = 998; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2192; SumSQ.u64 = 2192; Count.u64 = 2192; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 14941; SumSQ.u64 = 9795329; Count.u64 = 66; Min.u64 = 3; Max.u64 = 1376; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 1014990; SumSQ.u64 = 739201090; Count.u64 = 1824; Min.u64 = 20; Max.u64 = 2550; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 10830; SumSQ.u64 = 3976230; Count.u64 = 48; Min.u64 = 3; Max.u64 = 662; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 517847; SumSQ.u64 = 373004061; Count.u64 = 936; Min.u64 = 19; Max.u64 = 2227; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 1573; SumSQ.u64 = 1208451; Count.u64 = 4; Min.u64 = 25; Max.u64 = 921; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 53; SumSQ.u64 = 2809; Count.u64 = 1; Min.u64 = 53; Max.u64 = 53; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 16575; SumSQ.u64 = 10144229; Count.u64 = 34; Min.u64 = 187; Max.u64 = 1225; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1736; SumSQ.u64 = 1736; Count.u64 = 1736; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2798; SumSQ.u64 = 2798; Count.u64 = 2798; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1842; SumSQ.u64 = 1842; Count.u64 = 1842; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 9052; SumSQ.u64 = 9052; Count.u64 = 9052; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1764; SumSQ.u64 = 1764; Count.u64 = 1764; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1890; SumSQ.u64 = 1890; Count.u64 = 1890; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 998; SumSQ.u64 = 998; Count.u64 = 998; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 434; SumSQ.u64 = 434; Count.u64 = 434; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2364; SumSQ.u64 = 2364; Count.u64 = 2364; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 350; SumSQ.u64 = 350; Count.u64 = 350; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 1842; SumSQ.u64 = 1842; Count.u64 = 1842; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1138740; SumSQ.u64 = 7312402; Count.u64 = 205809; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3337; SumSQ.u64 = 3337; Count.u64 = 3337; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2059; SumSQ.u64 = 2059; Count.u64 = 2059; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 609645; SumSQ.u64 = 7629835; Count.u64 = 68534; Min.u64 = 0; Max.u64 = 30; + memory.latency_GetS : Accumulator : Sum.u64 = 275148; SumSQ.u64 = 22703630; Count.u64 = 3337; Min.u64 = 81; Max.u64 = 92; + memory.latency_GetSX : Accumulator : Sum.u64 = 8782; SumSQ.u64 = 721052; Count.u64 = 107; Min.u64 = 81; Max.u64 = 89; + memory.latency_GetX : Accumulator : Sum.u64 = 157605; SumSQ.u64 = 13000343; Count.u64 = 1912; Min.u64 = 81; Max.u64 = 92; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 168110; SumSQ.u64 = 13727804; Count.u64 = 2059; Min.u64 = 81; Max.u64 = 89; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7415; SumSQ.u64 = 7415; Count.u64 = 7415; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 68534; SumSQ.u64 = 4696909156; Count.u64 = 1; Min.u64 = 68534; Max.u64 = 68534; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2696; SumSQ.u64 = 2696; Count.u64 = 2696; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IM : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1661; SumSQ.u64 = 1661; Count.u64 = 1661; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1478; SumSQ.u64 = 1478; Count.u64 = 1478; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2074; SumSQ.u64 = 2074; Count.u64 = 2074; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1661; SumSQ.u64 = 1661; Count.u64 = 1661; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 816; SumSQ.u64 = 816; Count.u64 = 816; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2389; SumSQ.u64 = 2389; Count.u64 = 2389; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 730; SumSQ.u64 = 730; Count.u64 = 730; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 5650; SumSQ.u64 = 1939490; Count.u64 = 55; Min.u64 = 12; Max.u64 = 619; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 583025; SumSQ.u64 = 234070451; Count.u64 = 1661; Min.u64 = 34; Max.u64 = 1243; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 2758; SumSQ.u64 = 682656; Count.u64 = 29; Min.u64 = 12; Max.u64 = 335; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 343108; SumSQ.u64 = 135236786; Count.u64 = 988; Min.u64 = 65; Max.u64 = 1510; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 3872; SumSQ.u64 = 3986724; Count.u64 = 4; Min.u64 = 611; Max.u64 = 1195; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 51; SumSQ.u64 = 905; Count.u64 = 3; Min.u64 = 12; Max.u64 = 20; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 19431; SumSQ.u64 = 7173501; Count.u64 = 57; Min.u64 = 281; Max.u64 = 636; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 807; SumSQ.u64 = 807; Count.u64 = 807; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheHits : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2710; SumSQ.u64 = 2710; Count.u64 = 2710; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 614; SumSQ.u64 = 614; Count.u64 = 614; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 216; SumSQ.u64 = 216; Count.u64 = 216; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1226; SumSQ.u64 = 1226; Count.u64 = 1226; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 12160; SumSQ.u64 = 12160; Count.u64 = 12160; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 2619; Count.u64 = 2619; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1716; SumSQ.u64 = 1716; Count.u64 = 1716; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1021; SumSQ.u64 = 1021; Count.u64 = 1021; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2527; SumSQ.u64 = 2527; Count.u64 = 2527; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 675; SumSQ.u64 = 675; Count.u64 = 675; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1005; SumSQ.u64 = 1005; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 183; SumSQ.u64 = 183; Count.u64 = 183; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 697; SumSQ.u64 = 697; Count.u64 = 697; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 315; SumSQ.u64 = 315; Count.u64 = 315; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 2074; SumSQ.u64 = 2074; Count.u64 = 2074; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1127689; SumSQ.u64 = 7311843; Count.u64 = 205809; Min.u64 = 0; Max.u64 = 12; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2643; SumSQ.u64 = 2643; Count.u64 = 2643; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IM : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1686; SumSQ.u64 = 1686; Count.u64 = 1686; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 919; SumSQ.u64 = 919; Count.u64 = 919; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1499; SumSQ.u64 = 1499; Count.u64 = 1499; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 605; SumSQ.u64 = 605; Count.u64 = 605; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1686; SumSQ.u64 = 1686; Count.u64 = 1686; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 922; SumSQ.u64 = 922; Count.u64 = 922; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2308; SumSQ.u64 = 2308; Count.u64 = 2308; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 691; SumSQ.u64 = 691; Count.u64 = 691; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 1772; SumSQ.u64 = 1772; Count.u64 = 1772; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 8700; SumSQ.u64 = 2768282; Count.u64 = 70; Min.u64 = 12; Max.u64 = 638; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 586128; SumSQ.u64 = 231426772; Count.u64 = 1686; Min.u64 = 48; Max.u64 = 1461; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 4245; SumSQ.u64 = 1006769; Count.u64 = 38; Min.u64 = 12; Max.u64 = 332; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 323524; SumSQ.u64 = 130429144; Count.u64 = 919; Min.u64 = 35; Max.u64 = 1246; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 3357994; Count.u64 = 3; Min.u64 = 628; Max.u64 = 1473; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 15925; SumSQ.u64 = 5531471; Count.u64 = 50; Min.u64 = 281; Max.u64 = 872; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1352; SumSQ.u64 = 1352; Count.u64 = 1352; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheHits : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2658; SumSQ.u64 = 2658; Count.u64 = 2658; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_ED : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 208; SumSQ.u64 = 208; Count.u64 = 208; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 276; SumSQ.u64 = 276; Count.u64 = 276; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1249; SumSQ.u64 = 1249; Count.u64 = 1249; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11428; SumSQ.u64 = 11428; Count.u64 = 11428; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2622; SumSQ.u64 = 2622; Count.u64 = 2622; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1756; SumSQ.u64 = 1756; Count.u64 = 1756; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 960; SumSQ.u64 = 960; Count.u64 = 960; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2471; SumSQ.u64 = 2471; Count.u64 = 2471; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1011; SumSQ.u64 = 1011; Count.u64 = 1011; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1021568; SumSQ.u64 = 6527732; Count.u64 = 205809; Min.u64 = 0; Max.u64 = 13; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 4353; SumSQ.u64 = 4353; Count.u64 = 4353; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IM : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 1526; SumSQ.u64 = 1526; Count.u64 = 1526; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MA : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3337; SumSQ.u64 = 3337; Count.u64 = 3337; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3337; SumSQ.u64 = 3337; Count.u64 = 3337; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1451; SumSQ.u64 = 1451; Count.u64 = 1451; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 3337; SumSQ.u64 = 3337; Count.u64 = 3337; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2059; SumSQ.u64 = 2059; Count.u64 = 2059; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 4998; SumSQ.u64 = 4998; Count.u64 = 4998; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 4116; SumSQ.u64 = 4116; Count.u64 = 4116; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 190; SumSQ.u64 = 3610; Count.u64 = 10; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 1023902; SumSQ.u64 = 345251076; Count.u64 = 3337; Min.u64 = 265; Max.u64 = 1171; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 38; SumSQ.u64 = 722; Count.u64 = 2; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 589265; SumSQ.u64 = 200648913; Count.u64 = 1912; Min.u64 = 265; Max.u64 = 1188; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 32205; SumSQ.u64 = 10317973; Count.u64 = 107; Min.u64 = 265; Max.u64 = 592; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 2501; SumSQ.u64 = 2501; Count.u64 = 2501; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1403; SumSQ.u64 = 1403; Count.u64 = 1403; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 836; SumSQ.u64 = 836; Count.u64 = 836; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheHits : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 5356; SumSQ.u64 = 5356; Count.u64 = 5356; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_E : Accumulator : Sum.u64 = 2485; SumSQ.u64 = 2485; Count.u64 = 2485; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 2359; SumSQ.u64 = 2359; Count.u64 = 2359; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 444; SumSQ.u64 = 444; Count.u64 = 444; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 3277; SumSQ.u64 = 3277; Count.u64 = 3277; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 16491; SumSQ.u64 = 16491; Count.u64 = 16491; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 4468; SumSQ.u64 = 4468; Count.u64 = 4468; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 3347; SumSQ.u64 = 3347; Count.u64 = 3347; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 5356; SumSQ.u64 = 5356; Count.u64 = 5356; Min.u64 = 1; Max.u64 = 1; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l3cache.PutM_recv : Accumulator : Sum.u64 = 1583; SumSQ.u64 = 1583; Count.u64 = 1583; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 2475; SumSQ.u64 = 2475; Count.u64 = 2475; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 922; SumSQ.u64 = 922; Count.u64 = 922; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1697610; SumSQ.u64 = 17584352; Count.u64 = 205809; Min.u64 = 0; Max.u64 = 15; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 68.5344 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case11_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case11_mesi.out new file mode 100644 index 0000000000..dcd5e65376 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case11_mesi.out @@ -0,0 +1,939 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1275574; SumSQ.u64 = 10179566; Count.u64 = 159962; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1099; SumSQ.u64 = 1099; Count.u64 = 1099; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1396342; SumSQ.u64 = 11147792; Count.u64 = 174962; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 975; SumSQ.u64 = 975; Count.u64 = 975; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1654; SumSQ.u64 = 1654; Count.u64 = 1654; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1428; SumSQ.u64 = 1428; Count.u64 = 1428; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1654; SumSQ.u64 = 1654; Count.u64 = 1654; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1057; SumSQ.u64 = 1057; Count.u64 = 1057; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2039; SumSQ.u64 = 2039; Count.u64 = 2039; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 866; SumSQ.u64 = 866; Count.u64 = 866; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 9932; SumSQ.u64 = 3747740; Count.u64 = 69; Min.u64 = 3; Max.u64 = 910; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 726067; SumSQ.u64 = 391729619; Count.u64 = 1654; Min.u64 = 18; Max.u64 = 1428; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 14744; SumSQ.u64 = 4564822; Count.u64 = 80; Min.u64 = 3; Max.u64 = 569; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 457490; SumSQ.u64 = 246461886; Count.u64 = 1051; Min.u64 = 19; Max.u64 = 1417; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 2629; SumSQ.u64 = 1684267; Count.u64 = 6; Min.u64 = 21; Max.u64 = 825; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 328; SumSQ.u64 = 98194; Count.u64 = 2; Min.u64 = 15; Max.u64 = 313; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 24086; SumSQ.u64 = 13117798; Count.u64 = 53; Min.u64 = 37; Max.u64 = 1206; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1590; SumSQ.u64 = 1590; Count.u64 = 1590; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2764; SumSQ.u64 = 2764; Count.u64 = 2764; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2231; SumSQ.u64 = 2231; Count.u64 = 2231; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1260; SumSQ.u64 = 1260; Count.u64 = 1260; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1260; SumSQ.u64 = 1260; Count.u64 = 1260; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 9033; SumSQ.u64 = 9033; Count.u64 = 9033; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2029; SumSQ.u64 = 2029; Count.u64 = 2029; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 422; SumSQ.u64 = 422; Count.u64 = 422; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 2231; SumSQ.u64 = 2231; Count.u64 = 2231; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 881319; SumSQ.u64 = 5717897; Count.u64 = 174962; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1819; SumSQ.u64 = 1819; Count.u64 = 1819; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 941; SumSQ.u64 = 941; Count.u64 = 941; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1569; SumSQ.u64 = 1569; Count.u64 = 1569; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 966; SumSQ.u64 = 966; Count.u64 = 966; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1819; SumSQ.u64 = 1819; Count.u64 = 1819; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 947; SumSQ.u64 = 947; Count.u64 = 947; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1894; SumSQ.u64 = 1894; Count.u64 = 1894; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 11888; SumSQ.u64 = 7229868; Count.u64 = 70; Min.u64 = 3; Max.u64 = 1189; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 857881; SumSQ.u64 = 517971059; Count.u64 = 1819; Min.u64 = 21; Max.u64 = 1550; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 6402; SumSQ.u64 = 2303256; Count.u64 = 44; Min.u64 = 3; Max.u64 = 814; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 439603; SumSQ.u64 = 269232283; Count.u64 = 941; Min.u64 = 19; Max.u64 = 2105; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 2576; SumSQ.u64 = 1838928; Count.u64 = 6; Min.u64 = 19; Max.u64 = 840; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 612; SumSQ.u64 = 190154; Count.u64 = 3; Min.u64 = 3; Max.u64 = 353; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 12974; SumSQ.u64 = 10599498; Count.u64 = 22; Min.u64 = 272; Max.u64 = 1498; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1745; SumSQ.u64 = 1745; Count.u64 = 1745; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2788; SumSQ.u64 = 2788; Count.u64 = 2788; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2330; SumSQ.u64 = 2330; Count.u64 = 2330; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1433; SumSQ.u64 = 1433; Count.u64 = 1433; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1433; SumSQ.u64 = 1433; Count.u64 = 1433; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 9068; SumSQ.u64 = 9068; Count.u64 = 9068; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1943; SumSQ.u64 = 1943; Count.u64 = 1943; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2538; SumSQ.u64 = 2538; Count.u64 = 2538; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 2330; SumSQ.u64 = 2330; Count.u64 = 2330; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 940004; SumSQ.u64 = 6045758; Count.u64 = 174962; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3368; SumSQ.u64 = 3368; Count.u64 = 3368; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1933; SumSQ.u64 = 1933; Count.u64 = 1933; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2073; SumSQ.u64 = 2073; Count.u64 = 2073; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 614922; SumSQ.u64 = 8681178; Count.u64 = 58262; Min.u64 = 0; Max.u64 = 30; + memory.latency_GetS : Accumulator : Sum.u64 = 278912; SumSQ.u64 = 23115688; Count.u64 = 3368; Min.u64 = 81; Max.u64 = 91; + memory.latency_GetSX : Accumulator : Sum.u64 = 6092; SumSQ.u64 = 501782; Count.u64 = 74; Min.u64 = 81; Max.u64 = 89; + memory.latency_GetX : Accumulator : Sum.u64 = 159953; SumSQ.u64 = 13246393; Count.u64 = 1933; Min.u64 = 81; Max.u64 = 91; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 169965; SumSQ.u64 = 13939515; Count.u64 = 2073; Min.u64 = 81; Max.u64 = 90; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7448; SumSQ.u64 = 7448; Count.u64 = 7448; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 58262; SumSQ.u64 = 3394460644; Count.u64 = 1; Min.u64 = 58262; Max.u64 = 58262; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2644; SumSQ.u64 = 2644; Count.u64 = 2644; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IM : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 435; SumSQ.u64 = 435; Count.u64 = 435; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1660; SumSQ.u64 = 1660; Count.u64 = 1660; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1660; SumSQ.u64 = 1660; Count.u64 = 1660; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1019; SumSQ.u64 = 1019; Count.u64 = 1019; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 796; SumSQ.u64 = 796; Count.u64 = 796; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2674; SumSQ.u64 = 2674; Count.u64 = 2674; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1660; SumSQ.u64 = 1660; Count.u64 = 1660; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2540; SumSQ.u64 = 2540; Count.u64 = 2540; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 2288; SumSQ.u64 = 2288; Count.u64 = 2288; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 5157; SumSQ.u64 = 1195985; Count.u64 = 59; Min.u64 = 12; Max.u64 = 292; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 483944; SumSQ.u64 = 150085536; Count.u64 = 1660; Min.u64 = 262; Max.u64 = 842; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 1869; SumSQ.u64 = 375831; Count.u64 = 34; Min.u64 = 12; Max.u64 = 304; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 282900; SumSQ.u64 = 86029066; Count.u64 = 980; Min.u64 = 262; Max.u64 = 806; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 11614; SumSQ.u64 = 3825620; Count.u64 = 39; Min.u64 = 262; Max.u64 = 809; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1326; SumSQ.u64 = 1326; Count.u64 = 1326; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheHits : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2679; SumSQ.u64 = 2679; Count.u64 = 2679; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1302; SumSQ.u64 = 1302; Count.u64 = 1302; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1627; SumSQ.u64 = 1627; Count.u64 = 1627; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 12017; SumSQ.u64 = 12017; Count.u64 = 12017; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2119; SumSQ.u64 = 2119; Count.u64 = 2119; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1014; SumSQ.u64 = 1014; Count.u64 = 1014; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2679; SumSQ.u64 = 2679; Count.u64 = 2679; Min.u64 = 1; Max.u64 = 1; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 837; SumSQ.u64 = 837; Count.u64 = 837; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1334; SumSQ.u64 = 1334; Count.u64 = 1334; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 349; SumSQ.u64 = 349; Count.u64 = 349; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 462; SumSQ.u64 = 462; Count.u64 = 462; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 2674; SumSQ.u64 = 2674; Count.u64 = 2674; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 928774; SumSQ.u64 = 5943372; Count.u64 = 174962; Min.u64 = 0; Max.u64 = 13; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2653; SumSQ.u64 = 2653; Count.u64 = 2653; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IM : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1708; SumSQ.u64 = 1708; Count.u64 = 1708; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 953; SumSQ.u64 = 953; Count.u64 = 953; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1708; SumSQ.u64 = 1708; Count.u64 = 1708; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 778; SumSQ.u64 = 778; Count.u64 = 778; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 209; SumSQ.u64 = 209; Count.u64 = 209; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1708; SumSQ.u64 = 1708; Count.u64 = 1708; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 953; SumSQ.u64 = 953; Count.u64 = 953; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 1026; SumSQ.u64 = 1026; Count.u64 = 1026; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 244; SumSQ.u64 = 244; Count.u64 = 244; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 2273; SumSQ.u64 = 2273; Count.u64 = 2273; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 5196; SumSQ.u64 = 1526826; Count.u64 = 46; Min.u64 = 12; Max.u64 = 552; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 498268; SumSQ.u64 = 154735218; Count.u64 = 1708; Min.u64 = 262; Max.u64 = 1107; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 4724; SumSQ.u64 = 1442120; Count.u64 = 37; Min.u64 = 12; Max.u64 = 581; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 278695; SumSQ.u64 = 86198407; Count.u64 = 953; Min.u64 = 262; Max.u64 = 809; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 30; SumSQ.u64 = 900; Count.u64 = 1; Min.u64 = 30; Max.u64 = 30; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 10109; SumSQ.u64 = 3051841; Count.u64 = 35; Min.u64 = 263; Max.u64 = 551; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1364; SumSQ.u64 = 1364; Count.u64 = 1364; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 344; SumSQ.u64 = 344; Count.u64 = 344; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheHits : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2696; SumSQ.u64 = 2696; Count.u64 = 2696; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_ED : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1326; SumSQ.u64 = 1326; Count.u64 = 1326; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1662; SumSQ.u64 = 1662; Count.u64 = 1662; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11436; SumSQ.u64 = 11436; Count.u64 = 11436; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2179; SumSQ.u64 = 2179; Count.u64 = 2179; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1754; SumSQ.u64 = 1754; Count.u64 = 1754; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2696; SumSQ.u64 = 2696; Count.u64 = 2696; Min.u64 = 1; Max.u64 = 1; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 822; SumSQ.u64 = 822; Count.u64 = 822; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1359; SumSQ.u64 = 1359; Count.u64 = 1359; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 345; SumSQ.u64 = 345; Count.u64 = 345; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 2688; SumSQ.u64 = 2688; Count.u64 = 2688; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 860800; SumSQ.u64 = 5455418; Count.u64 = 174962; Min.u64 = 0; Max.u64 = 12; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 61784; SumSQ.u64 = 17815218; Count.u64 = 5516; Min.u64 = 2; Max.u64 = 589; + directory.get_request_latency : Accumulator : Sum.u64 = 909649; SumSQ.u64 = 154082225; Count.u64 = 5375; Min.u64 = 165; Max.u64 = 188; + directory.directory_cache_hits : Accumulator : Sum.u64 = 10737; SumSQ.u64 = 10737; Count.u64 = 10737; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 1933; SumSQ.u64 = 1933; Count.u64 = 1933; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 3368; SumSQ.u64 = 3368; Count.u64 = 3368; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 2073; SumSQ.u64 = 2073; Count.u64 = 2073; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 3289; SumSQ.u64 = 3289; Count.u64 = 3289; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 5375; SumSQ.u64 = 5375; Count.u64 = 5375; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckFlush_recv : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 3368; SumSQ.u64 = 3368; Count.u64 = 3368; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 1933; SumSQ.u64 = 1933; Count.u64 = 1933; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 2073; SumSQ.u64 = 2073; Count.u64 = 2073; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 5375; SumSQ.u64 = 5375; Count.u64 = 5375; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 5362; SumSQ.u64 = 5362; Count.u64 = 5362; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 947798; SumSQ.u64 = 9905540; Count.u64 = 116520; Min.u64 = 0; Max.u64 = 14; +Simulation is complete, simulated time: 58.2623 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case1_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case1_mesi.out new file mode 100644 index 0000000000..ed33b1efb0 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case1_mesi.out @@ -0,0 +1,1343 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. +l3cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1196900; SumSQ.u64 = 9549688; Count.u64 = 150136; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1318875; SumSQ.u64 = 10525493; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1026; SumSQ.u64 = 1026; Count.u64 = 1026; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1617; SumSQ.u64 = 1617; Count.u64 = 1617; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1095; SumSQ.u64 = 1095; Count.u64 = 1095; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1533; SumSQ.u64 = 1533; Count.u64 = 1533; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1153; SumSQ.u64 = 1153; Count.u64 = 1153; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1617; SumSQ.u64 = 1617; Count.u64 = 1617; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1096; SumSQ.u64 = 1096; Count.u64 = 1096; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 1115; SumSQ.u64 = 1115; Count.u64 = 1115; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1199; SumSQ.u64 = 1199; Count.u64 = 1199; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1739; SumSQ.u64 = 1739; Count.u64 = 1739; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 1115; SumSQ.u64 = 1115; Count.u64 = 1115; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 9887; SumSQ.u64 = 3865101; Count.u64 = 71; Min.u64 = 3; Max.u64 = 646; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 666805; SumSQ.u64 = 344213155; Count.u64 = 1617; Min.u64 = 16; Max.u64 = 1380; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 14093; SumSQ.u64 = 4628535; Count.u64 = 86; Min.u64 = 3; Max.u64 = 634; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 454410; SumSQ.u64 = 234720462; Count.u64 = 1095; Min.u64 = 19; Max.u64 = 1383; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 303; SumSQ.u64 = 91809; Count.u64 = 1; Min.u64 = 303; Max.u64 = 303; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 21246; SumSQ.u64 = 9869482; Count.u64 = 58; Min.u64 = 23; Max.u64 = 759; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1566; SumSQ.u64 = 1566; Count.u64 = 1566; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1059; SumSQ.u64 = 1059; Count.u64 = 1059; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6225; SumSQ.u64 = 6225; Count.u64 = 6225; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2175; SumSQ.u64 = 2175; Count.u64 = 2175; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1688; SumSQ.u64 = 1688; Count.u64 = 1688; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1199; SumSQ.u64 = 1199; Count.u64 = 1199; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2687; SumSQ.u64 = 2687; Count.u64 = 2687; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 845006; SumSQ.u64 = 5553806; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1740; SumSQ.u64 = 1740; Count.u64 = 1740; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1627; SumSQ.u64 = 1627; Count.u64 = 1627; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1018; SumSQ.u64 = 1018; Count.u64 = 1018; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1740; SumSQ.u64 = 1740; Count.u64 = 1740; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 986; SumSQ.u64 = 986; Count.u64 = 986; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1063; SumSQ.u64 = 1063; Count.u64 = 1063; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1676; SumSQ.u64 = 1676; Count.u64 = 1676; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 7534; SumSQ.u64 = 3769134; Count.u64 = 69; Min.u64 = 3; Max.u64 = 929; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 770820; SumSQ.u64 = 448747362; Count.u64 = 1740; Min.u64 = 18; Max.u64 = 1999; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 13172; SumSQ.u64 = 4787520; Count.u64 = 67; Min.u64 = 3; Max.u64 = 652; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 448276; SumSQ.u64 = 276793558; Count.u64 = 982; Min.u64 = 19; Max.u64 = 2287; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 967; SumSQ.u64 = 500279; Count.u64 = 4; Min.u64 = 21; Max.u64 = 653; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 261; SumSQ.u64 = 68121; Count.u64 = 1; Min.u64 = 261; Max.u64 = 261; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 16661; SumSQ.u64 = 9508593; Count.u64 = 36; Min.u64 = 25; Max.u64 = 1023; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1685; SumSQ.u64 = 1685; Count.u64 = 1685; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 945; SumSQ.u64 = 945; Count.u64 = 945; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2762; SumSQ.u64 = 2762; Count.u64 = 2762; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1588; SumSQ.u64 = 1588; Count.u64 = 1588; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1588; SumSQ.u64 = 1588; Count.u64 = 1588; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6217; SumSQ.u64 = 6217; Count.u64 = 6217; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2101; SumSQ.u64 = 2101; Count.u64 = 2101; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1809; SumSQ.u64 = 1809; Count.u64 = 1809; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1063; SumSQ.u64 = 1063; Count.u64 = 1063; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2649; SumSQ.u64 = 2649; Count.u64 = 2649; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 882050; SumSQ.u64 = 5702238; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3053; SumSQ.u64 = 3053; Count.u64 = 3053; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2141; SumSQ.u64 = 2141; Count.u64 = 2141; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 615037; SumSQ.u64 = 12888525; Count.u64 = 55072; Min.u64 = 0; Max.u64 = 66; + memory.latency_GetS : Accumulator : Sum.u64 = 258612; SumSQ.u64 = 22063976; Count.u64 = 3053; Min.u64 = 81; Max.u64 = 128; + memory.latency_GetSX : Accumulator : Sum.u64 = 7141; SumSQ.u64 = 612131; Count.u64 = 84; Min.u64 = 81; Max.u64 = 124; + memory.latency_GetX : Accumulator : Sum.u64 = 161394; SumSQ.u64 = 13716098; Count.u64 = 1911; Min.u64 = 81; Max.u64 = 129; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 187890; SumSQ.u64 = 16587492; Count.u64 = 2141; Min.u64 = 81; Max.u64 = 118; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7189; SumSQ.u64 = 7189; Count.u64 = 7189; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 55072; SumSQ.u64 = 3032925184; Count.u64 = 1; Min.u64 = 55072; Max.u64 = 55072; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2126; SumSQ.u64 = 2126; Count.u64 = 2126; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 1057; SumSQ.u64 = 1057; Count.u64 = 1057; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1504; SumSQ.u64 = 1504; Count.u64 = 1504; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 938; SumSQ.u64 = 938; Count.u64 = 938; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1504; SumSQ.u64 = 1504; Count.u64 = 1504; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1504; SumSQ.u64 = 1504; Count.u64 = 1504; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 938; SumSQ.u64 = 938; Count.u64 = 938; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 1057; SumSQ.u64 = 1057; Count.u64 = 1057; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2601; SumSQ.u64 = 2601; Count.u64 = 2601; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 4177; SumSQ.u64 = 947981; Count.u64 = 75; Min.u64 = 12; Max.u64 = 314; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 437440; SumSQ.u64 = 129318114; Count.u64 = 1504; Min.u64 = 35; Max.u64 = 422; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 3814; SumSQ.u64 = 905870; Count.u64 = 46; Min.u64 = 14; Max.u64 = 369; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 468; SumSQ.u64 = 5616; Count.u64 = 39; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 273831; SumSQ.u64 = 80900287; Count.u64 = 938; Min.u64 = 35; Max.u64 = 418; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 2639; SumSQ.u64 = 520279; Count.u64 = 41; Min.u64 = 13; Max.u64 = 295; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 12621; SumSQ.u64 = 3677065; Count.u64 = 45; Min.u64 = 35; Max.u64 = 358; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 342; SumSQ.u64 = 83922; Count.u64 = 4; Min.u64 = 16; Max.u64 = 288; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1504; SumSQ.u64 = 1504; Count.u64 = 1504; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 938; SumSQ.u64 = 938; Count.u64 = 938; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 206; SumSQ.u64 = 206; Count.u64 = 206; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2487; SumSQ.u64 = 2487; Count.u64 = 2487; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_E : Accumulator : Sum.u64 = 1425; SumSQ.u64 = 1425; Count.u64 = 1425; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1446; SumSQ.u64 = 1446; Count.u64 = 1446; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1425; SumSQ.u64 = 1425; Count.u64 = 1425; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8928; SumSQ.u64 = 8928; Count.u64 = 8928; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2565; SumSQ.u64 = 2565; Count.u64 = 2565; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1625; SumSQ.u64 = 1625; Count.u64 = 1625; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1018; SumSQ.u64 = 1018; Count.u64 = 1018; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2487; SumSQ.u64 = 2487; Count.u64 = 2487; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 1038; SumSQ.u64 = 1038; Count.u64 = 1038; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1491; SumSQ.u64 = 1491; Count.u64 = 1491; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 859487; SumSQ.u64 = 5424507; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 12; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2239; SumSQ.u64 = 2239; Count.u64 = 2239; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 1091; SumSQ.u64 = 1091; Count.u64 = 1091; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1600; Count.u64 = 1600; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1600; Count.u64 = 1600; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1600; Count.u64 = 1600; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 1091; SumSQ.u64 = 1091; Count.u64 = 1091; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2735; SumSQ.u64 = 2735; Count.u64 = 2735; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 5947; SumSQ.u64 = 1434905; Count.u64 = 91; Min.u64 = 6; Max.u64 = 356; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 465644; SumSQ.u64 = 138394056; Count.u64 = 1600; Min.u64 = 35; Max.u64 = 430; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 609010; Count.u64 = 41; Min.u64 = 16; Max.u64 = 323; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 408; SumSQ.u64 = 4896; Count.u64 = 34; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 289126; SumSQ.u64 = 85590396; Count.u64 = 983; Min.u64 = 35; Max.u64 = 435; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 4286; SumSQ.u64 = 967258; Count.u64 = 47; Min.u64 = 14; Max.u64 = 311; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 24; SumSQ.u64 = 288; Count.u64 = 2; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 12347; SumSQ.u64 = 3735795; Count.u64 = 42; Min.u64 = 35; Max.u64 = 422; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1600; Count.u64 = 1600; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2625; SumSQ.u64 = 2625; Count.u64 = 2625; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_E : Accumulator : Sum.u64 = 1522; SumSQ.u64 = 1522; Count.u64 = 1522; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1549; SumSQ.u64 = 1549; Count.u64 = 1549; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1522; SumSQ.u64 = 1522; Count.u64 = 1522; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8770; SumSQ.u64 = 8770; Count.u64 = 8770; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2665; SumSQ.u64 = 2665; Count.u64 = 2665; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1732; SumSQ.u64 = 1732; Count.u64 = 1732; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 1064; SumSQ.u64 = 1064; Count.u64 = 1064; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2625; SumSQ.u64 = 2625; Count.u64 = 2625; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 1077; SumSQ.u64 = 1077; Count.u64 = 1077; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1586; SumSQ.u64 = 1586; Count.u64 = 1586; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 833015; SumSQ.u64 = 5446731; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 12; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_I : Accumulator : Sum.u64 = 2347; SumSQ.u64 = 2347; Count.u64 = 2347; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_M : Accumulator : Sum.u64 = 1052; SumSQ.u64 = 1052; Count.u64 = 1052; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1483; SumSQ.u64 = 1483; Count.u64 = 1483; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1483; SumSQ.u64 = 1483; Count.u64 = 1483; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 973; SumSQ.u64 = 973; Count.u64 = 973; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetS : Accumulator : Sum.u64 = 1483; SumSQ.u64 = 1483; Count.u64 = 1483; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetX : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSX : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 1052; SumSQ.u64 = 1052; Count.u64 = 1052; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2487; SumSQ.u64 = 2487; Count.u64 = 2487; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 399; SumSQ.u64 = 7581; Count.u64 = 21; Min.u64 = 19; Max.u64 = 19; + l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 413470; SumSQ.u64 = 115969002; Count.u64 = 1483; Min.u64 = 266; Max.u64 = 405; + l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 152; SumSQ.u64 = 2888; Count.u64 = 8; Min.u64 = 19; Max.u64 = 19; + l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 259025; SumSQ.u64 = 72573873; Count.u64 = 930; Min.u64 = 266; Max.u64 = 402; + l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 38; SumSQ.u64 = 722; Count.u64 = 2; Min.u64 = 19; Max.u64 = 19; + l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 11877; SumSQ.u64 = 3291937; Count.u64 = 43; Min.u64 = 266; Max.u64 = 341; + l3cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1483; SumSQ.u64 = 1483; Count.u64 = 1483; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 930; SumSQ.u64 = 930; Count.u64 = 930; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CacheHits : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheMisses : Accumulator : Sum.u64 = 2456; SumSQ.u64 = 2456; Count.u64 = 2456; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_E : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1417; SumSQ.u64 = 1417; Count.u64 = 1417; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutE : Accumulator : Sum.u64 = 1399; SumSQ.u64 = 1399; Count.u64 = 1399; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8009; SumSQ.u64 = 8009; Count.u64 = 8009; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2634; SumSQ.u64 = 2634; Count.u64 = 2634; Min.u64 = 1; Max.u64 = 1; + l3cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_recv : Accumulator : Sum.u64 = 1504; SumSQ.u64 = 1504; Count.u64 = 1504; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetX_recv : Accumulator : Sum.u64 = 938; SumSQ.u64 = 938; Count.u64 = 938; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 2456; SumSQ.u64 = 2456; Count.u64 = 2456; Min.u64 = 1; Max.u64 = 1; + l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.PutM_recv : Accumulator : Sum.u64 = 1057; SumSQ.u64 = 1057; Count.u64 = 1057; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutE_recv : Accumulator : Sum.u64 = 1425; SumSQ.u64 = 1425; Count.u64 = 1425; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 438; SumSQ.u64 = 438; Count.u64 = 438; Min.u64 = 1; Max.u64 = 1; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 737040; SumSQ.u64 = 4382324; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 11; + l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_I : Accumulator : Sum.u64 = 2467; SumSQ.u64 = 2467; Count.u64 = 2467; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_M : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 981; SumSQ.u64 = 981; Count.u64 = 981; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1022; SumSQ.u64 = 1022; Count.u64 = 1022; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 1018; SumSQ.u64 = 1018; Count.u64 = 1018; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetS : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetX : Accumulator : Sum.u64 = 981; SumSQ.u64 = 981; Count.u64 = 981; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSX : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2625; SumSQ.u64 = 2625; Count.u64 = 2625; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 570; SumSQ.u64 = 10830; Count.u64 = 30; Min.u64 = 19; Max.u64 = 19; + l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 439820; SumSQ.u64 = 124084850; Count.u64 = 1570; Min.u64 = 266; Max.u64 = 414; + l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 38; SumSQ.u64 = 722; Count.u64 = 2; Min.u64 = 19; Max.u64 = 19; + l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 273556; SumSQ.u64 = 76693184; Count.u64 = 981; Min.u64 = 266; Max.u64 = 419; + l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 19; SumSQ.u64 = 361; Count.u64 = 1; Min.u64 = 19; Max.u64 = 19; + l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 11666; SumSQ.u64 = 3356920; Count.u64 = 41; Min.u64 = 266; Max.u64 = 407; + l3cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 981; SumSQ.u64 = 981; Count.u64 = 981; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CacheHits : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheMisses : Accumulator : Sum.u64 = 2592; SumSQ.u64 = 2592; Count.u64 = 2592; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_E : Accumulator : Sum.u64 = 1491; SumSQ.u64 = 1491; Count.u64 = 1491; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1507; SumSQ.u64 = 1507; Count.u64 = 1507; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutE : Accumulator : Sum.u64 = 1491; SumSQ.u64 = 1491; Count.u64 = 1491; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 7976; SumSQ.u64 = 7976; Count.u64 = 7976; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2600; SumSQ.u64 = 2600; Count.u64 = 2600; Min.u64 = 1; Max.u64 = 1; + l3cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_recv : Accumulator : Sum.u64 = 1600; SumSQ.u64 = 1600; Count.u64 = 1600; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetX_recv : Accumulator : Sum.u64 = 983; SumSQ.u64 = 983; Count.u64 = 983; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 2592; SumSQ.u64 = 2592; Count.u64 = 2592; Min.u64 = 1; Max.u64 = 1; + l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.PutM_recv : Accumulator : Sum.u64 = 1091; SumSQ.u64 = 1091; Count.u64 = 1091; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutE_recv : Accumulator : Sum.u64 = 1522; SumSQ.u64 = 1522; Count.u64 = 1522; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 709780; SumSQ.u64 = 4475350; Count.u64 = 165383; Min.u64 = 0; Max.u64 = 12; + l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 55.0725 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case2_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case2_mesi.out new file mode 100644 index 0000000000..d155d7a763 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case2_mesi.out @@ -0,0 +1,1045 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1236005; SumSQ.u64 = 9863499; Count.u64 = 155077; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1279633; SumSQ.u64 = 10212661; Count.u64 = 160544; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 1833; Count.u64 = 1833; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1032; SumSQ.u64 = 1032; Count.u64 = 1032; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1097; SumSQ.u64 = 1097; Count.u64 = 1097; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1452; SumSQ.u64 = 1452; Count.u64 = 1452; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1098; SumSQ.u64 = 1098; Count.u64 = 1098; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1676; SumSQ.u64 = 1676; Count.u64 = 1676; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 12508; SumSQ.u64 = 4860050; Count.u64 = 89; Min.u64 = 3; Max.u64 = 792; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 676280; SumSQ.u64 = 362922076; Count.u64 = 1595; Min.u64 = 18; Max.u64 = 1707; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 14630; SumSQ.u64 = 4463264; Count.u64 = 82; Min.u64 = 3; Max.u64 = 633; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 474374; SumSQ.u64 = 263140630; Count.u64 = 1097; Min.u64 = 18; Max.u64 = 1666; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 74; SumSQ.u64 = 5476; Count.u64 = 1; Min.u64 = 74; Max.u64 = 74; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 308; SumSQ.u64 = 81400; Count.u64 = 5; Min.u64 = 3; Max.u64 = 285; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 23166; SumSQ.u64 = 12957394; Count.u64 = 55; Min.u64 = 43; Max.u64 = 1188; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1541; SumSQ.u64 = 1541; Count.u64 = 1541; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1056; SumSQ.u64 = 1056; Count.u64 = 1056; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2748; SumSQ.u64 = 2748; Count.u64 = 2748; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2684; SumSQ.u64 = 2684; Count.u64 = 2684; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8883; SumSQ.u64 = 8883; Count.u64 = 8883; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2104; SumSQ.u64 = 2104; Count.u64 = 2104; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1196; SumSQ.u64 = 1196; Count.u64 = 1196; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 2684; SumSQ.u64 = 2684; Count.u64 = 2684; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 864865; SumSQ.u64 = 5655999; Count.u64 = 160544; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1763; SumSQ.u64 = 1763; Count.u64 = 1763; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1610; SumSQ.u64 = 1610; Count.u64 = 1610; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1763; SumSQ.u64 = 1763; Count.u64 = 1763; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 978; SumSQ.u64 = 978; Count.u64 = 978; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 1833; Count.u64 = 1833; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1058; SumSQ.u64 = 1058; Count.u64 = 1058; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1675; SumSQ.u64 = 1675; Count.u64 = 1675; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 10551; SumSQ.u64 = 3969603; Count.u64 = 70; Min.u64 = 3; Max.u64 = 696; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 774969; SumSQ.u64 = 448876283; Count.u64 = 1763; Min.u64 = 18; Max.u64 = 1904; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 13474; SumSQ.u64 = 5183414; Count.u64 = 74; Min.u64 = 3; Max.u64 = 975; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 416979; SumSQ.u64 = 231817375; Count.u64 = 976; Min.u64 = 18; Max.u64 = 1870; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 138; SumSQ.u64 = 9620; Count.u64 = 2; Min.u64 = 62; Max.u64 = 76; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 719; SumSQ.u64 = 512665; Count.u64 = 2; Min.u64 = 3; Max.u64 = 716; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 9632; SumSQ.u64 = 5261778; Count.u64 = 24; Min.u64 = 44; Max.u64 = 1242; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1698; SumSQ.u64 = 1698; Count.u64 = 1698; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2765; SumSQ.u64 = 2765; Count.u64 = 2765; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2694; SumSQ.u64 = 2694; Count.u64 = 2694; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1541; SumSQ.u64 = 1541; Count.u64 = 1541; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1541; SumSQ.u64 = 1541; Count.u64 = 1541; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8930; SumSQ.u64 = 8930; Count.u64 = 8930; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2116; SumSQ.u64 = 2116; Count.u64 = 2116; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1833; SumSQ.u64 = 1833; Count.u64 = 1833; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1058; SumSQ.u64 = 1058; Count.u64 = 1058; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2612; SumSQ.u64 = 2612; Count.u64 = 2612; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 2694; SumSQ.u64 = 2694; Count.u64 = 2694; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 889324; SumSQ.u64 = 5801074; Count.u64 = 160544; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3063; SumSQ.u64 = 3063; Count.u64 = 3063; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1904; SumSQ.u64 = 1904; Count.u64 = 1904; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2120; SumSQ.u64 = 2120; Count.u64 = 2120; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 624115; SumSQ.u64 = 13475833; Count.u64 = 53461; Min.u64 = 0; Max.u64 = 61; + memory.latency_GetS : Accumulator : Sum.u64 = 261139; SumSQ.u64 = 22470161; Count.u64 = 3063; Min.u64 = 81; Max.u64 = 128; + memory.latency_GetSX : Accumulator : Sum.u64 = 5953; SumSQ.u64 = 510917; Count.u64 = 70; Min.u64 = 81; Max.u64 = 120; + memory.latency_GetX : Accumulator : Sum.u64 = 162238; SumSQ.u64 = 13955018; Count.u64 = 1904; Min.u64 = 81; Max.u64 = 126; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 194785; SumSQ.u64 = 18116017; Count.u64 = 2120; Min.u64 = 81; Max.u64 = 128; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7157; SumSQ.u64 = 7157; Count.u64 = 7157; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 53461; SumSQ.u64 = 2858078521; Count.u64 = 1; Min.u64 = 53461; Max.u64 = 53461; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2207; SumSQ.u64 = 2207; Count.u64 = 2207; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_S : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_M : Accumulator : Sum.u64 = 1056; SumSQ.u64 = 1056; Count.u64 = 1056; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1552; SumSQ.u64 = 1552; Count.u64 = 1552; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1072; SumSQ.u64 = 1072; Count.u64 = 1072; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2536; SumSQ.u64 = 2536; Count.u64 = 2536; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_I : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_I : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1552; SumSQ.u64 = 1552; Count.u64 = 1552; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1074; SumSQ.u64 = 1074; Count.u64 = 1074; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 1056; SumSQ.u64 = 1056; Count.u64 = 1056; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2605; SumSQ.u64 = 2605; Count.u64 = 2605; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 2684; SumSQ.u64 = 2684; Count.u64 = 2684; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 516; SumSQ.u64 = 6192; Count.u64 = 43; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 444697; SumSQ.u64 = 134669889; Count.u64 = 1552; Min.u64 = 27; Max.u64 = 924; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 288; SumSQ.u64 = 3456; Count.u64 = 24; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 305292; SumSQ.u64 = 91670074; Count.u64 = 1072; Min.u64 = 34; Max.u64 = 837; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 107; SumSQ.u64 = 5725; Count.u64 = 2; Min.u64 = 53; Max.u64 = 54; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 14894; SumSQ.u64 = 4463720; Count.u64 = 53; Min.u64 = 35; Max.u64 = 422; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 68; SumSQ.u64 = 4624; Count.u64 = 1; Min.u64 = 68; Max.u64 = 68; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1540; SumSQ.u64 = 1540; Count.u64 = 1540; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2680; SumSQ.u64 = 2680; Count.u64 = 2680; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2569; SumSQ.u64 = 2569; Count.u64 = 2569; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 1328; SumSQ.u64 = 1328; Count.u64 = 1328; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_I : Accumulator : Sum.u64 = 1386; SumSQ.u64 = 1386; Count.u64 = 1386; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1328; SumSQ.u64 = 1328; Count.u64 = 1328; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 11520; SumSQ.u64 = 11520; Count.u64 = 11520; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2479; SumSQ.u64 = 2479; Count.u64 = 2479; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1098; SumSQ.u64 = 1098; Count.u64 = 1098; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2539; SumSQ.u64 = 2539; Count.u64 = 2539; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 2569; SumSQ.u64 = 2569; Count.u64 = 2569; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 834952; SumSQ.u64 = 5344456; Count.u64 = 160544; Min.u64 = 0; Max.u64 = 9; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2195; SumSQ.u64 = 2195; Count.u64 = 2195; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_S : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_M : Accumulator : Sum.u64 = 934; SumSQ.u64 = 934; Count.u64 = 934; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1731; SumSQ.u64 = 1731; Count.u64 = 1731; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2569; SumSQ.u64 = 2569; Count.u64 = 2569; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_I : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_I : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1731; SumSQ.u64 = 1731; Count.u64 = 1731; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 965; SumSQ.u64 = 965; Count.u64 = 965; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 934; SumSQ.u64 = 934; Count.u64 = 934; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2612; SumSQ.u64 = 2612; Count.u64 = 2612; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 2694; SumSQ.u64 = 2694; Count.u64 = 2694; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 384; SumSQ.u64 = 4608; Count.u64 = 32; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 498329; SumSQ.u64 = 152451125; Count.u64 = 1731; Min.u64 = 31; Max.u64 = 916; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 156; SumSQ.u64 = 1872; Count.u64 = 13; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 275711; SumSQ.u64 = 82789081; Count.u64 = 965; Min.u64 = 34; Max.u64 = 827; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 6224; SumSQ.u64 = 1793470; Count.u64 = 23; Min.u64 = 35; Max.u64 = 333; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1718; SumSQ.u64 = 1718; Count.u64 = 1718; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 958; SumSQ.u64 = 958; Count.u64 = 958; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2719; SumSQ.u64 = 2719; Count.u64 = 2719; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2587; SumSQ.u64 = 2587; Count.u64 = 2587; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 1465; SumSQ.u64 = 1465; Count.u64 = 1465; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_I : Accumulator : Sum.u64 = 1523; SumSQ.u64 = 1523; Count.u64 = 1523; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1465; SumSQ.u64 = 1465; Count.u64 = 1465; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11646; SumSQ.u64 = 11646; Count.u64 = 11646; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2450; SumSQ.u64 = 2450; Count.u64 = 2450; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1763; SumSQ.u64 = 1763; Count.u64 = 1763; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 978; SumSQ.u64 = 978; Count.u64 = 978; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2569; SumSQ.u64 = 2569; Count.u64 = 2569; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 164; SumSQ.u64 = 164; Count.u64 = 164; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1541; SumSQ.u64 = 1541; Count.u64 = 1541; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 2587; SumSQ.u64 = 2587; Count.u64 = 2587; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 858432; SumSQ.u64 = 5468816; Count.u64 = 160544; Min.u64 = 0; Max.u64 = 9; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 4891; SumSQ.u64 = 4891; Count.u64 = 4891; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IM : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 2159; SumSQ.u64 = 2159; Count.u64 = 2159; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3063; SumSQ.u64 = 3063; Count.u64 = 3063; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1904; SumSQ.u64 = 1904; Count.u64 = 1904; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3063; SumSQ.u64 = 3063; Count.u64 = 3063; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1974; SumSQ.u64 = 1974; Count.u64 = 1974; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1847; SumSQ.u64 = 1847; Count.u64 = 1847; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 3063; SumSQ.u64 = 3063; Count.u64 = 3063; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 1904; SumSQ.u64 = 1904; Count.u64 = 1904; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2120; SumSQ.u64 = 2120; Count.u64 = 2120; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 5156; SumSQ.u64 = 5156; Count.u64 = 5156; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5108; SumSQ.u64 = 5108; Count.u64 = 5108; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 9203; SumSQ.u64 = 2597385; Count.u64 = 61; Min.u64 = 11; Max.u64 = 535; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 869810; SumSQ.u64 = 252906682; Count.u64 = 3063; Min.u64 = 265; Max.u64 = 908; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 10065; SumSQ.u64 = 1413757; Count.u64 = 159; Min.u64 = 24; Max.u64 = 501; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 133; SumSQ.u64 = 2527; Count.u64 = 7; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 536941; SumSQ.u64 = 153984525; Count.u64 = 1904; Min.u64 = 265; Max.u64 = 821; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 10627; SumSQ.u64 = 1888461; Count.u64 = 128; Min.u64 = 38; Max.u64 = 402; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 38; SumSQ.u64 = 722; Count.u64 = 2; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 19650; SumSQ.u64 = 5574818; Count.u64 = 70; Min.u64 = 265; Max.u64 = 407; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 243; SumSQ.u64 = 12091; Count.u64 = 5; Min.u64 = 39; Max.u64 = 56; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 2998; SumSQ.u64 = 2998; Count.u64 = 2998; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1875; SumSQ.u64 = 1875; Count.u64 = 1875; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheHits : Accumulator : Sum.u64 = 362; SumSQ.u64 = 362; Count.u64 = 362; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 5037; SumSQ.u64 = 5037; Count.u64 = 5037; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_E : Accumulator : Sum.u64 = 2954; SumSQ.u64 = 2954; Count.u64 = 2954; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 218; SumSQ.u64 = 218; Count.u64 = 218; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 2763; SumSQ.u64 = 2763; Count.u64 = 2763; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 2902; SumSQ.u64 = 2902; Count.u64 = 2902; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 16396; SumSQ.u64 = 16396; Count.u64 = 16396; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 5756; SumSQ.u64 = 5756; Count.u64 = 5756; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 3283; SumSQ.u64 = 3283; Count.u64 = 3283; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 2039; SumSQ.u64 = 2039; Count.u64 = 2039; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 5037; SumSQ.u64 = 5037; Count.u64 = 5037; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l3cache.PutM_recv : Accumulator : Sum.u64 = 1990; SumSQ.u64 = 1990; Count.u64 = 1990; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 2793; SumSQ.u64 = 2793; Count.u64 = 2793; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 286; SumSQ.u64 = 286; Count.u64 = 286; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1490332; SumSQ.u64 = 17432428; Count.u64 = 160544; Min.u64 = 0; Max.u64 = 14; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 53.4612 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case3_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case3_mesi.out new file mode 100644 index 0000000000..2d9be95adc --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case3_mesi.out @@ -0,0 +1,865 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1459432; SumSQ.u64 = 11649974; Count.u64 = 183104; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1114; SumSQ.u64 = 1114; Count.u64 = 1114; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1582524; SumSQ.u64 = 12635682; Count.u64 = 198406; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1845; SumSQ.u64 = 1845; Count.u64 = 1845; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 998; SumSQ.u64 = 998; Count.u64 = 998; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1666; SumSQ.u64 = 1666; Count.u64 = 1666; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1224; SumSQ.u64 = 1224; Count.u64 = 1224; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1131; SumSQ.u64 = 1131; Count.u64 = 1131; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1666; SumSQ.u64 = 1666; Count.u64 = 1666; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2276; SumSQ.u64 = 2276; Count.u64 = 2276; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 695; SumSQ.u64 = 695; Count.u64 = 695; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 11117; SumSQ.u64 = 6237661; Count.u64 = 57; Min.u64 = 3; Max.u64 = 1237; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 821802; SumSQ.u64 = 524083216; Count.u64 = 1666; Min.u64 = 19; Max.u64 = 2104; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 16097; SumSQ.u64 = 6280299; Count.u64 = 66; Min.u64 = 3; Max.u64 = 934; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 537071; SumSQ.u64 = 348778683; Count.u64 = 1083; Min.u64 = 22; Max.u64 = 1828; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 2700; SumSQ.u64 = 2459334; Count.u64 = 4; Min.u64 = 350; Max.u64 = 1337; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 307907; Count.u64 = 5; Min.u64 = 6; Max.u64 = 305; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 21216; SumSQ.u64 = 12426082; Count.u64 = 45; Min.u64 = 65; Max.u64 = 1300; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1599; SumSQ.u64 = 1599; Count.u64 = 1599; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2798; SumSQ.u64 = 2798; Count.u64 = 2798; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1775; SumSQ.u64 = 1775; Count.u64 = 1775; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 961; SumSQ.u64 = 961; Count.u64 = 961; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 961; SumSQ.u64 = 961; Count.u64 = 961; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 9161; SumSQ.u64 = 9161; Count.u64 = 9161; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1774; SumSQ.u64 = 1774; Count.u64 = 1774; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1723; SumSQ.u64 = 1723; Count.u64 = 1723; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2356; SumSQ.u64 = 2356; Count.u64 = 2356; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 419; SumSQ.u64 = 419; Count.u64 = 419; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 729; SumSQ.u64 = 729; Count.u64 = 729; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 1775; SumSQ.u64 = 1775; Count.u64 = 1775; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1007310; SumSQ.u64 = 6497318; Count.u64 = 198406; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1792; SumSQ.u64 = 1792; Count.u64 = 1792; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 974; SumSQ.u64 = 974; Count.u64 = 974; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1338; SumSQ.u64 = 1338; Count.u64 = 1338; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1009; SumSQ.u64 = 1009; Count.u64 = 1009; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1792; SumSQ.u64 = 1792; Count.u64 = 1792; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 356; SumSQ.u64 = 356; Count.u64 = 356; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1845; SumSQ.u64 = 1845; Count.u64 = 1845; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2246; SumSQ.u64 = 2246; Count.u64 = 2246; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 9967; SumSQ.u64 = 8519261; Count.u64 = 53; Min.u64 = 3; Max.u64 = 1624; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 947934; SumSQ.u64 = 701114690; Count.u64 = 1792; Min.u64 = 19; Max.u64 = 2257; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 13417; SumSQ.u64 = 7134277; Count.u64 = 47; Min.u64 = 3; Max.u64 = 1263; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 522057; SumSQ.u64 = 393370613; Count.u64 = 974; Min.u64 = 18; Max.u64 = 2251; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 134; SumSQ.u64 = 11026; Count.u64 = 2; Min.u64 = 35; Max.u64 = 99; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 16865; SumSQ.u64 = 11125807; Count.u64 = 33; Min.u64 = 41; Max.u64 = 1193; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1717; SumSQ.u64 = 1717; Count.u64 = 1717; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 931; SumSQ.u64 = 931; Count.u64 = 931; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2801; SumSQ.u64 = 2801; Count.u64 = 2801; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1830; SumSQ.u64 = 1830; Count.u64 = 1830; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1052; SumSQ.u64 = 1052; Count.u64 = 1052; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1052; SumSQ.u64 = 1052; Count.u64 = 1052; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 9146; SumSQ.u64 = 9146; Count.u64 = 9146; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1783; SumSQ.u64 = 1783; Count.u64 = 1783; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1845; SumSQ.u64 = 1845; Count.u64 = 1845; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2347; SumSQ.u64 = 2347; Count.u64 = 2347; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 1830; SumSQ.u64 = 1830; Count.u64 = 1830; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1086577; SumSQ.u64 = 6983251; Count.u64 = 198406; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3102; SumSQ.u64 = 3102; Count.u64 = 3102; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 601267; SumSQ.u64 = 10598729; Count.u64 = 66069; Min.u64 = 0; Max.u64 = 54; + memory.latency_GetS : Accumulator : Sum.u64 = 260742; SumSQ.u64 = 22048884; Count.u64 = 3102; Min.u64 = 81; Max.u64 = 123; + memory.latency_GetSX : Accumulator : Sum.u64 = 5977; SumSQ.u64 = 506303; Count.u64 = 71; Min.u64 = 81; Max.u64 = 109; + memory.latency_GetX : Accumulator : Sum.u64 = 155950; SumSQ.u64 = 13197742; Count.u64 = 1854; Min.u64 = 81; Max.u64 = 122; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 178598; SumSQ.u64 = 16296248; Count.u64 = 1976; Min.u64 = 81; Max.u64 = 121; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7003; SumSQ.u64 = 7003; Count.u64 = 7003; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 66069; SumSQ.u64 = 4365112761; Count.u64 = 1; Min.u64 = 66069; Max.u64 = 66069; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 5429; SumSQ.u64 = 5429; Count.u64 = 5429; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IS : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IM : Accumulator : Sum.u64 = 486; SumSQ.u64 = 486; Count.u64 = 486; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 1747; SumSQ.u64 = 1747; Count.u64 = 1747; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3341; SumSQ.u64 = 3341; Count.u64 = 3341; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3341; SumSQ.u64 = 3341; Count.u64 = 3341; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2069; SumSQ.u64 = 2069; Count.u64 = 2069; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1244; SumSQ.u64 = 1244; Count.u64 = 1244; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 3341; SumSQ.u64 = 3341; Count.u64 = 3341; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 2126; SumSQ.u64 = 2126; Count.u64 = 2126; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 4703; SumSQ.u64 = 4703; Count.u64 = 4703; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1407; SumSQ.u64 = 1407; Count.u64 = 1407; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 3605; SumSQ.u64 = 3605; Count.u64 = 3605; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 14308; SumSQ.u64 = 4391304; Count.u64 = 117; Min.u64 = 12; Max.u64 = 609; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 1110937; SumSQ.u64 = 435125015; Count.u64 = 3341; Min.u64 = 34; Max.u64 = 1180; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 6492; SumSQ.u64 = 1690728; Count.u64 = 71; Min.u64 = 12; Max.u64 = 577; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 649983; SumSQ.u64 = 247783577; Count.u64 = 1992; Min.u64 = 34; Max.u64 = 1238; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 293; SumSQ.u64 = 85849; Count.u64 = 1; Min.u64 = 293; Max.u64 = 293; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 24658; SumSQ.u64 = 9090906; Count.u64 = 77; Min.u64 = 34; Max.u64 = 851; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 2029; SumSQ.u64 = 2029; Count.u64 = 2029; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1245; SumSQ.u64 = 1245; Count.u64 = 1245; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheHits : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 5410; SumSQ.u64 = 5410; Count.u64 = 5410; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_E : Accumulator : Sum.u64 = 2734; SumSQ.u64 = 2734; Count.u64 = 2734; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_ED : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 1958; SumSQ.u64 = 1958; Count.u64 = 1958; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 487; SumSQ.u64 = 487; Count.u64 = 487; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 690; SumSQ.u64 = 690; Count.u64 = 690; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 3270; SumSQ.u64 = 3270; Count.u64 = 3270; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 17617; SumSQ.u64 = 17617; Count.u64 = 17617; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 7309; SumSQ.u64 = 7309; Count.u64 = 7309; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 3458; SumSQ.u64 = 3458; Count.u64 = 3458; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 2063; SumSQ.u64 = 2063; Count.u64 = 2063; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 5410; SumSQ.u64 = 5410; Count.u64 = 5410; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.PutS_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; + l2cache.PutM_recv : Accumulator : Sum.u64 = 1369; SumSQ.u64 = 1369; Count.u64 = 1369; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 2013; SumSQ.u64 = 2013; Count.u64 = 2013; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 1301; SumSQ.u64 = 1301; Count.u64 = 1301; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 308; SumSQ.u64 = 308; Count.u64 = 308; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 1962149; SumSQ.u64 = 22970743; Count.u64 = 198406; Min.u64 = 0; Max.u64 = 15; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 4815; SumSQ.u64 = 4815; Count.u64 = 4815; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3102; SumSQ.u64 = 3102; Count.u64 = 3102; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3102; SumSQ.u64 = 3102; Count.u64 = 3102; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1925; SumSQ.u64 = 1925; Count.u64 = 1925; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1986; SumSQ.u64 = 1986; Count.u64 = 1986; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 3102; SumSQ.u64 = 3102; Count.u64 = 3102; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5410; SumSQ.u64 = 5410; Count.u64 = 5410; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 4544; SumSQ.u64 = 86396; Count.u64 = 239; Min.u64 = 19; Max.u64 = 20; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 856125; SumSQ.u64 = 237474095; Count.u64 = 3102; Min.u64 = 265; Max.u64 = 392; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 2623; SumSQ.u64 = 49857; Count.u64 = 138; Min.u64 = 19; Max.u64 = 20; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 512011; SumSQ.u64 = 142122317; Count.u64 = 1854; Min.u64 = 265; Max.u64 = 390; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 115; SumSQ.u64 = 2205; Count.u64 = 6; Min.u64 = 19; Max.u64 = 20; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 19615; SumSQ.u64 = 5447397; Count.u64 = 71; Min.u64 = 265; Max.u64 = 351; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 3102; SumSQ.u64 = 3102; Count.u64 = 3102; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CacheHits : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 5027; SumSQ.u64 = 5027; Count.u64 = 5027; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_E : Accumulator : Sum.u64 = 3030; SumSQ.u64 = 3030; Count.u64 = 3030; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 3173; SumSQ.u64 = 3173; Count.u64 = 3173; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 3030; SumSQ.u64 = 3030; Count.u64 = 3030; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 16141; SumSQ.u64 = 16141; Count.u64 = 16141; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 5099; SumSQ.u64 = 5099; Count.u64 = 5099; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 3341; SumSQ.u64 = 3341; Count.u64 = 3341; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 5027; SumSQ.u64 = 5027; Count.u64 = 5027; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutM_recv : Accumulator : Sum.u64 = 2126; SumSQ.u64 = 2126; Count.u64 = 2126; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 3270; SumSQ.u64 = 3270; Count.u64 = 3270; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1442341; SumSQ.u64 = 13333701; Count.u64 = 198406; Min.u64 = 0; Max.u64 = 14; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 66.0692 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case4_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case4_mesi.out new file mode 100644 index 0000000000..67d1083ce9 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case4_mesi.out @@ -0,0 +1,825 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1131013; SumSQ.u64 = 9024805; Count.u64 = 141992; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1239402; SumSQ.u64 = 9890846; Count.u64 = 155386; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1861; SumSQ.u64 = 1861; Count.u64 = 1861; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1017; SumSQ.u64 = 1017; Count.u64 = 1017; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1636; SumSQ.u64 = 1636; Count.u64 = 1636; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1564; SumSQ.u64 = 1564; Count.u64 = 1564; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1143; SumSQ.u64 = 1143; Count.u64 = 1143; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1636; SumSQ.u64 = 1636; Count.u64 = 1636; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1091; SumSQ.u64 = 1091; Count.u64 = 1091; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 1121; SumSQ.u64 = 1121; Count.u64 = 1121; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1194; SumSQ.u64 = 1194; Count.u64 = 1194; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1519; SumSQ.u64 = 1519; Count.u64 = 1519; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 1121; SumSQ.u64 = 1121; Count.u64 = 1121; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 7028; SumSQ.u64 = 2074344; Count.u64 = 69; Min.u64 = 3; Max.u64 = 624; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 645423; SumSQ.u64 = 331889221; Count.u64 = 1636; Min.u64 = 19; Max.u64 = 1906; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 16888; SumSQ.u64 = 5866078; Count.u64 = 91; Min.u64 = 3; Max.u64 = 1008; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 416819; SumSQ.u64 = 201444137; Count.u64 = 1089; Min.u64 = 19; Max.u64 = 1290; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 402; SumSQ.u64 = 136580; Count.u64 = 2; Min.u64 = 34; Max.u64 = 368; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 19120; SumSQ.u64 = 8803728; Count.u64 = 53; Min.u64 = 20; Max.u64 = 976; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1590; SumSQ.u64 = 1590; Count.u64 = 1590; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1056; SumSQ.u64 = 1056; Count.u64 = 1056; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2780; SumSQ.u64 = 2780; Count.u64 = 2780; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1517; SumSQ.u64 = 1517; Count.u64 = 1517; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1517; SumSQ.u64 = 1517; Count.u64 = 1517; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6178; SumSQ.u64 = 6178; Count.u64 = 6178; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1922; SumSQ.u64 = 1922; Count.u64 = 1922; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1705; SumSQ.u64 = 1705; Count.u64 = 1705; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1194; SumSQ.u64 = 1194; Count.u64 = 1194; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2708; SumSQ.u64 = 2708; Count.u64 = 2708; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 824442; SumSQ.u64 = 5444798; Count.u64 = 155386; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1783; SumSQ.u64 = 1783; Count.u64 = 1783; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 966; SumSQ.u64 = 966; Count.u64 = 966; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1689; SumSQ.u64 = 1689; Count.u64 = 1689; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 985; SumSQ.u64 = 985; Count.u64 = 985; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1783; SumSQ.u64 = 1783; Count.u64 = 1783; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1861; SumSQ.u64 = 1861; Count.u64 = 1861; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1532; SumSQ.u64 = 1532; Count.u64 = 1532; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 7500; SumSQ.u64 = 4271568; Count.u64 = 78; Min.u64 = 3; Max.u64 = 1459; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 752833; SumSQ.u64 = 442842373; Count.u64 = 1783; Min.u64 = 18; Max.u64 = 2017; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 9887; SumSQ.u64 = 3325201; Count.u64 = 62; Min.u64 = 3; Max.u64 = 626; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 404396; SumSQ.u64 = 235251112; Count.u64 = 966; Min.u64 = 19; Max.u64 = 1948; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 349; SumSQ.u64 = 87953; Count.u64 = 3; Min.u64 = 26; Max.u64 = 294; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 8743; SumSQ.u64 = 6296781; Count.u64 = 19; Min.u64 = 19; Max.u64 = 1266; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1722; SumSQ.u64 = 1722; Count.u64 = 1722; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 928; SumSQ.u64 = 928; Count.u64 = 928; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1629; SumSQ.u64 = 1629; Count.u64 = 1629; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1629; SumSQ.u64 = 1629; Count.u64 = 1629; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6204; SumSQ.u64 = 6204; Count.u64 = 6204; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1902; SumSQ.u64 = 1902; Count.u64 = 1902; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1861; SumSQ.u64 = 1861; Count.u64 = 1861; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2677; SumSQ.u64 = 2677; Count.u64 = 2677; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 853734; SumSQ.u64 = 5569734; Count.u64 = 155386; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3055; SumSQ.u64 = 3055; Count.u64 = 3055; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1849; SumSQ.u64 = 1849; Count.u64 = 1849; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2086; SumSQ.u64 = 2086; Count.u64 = 2086; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 615017; SumSQ.u64 = 13583547; Count.u64 = 51743; Min.u64 = 0; Max.u64 = 71; + memory.latency_GetS : Accumulator : Sum.u64 = 259726; SumSQ.u64 = 22300956; Count.u64 = 3055; Min.u64 = 81; Max.u64 = 139; + memory.latency_GetSX : Accumulator : Sum.u64 = 5362; SumSQ.u64 = 460980; Count.u64 = 63; Min.u64 = 81; Max.u64 = 121; + memory.latency_GetX : Accumulator : Sum.u64 = 156476; SumSQ.u64 = 13360520; Count.u64 = 1849; Min.u64 = 81; Max.u64 = 136; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 193453; SumSQ.u64 = 18198551; Count.u64 = 2086; Min.u64 = 81; Max.u64 = 136; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7053; SumSQ.u64 = 7053; Count.u64 = 7053; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 51743; SumSQ.u64 = 2677338049; Count.u64 = 1; Min.u64 = 51743; Max.u64 = 51743; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 4053; SumSQ.u64 = 4053; Count.u64 = 4053; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 2139; SumSQ.u64 = 2139; Count.u64 = 2139; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 3133; Count.u64 = 3133; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 3133; Count.u64 = 3133; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1953; SumSQ.u64 = 1953; Count.u64 = 1953; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1928; SumSQ.u64 = 1928; Count.u64 = 1928; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 3133; Count.u64 = 3133; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 2139; SumSQ.u64 = 2139; Count.u64 = 2139; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5385; SumSQ.u64 = 5385; Count.u64 = 5385; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 5162; SumSQ.u64 = 874734; Count.u64 = 195; Min.u64 = 12; Max.u64 = 365; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 900833; SumSQ.u64 = 266049233; Count.u64 = 3133; Min.u64 = 34; Max.u64 = 456; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 5583; SumSQ.u64 = 1199887; Count.u64 = 91; Min.u64 = 13; Max.u64 = 433; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 1008; SumSQ.u64 = 12096; Count.u64 = 84; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 542780; SumSQ.u64 = 159608012; Count.u64 = 1889; Min.u64 = 34; Max.u64 = 448; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 8105; SumSQ.u64 = 1894127; Count.u64 = 87; Min.u64 = 14; Max.u64 = 326; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 60; SumSQ.u64 = 720; Count.u64 = 5; Min.u64 = 12; Max.u64 = 12; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 18571; SumSQ.u64 = 5496907; Count.u64 = 64; Min.u64 = 34; Max.u64 = 401; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 2606; Count.u64 = 3; Min.u64 = 14; Max.u64 = 41; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 3109; SumSQ.u64 = 3109; Count.u64 = 3109; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1880; SumSQ.u64 = 1880; Count.u64 = 1880; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CacheHits : Accumulator : Sum.u64 = 465; SumSQ.u64 = 465; Count.u64 = 465; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 5086; SumSQ.u64 = 5086; Count.u64 = 5086; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 5060; SumSQ.u64 = 5060; Count.u64 = 5060; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_E : Accumulator : Sum.u64 = 2921; SumSQ.u64 = 2921; Count.u64 = 2921; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 3017; SumSQ.u64 = 3017; Count.u64 = 3017; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 2921; SumSQ.u64 = 2921; Count.u64 = 2921; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 22093; SumSQ.u64 = 22093; Count.u64 = 22093; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 4606; SumSQ.u64 = 4606; Count.u64 = 4606; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 3419; SumSQ.u64 = 3419; Count.u64 = 3419; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 2060; SumSQ.u64 = 2060; Count.u64 = 2060; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 5086; SumSQ.u64 = 5086; Count.u64 = 5086; Min.u64 = 1; Max.u64 = 1; + l2cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.PutS_recv : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; + l2cache.PutM_recv : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 2093; Count.u64 = 2093; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 3146; SumSQ.u64 = 3146; Count.u64 = 3146; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 5060; SumSQ.u64 = 5060; Count.u64 = 5060; Min.u64 = 1; Max.u64 = 1; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 1581547; SumSQ.u64 = 18848779; Count.u64 = 155386; Min.u64 = 0; Max.u64 = 15; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 3598; SumSQ.u64 = 3598; Count.u64 = 3598; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 2086; SumSQ.u64 = 2086; Count.u64 = 2086; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3055; SumSQ.u64 = 3055; Count.u64 = 3055; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1849; SumSQ.u64 = 1849; Count.u64 = 1849; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 4967; SumSQ.u64 = 4967; Count.u64 = 4967; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_I : Accumulator : Sum.u64 = 2062; SumSQ.u64 = 2062; Count.u64 = 2062; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 3055; SumSQ.u64 = 3055; Count.u64 = 3055; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 1849; SumSQ.u64 = 1849; Count.u64 = 1849; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2086; SumSQ.u64 = 2086; Count.u64 = 2086; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5086; SumSQ.u64 = 5086; Count.u64 = 5086; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 5060; SumSQ.u64 = 5060; Count.u64 = 5060; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 1482; SumSQ.u64 = 28158; Count.u64 = 78; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 852137; SumSQ.u64 = 239671341; Count.u64 = 3055; Min.u64 = 265; Max.u64 = 441; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 760; SumSQ.u64 = 14440; Count.u64 = 40; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 513584; SumSQ.u64 = 143722348; Count.u64 = 1849; Min.u64 = 265; Max.u64 = 433; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 19; SumSQ.u64 = 361; Count.u64 = 1; Min.u64 = 19; Max.u64 = 19; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 17592; SumSQ.u64 = 4953816; Count.u64 = 63; Min.u64 = 265; Max.u64 = 386; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 3055; SumSQ.u64 = 3055; Count.u64 = 3055; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1849; SumSQ.u64 = 1849; Count.u64 = 1849; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CacheHits : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 4967; SumSQ.u64 = 4967; Count.u64 = 4967; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_E : Accumulator : Sum.u64 = 2855; SumSQ.u64 = 2855; Count.u64 = 2855; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_I : Accumulator : Sum.u64 = 2879; SumSQ.u64 = 2879; Count.u64 = 2879; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 2855; SumSQ.u64 = 2855; Count.u64 = 2855; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 15373; SumSQ.u64 = 15373; Count.u64 = 15373; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 3857; SumSQ.u64 = 3857; Count.u64 = 3857; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 3133; SumSQ.u64 = 3133; Count.u64 = 3133; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 1889; SumSQ.u64 = 1889; Count.u64 = 1889; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 4967; SumSQ.u64 = 4967; Count.u64 = 4967; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutM_recv : Accumulator : Sum.u64 = 2139; SumSQ.u64 = 2139; Count.u64 = 2139; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 2921; SumSQ.u64 = 2921; Count.u64 = 2921; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1412042; SumSQ.u64 = 16144450; Count.u64 = 155386; Min.u64 = 0; Max.u64 = 14; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 51.7435 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case5_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case5_mesi.out new file mode 100644 index 0000000000..046c1c78d2 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case5_mesi.out @@ -0,0 +1,1371 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. +l3cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1374260; SumSQ.u64 = 10968510; Count.u64 = 172261; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1734; SumSQ.u64 = 1734; Count.u64 = 1734; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1086; SumSQ.u64 = 1086; Count.u64 = 1086; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1398984; SumSQ.u64 = 11167158; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1021; SumSQ.u64 = 1021; Count.u64 = 1021; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1659; SumSQ.u64 = 1659; Count.u64 = 1659; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1422; SumSQ.u64 = 1422; Count.u64 = 1422; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1107; SumSQ.u64 = 1107; Count.u64 = 1107; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1659; SumSQ.u64 = 1659; Count.u64 = 1659; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1734; SumSQ.u64 = 1734; Count.u64 = 1734; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1148; SumSQ.u64 = 1148; Count.u64 = 1148; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1901; SumSQ.u64 = 1901; Count.u64 = 1901; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 9955; SumSQ.u64 = 4125135; Count.u64 = 75; Min.u64 = 3; Max.u64 = 708; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 782041; SumSQ.u64 = 455966647; Count.u64 = 1659; Min.u64 = 18; Max.u64 = 1679; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 18744; SumSQ.u64 = 9749982; Count.u64 = 75; Min.u64 = 3; Max.u64 = 1662; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 488388; SumSQ.u64 = 287142672; Count.u64 = 1047; Min.u64 = 21; Max.u64 = 1627; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 348; SumSQ.u64 = 33410; Count.u64 = 4; Min.u64 = 59; Max.u64 = 133; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 32422; SumSQ.u64 = 21959286; Count.u64 = 60; Min.u64 = 88; Max.u64 = 1420; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 87; SumSQ.u64 = 7569; Count.u64 = 1; Min.u64 = 87; Max.u64 = 87; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1006; SumSQ.u64 = 1006; Count.u64 = 1006; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1253; SumSQ.u64 = 1253; Count.u64 = 1253; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1253; SumSQ.u64 = 1253; Count.u64 = 1253; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6638; SumSQ.u64 = 6638; Count.u64 = 6638; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1936; SumSQ.u64 = 1936; Count.u64 = 1936; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1734; SumSQ.u64 = 1734; Count.u64 = 1734; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1148; SumSQ.u64 = 1148; Count.u64 = 1148; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2534; SumSQ.u64 = 2534; Count.u64 = 2534; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 957983; SumSQ.u64 = 6256879; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1762; SumSQ.u64 = 1762; Count.u64 = 1762; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1504; SumSQ.u64 = 1504; Count.u64 = 1504; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1009; SumSQ.u64 = 1009; Count.u64 = 1009; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1762; SumSQ.u64 = 1762; Count.u64 = 1762; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 979; SumSQ.u64 = 979; Count.u64 = 979; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 790; SumSQ.u64 = 790; Count.u64 = 790; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1053; SumSQ.u64 = 1053; Count.u64 = 1053; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1955; SumSQ.u64 = 1955; Count.u64 = 1955; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 790; SumSQ.u64 = 790; Count.u64 = 790; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 99; SumSQ.u64 = 99; Count.u64 = 99; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 12148; SumSQ.u64 = 5404374; Count.u64 = 69; Min.u64 = 3; Max.u64 = 1063; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 833751; SumSQ.u64 = 501176651; Count.u64 = 1762; Min.u64 = 18; Max.u64 = 1972; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 14078; SumSQ.u64 = 6559902; Count.u64 = 60; Min.u64 = 3; Max.u64 = 1001; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 463649; SumSQ.u64 = 280452803; Count.u64 = 976; Min.u64 = 18; Max.u64 = 1747; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 882; SumSQ.u64 = 492386; Count.u64 = 3; Min.u64 = 71; Max.u64 = 687; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 16775; SumSQ.u64 = 10148159; Count.u64 = 32; Min.u64 = 289; Max.u64 = 1008; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1683; SumSQ.u64 = 1683; Count.u64 = 1683; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 937; SumSQ.u64 = 937; Count.u64 = 937; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2773; SumSQ.u64 = 2773; Count.u64 = 2773; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6719; SumSQ.u64 = 6719; Count.u64 = 6719; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1928; SumSQ.u64 = 1928; Count.u64 = 1928; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1053; SumSQ.u64 = 1053; Count.u64 = 1053; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2515; SumSQ.u64 = 2515; Count.u64 = 2515; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 981049; SumSQ.u64 = 6365021; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3209; SumSQ.u64 = 3209; Count.u64 = 3209; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1894; SumSQ.u64 = 1894; Count.u64 = 1894; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2084; SumSQ.u64 = 2084; Count.u64 = 2084; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 600256; SumSQ.u64 = 8704652; Count.u64 = 58395; Min.u64 = 0; Max.u64 = 38; + memory.latency_GetS : Accumulator : Sum.u64 = 264900; SumSQ.u64 = 21888218; Count.u64 = 3209; Min.u64 = 81; Max.u64 = 92; + memory.latency_GetSX : Accumulator : Sum.u64 = 7212; SumSQ.u64 = 598556; Count.u64 = 87; Min.u64 = 81; Max.u64 = 91; + memory.latency_GetX : Accumulator : Sum.u64 = 156234; SumSQ.u64 = 12899394; Count.u64 = 1894; Min.u64 = 81; Max.u64 = 92; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 171910; SumSQ.u64 = 14189190; Count.u64 = 2084; Min.u64 = 81; Max.u64 = 92; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7274; SumSQ.u64 = 7274; Count.u64 = 7274; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 58395; SumSQ.u64 = 3409976025; Count.u64 = 1; Min.u64 = 58395; Max.u64 = 58395; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2531; SumSQ.u64 = 2531; Count.u64 = 2531; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1642; SumSQ.u64 = 1642; Count.u64 = 1642; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1406; SumSQ.u64 = 1406; Count.u64 = 1406; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1094; SumSQ.u64 = 1094; Count.u64 = 1094; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 319; SumSQ.u64 = 319; Count.u64 = 319; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1642; SumSQ.u64 = 1642; Count.u64 = 1642; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 644; SumSQ.u64 = 644; Count.u64 = 644; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2534; SumSQ.u64 = 2534; Count.u64 = 2534; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 204; SumSQ.u64 = 2448; Count.u64 = 17; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 505818; SumSQ.u64 = 168395436; Count.u64 = 1642; Min.u64 = 34; Max.u64 = 914; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 120; SumSQ.u64 = 1440; Count.u64 = 10; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 321054; SumSQ.u64 = 109449886; Count.u64 = 1034; Min.u64 = 34; Max.u64 = 915; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 411; SumSQ.u64 = 24627; Count.u64 = 7; Min.u64 = 53; Max.u64 = 72; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 19042; SumSQ.u64 = 6658172; Count.u64 = 60; Min.u64 = 66; Max.u64 = 653; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 71; SumSQ.u64 = 5041; Count.u64 = 1; Min.u64 = 71; Max.u64 = 71; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1642; SumSQ.u64 = 1642; Count.u64 = 1642; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2744; SumSQ.u64 = 2744; Count.u64 = 2744; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1915; SumSQ.u64 = 1915; Count.u64 = 1915; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 1038; SumSQ.u64 = 1038; Count.u64 = 1038; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1223; SumSQ.u64 = 1223; Count.u64 = 1223; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1038; SumSQ.u64 = 1038; Count.u64 = 1038; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 11703; SumSQ.u64 = 11703; Count.u64 = 11703; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2557; SumSQ.u64 = 2557; Count.u64 = 2557; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1659; SumSQ.u64 = 1659; Count.u64 = 1659; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2508; SumSQ.u64 = 2508; Count.u64 = 2508; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1253; SumSQ.u64 = 1253; Count.u64 = 1253; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 1915; SumSQ.u64 = 1915; Count.u64 = 1915; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 930589; SumSQ.u64 = 5987659; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 10; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2557; SumSQ.u64 = 2557; Count.u64 = 2557; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1746; SumSQ.u64 = 1746; Count.u64 = 1746; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 758; SumSQ.u64 = 758; Count.u64 = 758; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 191; SumSQ.u64 = 191; Count.u64 = 191; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 196; SumSQ.u64 = 196; Count.u64 = 196; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1746; SumSQ.u64 = 1746; Count.u64 = 1746; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 192; SumSQ.u64 = 192; Count.u64 = 192; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 258; SumSQ.u64 = 258; Count.u64 = 258; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2515; SumSQ.u64 = 2515; Count.u64 = 2515; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 192; SumSQ.u64 = 2304; Count.u64 = 16; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 541436; SumSQ.u64 = 183114726; Count.u64 = 1746; Min.u64 = 34; Max.u64 = 927; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 180; SumSQ.u64 = 2160; Count.u64 = 15; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 299149; SumSQ.u64 = 101236693; Count.u64 = 959; Min.u64 = 35; Max.u64 = 915; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 860; SumSQ.u64 = 405778; Count.u64 = 5; Min.u64 = 53; Max.u64 = 626; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 10520; SumSQ.u64 = 3718280; Count.u64 = 32; Min.u64 = 283; Max.u64 = 625; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1745; SumSQ.u64 = 1745; Count.u64 = 1745; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2742; SumSQ.u64 = 2742; Count.u64 = 2742; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1864; SumSQ.u64 = 1864; Count.u64 = 1864; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1285; SumSQ.u64 = 1285; Count.u64 = 1285; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 173; SumSQ.u64 = 173; Count.u64 = 173; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11703; SumSQ.u64 = 11703; Count.u64 = 11703; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2577; SumSQ.u64 = 2577; Count.u64 = 2577; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1762; SumSQ.u64 = 1762; Count.u64 = 1762; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 979; SumSQ.u64 = 979; Count.u64 = 979; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2485; SumSQ.u64 = 2485; Count.u64 = 2485; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 790; SumSQ.u64 = 790; Count.u64 = 790; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 1864; SumSQ.u64 = 1864; Count.u64 = 1864; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 952355; SumSQ.u64 = 6067827; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 10; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_I : Accumulator : Sum.u64 = 2645; SumSQ.u64 = 2645; Count.u64 = 2645; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_IS : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_IM : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_M : Accumulator : Sum.u64 = 615; SumSQ.u64 = 615; Count.u64 = 615; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_MInv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1651; SumSQ.u64 = 1651; Count.u64 = 1651; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 944; SumSQ.u64 = 944; Count.u64 = 944; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1651; SumSQ.u64 = 1651; Count.u64 = 1651; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 986; SumSQ.u64 = 986; Count.u64 = 986; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 689; SumSQ.u64 = 689; Count.u64 = 689; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 340; SumSQ.u64 = 340; Count.u64 = 340; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetS : Accumulator : Sum.u64 = 1651; SumSQ.u64 = 1651; Count.u64 = 1651; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetX : Accumulator : Sum.u64 = 944; SumSQ.u64 = 944; Count.u64 = 944; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 1036; SumSQ.u64 = 1036; Count.u64 = 1036; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2548; SumSQ.u64 = 2548; Count.u64 = 2548; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 660; SumSQ.u64 = 660; Count.u64 = 660; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 1951; SumSQ.u64 = 1951; Count.u64 = 1951; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 11150; SumSQ.u64 = 2598726; Count.u64 = 102; Min.u64 = 19; Max.u64 = 576; + l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 502499; SumSQ.u64 = 163773045; Count.u64 = 1651; Min.u64 = 266; Max.u64 = 903; + l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 5986; SumSQ.u64 = 1262026; Count.u64 = 60; Min.u64 = 19; Max.u64 = 344; + l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 284949; SumSQ.u64 = 91440267; Count.u64 = 944; Min.u64 = 266; Max.u64 = 898; + l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 55; SumSQ.u64 = 3025; Count.u64 = 1; Min.u64 = 55; Max.u64 = 55; + l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 12745; SumSQ.u64 = 4133473; Count.u64 = 42; Min.u64 = 267; Max.u64 = 610; + l3cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1177; SumSQ.u64 = 1177; Count.u64 = 1177; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheHits : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheMisses : Accumulator : Sum.u64 = 2637; SumSQ.u64 = 2637; Count.u64 = 2637; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_E : Accumulator : Sum.u64 = 933; SumSQ.u64 = 933; Count.u64 = 933; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_EInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1101; SumSQ.u64 = 1101; Count.u64 = 1101; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutE : Accumulator : Sum.u64 = 1594; SumSQ.u64 = 1594; Count.u64 = 1594; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8876; SumSQ.u64 = 8876; Count.u64 = 8876; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2584; SumSQ.u64 = 2584; Count.u64 = 2584; Min.u64 = 1; Max.u64 = 1; + l3cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_recv : Accumulator : Sum.u64 = 1753; SumSQ.u64 = 1753; Count.u64 = 1753; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetX_recv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 2637; SumSQ.u64 = 2637; Count.u64 = 2637; Min.u64 = 1; Max.u64 = 1; + l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.PutS_recv : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutM_recv : Accumulator : Sum.u64 = 715; SumSQ.u64 = 715; Count.u64 = 715; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutE_recv : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckInv_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 874351; SumSQ.u64 = 5604903; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 12; + l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_I : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_IS : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_IM : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_M : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_MInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1558; SumSQ.u64 = 1558; Count.u64 = 1558; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1558; SumSQ.u64 = 1558; Count.u64 = 1558; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 995; SumSQ.u64 = 995; Count.u64 = 995; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetS : Accumulator : Sum.u64 = 1558; SumSQ.u64 = 1558; Count.u64 = 1558; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetX : Accumulator : Sum.u64 = 950; SumSQ.u64 = 950; Count.u64 = 950; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 1048; SumSQ.u64 = 1048; Count.u64 = 1048; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2445; SumSQ.u64 = 2445; Count.u64 = 2445; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 1828; SumSQ.u64 = 1828; Count.u64 = 1828; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 7947; SumSQ.u64 = 1766595; Count.u64 = 77; Min.u64 = 19; Max.u64 = 547; + l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 470409; SumSQ.u64 = 149989923; Count.u64 = 1558; Min.u64 = 266; Max.u64 = 907; + l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 4826; SumSQ.u64 = 932628; Count.u64 = 51; Min.u64 = 19; Max.u64 = 323; + l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 293068; SumSQ.u64 = 97722354; Count.u64 = 950; Min.u64 = 266; Max.u64 = 897; + l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 920; SumSQ.u64 = 230224; Count.u64 = 5; Min.u64 = 51; Max.u64 = 299; + l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 14367; SumSQ.u64 = 5055239; Count.u64 = 45; Min.u64 = 266; Max.u64 = 638; + l3cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1080; SumSQ.u64 = 1080; Count.u64 = 1080; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 478; SumSQ.u64 = 478; Count.u64 = 478; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 280; SumSQ.u64 = 280; Count.u64 = 280; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheHits : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheMisses : Accumulator : Sum.u64 = 2553; SumSQ.u64 = 2553; Count.u64 = 2553; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_E : Accumulator : Sum.u64 = 929; SumSQ.u64 = 929; Count.u64 = 929; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_EInv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1009; SumSQ.u64 = 1009; Count.u64 = 1009; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutE : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8121; SumSQ.u64 = 8121; Count.u64 = 8121; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2446; SumSQ.u64 = 2446; Count.u64 = 2446; Min.u64 = 1; Max.u64 = 1; + l3cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_recv : Accumulator : Sum.u64 = 1635; SumSQ.u64 = 1635; Count.u64 = 1635; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetX_recv : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 2553; SumSQ.u64 = 2553; Count.u64 = 2553; Min.u64 = 1; Max.u64 = 1; + l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.PutS_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutM_recv : Accumulator : Sum.u64 = 725; SumSQ.u64 = 725; Count.u64 = 725; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutE_recv : Accumulator : Sum.u64 = 1016; SumSQ.u64 = 1016; Count.u64 = 1016; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckInv_recv : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 775630; SumSQ.u64 = 4810218; Count.u64 = 175362; Min.u64 = 0; Max.u64 = 11; + l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 58.3955 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case6_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case6_mesi.out new file mode 100644 index 0000000000..7d5a7f6c61 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case6_mesi.out @@ -0,0 +1,911 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1121034; SumSQ.u64 = 8943352; Count.u64 = 140611; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1707; SumSQ.u64 = 1707; Count.u64 = 1707; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1138; SumSQ.u64 = 1138; Count.u64 = 1138; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1159286; SumSQ.u64 = 9249404; Count.u64 = 145392; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1787; SumSQ.u64 = 1787; Count.u64 = 1787; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1040; SumSQ.u64 = 1040; Count.u64 = 1040; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1621; SumSQ.u64 = 1621; Count.u64 = 1621; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1097; SumSQ.u64 = 1097; Count.u64 = 1097; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1528; SumSQ.u64 = 1528; Count.u64 = 1528; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1146; SumSQ.u64 = 1146; Count.u64 = 1146; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1621; SumSQ.u64 = 1621; Count.u64 = 1621; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 1124; SumSQ.u64 = 1124; Count.u64 = 1124; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1707; SumSQ.u64 = 1707; Count.u64 = 1707; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1188; SumSQ.u64 = 1188; Count.u64 = 1188; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1614; SumSQ.u64 = 1614; Count.u64 = 1614; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 1124; SumSQ.u64 = 1124; Count.u64 = 1124; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 10396; SumSQ.u64 = 3355690; Count.u64 = 86; Min.u64 = 3; Max.u64 = 571; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 622061; SumSQ.u64 = 303841319; Count.u64 = 1621; Min.u64 = 18; Max.u64 = 1494; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 11603; SumSQ.u64 = 3313077; Count.u64 = 71; Min.u64 = 3; Max.u64 = 524; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 426009; SumSQ.u64 = 207354237; Count.u64 = 1097; Min.u64 = 18; Max.u64 = 1499; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 181; SumSQ.u64 = 11345; Count.u64 = 3; Min.u64 = 50; Max.u64 = 77; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 19435; SumSQ.u64 = 8826407; Count.u64 = 49; Min.u64 = 22; Max.u64 = 793; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 76; SumSQ.u64 = 5776; Count.u64 = 1; Min.u64 = 76; Max.u64 = 76; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1566; SumSQ.u64 = 1566; Count.u64 = 1566; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1068; SumSQ.u64 = 1068; Count.u64 = 1068; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1461; SumSQ.u64 = 1461; Count.u64 = 1461; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1461; SumSQ.u64 = 1461; Count.u64 = 1461; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6222; SumSQ.u64 = 6222; Count.u64 = 6222; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2049; SumSQ.u64 = 2049; Count.u64 = 2049; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1707; SumSQ.u64 = 1707; Count.u64 = 1707; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1188; SumSQ.u64 = 1188; Count.u64 = 1188; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2678; SumSQ.u64 = 2678; Count.u64 = 2678; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 785593; SumSQ.u64 = 5169833; Count.u64 = 145392; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1710; SumSQ.u64 = 1710; Count.u64 = 1710; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 1008; SumSQ.u64 = 1008; Count.u64 = 1008; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1710; SumSQ.u64 = 1710; Count.u64 = 1710; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 1008; SumSQ.u64 = 1008; Count.u64 = 1008; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1787; SumSQ.u64 = 1787; Count.u64 = 1787; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1615; SumSQ.u64 = 1615; Count.u64 = 1615; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 10606; SumSQ.u64 = 4754596; Count.u64 = 77; Min.u64 = 3; Max.u64 = 865; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 677617; SumSQ.u64 = 356858191; Count.u64 = 1710; Min.u64 = 18; Max.u64 = 1724; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 15854; SumSQ.u64 = 5502116; Count.u64 = 70; Min.u64 = 3; Max.u64 = 915; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 390744; SumSQ.u64 = 193553744; Count.u64 = 1008; Min.u64 = 18; Max.u64 = 1429; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 3; SumSQ.u64 = 9; Count.u64 = 1; Min.u64 = 3; Max.u64 = 3; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 15004; SumSQ.u64 = 6286770; Count.u64 = 41; Min.u64 = 61; Max.u64 = 645; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1650; SumSQ.u64 = 1650; Count.u64 = 1650; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 982; SumSQ.u64 = 982; Count.u64 = 982; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CacheHits : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2759; SumSQ.u64 = 2759; Count.u64 = 2759; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1515; SumSQ.u64 = 1515; Count.u64 = 1515; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1515; SumSQ.u64 = 1515; Count.u64 = 1515; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6237; SumSQ.u64 = 6237; Count.u64 = 6237; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2019; SumSQ.u64 = 2019; Count.u64 = 2019; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1787; SumSQ.u64 = 1787; Count.u64 = 1787; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1082; SumSQ.u64 = 1082; Count.u64 = 1082; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2644; SumSQ.u64 = 2644; Count.u64 = 2644; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 803699; SumSQ.u64 = 5212961; Count.u64 = 145392; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3061; SumSQ.u64 = 3061; Count.u64 = 3061; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1949; SumSQ.u64 = 1949; Count.u64 = 1949; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2222; SumSQ.u64 = 2222; Count.u64 = 2222; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 605855; SumSQ.u64 = 10402801; Count.u64 = 48415; Min.u64 = 0; Max.u64 = 51; + memory.latency_GetS : Accumulator : Sum.u64 = 253084; SumSQ.u64 = 20945390; Count.u64 = 3061; Min.u64 = 81; Max.u64 = 94; + memory.latency_GetSX : Accumulator : Sum.u64 = 7268; SumSQ.u64 = 600958; Count.u64 = 88; Min.u64 = 81; Max.u64 = 95; + memory.latency_GetX : Accumulator : Sum.u64 = 160879; SumSQ.u64 = 13291937; Count.u64 = 1949; Min.u64 = 81; Max.u64 = 96; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 184624; SumSQ.u64 = 15352754; Count.u64 = 2222; Min.u64 = 81; Max.u64 = 95; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7320; SumSQ.u64 = 7320; Count.u64 = 7320; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 48415; SumSQ.u64 = 2344012225; Count.u64 = 1; Min.u64 = 48415; Max.u64 = 48415; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2221; SumSQ.u64 = 2221; Count.u64 = 2221; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 1101; SumSQ.u64 = 1101; Count.u64 = 1101; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1589; SumSQ.u64 = 1589; Count.u64 = 1589; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1078; SumSQ.u64 = 1078; Count.u64 = 1078; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1501; SumSQ.u64 = 1501; Count.u64 = 1501; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1126; SumSQ.u64 = 1126; Count.u64 = 1126; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 1090; SumSQ.u64 = 1090; Count.u64 = 1090; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1589; SumSQ.u64 = 1589; Count.u64 = 1589; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 1101; SumSQ.u64 = 1101; Count.u64 = 1101; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2678; SumSQ.u64 = 2678; Count.u64 = 2678; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 78; SumSQ.u64 = 78; Count.u64 = 78; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 384; SumSQ.u64 = 4608; Count.u64 = 32; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 410663; SumSQ.u64 = 109991385; Count.u64 = 1589; Min.u64 = 34; Max.u64 = 304; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 204; SumSQ.u64 = 2448; Count.u64 = 17; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 277950; SumSQ.u64 = 74445702; Count.u64 = 1078; Min.u64 = 34; Max.u64 = 313; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 158; SumSQ.u64 = 5736; Count.u64 = 5; Min.u64 = 18; Max.u64 = 51; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 12923; SumSQ.u64 = 3482671; Count.u64 = 48; Min.u64 = 263; Max.u64 = 297; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 52; SumSQ.u64 = 2704; Count.u64 = 1; Min.u64 = 52; Max.u64 = 52; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1586; SumSQ.u64 = 1586; Count.u64 = 1586; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2721; SumSQ.u64 = 2721; Count.u64 = 2721; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2667; SumSQ.u64 = 2667; Count.u64 = 2667; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 1426; SumSQ.u64 = 1426; Count.u64 = 1426; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1373; SumSQ.u64 = 1373; Count.u64 = 1373; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 11693; SumSQ.u64 = 11693; Count.u64 = 11693; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2561; SumSQ.u64 = 2561; Count.u64 = 2561; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1621; SumSQ.u64 = 1621; Count.u64 = 1621; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2633; SumSQ.u64 = 2633; Count.u64 = 2633; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 1124; SumSQ.u64 = 1124; Count.u64 = 1124; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1461; SumSQ.u64 = 1461; Count.u64 = 1461; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 2667; SumSQ.u64 = 2667; Count.u64 = 2667; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 759819; SumSQ.u64 = 4898703; Count.u64 = 145392; Min.u64 = 0; Max.u64 = 10; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2254; SumSQ.u64 = 2254; Count.u64 = 2254; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 995; SumSQ.u64 = 995; Count.u64 = 995; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1671; SumSQ.u64 = 1671; Count.u64 = 1671; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1559; SumSQ.u64 = 1559; Count.u64 = 1559; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1031; SumSQ.u64 = 1031; Count.u64 = 1031; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 993; SumSQ.u64 = 993; Count.u64 = 993; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1671; SumSQ.u64 = 1671; Count.u64 = 1671; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 995; SumSQ.u64 = 995; Count.u64 = 995; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2644; SumSQ.u64 = 2644; Count.u64 = 2644; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 468; SumSQ.u64 = 5616; Count.u64 = 39; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 434120; SumSQ.u64 = 116925312; Count.u64 = 1671; Min.u64 = 34; Max.u64 = 317; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 192; SumSQ.u64 = 2304; Count.u64 = 16; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 258529; SumSQ.u64 = 69514317; Count.u64 = 990; Min.u64 = 34; Max.u64 = 316; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 38; SumSQ.u64 = 724; Count.u64 = 2; Min.u64 = 18; Max.u64 = 20; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 10841; SumSQ.u64 = 2918907; Count.u64 = 41; Min.u64 = 52; Max.u64 = 313; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1671; SumSQ.u64 = 1671; Count.u64 = 1671; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2704; SumSQ.u64 = 2704; Count.u64 = 2704; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2613; SumSQ.u64 = 2613; Count.u64 = 2613; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 1425; SumSQ.u64 = 1425; Count.u64 = 1425; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1490; SumSQ.u64 = 1490; Count.u64 = 1490; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1425; SumSQ.u64 = 1425; Count.u64 = 1425; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11646; SumSQ.u64 = 11646; Count.u64 = 11646; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2545; SumSQ.u64 = 2545; Count.u64 = 2545; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1710; SumSQ.u64 = 1710; Count.u64 = 1710; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 1008; SumSQ.u64 = 1008; Count.u64 = 1008; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2592; SumSQ.u64 = 2592; Count.u64 = 2592; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 1028; SumSQ.u64 = 1028; Count.u64 = 1028; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1515; SumSQ.u64 = 1515; Count.u64 = 1515; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 2613; SumSQ.u64 = 2613; Count.u64 = 2613; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 774372; SumSQ.u64 = 4892522; Count.u64 = 145392; Min.u64 = 0; Max.u64 = 9; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 59461; SumSQ.u64 = 12633711; Count.u64 = 5424; Min.u64 = 2; Max.u64 = 580; + directory.get_request_latency : Accumulator : Sum.u64 = 876877; SumSQ.u64 = 147537557; Count.u64 = 5425; Min.u64 = 2; Max.u64 = 198; + directory.directory_cache_hits : Accumulator : Sum.u64 = 10705; SumSQ.u64 = 10705; Count.u64 = 10705; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 2075; SumSQ.u64 = 2075; Count.u64 = 2075; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 3260; SumSQ.u64 = 3260; Count.u64 = 3260; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 2096; SumSQ.u64 = 2096; Count.u64 = 2096; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 2798; SumSQ.u64 = 2798; Count.u64 = 2798; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 5098; SumSQ.u64 = 5098; Count.u64 = 5098; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + directory.AckFlush_recv : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 3061; SumSQ.u64 = 3061; Count.u64 = 3061; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 1949; SumSQ.u64 = 1949; Count.u64 = 1949; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 2222; SumSQ.u64 = 2222; Count.u64 = 2222; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 5225; SumSQ.u64 = 5225; Count.u64 = 5225; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 5280; SumSQ.u64 = 5280; Count.u64 = 5280; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 904795; SumSQ.u64 = 10537429; Count.u64 = 96826; Min.u64 = 0; Max.u64 = 14; +Simulation is complete, simulated time: 48.4155 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case7_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case7_mesi.out new file mode 100644 index 0000000000..71786685b0 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case7_mesi.out @@ -0,0 +1,1059 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. +l3cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1401299; SumSQ.u64 = 11185247; Count.u64 = 175632; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1081; SumSQ.u64 = 1081; Count.u64 = 1081; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1489053; SumSQ.u64 = 11886769; Count.u64 = 186671; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1002; SumSQ.u64 = 1002; Count.u64 = 1002; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1668; SumSQ.u64 = 1668; Count.u64 = 1668; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1217; SumSQ.u64 = 1217; Count.u64 = 1217; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1122; SumSQ.u64 = 1122; Count.u64 = 1122; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 343; SumSQ.u64 = 343; Count.u64 = 343; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1668; SumSQ.u64 = 1668; Count.u64 = 1668; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1056; SumSQ.u64 = 1056; Count.u64 = 1056; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1149; SumSQ.u64 = 1149; Count.u64 = 1149; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2351; SumSQ.u64 = 2351; Count.u64 = 2351; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 10847; SumSQ.u64 = 5367191; Count.u64 = 51; Min.u64 = 3; Max.u64 = 890; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 805295; SumSQ.u64 = 504152633; Count.u64 = 1668; Min.u64 = 26; Max.u64 = 1923; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 20513; SumSQ.u64 = 8571279; Count.u64 = 77; Min.u64 = 3; Max.u64 = 890; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 484432; SumSQ.u64 = 288773982; Count.u64 = 1051; Min.u64 = 22; Max.u64 = 1650; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 2088; SumSQ.u64 = 1292026; Count.u64 = 5; Min.u64 = 29; Max.u64 = 931; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 288; SumSQ.u64 = 82944; Count.u64 = 1; Min.u64 = 288; Max.u64 = 288; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 32487; SumSQ.u64 = 21038967; Count.u64 = 67; Min.u64 = 20; Max.u64 = 1519; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1589; SumSQ.u64 = 1589; Count.u64 = 1589; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1000; SumSQ.u64 = 1000; Count.u64 = 1000; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2791; SumSQ.u64 = 2791; Count.u64 = 2791; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 963; SumSQ.u64 = 963; Count.u64 = 963; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 963; SumSQ.u64 = 963; Count.u64 = 963; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 9147; SumSQ.u64 = 9147; Count.u64 = 9147; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1883; SumSQ.u64 = 1883; Count.u64 = 1883; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1149; SumSQ.u64 = 1149; Count.u64 = 1149; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2340; SumSQ.u64 = 2340; Count.u64 = 2340; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 761; SumSQ.u64 = 761; Count.u64 = 761; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 971631; SumSQ.u64 = 6325025; Count.u64 = 186671; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 968; SumSQ.u64 = 968; Count.u64 = 968; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1349; SumSQ.u64 = 1349; Count.u64 = 1349; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1003; SumSQ.u64 = 1003; Count.u64 = 1003; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 332; SumSQ.u64 = 332; Count.u64 = 332; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 974; SumSQ.u64 = 974; Count.u64 = 974; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 623; SumSQ.u64 = 623; Count.u64 = 623; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1033; SumSQ.u64 = 1033; Count.u64 = 1033; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2284; SumSQ.u64 = 2284; Count.u64 = 2284; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 12808; SumSQ.u64 = 6971960; Count.u64 = 66; Min.u64 = 3; Max.u64 = 944; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 898067; SumSQ.u64 = 604968311; Count.u64 = 1788; Min.u64 = 18; Max.u64 = 1935; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 11773; SumSQ.u64 = 5228995; Count.u64 = 49; Min.u64 = 3; Max.u64 = 889; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 488538; SumSQ.u64 = 326064266; Count.u64 = 968; Min.u64 = 25; Max.u64 = 2578; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 2793; SumSQ.u64 = 1602245; Count.u64 = 6; Min.u64 = 31; Max.u64 = 656; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 640; SumSQ.u64 = 409600; Count.u64 = 1; Min.u64 = 640; Max.u64 = 640; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 14550; SumSQ.u64 = 8418288; Count.u64 = 30; Min.u64 = 40; Max.u64 = 1010; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1721; SumSQ.u64 = 1721; Count.u64 = 1721; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 931; SumSQ.u64 = 931; Count.u64 = 931; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2792; SumSQ.u64 = 2792; Count.u64 = 2792; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1823; SumSQ.u64 = 1823; Count.u64 = 1823; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 274; SumSQ.u64 = 274; Count.u64 = 274; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 9087; SumSQ.u64 = 9087; Count.u64 = 9087; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1840; SumSQ.u64 = 1840; Count.u64 = 1840; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1854; SumSQ.u64 = 1854; Count.u64 = 1854; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1033; SumSQ.u64 = 1033; Count.u64 = 1033; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2353; SumSQ.u64 = 2353; Count.u64 = 2353; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 1823; SumSQ.u64 = 1823; Count.u64 = 1823; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1047690; SumSQ.u64 = 6737668; Count.u64 = 186671; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 2975; SumSQ.u64 = 2975; Count.u64 = 2975; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1726; SumSQ.u64 = 1726; Count.u64 = 1726; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2004; SumSQ.u64 = 2004; Count.u64 = 2004; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 560283; SumSQ.u64 = 7814027; Count.u64 = 62161; Min.u64 = 0; Max.u64 = 39; + memory.latency_GetS : Accumulator : Sum.u64 = 245478; SumSQ.u64 = 20274298; Count.u64 = 2975; Min.u64 = 81; Max.u64 = 99; + memory.latency_GetSX : Accumulator : Sum.u64 = 6732; SumSQ.u64 = 552926; Count.u64 = 82; Min.u64 = 81; Max.u64 = 88; + memory.latency_GetX : Accumulator : Sum.u64 = 142397; SumSQ.u64 = 11758933; Count.u64 = 1726; Min.u64 = 81; Max.u64 = 100; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 165676; SumSQ.u64 = 13707914; Count.u64 = 2004; Min.u64 = 81; Max.u64 = 96; + memory.cycles_with_issue : Accumulator : Sum.u64 = 6787; SumSQ.u64 = 6787; Count.u64 = 6787; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 62161; SumSQ.u64 = 3863989921; Count.u64 = 1; Min.u64 = 62161; Max.u64 = 62161; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 5432; SumSQ.u64 = 5432; Count.u64 = 5432; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IS : Accumulator : Sum.u64 = 823; SumSQ.u64 = 823; Count.u64 = 823; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IM : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 1881; SumSQ.u64 = 1881; Count.u64 = 1881; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3347; SumSQ.u64 = 3347; Count.u64 = 3347; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3347; SumSQ.u64 = 3347; Count.u64 = 3347; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2060; SumSQ.u64 = 2060; Count.u64 = 2060; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1238; SumSQ.u64 = 1238; Count.u64 = 1238; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 819; SumSQ.u64 = 819; Count.u64 = 819; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 5397; SumSQ.u64 = 5397; Count.u64 = 5397; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 3347; SumSQ.u64 = 3347; Count.u64 = 3347; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 2267; SumSQ.u64 = 2267; Count.u64 = 2267; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 890; SumSQ.u64 = 890; Count.u64 = 890; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 4693; SumSQ.u64 = 4693; Count.u64 = 4693; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1435; SumSQ.u64 = 1435; Count.u64 = 1435; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 3588; SumSQ.u64 = 3588; Count.u64 = 3588; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 14423; SumSQ.u64 = 4176049; Count.u64 = 109; Min.u64 = 12; Max.u64 = 591; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 1064605; SumSQ.u64 = 411780365; Count.u64 = 3347; Min.u64 = 34; Max.u64 = 1479; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 9067; SumSQ.u64 = 2513821; Count.u64 = 65; Min.u64 = 12; Max.u64 = 596; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 611296; SumSQ.u64 = 229640844; Count.u64 = 1965; Min.u64 = 34; Max.u64 = 1220; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 33; SumSQ.u64 = 585; Count.u64 = 2; Min.u64 = 12; Max.u64 = 21; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 29575; SumSQ.u64 = 10932525; Count.u64 = 95; Min.u64 = 34; Max.u64 = 746; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1998; SumSQ.u64 = 1998; Count.u64 = 1998; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 1349; SumSQ.u64 = 1349; Count.u64 = 1349; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheHits : Accumulator : Sum.u64 = 176; SumSQ.u64 = 176; Count.u64 = 176; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 5407; SumSQ.u64 = 5407; Count.u64 = 5407; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_E : Accumulator : Sum.u64 = 2638; SumSQ.u64 = 2638; Count.u64 = 2638; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_ED : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 1857; SumSQ.u64 = 1857; Count.u64 = 1857; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 471; SumSQ.u64 = 471; Count.u64 = 471; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 646; SumSQ.u64 = 646; Count.u64 = 646; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 3130; SumSQ.u64 = 3130; Count.u64 = 3130; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 22921; SumSQ.u64 = 22921; Count.u64 = 22921; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 7331; SumSQ.u64 = 7331; Count.u64 = 7331; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 3456; SumSQ.u64 = 3456; Count.u64 = 3456; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 2030; SumSQ.u64 = 2030; Count.u64 = 2030; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 5407; SumSQ.u64 = 5407; Count.u64 = 5407; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.PutS_recv : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l2cache.PutM_recv : Accumulator : Sum.u64 = 1350; SumSQ.u64 = 1350; Count.u64 = 1350; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 2012; SumSQ.u64 = 2012; Count.u64 = 2012; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 1322; SumSQ.u64 = 1322; Count.u64 = 1322; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 292; SumSQ.u64 = 292; Count.u64 = 292; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 5397; SumSQ.u64 = 5397; Count.u64 = 5397; Min.u64 = 1; Max.u64 = 1; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 1871631; SumSQ.u64 = 22022475; Count.u64 = 186671; Min.u64 = 0; Max.u64 = 15; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_I : Accumulator : Sum.u64 = 2041; SumSQ.u64 = 2041; Count.u64 = 2041; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_M : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_I : Accumulator : Sum.u64 = 1032; SumSQ.u64 = 1032; Count.u64 = 1032; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetS : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetX : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSX : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2708; SumSQ.u64 = 2708; Count.u64 = 2708; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 2703; SumSQ.u64 = 2703; Count.u64 = 2703; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 1501; SumSQ.u64 = 28519; Count.u64 = 79; Min.u64 = 19; Max.u64 = 19; + l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 427413; SumSQ.u64 = 116449383; Count.u64 = 1570; Min.u64 = 266; Max.u64 = 323; + l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 1007; SumSQ.u64 = 19133; Count.u64 = 53; Min.u64 = 19; Max.u64 = 19; + l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 259266; SumSQ.u64 = 70662192; Count.u64 = 952; Min.u64 = 266; Max.u64 = 314; + l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 76; SumSQ.u64 = 1444; Count.u64 = 4; Min.u64 = 19; Max.u64 = 19; + l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 13544; SumSQ.u64 = 3669808; Count.u64 = 50; Min.u64 = 266; Max.u64 = 289; + l3cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 79; SumSQ.u64 = 79; Count.u64 = 79; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CacheHits : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; + l3cache0.CacheMisses : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_E : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_I : Accumulator : Sum.u64 = 1535; SumSQ.u64 = 1535; Count.u64 = 1535; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutE : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8275; SumSQ.u64 = 8275; Count.u64 = 8275; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2333; SumSQ.u64 = 2333; Count.u64 = 2333; Min.u64 = 1; Max.u64 = 1; + l3cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_recv : Accumulator : Sum.u64 = 1649; SumSQ.u64 = 1649; Count.u64 = 1649; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetX_recv : Accumulator : Sum.u64 = 1005; SumSQ.u64 = 1005; Count.u64 = 1005; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSX_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.PutM_recv : Accumulator : Sum.u64 = 1122; SumSQ.u64 = 1122; Count.u64 = 1122; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutE_recv : Accumulator : Sum.u64 = 1581; SumSQ.u64 = 1581; Count.u64 = 1581; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 764525; SumSQ.u64 = 4034265; Count.u64 = 186671; Min.u64 = 0; Max.u64 = 10; + l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_M : Accumulator : Sum.u64 = 934; SumSQ.u64 = 934; Count.u64 = 934; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1405; SumSQ.u64 = 1405; Count.u64 = 1405; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2211; SumSQ.u64 = 2211; Count.u64 = 2211; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_I : Accumulator : Sum.u64 = 827; SumSQ.u64 = 827; Count.u64 = 827; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetS : Accumulator : Sum.u64 = 1405; SumSQ.u64 = 1405; Count.u64 = 1405; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetX : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSX : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 934; SumSQ.u64 = 934; Count.u64 = 934; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2699; SumSQ.u64 = 2699; Count.u64 = 2699; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 2694; SumSQ.u64 = 2694; Count.u64 = 2694; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 5567; SumSQ.u64 = 105773; Count.u64 = 293; Min.u64 = 19; Max.u64 = 19; + l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 383554; SumSQ.u64 = 104790602; Count.u64 = 1405; Min.u64 = 266; Max.u64 = 321; + l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 3534; SumSQ.u64 = 67146; Count.u64 = 186; Min.u64 = 19; Max.u64 = 19; + l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 211199; SumSQ.u64 = 57675837; Count.u64 = 774; Min.u64 = 266; Max.u64 = 325; + l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 171; SumSQ.u64 = 3249; Count.u64 = 9; Min.u64 = 19; Max.u64 = 19; + l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 8703; SumSQ.u64 = 2368155; Count.u64 = 32; Min.u64 = 267; Max.u64 = 291; + l3cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1405; SumSQ.u64 = 1405; Count.u64 = 1405; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 774; SumSQ.u64 = 774; Count.u64 = 774; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CacheHits : Accumulator : Sum.u64 = 488; SumSQ.u64 = 488; Count.u64 = 488; Min.u64 = 1; Max.u64 = 1; + l3cache1.CacheMisses : Accumulator : Sum.u64 = 2211; SumSQ.u64 = 2211; Count.u64 = 2211; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_E : Accumulator : Sum.u64 = 1248; SumSQ.u64 = 1248; Count.u64 = 1248; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_I : Accumulator : Sum.u64 = 1379; SumSQ.u64 = 1379; Count.u64 = 1379; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutE : Accumulator : Sum.u64 = 1248; SumSQ.u64 = 1248; Count.u64 = 1248; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 7604; SumSQ.u64 = 7604; Count.u64 = 7604; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_recv : Accumulator : Sum.u64 = 1698; SumSQ.u64 = 1698; Count.u64 = 1698; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetX_recv : Accumulator : Sum.u64 = 960; SumSQ.u64 = 960; Count.u64 = 960; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 2211; SumSQ.u64 = 2211; Count.u64 = 2211; Min.u64 = 1; Max.u64 = 1; + l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.PutM_recv : Accumulator : Sum.u64 = 1145; SumSQ.u64 = 1145; Count.u64 = 1145; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutE_recv : Accumulator : Sum.u64 = 1549; SumSQ.u64 = 1549; Count.u64 = 1549; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 590190; SumSQ.u64 = 2715264; Count.u64 = 186671; Min.u64 = 0; Max.u64 = 9; + l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 62.1614 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case8_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case8_mesi.out new file mode 100644 index 0000000000..ab82ba2c6d --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case8_mesi.out @@ -0,0 +1,919 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1160472; SumSQ.u64 = 9258778; Count.u64 = 145545; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1184279; SumSQ.u64 = 9450217; Count.u64 = 148584; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 1013; SumSQ.u64 = 1013; Count.u64 = 1013; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1619; SumSQ.u64 = 1619; Count.u64 = 1619; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1062; SumSQ.u64 = 1062; Count.u64 = 1062; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1532; SumSQ.u64 = 1532; Count.u64 = 1532; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1132; SumSQ.u64 = 1132; Count.u64 = 1132; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1619; SumSQ.u64 = 1619; Count.u64 = 1619; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1181; SumSQ.u64 = 1181; Count.u64 = 1181; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 1759; SumSQ.u64 = 1759; Count.u64 = 1759; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 7814; SumSQ.u64 = 2764074; Count.u64 = 65; Min.u64 = 3; Max.u64 = 586; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 659489; SumSQ.u64 = 336186311; Count.u64 = 1619; Min.u64 = 18; Max.u64 = 1498; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 16838; SumSQ.u64 = 4846930; Count.u64 = 93; Min.u64 = 3; Max.u64 = 603; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 415061; SumSQ.u64 = 199776263; Count.u64 = 1062; Min.u64 = 18; Max.u64 = 1483; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 387; SumSQ.u64 = 69219; Count.u64 = 4; Min.u64 = 41; Max.u64 = 251; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 15; SumSQ.u64 = 153; Count.u64 = 2; Min.u64 = 3; Max.u64 = 12; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 26331; SumSQ.u64 = 12495565; Count.u64 = 70; Min.u64 = 18; Max.u64 = 966; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1570; SumSQ.u64 = 1570; Count.u64 = 1570; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1030; SumSQ.u64 = 1030; Count.u64 = 1030; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2755; SumSQ.u64 = 2755; Count.u64 = 2755; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2710; SumSQ.u64 = 2710; Count.u64 = 2710; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1462; SumSQ.u64 = 1462; Count.u64 = 1462; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1462; SumSQ.u64 = 1462; Count.u64 = 1462; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8944; SumSQ.u64 = 8944; Count.u64 = 8944; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2218; SumSQ.u64 = 2218; Count.u64 = 2218; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1181; SumSQ.u64 = 1181; Count.u64 = 1181; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2668; SumSQ.u64 = 2668; Count.u64 = 2668; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 2710; SumSQ.u64 = 2710; Count.u64 = 2710; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 796652; SumSQ.u64 = 5179538; Count.u64 = 148584; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1761; SumSQ.u64 = 1761; Count.u64 = 1761; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 980; SumSQ.u64 = 980; Count.u64 = 980; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1653; SumSQ.u64 = 1653; Count.u64 = 1653; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1012; SumSQ.u64 = 1012; Count.u64 = 1012; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1761; SumSQ.u64 = 1761; Count.u64 = 1761; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 981; SumSQ.u64 = 981; Count.u64 = 981; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1727; SumSQ.u64 = 1727; Count.u64 = 1727; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 7453; SumSQ.u64 = 2764173; Count.u64 = 70; Min.u64 = 3; Max.u64 = 841; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 701675; SumSQ.u64 = 362866841; Count.u64 = 1761; Min.u64 = 18; Max.u64 = 2004; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 9101; SumSQ.u64 = 2628861; Count.u64 = 58; Min.u64 = 3; Max.u64 = 594; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 400745; SumSQ.u64 = 216379207; Count.u64 = 980; Min.u64 = 18; Max.u64 = 1969; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 72; SumSQ.u64 = 5184; Count.u64 = 1; Min.u64 = 72; Max.u64 = 72; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 228; SumSQ.u64 = 51984; Count.u64 = 1; Min.u64 = 228; Max.u64 = 228; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 11277; SumSQ.u64 = 5101743; Count.u64 = 32; Min.u64 = 18; Max.u64 = 943; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1707; SumSQ.u64 = 1707; Count.u64 = 1707; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 956; SumSQ.u64 = 956; Count.u64 = 956; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CacheHits : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2774; SumSQ.u64 = 2774; Count.u64 = 2774; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2713; SumSQ.u64 = 2713; Count.u64 = 2713; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1561; SumSQ.u64 = 1561; Count.u64 = 1561; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1561; SumSQ.u64 = 1561; Count.u64 = 1561; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8983; SumSQ.u64 = 8983; Count.u64 = 8983; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2128; SumSQ.u64 = 2128; Count.u64 = 2128; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1831; SumSQ.u64 = 1831; Count.u64 = 1831; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1046; SumSQ.u64 = 1046; Count.u64 = 1046; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2666; SumSQ.u64 = 2666; Count.u64 = 2666; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 2713; SumSQ.u64 = 2713; Count.u64 = 2713; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 802083; SumSQ.u64 = 5202691; Count.u64 = 148584; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3121; SumSQ.u64 = 3121; Count.u64 = 3121; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1868; SumSQ.u64 = 1868; Count.u64 = 1868; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2123; SumSQ.u64 = 2123; Count.u64 = 2123; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 598665; SumSQ.u64 = 10399293; Count.u64 = 49478; Min.u64 = 0; Max.u64 = 58; + memory.latency_GetS : Accumulator : Sum.u64 = 258639; SumSQ.u64 = 21459695; Count.u64 = 3121; Min.u64 = 81; Max.u64 = 94; + memory.latency_GetSX : Accumulator : Sum.u64 = 7626; SumSQ.u64 = 632952; Count.u64 = 92; Min.u64 = 81; Max.u64 = 92; + memory.latency_GetX : Accumulator : Sum.u64 = 154687; SumSQ.u64 = 12825497; Count.u64 = 1868; Min.u64 = 81; Max.u64 = 93; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 177713; SumSQ.u64 = 14896867; Count.u64 = 2123; Min.u64 = 81; Max.u64 = 98; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7204; SumSQ.u64 = 7204; Count.u64 = 7204; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 49478; SumSQ.u64 = 2448072484; Count.u64 = 1; Min.u64 = 49478; Max.u64 = 49478; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 2280; SumSQ.u64 = 2280; Count.u64 = 2280; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_S : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_M : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1593; SumSQ.u64 = 1593; Count.u64 = 1593; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 2619; Count.u64 = 2619; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_I : Accumulator : Sum.u64 = 136; SumSQ.u64 = 136; Count.u64 = 136; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_I : Accumulator : Sum.u64 = 1075; SumSQ.u64 = 1075; Count.u64 = 1075; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1593; SumSQ.u64 = 1593; Count.u64 = 1593; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1045; SumSQ.u64 = 1045; Count.u64 = 1045; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2668; SumSQ.u64 = 2668; Count.u64 = 2668; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 2710; SumSQ.u64 = 2710; Count.u64 = 2710; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 312; SumSQ.u64 = 3744; Count.u64 = 26; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 416309; SumSQ.u64 = 112138367; Count.u64 = 1593; Min.u64 = 34; Max.u64 = 312; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 252; SumSQ.u64 = 3024; Count.u64 = 21; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 268796; SumSQ.u64 = 72089886; Count.u64 = 1042; Min.u64 = 34; Max.u64 = 314; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 92; SumSQ.u64 = 3026; Count.u64 = 3; Min.u64 = 19; Max.u64 = 37; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 24; SumSQ.u64 = 288; Count.u64 = 2; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 17742; SumSQ.u64 = 4783746; Count.u64 = 68; Min.u64 = 35; Max.u64 = 308; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1591; SumSQ.u64 = 1591; Count.u64 = 1591; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2706; SumSQ.u64 = 2706; Count.u64 = 2706; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2628; SumSQ.u64 = 2628; Count.u64 = 2628; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 1401; SumSQ.u64 = 1401; Count.u64 = 1401; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_I : Accumulator : Sum.u64 = 1449; SumSQ.u64 = 1449; Count.u64 = 1449; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 1401; SumSQ.u64 = 1401; Count.u64 = 1401; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 11641; SumSQ.u64 = 11641; Count.u64 = 11641; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2588; SumSQ.u64 = 2588; Count.u64 = 2588; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1619; SumSQ.u64 = 1619; Count.u64 = 1619; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2622; SumSQ.u64 = 2622; Count.u64 = 2622; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1462; SumSQ.u64 = 1462; Count.u64 = 1462; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 2628; SumSQ.u64 = 2628; Count.u64 = 2628; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 772866; SumSQ.u64 = 4941500; Count.u64 = 148584; Min.u64 = 0; Max.u64 = 9; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 2230; SumSQ.u64 = 2230; Count.u64 = 2230; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_S : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_M : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1717; SumSQ.u64 = 1717; Count.u64 = 1717; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 953; SumSQ.u64 = 953; Count.u64 = 953; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2596; SumSQ.u64 = 2596; Count.u64 = 2596; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_I : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_I : Accumulator : Sum.u64 = 960; SumSQ.u64 = 960; Count.u64 = 960; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1717; SumSQ.u64 = 1717; Count.u64 = 1717; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 956; SumSQ.u64 = 956; Count.u64 = 956; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 936; SumSQ.u64 = 936; Count.u64 = 936; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2666; SumSQ.u64 = 2666; Count.u64 = 2666; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 2713; SumSQ.u64 = 2713; Count.u64 = 2713; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 528; SumSQ.u64 = 6336; Count.u64 = 44; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 448651; SumSQ.u64 = 121032141; Count.u64 = 1717; Min.u64 = 34; Max.u64 = 327; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 300; SumSQ.u64 = 3600; Count.u64 = 25; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 248210; SumSQ.u64 = 66974214; Count.u64 = 953; Min.u64 = 35; Max.u64 = 307; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 121; SumSQ.u64 = 5563; Count.u64 = 3; Min.u64 = 19; Max.u64 = 51; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 144; Count.u64 = 1; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 7943; SumSQ.u64 = 2133897; Count.u64 = 31; Min.u64 = 37; Max.u64 = 302; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1711; SumSQ.u64 = 1711; Count.u64 = 1711; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2704; SumSQ.u64 = 2704; Count.u64 = 2704; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_I : Accumulator : Sum.u64 = 1534; SumSQ.u64 = 1534; Count.u64 = 1534; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11657; SumSQ.u64 = 11657; Count.u64 = 11657; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2488; SumSQ.u64 = 2488; Count.u64 = 2488; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1761; SumSQ.u64 = 1761; Count.u64 = 1761; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 981; SumSQ.u64 = 981; Count.u64 = 981; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2599; SumSQ.u64 = 2599; Count.u64 = 2599; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1561; SumSQ.u64 = 1561; Count.u64 = 1561; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 2572; SumSQ.u64 = 2572; Count.u64 = 2572; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 780525; SumSQ.u64 = 4983629; Count.u64 = 148584; Min.u64 = 0; Max.u64 = 9; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.replacement_request_latency : Accumulator : Sum.u64 = 50125; SumSQ.u64 = 13306753; Count.u64 = 2716; Min.u64 = 2; Max.u64 = 438; + directory0.get_request_latency : Accumulator : Sum.u64 = 431714; SumSQ.u64 = 72606904; Count.u64 = 2668; Min.u64 = 13; Max.u64 = 194; + directory0.directory_cache_hits : Accumulator : Sum.u64 = 5231; SumSQ.u64 = 5231; Count.u64 = 5231; Min.u64 = 1; Max.u64 = 1; + directory0.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.GetX_recv : Accumulator : Sum.u64 = 989; SumSQ.u64 = 989; Count.u64 = 989; Min.u64 = 1; Max.u64 = 1; + directory0.GetS_recv : Accumulator : Sum.u64 = 1626; SumSQ.u64 = 1626; Count.u64 = 1626; Min.u64 = 1; Max.u64 = 1; + directory0.GetSX_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + directory0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.PutM_recv : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; + directory0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.PutE_recv : Accumulator : Sum.u64 = 1387; SumSQ.u64 = 1387; Count.u64 = 1387; Min.u64 = 1; Max.u64 = 1; + directory0.PutS_recv : Accumulator : Sum.u64 = 188; SumSQ.u64 = 188; Count.u64 = 188; Min.u64 = 1; Max.u64 = 1; + directory0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FetchResp_recv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + directory0.FetchXResp_recv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + directory0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.GetXResp_recv : Accumulator : Sum.u64 = 2503; SumSQ.u64 = 2503; Count.u64 = 2503; Min.u64 = 1; Max.u64 = 1; + directory0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.AckInv_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + directory0.AckFlush_recv : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + directory0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.FlushAll_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + directory0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_GetS : Accumulator : Sum.u64 = 1529; SumSQ.u64 = 1529; Count.u64 = 1529; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetX : Accumulator : Sum.u64 = 927; SumSQ.u64 = 927; Count.u64 = 927; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetSX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_PutM : Accumulator : Sum.u64 = 1053; SumSQ.u64 = 1053; Count.u64 = 1053; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_Inv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FetchInv : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FetchInvX : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_GetSResp : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_GetXResp : Accumulator : Sum.u64 = 2571; SumSQ.u64 = 2571; Count.u64 = 2571; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_AckPut : Accumulator : Sum.u64 = 2563; SumSQ.u64 = 2563; Count.u64 = 2563; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + directory0.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory0.MSHR_occupancy : Accumulator : Sum.u64 = 469265; SumSQ.u64 = 2905839; Count.u64 = 98822; Min.u64 = 0; Max.u64 = 12; + directory1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.replacement_request_latency : Accumulator : Sum.u64 = 6994; SumSQ.u64 = 20016; Count.u64 = 2637; Min.u64 = 2; Max.u64 = 5; + directory1.get_request_latency : Accumulator : Sum.u64 = 446507; SumSQ.u64 = 75523659; Count.u64 = 2742; Min.u64 = 2; Max.u64 = 204; + directory1.directory_cache_hits : Accumulator : Sum.u64 = 5379; SumSQ.u64 = 5379; Count.u64 = 5379; Min.u64 = 1; Max.u64 = 1; + directory1.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.GetX_recv : Accumulator : Sum.u64 = 1012; SumSQ.u64 = 1012; Count.u64 = 1012; Min.u64 = 1; Max.u64 = 1; + directory1.GetS_recv : Accumulator : Sum.u64 = 1684; SumSQ.u64 = 1684; Count.u64 = 1684; Min.u64 = 1; Max.u64 = 1; + directory1.GetSX_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + directory1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.PutM_recv : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; + directory1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.PutE_recv : Accumulator : Sum.u64 = 1472; SumSQ.u64 = 1472; Count.u64 = 1472; Min.u64 = 1; Max.u64 = 1; + directory1.PutS_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + directory1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FetchResp_recv : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + directory1.FetchXResp_recv : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + directory1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.GetXResp_recv : Accumulator : Sum.u64 = 2578; SumSQ.u64 = 2578; Count.u64 = 2578; Min.u64 = 1; Max.u64 = 1; + directory1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.AckInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + directory1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_GetS : Accumulator : Sum.u64 = 1592; SumSQ.u64 = 1592; Count.u64 = 1592; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetX : Accumulator : Sum.u64 = 941; SumSQ.u64 = 941; Count.u64 = 941; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_PutM : Accumulator : Sum.u64 = 1070; SumSQ.u64 = 1070; Count.u64 = 1070; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_Inv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FetchInv : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FetchInvX : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_GetSResp : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_GetXResp : Accumulator : Sum.u64 = 2650; SumSQ.u64 = 2650; Count.u64 = 2650; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_AckPut : Accumulator : Sum.u64 = 2637; SumSQ.u64 = 2637; Count.u64 = 2637; Min.u64 = 1; Max.u64 = 1; + directory1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory1.MSHR_occupancy : Accumulator : Sum.u64 = 440934; SumSQ.u64 = 2825336; Count.u64 = 98952; Min.u64 = 0; Max.u64 = 11; +Simulation is complete, simulated time: 49.4785 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case9_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case9_mesi.out new file mode 100644 index 0000000000..5e10efa63d --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_2core_3level_case9_mesi.out @@ -0,0 +1,1059 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 5 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1550570; SumSQ.u64 = 12381118; Count.u64 = 194250; Min.u64 = 0; Max.u64 = 8; + core0.reads : Accumulator : Sum.u64 = 1716; SumSQ.u64 = 1716; Count.u64 = 1716; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 1102; SumSQ.u64 = 1102; Count.u64 = 1102; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1629352; SumSQ.u64 = 13006668; Count.u64 = 204491; Min.u64 = 0; Max.u64 = 8; + core1.reads : Accumulator : Sum.u64 = 1868; SumSQ.u64 = 1868; Count.u64 = 1868; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 985; SumSQ.u64 = 985; Count.u64 = 985; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1657; SumSQ.u64 = 1657; Count.u64 = 1657; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1063; SumSQ.u64 = 1063; Count.u64 = 1063; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1242; SumSQ.u64 = 1242; Count.u64 = 1242; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 1129; SumSQ.u64 = 1129; Count.u64 = 1129; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1657; SumSQ.u64 = 1657; Count.u64 = 1657; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 1071; SumSQ.u64 = 1071; Count.u64 = 1071; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 637; SumSQ.u64 = 637; Count.u64 = 637; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1716; SumSQ.u64 = 1716; Count.u64 = 1716; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2269; SumSQ.u64 = 2269; Count.u64 = 2269; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 11886; SumSQ.u64 = 5769750; Count.u64 = 59; Min.u64 = 3; Max.u64 = 1249; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 879618; SumSQ.u64 = 581358842; Count.u64 = 1657; Min.u64 = 18; Max.u64 = 2223; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 17056; SumSQ.u64 = 8722288; Count.u64 = 72; Min.u64 = 3; Max.u64 = 1628; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 557178; SumSQ.u64 = 358321246; Count.u64 = 1063; Min.u64 = 30; Max.u64 = 1587; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 5532; SumSQ.u64 = 5392758; Count.u64 = 8; Min.u64 = 134; Max.u64 = 1248; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 290; SumSQ.u64 = 84100; Count.u64 = 1; Min.u64 = 290; Max.u64 = 290; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 33491; SumSQ.u64 = 22733587; Count.u64 = 61; Min.u64 = 145; Max.u64 = 1632; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1564; SumSQ.u64 = 1564; Count.u64 = 1564; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 2789; SumSQ.u64 = 2789; Count.u64 = 2789; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1869; SumSQ.u64 = 1869; Count.u64 = 1869; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 971; SumSQ.u64 = 971; Count.u64 = 971; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 59; SumSQ.u64 = 59; Count.u64 = 59; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 971; SumSQ.u64 = 971; Count.u64 = 971; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 9005; SumSQ.u64 = 9005; Count.u64 = 9005; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1893; SumSQ.u64 = 1893; Count.u64 = 1893; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1716; SumSQ.u64 = 1716; Count.u64 = 1716; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 1164; SumSQ.u64 = 1164; Count.u64 = 1164; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 2374; Count.u64 = 2374; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 636; SumSQ.u64 = 636; Count.u64 = 636; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 1869; SumSQ.u64 = 1869; Count.u64 = 1869; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1094343; SumSQ.u64 = 7102909; Count.u64 = 204491; Min.u64 = 0; Max.u64 = 7; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1803; SumSQ.u64 = 1803; Count.u64 = 1803; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1387; SumSQ.u64 = 1387; Count.u64 = 1387; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 985; SumSQ.u64 = 985; Count.u64 = 985; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1803; SumSQ.u64 = 1803; Count.u64 = 1803; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 285; SumSQ.u64 = 285; Count.u64 = 285; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1868; SumSQ.u64 = 1868; Count.u64 = 1868; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 1014; SumSQ.u64 = 1014; Count.u64 = 1014; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2216; SumSQ.u64 = 2216; Count.u64 = 2216; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 14101; SumSQ.u64 = 6785599; Count.u64 = 65; Min.u64 = 3; Max.u64 = 701; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 982407; SumSQ.u64 = 701108427; Count.u64 = 1803; Min.u64 = 18; Max.u64 = 2599; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 13306; SumSQ.u64 = 5965968; Count.u64 = 48; Min.u64 = 3; Max.u64 = 1186; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 527120; SumSQ.u64 = 380771028; Count.u64 = 952; Min.u64 = 18; Max.u64 = 1972; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 5757; SumSQ.u64 = 5735331; Count.u64 = 7; Min.u64 = 62; Max.u64 = 1248; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 342; SumSQ.u64 = 114930; Count.u64 = 2; Min.u64 = 3; Max.u64 = 339; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 13694; SumSQ.u64 = 9368156; Count.u64 = 27; Min.u64 = 287; Max.u64 = 1549; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1710; SumSQ.u64 = 1710; Count.u64 = 1710; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CacheHits : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 2789; SumSQ.u64 = 2789; Count.u64 = 2789; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 1839; Count.u64 = 1839; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 306; SumSQ.u64 = 306; Count.u64 = 306; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 9038; SumSQ.u64 = 9038; Count.u64 = 9038; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1816; SumSQ.u64 = 1816; Count.u64 = 1816; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1868; SumSQ.u64 = 1868; Count.u64 = 1868; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 1014; SumSQ.u64 = 1014; Count.u64 = 1014; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 2373; SumSQ.u64 = 2373; Count.u64 = 2373; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 296; SumSQ.u64 = 296; Count.u64 = 296; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 1839; Count.u64 = 1839; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1128433; SumSQ.u64 = 7301731; Count.u64 = 204491; Min.u64 = 0; Max.u64 = 7; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 3314; SumSQ.u64 = 3314; Count.u64 = 3314; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2089; SumSQ.u64 = 2089; Count.u64 = 2089; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 611904; SumSQ.u64 = 7666974; Count.u64 = 68095; Min.u64 = 0; Max.u64 = 30; + memory.latency_GetS : Accumulator : Sum.u64 = 273097; SumSQ.u64 = 22521815; Count.u64 = 3314; Min.u64 = 81; Max.u64 = 92; + memory.latency_GetSX : Accumulator : Sum.u64 = 7200; SumSQ.u64 = 596432; Count.u64 = 87; Min.u64 = 81; Max.u64 = 90; + memory.latency_GetX : Accumulator : Sum.u64 = 160464; SumSQ.u64 = 13227574; Count.u64 = 1948; Min.u64 = 81; Max.u64 = 93; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 171143; SumSQ.u64 = 14025143; Count.u64 = 2089; Min.u64 = 81; Max.u64 = 89; + memory.cycles_with_issue : Accumulator : Sum.u64 = 7438; SumSQ.u64 = 7438; Count.u64 = 7438; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 68095; SumSQ.u64 = 4636929025; Count.u64 = 1; Min.u64 = 68095; Max.u64 = 68095; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 1832; SumSQ.u64 = 1832; Count.u64 = 1832; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_S : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_M : Accumulator : Sum.u64 = 562; SumSQ.u64 = 562; Count.u64 = 562; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1646; SumSQ.u64 = 1646; Count.u64 = 1646; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 1064; SumSQ.u64 = 1064; Count.u64 = 1064; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2358; SumSQ.u64 = 2358; Count.u64 = 2358; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_I : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_I : Accumulator : Sum.u64 = 748; SumSQ.u64 = 748; Count.u64 = 748; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 309; SumSQ.u64 = 309; Count.u64 = 309; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 77; SumSQ.u64 = 77; Count.u64 = 77; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 640; SumSQ.u64 = 640; Count.u64 = 640; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 633; SumSQ.u64 = 633; Count.u64 = 633; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1646; SumSQ.u64 = 1646; Count.u64 = 1646; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 1067; SumSQ.u64 = 1067; Count.u64 = 1067; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 562; SumSQ.u64 = 562; Count.u64 = 562; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 976; SumSQ.u64 = 976; Count.u64 = 976; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 2374; SumSQ.u64 = 2374; Count.u64 = 2374; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 636; SumSQ.u64 = 636; Count.u64 = 636; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 304; SumSQ.u64 = 304; Count.u64 = 304; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 1869; SumSQ.u64 = 1869; Count.u64 = 1869; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 132; SumSQ.u64 = 1584; Count.u64 = 11; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 575628; SumSQ.u64 = 229123790; Count.u64 = 1646; Min.u64 = 53; Max.u64 = 1200; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 48; SumSQ.u64 = 576; Count.u64 = 4; Min.u64 = 12; Max.u64 = 12; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 367690; SumSQ.u64 = 146314480; Count.u64 = 1064; Min.u64 = 53; Max.u64 = 1146; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 193; SumSQ.u64 = 12581; Count.u64 = 3; Min.u64 = 54; Max.u64 = 71; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 20447; SumSQ.u64 = 7672149; Count.u64 = 61; Min.u64 = 70; Max.u64 = 897; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1638; SumSQ.u64 = 1638; Count.u64 = 1638; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 1062; SumSQ.u64 = 1062; Count.u64 = 1062; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheHits : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 2774; SumSQ.u64 = 2774; Count.u64 = 2774; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1430; SumSQ.u64 = 1430; Count.u64 = 1430; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 801; SumSQ.u64 = 801; Count.u64 = 801; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_I : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 801; SumSQ.u64 = 801; Count.u64 = 801; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 11798; SumSQ.u64 = 11798; Count.u64 = 11798; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1771; SumSQ.u64 = 1771; Count.u64 = 1771; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1657; SumSQ.u64 = 1657; Count.u64 = 1657; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 1071; SumSQ.u64 = 1071; Count.u64 = 1071; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 413; SumSQ.u64 = 413; Count.u64 = 413; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 2361; SumSQ.u64 = 2361; Count.u64 = 2361; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 756; SumSQ.u64 = 756; Count.u64 = 756; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 971; SumSQ.u64 = 971; Count.u64 = 971; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 966; SumSQ.u64 = 966; Count.u64 = 966; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 637; SumSQ.u64 = 637; Count.u64 = 637; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 1430; SumSQ.u64 = 1430; Count.u64 = 1430; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1070709; SumSQ.u64 = 6883845; Count.u64 = 204491; Min.u64 = 0; Max.u64 = 11; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 1786; SumSQ.u64 = 1786; Count.u64 = 1786; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_S : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_M : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1791; SumSQ.u64 = 1791; Count.u64 = 1791; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 2358; SumSQ.u64 = 2358; Count.u64 = 2358; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_I : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_I : Accumulator : Sum.u64 = 633; SumSQ.u64 = 633; Count.u64 = 633; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1791; SumSQ.u64 = 1791; Count.u64 = 1791; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 475; SumSQ.u64 = 475; Count.u64 = 475; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 377; SumSQ.u64 = 377; Count.u64 = 377; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 2373; SumSQ.u64 = 2373; Count.u64 = 2373; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 296; SumSQ.u64 = 296; Count.u64 = 296; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 1839; SumSQ.u64 = 1839; Count.u64 = 1839; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 144; SumSQ.u64 = 1728; Count.u64 = 12; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 629238; SumSQ.u64 = 251997652; Count.u64 = 1791; Min.u64 = 52; Max.u64 = 1173; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 48; SumSQ.u64 = 576; Count.u64 = 4; Min.u64 = 12; Max.u64 = 12; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 341937; SumSQ.u64 = 141468399; Count.u64 = 955; Min.u64 = 53; Max.u64 = 1251; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 8702; SumSQ.u64 = 2941362; Count.u64 = 27; Min.u64 = 281; Max.u64 = 657; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 952; SumSQ.u64 = 952; Count.u64 = 952; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 2773; SumSQ.u64 = 2773; Count.u64 = 2773; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1357; SumSQ.u64 = 1357; Count.u64 = 1357; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 815; SumSQ.u64 = 815; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_I : Accumulator : Sum.u64 = 1044; SumSQ.u64 = 1044; Count.u64 = 1044; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 815; SumSQ.u64 = 815; Count.u64 = 815; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 11825; SumSQ.u64 = 11825; Count.u64 = 11825; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1695; SumSQ.u64 = 1695; Count.u64 = 1695; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1803; SumSQ.u64 = 1803; Count.u64 = 1803; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 959; SumSQ.u64 = 959; Count.u64 = 959; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 2358; SumSQ.u64 = 2358; Count.u64 = 2358; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1047; SumSQ.u64 = 1047; Count.u64 = 1047; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 383; SumSQ.u64 = 383; Count.u64 = 383; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 285; SumSQ.u64 = 285; Count.u64 = 285; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 1357; SumSQ.u64 = 1357; Count.u64 = 1357; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1098338; SumSQ.u64 = 6992136; Count.u64 = 204491; Min.u64 = 0; Max.u64 = 11; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 5695; SumSQ.u64 = 5695; Count.u64 = 5695; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 733; SumSQ.u64 = 733; Count.u64 = 733; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IM : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 2057; SumSQ.u64 = 2057; Count.u64 = 2057; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 3314; SumSQ.u64 = 3314; Count.u64 = 3314; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 3314; SumSQ.u64 = 3314; Count.u64 = 3314; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2035; SumSQ.u64 = 2035; Count.u64 = 2035; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1010; SumSQ.u64 = 1010; Count.u64 = 1010; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1065; SumSQ.u64 = 1065; Count.u64 = 1065; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 3314; SumSQ.u64 = 3314; Count.u64 = 3314; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 87; SumSQ.u64 = 87; Count.u64 = 87; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2089; SumSQ.u64 = 2089; Count.u64 = 2089; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 828; SumSQ.u64 = 828; Count.u64 = 828; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 4719; SumSQ.u64 = 4719; Count.u64 = 4719; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 769; SumSQ.u64 = 769; Count.u64 = 769; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1991; SumSQ.u64 = 1991; Count.u64 = 1991; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 2787; SumSQ.u64 = 2787; Count.u64 = 2787; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 19498; SumSQ.u64 = 5385654; Count.u64 = 123; Min.u64 = 36; Max.u64 = 617; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 1129403; SumSQ.u64 = 437318117; Count.u64 = 3314; Min.u64 = 265; Max.u64 = 1180; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 9837; SumSQ.u64 = 3450837; Count.u64 = 74; Min.u64 = 38; Max.u64 = 923; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 667092; SumSQ.u64 = 261746602; Count.u64 = 1948; Min.u64 = 265; Max.u64 = 1236; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 54; SumSQ.u64 = 2916; Count.u64 = 1; Min.u64 = 54; Max.u64 = 54; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 27644; SumSQ.u64 = 9674128; Count.u64 = 87; Min.u64 = 265; Max.u64 = 882; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1693; SumSQ.u64 = 1693; Count.u64 = 1693; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 978; SumSQ.u64 = 978; Count.u64 = 978; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 1621; SumSQ.u64 = 1621; Count.u64 = 1621; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 970; SumSQ.u64 = 970; Count.u64 = 970; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheHits : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 5349; SumSQ.u64 = 5349; Count.u64 = 5349; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_E : Accumulator : Sum.u64 = 3204; SumSQ.u64 = 3204; Count.u64 = 3204; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_ED : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 1599; SumSQ.u64 = 1599; Count.u64 = 1599; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 915; SumSQ.u64 = 915; Count.u64 = 915; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 708; SumSQ.u64 = 708; Count.u64 = 708; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 3244; SumSQ.u64 = 3244; Count.u64 = 3244; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 16983; SumSQ.u64 = 16983; Count.u64 = 16983; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 8318; SumSQ.u64 = 8318; Count.u64 = 8318; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 3437; SumSQ.u64 = 3437; Count.u64 = 3437; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 2022; SumSQ.u64 = 2022; Count.u64 = 2022; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 5349; SumSQ.u64 = 5349; Count.u64 = 5349; Min.u64 = 1; Max.u64 = 1; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutS_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l3cache.PutM_recv : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 1616; SumSQ.u64 = 1616; Count.u64 = 1616; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 757; SumSQ.u64 = 757; Count.u64 = 757; Min.u64 = 1; Max.u64 = 1; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 1907464; SumSQ.u64 = 21994842; Count.u64 = 204491; Min.u64 = 0; Max.u64 = 14; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; +Simulation is complete, simulated time: 68.0955 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case0_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case0_mesi.out new file mode 100644 index 0000000000..4c13fb9150 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case0_mesi.out @@ -0,0 +1,2213 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache2: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l4cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 1515875; SumSQ.u64 = 24212203; Count.u64 = 95100; Min.u64 = 0; Max.u64 = 16; + core0.reads : Accumulator : Sum.u64 = 1118; SumSQ.u64 = 1118; Count.u64 = 1118; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 763; SumSQ.u64 = 763; Count.u64 = 763; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 1684854; SumSQ.u64 = 26860112; Count.u64 = 105922; Min.u64 = 0; Max.u64 = 16; + core1.reads : Accumulator : Sum.u64 = 1240; SumSQ.u64 = 1240; Count.u64 = 1240; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + core2.pendCycle : Accumulator : Sum.u64 = 1578196; SumSQ.u64 = 25179146; Count.u64 = 99231; Min.u64 = 0; Max.u64 = 16; + core2.reads : Accumulator : Sum.u64 = 1055; SumSQ.u64 = 1055; Count.u64 = 1055; Min.u64 = 1; Max.u64 = 1; + core2.writes : Accumulator : Sum.u64 = 858; SumSQ.u64 = 858; Count.u64 = 858; Min.u64 = 1; Max.u64 = 1; + core2.flushcaches : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + core2.llsc : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + core2.llsc_success : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + core3.pendCycle : Accumulator : Sum.u64 = 1851369; SumSQ.u64 = 29574335; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 16; + core3.reads : Accumulator : Sum.u64 = 1263; SumSQ.u64 = 1263; Count.u64 = 1263; Min.u64 = 1; Max.u64 = 1; + core3.writes : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + core3.flushcaches : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + core3.llsc : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + core3.llsc_success : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 751; SumSQ.u64 = 751; Count.u64 = 751; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 990; SumSQ.u64 = 990; Count.u64 = 990; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 751; SumSQ.u64 = 751; Count.u64 = 751; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 725; SumSQ.u64 = 725; Count.u64 = 725; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1118; SumSQ.u64 = 1118; Count.u64 = 1118; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2060; SumSQ.u64 = 2060; Count.u64 = 2060; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 725; SumSQ.u64 = 725; Count.u64 = 725; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 7217; SumSQ.u64 = 5094695; Count.u64 = 18; Min.u64 = 2; Max.u64 = 1174; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 852493; SumSQ.u64 = 890894369; Count.u64 = 1100; Min.u64 = 9; Max.u64 = 3329; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 12814; SumSQ.u64 = 13952980; Count.u64 = 25; Min.u64 = 2; Max.u64 = 2083; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 573841; SumSQ.u64 = 584639275; Count.u64 = 751; Min.u64 = 10; Max.u64 = 2885; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 31611; SumSQ.u64 = 26005457; Count.u64 = 47; Min.u64 = 220; Max.u64 = 1666; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 869; SumSQ.u64 = 869; Count.u64 = 869; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 1898; SumSQ.u64 = 1898; Count.u64 = 1898; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 4282; SumSQ.u64 = 4282; Count.u64 = 4282; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 3066; SumSQ.u64 = 3066; Count.u64 = 3066; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1118; SumSQ.u64 = 1118; Count.u64 = 1118; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 810; SumSQ.u64 = 810; Count.u64 = 810; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 691141; SumSQ.u64 = 8794775; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 15; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1218; SumSQ.u64 = 1218; Count.u64 = 1218; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1097; SumSQ.u64 = 1097; Count.u64 = 1097; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1218; SumSQ.u64 = 1218; Count.u64 = 1218; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1240; SumSQ.u64 = 1240; Count.u64 = 1240; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 698; SumSQ.u64 = 698; Count.u64 = 698; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2007; SumSQ.u64 = 2007; Count.u64 = 2007; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 498; SumSQ.u64 = 498; Count.u64 = 498; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 15021; SumSQ.u64 = 17105447; Count.u64 = 22; Min.u64 = 2; Max.u64 = 2134; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 1032739; SumSQ.u64 = 1293109087; Count.u64 = 1218; Min.u64 = 9; Max.u64 = 3768; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 10790; SumSQ.u64 = 8836404; Count.u64 = 24; Min.u64 = 2; Max.u64 = 1624; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 553591; SumSQ.u64 = 651227043; Count.u64 = 662; Min.u64 = 21; Max.u64 = 3774; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 12158; SumSQ.u64 = 9227972; Count.u64 = 19; Min.u64 = 283; Max.u64 = 1122; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 1899; SumSQ.u64 = 1899; Count.u64 = 1899; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 4279; SumSQ.u64 = 4279; Count.u64 = 4279; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2977; SumSQ.u64 = 2977; Count.u64 = 2977; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1240; SumSQ.u64 = 1240; Count.u64 = 1240; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 698; SumSQ.u64 = 698; Count.u64 = 698; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 729908; SumSQ.u64 = 9121636; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 15; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 931; SumSQ.u64 = 931; Count.u64 = 931; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 872; SumSQ.u64 = 872; Count.u64 = 872; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 840; SumSQ.u64 = 840; Count.u64 = 840; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1055; SumSQ.u64 = 1055; Count.u64 = 1055; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 891; SumSQ.u64 = 891; Count.u64 = 891; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_I : Accumulator : Sum.u64 = 2045; SumSQ.u64 = 2045; Count.u64 = 2045; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_S : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_M : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IS : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IM : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 8633; SumSQ.u64 = 9057021; Count.u64 = 14; Min.u64 = 2; Max.u64 = 2027; + l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 826109; SumSQ.u64 = 844699093; Count.u64 = 1041; Min.u64 = 8; Max.u64 = 3390; + l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 12996; SumSQ.u64 = 9106432; Count.u64 = 27; Min.u64 = 2; Max.u64 = 1361; + l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 671599; SumSQ.u64 = 695918059; Count.u64 = 839; Min.u64 = 11; Max.u64 = 3390; + l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 43; SumSQ.u64 = 1849; Count.u64 = 1; Min.u64 = 43; Max.u64 = 43; + l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 28488; SumSQ.u64 = 29793142; Count.u64 = 33; Min.u64 = 288; Max.u64 = 2209; + l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 842; SumSQ.u64 = 842; Count.u64 = 842; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 199; SumSQ.u64 = 199; Count.u64 = 199; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheHits : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheMisses : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_E : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 4275; SumSQ.u64 = 4275; Count.u64 = 4275; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 2933; SumSQ.u64 = 2933; Count.u64 = 2933; Min.u64 = 1; Max.u64 = 1; + l1cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_recv : Accumulator : Sum.u64 = 1055; SumSQ.u64 = 1055; Count.u64 = 1055; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_recv : Accumulator : Sum.u64 = 891; SumSQ.u64 = 891; Count.u64 = 891; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache2.Inv_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 764987; SumSQ.u64 = 9867341; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 15; + l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1233; SumSQ.u64 = 1233; Count.u64 = 1233; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 658; SumSQ.u64 = 658; Count.u64 = 658; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 1233; SumSQ.u64 = 1233; Count.u64 = 1233; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 622; SumSQ.u64 = 622; Count.u64 = 622; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1263; SumSQ.u64 = 1263; Count.u64 = 1263; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_I : Accumulator : Sum.u64 = 1935; SumSQ.u64 = 1935; Count.u64 = 1935; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_S : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_M : Accumulator : Sum.u64 = 622; SumSQ.u64 = 622; Count.u64 = 622; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IS : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IM : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 18650; SumSQ.u64 = 28640114; Count.u64 = 30; Min.u64 = 2; Max.u64 = 4073; + l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 1159571; SumSQ.u64 = 1660561525; Count.u64 = 1233; Min.u64 = 8; Max.u64 = 4793; + l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 7275; SumSQ.u64 = 7447671; Count.u64 = 17; Min.u64 = 2; Max.u64 = 2060; + l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 573872; SumSQ.u64 = 777293736; Count.u64 = 639; Min.u64 = 8; Max.u64 = 4786; + l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 1627; SumSQ.u64 = 1979077; Count.u64 = 2; Min.u64 = 241; Max.u64 = 1386; + l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 17371; SumSQ.u64 = 21315965; Count.u64 = 19; Min.u64 = 282; Max.u64 = 2283; + l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 994; SumSQ.u64 = 994; Count.u64 = 994; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 533; SumSQ.u64 = 533; Count.u64 = 533; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheHits : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheMisses : Accumulator : Sum.u64 = 1891; SumSQ.u64 = 1891; Count.u64 = 1891; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_E : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 4242; SumSQ.u64 = 4242; Count.u64 = 4242; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 2827; SumSQ.u64 = 2827; Count.u64 = 2827; Min.u64 = 1; Max.u64 = 1; + l1cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_recv : Accumulator : Sum.u64 = 1263; SumSQ.u64 = 1263; Count.u64 = 1263; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 1785; SumSQ.u64 = 1785; Count.u64 = 1785; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache3.Inv_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 841866; SumSQ.u64 = 10594300; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 15; + l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 4272; SumSQ.u64 = 4272; Count.u64 = 4272; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2910; SumSQ.u64 = 2910; Count.u64 = 2910; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 897736; SumSQ.u64 = 39687506; Count.u64 = 38630; Min.u64 = 0; Max.u64 = 123; + memory.latency_GetS : Accumulator : Sum.u64 = 388310; SumSQ.u64 = 35782748; Count.u64 = 4272; Min.u64 = 81; Max.u64 = 138; + memory.latency_GetSX : Accumulator : Sum.u64 = 9915; SumSQ.u64 = 906107; Count.u64 = 110; Min.u64 = 81; Max.u64 = 125; + memory.latency_GetX : Accumulator : Sum.u64 = 244264; SumSQ.u64 = 22644140; Count.u64 = 2672; Min.u64 = 81; Max.u64 = 138; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 255247; SumSQ.u64 = 22511043; Count.u64 = 2910; Min.u64 = 81; Max.u64 = 118; + memory.cycles_with_issue : Accumulator : Sum.u64 = 9964; SumSQ.u64 = 9964; Count.u64 = 9964; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 38630; SumSQ.u64 = 1492276900; Count.u64 = 1; Min.u64 = 38630; Max.u64 = 38630; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 732; SumSQ.u64 = 732; Count.u64 = 732; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 979; SumSQ.u64 = 979; Count.u64 = 979; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 732; SumSQ.u64 = 732; Count.u64 = 732; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1788; SumSQ.u64 = 1788; Count.u64 = 1788; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 45; SumSQ.u64 = 185; Count.u64 = 11; Min.u64 = 4; Max.u64 = 5; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 311242; SumSQ.u64 = 92581088; Count.u64 = 1089; Min.u64 = 15; Max.u64 = 491; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 18; SumSQ.u64 = 82; Count.u64 = 4; Min.u64 = 4; Max.u64 = 5; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 213479; SumSQ.u64 = 63253381; Count.u64 = 747; Min.u64 = 15; Max.u64 = 398; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 13239; SumSQ.u64 = 3890529; Count.u64 = 46; Min.u64 = 26; Max.u64 = 343; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1089; SumSQ.u64 = 1089; Count.u64 = 1089; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 1882; SumSQ.u64 = 1882; Count.u64 = 1882; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_E : Accumulator : Sum.u64 = 942; SumSQ.u64 = 942; Count.u64 = 942; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 967; SumSQ.u64 = 967; Count.u64 = 967; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 942; SumSQ.u64 = 942; Count.u64 = 942; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6305; SumSQ.u64 = 6305; Count.u64 = 6305; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1976; SumSQ.u64 = 1976; Count.u64 = 1976; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1100; SumSQ.u64 = 1100; Count.u64 = 1100; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 751; SumSQ.u64 = 751; Count.u64 = 751; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 1772; SumSQ.u64 = 1772; Count.u64 = 1772; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 725; SumSQ.u64 = 725; Count.u64 = 725; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 608955; SumSQ.u64 = 6732635; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 16; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 1739; SumSQ.u64 = 1739; Count.u64 = 1739; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1214; SumSQ.u64 = 1214; Count.u64 = 1214; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 657; SumSQ.u64 = 657; Count.u64 = 657; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1093; SumSQ.u64 = 1093; Count.u64 = 1093; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 676; SumSQ.u64 = 676; Count.u64 = 676; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1220; SumSQ.u64 = 1220; Count.u64 = 1220; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 657; SumSQ.u64 = 657; Count.u64 = 657; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 652; SumSQ.u64 = 652; Count.u64 = 652; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1778; SumSQ.u64 = 1778; Count.u64 = 1778; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 16; SumSQ.u64 = 64; Count.u64 = 4; Min.u64 = 4; Max.u64 = 4; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 358765; SumSQ.u64 = 110638499; Count.u64 = 1214; Min.u64 = 16; Max.u64 = 435; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 20; SumSQ.u64 = 80; Count.u64 = 5; Min.u64 = 4; Max.u64 = 4; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 195219; SumSQ.u64 = 60461747; Count.u64 = 657; Min.u64 = 15; Max.u64 = 427; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 5725; SumSQ.u64 = 1745117; Count.u64 = 19; Min.u64 = 277; Max.u64 = 403; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1214; SumSQ.u64 = 1214; Count.u64 = 1214; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 657; SumSQ.u64 = 657; Count.u64 = 657; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 1890; SumSQ.u64 = 1890; Count.u64 = 1890; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_E : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 1076; SumSQ.u64 = 1076; Count.u64 = 1076; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6311; SumSQ.u64 = 6311; Count.u64 = 6311; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1987; SumSQ.u64 = 1987; Count.u64 = 1987; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1218; SumSQ.u64 = 1218; Count.u64 = 1218; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 662; SumSQ.u64 = 662; Count.u64 = 662; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 645608; SumSQ.u64 = 6948040; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 15; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_I : Accumulator : Sum.u64 = 1817; SumSQ.u64 = 1817; Count.u64 = 1817; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_S : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_M : Accumulator : Sum.u64 = 824; SumSQ.u64 = 824; Count.u64 = 824; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 927; SumSQ.u64 = 927; Count.u64 = 927; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 865; SumSQ.u64 = 865; Count.u64 = 865; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 797; SumSQ.u64 = 797; Count.u64 = 797; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 1039; SumSQ.u64 = 1039; Count.u64 = 1039; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 839; SumSQ.u64 = 839; Count.u64 = 839; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSX : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 824; SumSQ.u64 = 824; Count.u64 = 824; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1804; SumSQ.u64 = 1804; Count.u64 = 1804; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 16; SumSQ.u64 = 64; Count.u64 = 4; Min.u64 = 4; Max.u64 = 4; + l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 333081; SumSQ.u64 = 111483505; Count.u64 = 1037; Min.u64 = 13; Max.u64 = 451; + l2cache2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 28; SumSQ.u64 = 112; Count.u64 = 7; Min.u64 = 4; Max.u64 = 4; + l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 267375; SumSQ.u64 = 90192971; Count.u64 = 832; Min.u64 = 16; Max.u64 = 458; + l2cache2.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 30; SumSQ.u64 = 900; Count.u64 = 1; Min.u64 = 30; Max.u64 = 30; + l2cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 10851; SumSQ.u64 = 3729331; Count.u64 = 33; Min.u64 = 26; Max.u64 = 435; + l2cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 833; SumSQ.u64 = 833; Count.u64 = 833; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CacheHits : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheMisses : Accumulator : Sum.u64 = 1903; SumSQ.u64 = 1903; Count.u64 = 1903; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_E : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_PutE : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 6292; SumSQ.u64 = 6292; Count.u64 = 6292; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 2085; SumSQ.u64 = 2085; Count.u64 = 2085; Min.u64 = 1; Max.u64 = 1; + l2cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetS_recv : Accumulator : Sum.u64 = 1041; SumSQ.u64 = 1041; Count.u64 = 1041; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetX_recv : Accumulator : Sum.u64 = 840; SumSQ.u64 = 840; Count.u64 = 840; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSX_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 1793; SumSQ.u64 = 1793; Count.u64 = 1793; Min.u64 = 1; Max.u64 = 1; + l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutS_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutM_recv : Accumulator : Sum.u64 = 826; SumSQ.u64 = 826; Count.u64 = 826; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutE_recv : Accumulator : Sum.u64 = 943; SumSQ.u64 = 943; Count.u64 = 943; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Inv_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache2.NACK_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckInv_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 684450; SumSQ.u64 = 7798860; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 16; + l2cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_I : Accumulator : Sum.u64 = 1692; SumSQ.u64 = 1692; Count.u64 = 1692; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_S : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_M : Accumulator : Sum.u64 = 614; SumSQ.u64 = 614; Count.u64 = 614; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1221; SumSQ.u64 = 1221; Count.u64 = 1221; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 1116; SumSQ.u64 = 1116; Count.u64 = 1116; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 654; SumSQ.u64 = 654; Count.u64 = 654; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 109; SumSQ.u64 = 109; Count.u64 = 109; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 607; SumSQ.u64 = 607; Count.u64 = 607; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 2104; SumSQ.u64 = 2104; Count.u64 = 2104; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 972; SumSQ.u64 = 972; Count.u64 = 972; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSX : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 117; SumSQ.u64 = 117; Count.u64 = 117; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 614; SumSQ.u64 = 614; Count.u64 = 614; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 1785; SumSQ.u64 = 1785; Count.u64 = 1785; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 50; SumSQ.u64 = 210; Count.u64 = 12; Min.u64 = 4; Max.u64 = 5; + l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 429365; SumSQ.u64 = 167578461; Count.u64 = 1221; Min.u64 = 15; Max.u64 = 925; + l2cache3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 16; SumSQ.u64 = 64; Count.u64 = 4; Min.u64 = 4; Max.u64 = 4; + l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 220210; SumSQ.u64 = 83534378; Count.u64 = 635; Min.u64 = 16; Max.u64 = 666; + l2cache3.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 6521; SumSQ.u64 = 2391129; Count.u64 = 19; Min.u64 = 277; Max.u64 = 663; + l2cache3.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1221; SumSQ.u64 = 1221; Count.u64 = 1221; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 635; SumSQ.u64 = 635; Count.u64 = 635; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CacheHits : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache3.CacheMisses : Accumulator : Sum.u64 = 1875; SumSQ.u64 = 1875; Count.u64 = 1875; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_E : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_E : Accumulator : Sum.u64 = 1109; SumSQ.u64 = 1109; Count.u64 = 1109; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_PutE : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 7438; SumSQ.u64 = 7438; Count.u64 = 7438; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1905; SumSQ.u64 = 1905; Count.u64 = 1905; Min.u64 = 1; Max.u64 = 1; + l2cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetS_recv : Accumulator : Sum.u64 = 1233; SumSQ.u64 = 1233; Count.u64 = 1233; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetX_recv : Accumulator : Sum.u64 = 639; SumSQ.u64 = 639; Count.u64 = 639; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 105; SumSQ.u64 = 105; Count.u64 = 105; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 1770; SumSQ.u64 = 1770; Count.u64 = 1770; Min.u64 = 1; Max.u64 = 1; + l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutS_recv : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutM_recv : Accumulator : Sum.u64 = 622; SumSQ.u64 = 622; Count.u64 = 622; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutE_recv : Accumulator : Sum.u64 = 1127; SumSQ.u64 = 1127; Count.u64 = 1127; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Inv_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l2cache3.NACK_recv : Accumulator : Sum.u64 = 1234; SumSQ.u64 = 1234; Count.u64 = 1234; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckInv_recv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 752225; SumSQ.u64 = 8304393; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 16; + l2cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 7033; SumSQ.u64 = 7033; Count.u64 = 7033; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IM : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 2919; Count.u64 = 2919; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4273; SumSQ.u64 = 4273; Count.u64 = 4273; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2673; SumSQ.u64 = 2673; Count.u64 = 2673; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4273; SumSQ.u64 = 4273; Count.u64 = 4273; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2783; SumSQ.u64 = 2783; Count.u64 = 2783; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 2669; SumSQ.u64 = 2669; Count.u64 = 2669; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 4273; SumSQ.u64 = 4273; Count.u64 = 4273; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 2673; SumSQ.u64 = 2673; Count.u64 = 2673; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2912; SumSQ.u64 = 2912; Count.u64 = 2912; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 540; SumSQ.u64 = 540; Count.u64 = 540; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 1316; SumSQ.u64 = 1316; Count.u64 = 1316; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 7104; SumSQ.u64 = 7104; Count.u64 = 7104; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 540; SumSQ.u64 = 540; Count.u64 = 540; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 21687; SumSQ.u64 = 5794295; Count.u64 = 122; Min.u64 = 6; Max.u64 = 420; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 1292623; SumSQ.u64 = 396377855; Count.u64 = 4273; Min.u64 = 44; Max.u64 = 466; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 15194; SumSQ.u64 = 3544122; Count.u64 = 166; Min.u64 = 16; Max.u64 = 389; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 160; SumSQ.u64 = 1280; Count.u64 = 20; Min.u64 = 8; Max.u64 = 8; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 813041; SumSQ.u64 = 250685145; Count.u64 = 2673; Min.u64 = 264; Max.u64 = 453; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 28064; SumSQ.u64 = 7462374; Count.u64 = 179; Min.u64 = 16; Max.u64 = 408; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 32940; SumSQ.u64 = 9994760; Count.u64 = 110; Min.u64 = 268; Max.u64 = 410; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 426965; Count.u64 = 7; Min.u64 = 17; Max.u64 = 341; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 4266; SumSQ.u64 = 4266; Count.u64 = 4266; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 2668; SumSQ.u64 = 2668; Count.u64 = 2668; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CacheHits : Accumulator : Sum.u64 = 495; SumSQ.u64 = 495; Count.u64 = 495; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 7056; SumSQ.u64 = 7056; Count.u64 = 7056; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 6977; SumSQ.u64 = 6977; Count.u64 = 6977; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_E : Accumulator : Sum.u64 = 4070; SumSQ.u64 = 4070; Count.u64 = 4070; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 172; SumSQ.u64 = 172; Count.u64 = 172; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 3961; SumSQ.u64 = 3961; Count.u64 = 3961; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 4065; SumSQ.u64 = 4065; Count.u64 = 4065; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 31661; SumSQ.u64 = 31661; Count.u64 = 31661; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 7954; SumSQ.u64 = 7954; Count.u64 = 7954; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 5471; SumSQ.u64 = 5471; Count.u64 = 5471; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 3215; SumSQ.u64 = 3215; Count.u64 = 3215; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 7056; SumSQ.u64 = 7056; Count.u64 = 7056; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache.PutS_recv : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + l3cache.PutM_recv : Accumulator : Sum.u64 = 2822; SumSQ.u64 = 2822; Count.u64 = 2822; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 3971; SumSQ.u64 = 3971; Count.u64 = 3971; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 540; SumSQ.u64 = 540; Count.u64 = 540; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 6977; SumSQ.u64 = 6977; Count.u64 = 6977; Min.u64 = 1; Max.u64 = 1; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 2402124; SumSQ.u64 = 79467190; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 47; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_I : Accumulator : Sum.u64 = 5760; SumSQ.u64 = 5760; Count.u64 = 5760; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_M : Accumulator : Sum.u64 = 2910; SumSQ.u64 = 2910; Count.u64 = 2910; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4272; SumSQ.u64 = 4272; Count.u64 = 4272; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 7054; SumSQ.u64 = 7054; Count.u64 = 7054; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_I : Accumulator : Sum.u64 = 2910; SumSQ.u64 = 2910; Count.u64 = 2910; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetS : Accumulator : Sum.u64 = 4272; SumSQ.u64 = 4272; Count.u64 = 4272; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetX : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutM : Accumulator : Sum.u64 = 2910; SumSQ.u64 = 2910; Count.u64 = 2910; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAll : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_AckFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetXResp : Accumulator : Sum.u64 = 7056; SumSQ.u64 = 7056; Count.u64 = 7056; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckPut : Accumulator : Sum.u64 = 6977; SumSQ.u64 = 6977; Count.u64 = 6977; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetS_hit : Accumulator : Sum.u64 = 8; SumSQ.u64 = 64; Count.u64 = 1; Min.u64 = 8; Max.u64 = 8; + l4cache.latency_GetS_miss : Accumulator : Sum.u64 = 1245185; SumSQ.u64 = 368198133; Count.u64 = 4272; Min.u64 = 257; Max.u64 = 439; + l4cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_hit : Accumulator : Sum.u64 = 8; SumSQ.u64 = 64; Count.u64 = 1; Min.u64 = 8; Max.u64 = 8; + l4cache.latency_GetX_miss : Accumulator : Sum.u64 = 783128; SumSQ.u64 = 232903994; Count.u64 = 2672; Min.u64 = 257; Max.u64 = 442; + l4cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_miss : Accumulator : Sum.u64 = 31730; SumSQ.u64 = 9283390; Count.u64 = 110; Min.u64 = 257; Max.u64 = 399; + l4cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 4272; SumSQ.u64 = 4272; Count.u64 = 4272; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CacheHits : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l4cache.CacheMisses : Accumulator : Sum.u64 = 7054; SumSQ.u64 = 7054; Count.u64 = 7054; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 6975; SumSQ.u64 = 6975; Count.u64 = 6975; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_E : Accumulator : Sum.u64 = 4065; SumSQ.u64 = 4065; Count.u64 = 4065; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_I : Accumulator : Sum.u64 = 4065; SumSQ.u64 = 4065; Count.u64 = 4065; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutE : Accumulator : Sum.u64 = 4065; SumSQ.u64 = 4065; Count.u64 = 4065; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReceived : Accumulator : Sum.u64 = 28786; SumSQ.u64 = 28786; Count.u64 = 28786; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReplayed : Accumulator : Sum.u64 = 6029; SumSQ.u64 = 6029; Count.u64 = 6029; Min.u64 = 1; Max.u64 = 1; + l4cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_recv : Accumulator : Sum.u64 = 4273; SumSQ.u64 = 4273; Count.u64 = 4273; Min.u64 = 1; Max.u64 = 1; + l4cache.GetX_recv : Accumulator : Sum.u64 = 2673; SumSQ.u64 = 2673; Count.u64 = 2673; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAll_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXResp_recv : Accumulator : Sum.u64 = 7054; SumSQ.u64 = 7054; Count.u64 = 7054; Min.u64 = 1; Max.u64 = 1; + l4cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAllResp_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.PutM_recv : Accumulator : Sum.u64 = 2912; SumSQ.u64 = 2912; Count.u64 = 2912; Min.u64 = 1; Max.u64 = 1; + l4cache.PutE_recv : Accumulator : Sum.u64 = 4065; SumSQ.u64 = 4065; Count.u64 = 4065; Min.u64 = 1; Max.u64 = 1; + l4cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForwardFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.AckFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.UnblockFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l4cache.NACK_recv : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l4cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckPut_recv : Accumulator : Sum.u64 = 6975; SumSQ.u64 = 6975; Count.u64 = 6975; Min.u64 = 1; Max.u64 = 1; + l4cache.MSHR_occupancy : Accumulator : Sum.u64 = 2215847; SumSQ.u64 = 69500629; Count.u64 = 116009; Min.u64 = 0; Max.u64 = 48; + l4cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 188141; SumSQ.u64 = 33603315; Count.u64 = 7110; Min.u64 = 2; Max.u64 = 907; + directory.get_request_latency : Accumulator : Sum.u64 = 1321663; SumSQ.u64 = 251451771; Count.u64 = 7054; Min.u64 = 165; Max.u64 = 287; + directory.directory_cache_hits : Accumulator : Sum.u64 = 14029; SumSQ.u64 = 14029; Count.u64 = 14029; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 4272; SumSQ.u64 = 4272; Count.u64 = 4272; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 2910; SumSQ.u64 = 2910; Count.u64 = 2910; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 4065; SumSQ.u64 = 4065; Count.u64 = 4065; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 7054; SumSQ.u64 = 7054; Count.u64 = 7054; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckFlush_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 4272; SumSQ.u64 = 4272; Count.u64 = 4272; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 2672; SumSQ.u64 = 2672; Count.u64 = 2672; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 2910; SumSQ.u64 = 2910; Count.u64 = 2910; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 7054; SumSQ.u64 = 7054; Count.u64 = 7054; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 6975; SumSQ.u64 = 6975; Count.u64 = 6975; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 1357128; SumSQ.u64 = 41510108; Count.u64 = 77254; Min.u64 = 0; Max.u64 = 47; +Simulation is complete, simulated time: 38.631 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case1_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case1_mesi.out new file mode 100644 index 0000000000..244380e50a --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case1_mesi.out @@ -0,0 +1,2149 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache2: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l4cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 2316947; SumSQ.u64 = 36916053; Count.u64 = 146952; Min.u64 = 0; Max.u64 = 16; + core0.reads : Accumulator : Sum.u64 = 1177; SumSQ.u64 = 1177; Count.u64 = 1177; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 728; SumSQ.u64 = 728; Count.u64 = 728; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 2773302; SumSQ.u64 = 44269104; Count.u64 = 174189; Min.u64 = 0; Max.u64 = 16; + core1.reads : Accumulator : Sum.u64 = 1247; SumSQ.u64 = 1247; Count.u64 = 1247; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + core2.pendCycle : Accumulator : Sum.u64 = 2493468; SumSQ.u64 = 39814580; Count.u64 = 156618; Min.u64 = 0; Max.u64 = 16; + core2.reads : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; + core2.writes : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + core2.flushcaches : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + core2.llsc : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + core2.llsc_success : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + core3.pendCycle : Accumulator : Sum.u64 = 2806931; SumSQ.u64 = 44837735; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 16; + core3.reads : Accumulator : Sum.u64 = 1251; SumSQ.u64 = 1251; Count.u64 = 1251; Min.u64 = 1; Max.u64 = 1; + core3.writes : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; + core3.flushcaches : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + core3.llsc : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + core3.llsc_success : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 713; SumSQ.u64 = 713; Count.u64 = 713; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 600; SumSQ.u64 = 600; Count.u64 = 600; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 755; SumSQ.u64 = 755; Count.u64 = 755; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 719; SumSQ.u64 = 719; Count.u64 = 719; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 409; SumSQ.u64 = 409; Count.u64 = 409; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1177; SumSQ.u64 = 1177; Count.u64 = 1177; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2027; SumSQ.u64 = 2027; Count.u64 = 2027; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 25335; SumSQ.u64 = 28037555; Count.u64 = 36; Min.u64 = 2; Max.u64 = 1940; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 1340605; SumSQ.u64 = 2049881269; Count.u64 = 1141; Min.u64 = 8; Max.u64 = 4457; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 13945; SumSQ.u64 = 16085215; Count.u64 = 19; Min.u64 = 2; Max.u64 = 2089; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 836522; SumSQ.u64 = 1291058556; Count.u64 = 713; Min.u64 = 13; Max.u64 = 4699; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 8747; SumSQ.u64 = 15349631; Count.u64 = 6; Min.u64 = 328; Max.u64 = 2190; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 43452; SumSQ.u64 = 67386416; Count.u64 = 35; Min.u64 = 303; Max.u64 = 2926; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 2016; SumSQ.u64 = 2032146; Count.u64 = 2; Min.u64 = 1005; Max.u64 = 1011; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 228; SumSQ.u64 = 228; Count.u64 = 228; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 1897; SumSQ.u64 = 1897; Count.u64 = 1897; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 493; SumSQ.u64 = 493; Count.u64 = 493; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 493; SumSQ.u64 = 493; Count.u64 = 493; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 6157; SumSQ.u64 = 6157; Count.u64 = 6157; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2179; SumSQ.u64 = 2179; Count.u64 = 2179; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1177; SumSQ.u64 = 1177; Count.u64 = 1177; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 600; SumSQ.u64 = 600; Count.u64 = 600; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1297; SumSQ.u64 = 1297; Count.u64 = 1297; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 430; SumSQ.u64 = 430; Count.u64 = 430; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 351; SumSQ.u64 = 351; Count.u64 = 351; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 963744; SumSQ.u64 = 11714714; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 15; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1205; SumSQ.u64 = 1205; Count.u64 = 1205; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 636; SumSQ.u64 = 636; Count.u64 = 636; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 648; SumSQ.u64 = 648; Count.u64 = 648; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 659; SumSQ.u64 = 659; Count.u64 = 659; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1205; SumSQ.u64 = 1205; Count.u64 = 1205; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1247; SumSQ.u64 = 1247; Count.u64 = 1247; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2005; SumSQ.u64 = 2005; Count.u64 = 2005; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 415; SumSQ.u64 = 415; Count.u64 = 415; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 247; SumSQ.u64 = 247; Count.u64 = 247; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 23909; SumSQ.u64 = 23798611; Count.u64 = 42; Min.u64 = 2; Max.u64 = 1925; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 1655994; SumSQ.u64 = 3548151594; Count.u64 = 1205; Min.u64 = 17; Max.u64 = 7609; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 9395; SumSQ.u64 = 11953587; Count.u64 = 18; Min.u64 = 2; Max.u64 = 2694; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 893126; SumSQ.u64 = 1926974174; Count.u64 = 636; Min.u64 = 36; Max.u64 = 7074; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 9174; SumSQ.u64 = 18215988; Count.u64 = 6; Min.u64 = 51; Max.u64 = 2632; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 22111; SumSQ.u64 = 36423197; Count.u64 = 17; Min.u64 = 321; Max.u64 = 2751; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 3638; SumSQ.u64 = 13235044; Count.u64 = 1; Min.u64 = 3638; Max.u64 = 3638; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 948; SumSQ.u64 = 948; Count.u64 = 948; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 127; SumSQ.u64 = 127; Count.u64 = 127; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 60; SumSQ.u64 = 60; Count.u64 = 60; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 1865; SumSQ.u64 = 1865; Count.u64 = 1865; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1191; SumSQ.u64 = 1191; Count.u64 = 1191; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 6109; SumSQ.u64 = 6109; Count.u64 = 6109; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2282; SumSQ.u64 = 2282; Count.u64 = 2282; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1247; SumSQ.u64 = 1247; Count.u64 = 1247; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 1308; SumSQ.u64 = 1308; Count.u64 = 1308; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 1191; SumSQ.u64 = 1191; Count.u64 = 1191; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1104445; SumSQ.u64 = 12882909; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 15; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 904; SumSQ.u64 = 904; Count.u64 = 904; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 597; SumSQ.u64 = 597; Count.u64 = 597; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_I : Accumulator : Sum.u64 = 2046; SumSQ.u64 = 2046; Count.u64 = 2046; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_S : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_M : Accumulator : Sum.u64 = 597; SumSQ.u64 = 597; Count.u64 = 597; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IS : Accumulator : Sum.u64 = 278; SumSQ.u64 = 278; Count.u64 = 278; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IM : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 26655; SumSQ.u64 = 46373575; Count.u64 = 28; Min.u64 = 2; Max.u64 = 3106; + l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 1237253; SumSQ.u64 = 1991188643; Count.u64 = 997; Min.u64 = 29; Max.u64 = 4420; + l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 18438; SumSQ.u64 = 22875740; Count.u64 = 25; Min.u64 = 2; Max.u64 = 3109; + l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 1114531; SumSQ.u64 = 1858183937; Count.u64 = 857; Min.u64 = 29; Max.u64 = 4650; + l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 5049; SumSQ.u64 = 6821243; Count.u64 = 5; Min.u64 = 36; Max.u64 = 1791; + l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 53462; SumSQ.u64 = 90873852; Count.u64 = 43; Min.u64 = 319; Max.u64 = 4144; + l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 793; SumSQ.u64 = 793; Count.u64 = 793; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 684; SumSQ.u64 = 684; Count.u64 = 684; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 178; SumSQ.u64 = 178; Count.u64 = 178; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheHits : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheMisses : Accumulator : Sum.u64 = 1902; SumSQ.u64 = 1902; Count.u64 = 1902; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_E : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 6118; SumSQ.u64 = 6118; Count.u64 = 6118; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 2273; SumSQ.u64 = 2273; Count.u64 = 2273; Min.u64 = 1; Max.u64 = 1; + l1cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_recv : Accumulator : Sum.u64 = 1025; SumSQ.u64 = 1025; Count.u64 = 1025; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_recv : Accumulator : Sum.u64 = 917; SumSQ.u64 = 917; Count.u64 = 917; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1479; SumSQ.u64 = 1479; Count.u64 = 1479; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.Inv_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckPut_recv : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; + l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 1146100; SumSQ.u64 = 13942532; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 15; + l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1225; SumSQ.u64 = 1225; Count.u64 = 1225; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 828; SumSQ.u64 = 828; Count.u64 = 828; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 689; SumSQ.u64 = 689; Count.u64 = 689; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 159; SumSQ.u64 = 159; Count.u64 = 159; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 1225; SumSQ.u64 = 1225; Count.u64 = 1225; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 521; SumSQ.u64 = 521; Count.u64 = 521; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1251; SumSQ.u64 = 1251; Count.u64 = 1251; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_I : Accumulator : Sum.u64 = 2078; SumSQ.u64 = 2078; Count.u64 = 2078; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_S : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_M : Accumulator : Sum.u64 = 521; SumSQ.u64 = 521; Count.u64 = 521; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IS : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IM : Accumulator : Sum.u64 = 238; SumSQ.u64 = 238; Count.u64 = 238; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 25976; SumSQ.u64 = 35067534; Count.u64 = 26; Min.u64 = 2; Max.u64 = 2018; + l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 1725447; SumSQ.u64 = 3479244159; Count.u64 = 1225; Min.u64 = 9; Max.u64 = 6788; + l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 13008; SumSQ.u64 = 12827962; Count.u64 = 20; Min.u64 = 2; Max.u64 = 1489; + l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 934551; SumSQ.u64 = 1823772455; Count.u64 = 669; Min.u64 = 63; Max.u64 = 5939; + l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 904; SumSQ.u64 = 817216; Count.u64 = 1; Min.u64 = 904; Max.u64 = 904; + l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 23791; SumSQ.u64 = 39483001; Count.u64 = 19; Min.u64 = 309; Max.u64 = 2941; + l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 986; SumSQ.u64 = 986; Count.u64 = 986; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheHits : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheMisses : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 76; SumSQ.u64 = 76; Count.u64 = 76; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_E : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 6134; SumSQ.u64 = 6134; Count.u64 = 6134; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 2444; SumSQ.u64 = 2444; Count.u64 = 2444; Min.u64 = 1; Max.u64 = 1; + l1cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_recv : Accumulator : Sum.u64 = 1251; SumSQ.u64 = 1251; Count.u64 = 1251; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_recv : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 1517; SumSQ.u64 = 1517; Count.u64 = 1517; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache3.Inv_recv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckPut_recv : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; + l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1297354; SumSQ.u64 = 15729148; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 15; + l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2926; SumSQ.u64 = 2926; Count.u64 = 2926; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 857735; SumSQ.u64 = 21471845; Count.u64 = 58545; Min.u64 = 0; Max.u64 = 50; + memory.latency_GetS : Accumulator : Sum.u64 = 368839; SumSQ.u64 = 31490717; Count.u64 = 4336; Min.u64 = 81; Max.u64 = 104; + memory.latency_GetSX : Accumulator : Sum.u64 = 9480; SumSQ.u64 = 820856; Count.u64 = 110; Min.u64 = 81; Max.u64 = 102; + memory.latency_GetX : Accumulator : Sum.u64 = 236673; SumSQ.u64 = 20297827; Count.u64 = 2771; Min.u64 = 81; Max.u64 = 105; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 242743; SumSQ.u64 = 20153287; Count.u64 = 2926; Min.u64 = 81; Max.u64 = 96; + memory.cycles_with_issue : Accumulator : Sum.u64 = 10143; SumSQ.u64 = 10143; Count.u64 = 10143; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 58545; SumSQ.u64 = 3427517025; Count.u64 = 1; Min.u64 = 58545; Max.u64 = 58545; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_S : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_M : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1140; SumSQ.u64 = 1140; Count.u64 = 1140; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 600; SumSQ.u64 = 600; Count.u64 = 600; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1294; SumSQ.u64 = 1294; Count.u64 = 1294; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_I : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_I : Accumulator : Sum.u64 = 440; SumSQ.u64 = 440; Count.u64 = 440; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 442; SumSQ.u64 = 442; Count.u64 = 442; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 360; SumSQ.u64 = 360; Count.u64 = 360; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 112; SumSQ.u64 = 112; Count.u64 = 112; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 331; SumSQ.u64 = 331; Count.u64 = 331; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 409; SumSQ.u64 = 409; Count.u64 = 409; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1161; SumSQ.u64 = 1161; Count.u64 = 1161; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 725; SumSQ.u64 = 725; Count.u64 = 725; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 588; SumSQ.u64 = 588; Count.u64 = 588; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 600; SumSQ.u64 = 600; Count.u64 = 600; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1297; SumSQ.u64 = 1297; Count.u64 = 1297; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 351; SumSQ.u64 = 351; Count.u64 = 351; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 430; SumSQ.u64 = 430; Count.u64 = 430; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 1154; SumSQ.u64 = 1154; Count.u64 = 1154; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 432532; SumSQ.u64 = 198110016; Count.u64 = 1140; Min.u64 = 15; Max.u64 = 1198; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 8; SumSQ.u64 = 32; Count.u64 = 2; Min.u64 = 4; Max.u64 = 4; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 279987; SumSQ.u64 = 136495733; Count.u64 = 717; Min.u64 = 30; Max.u64 = 1735; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 14755; SumSQ.u64 = 8899745; Count.u64 = 37; Min.u64 = 50; Max.u64 = 1818; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1140; SumSQ.u64 = 1140; Count.u64 = 1140; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 1894; SumSQ.u64 = 1894; Count.u64 = 1894; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 781; SumSQ.u64 = 781; Count.u64 = 781; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_I : Accumulator : Sum.u64 = 493; SumSQ.u64 = 493; Count.u64 = 493; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8141; SumSQ.u64 = 8141; Count.u64 = 8141; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1063; SumSQ.u64 = 1063; Count.u64 = 1063; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1141; SumSQ.u64 = 1141; Count.u64 = 1141; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 719; SumSQ.u64 = 719; Count.u64 = 719; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 600; SumSQ.u64 = 600; Count.u64 = 600; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 1294; SumSQ.u64 = 1294; Count.u64 = 1294; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 220; SumSQ.u64 = 220; Count.u64 = 220; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 493; SumSQ.u64 = 493; Count.u64 = 493; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 600; SumSQ.u64 = 600; Count.u64 = 600; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 333; SumSQ.u64 = 333; Count.u64 = 333; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 409; SumSQ.u64 = 409; Count.u64 = 409; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 781; SumSQ.u64 = 781; Count.u64 = 781; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 837073; SumSQ.u64 = 8628373; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 16; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 1143; SumSQ.u64 = 1143; Count.u64 = 1143; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_S : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_M : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1203; SumSQ.u64 = 1203; Count.u64 = 1203; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1305; SumSQ.u64 = 1305; Count.u64 = 1305; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_I : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_I : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 404; SumSQ.u64 = 404; Count.u64 = 404; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 314; SumSQ.u64 = 314; Count.u64 = 314; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 124; SumSQ.u64 = 124; Count.u64 = 124; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 300; SumSQ.u64 = 300; Count.u64 = 300; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1217; SumSQ.u64 = 1217; Count.u64 = 1217; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 649; SumSQ.u64 = 649; Count.u64 = 649; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 281; SumSQ.u64 = 281; Count.u64 = 281; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 66; SumSQ.u64 = 66; Count.u64 = 66; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1308; SumSQ.u64 = 1308; Count.u64 = 1308; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 1191; SumSQ.u64 = 1191; Count.u64 = 1191; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 8; SumSQ.u64 = 32; Count.u64 = 2; Min.u64 = 4; Max.u64 = 4; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 485966; SumSQ.u64 = 240739882; Count.u64 = 1203; Min.u64 = 12; Max.u64 = 1516; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 271287; SumSQ.u64 = 144933639; Count.u64 = 641; Min.u64 = 24; Max.u64 = 1770; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 8192; SumSQ.u64 = 5215552; Count.u64 = 18; Min.u64 = 278; Max.u64 = 1181; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1203; SumSQ.u64 = 1203; Count.u64 = 1203; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 1862; SumSQ.u64 = 1862; Count.u64 = 1862; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_I : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8048; SumSQ.u64 = 8048; Count.u64 = 8048; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1063; SumSQ.u64 = 1063; Count.u64 = 1063; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1205; SumSQ.u64 = 1205; Count.u64 = 1205; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 557; SumSQ.u64 = 557; Count.u64 = 557; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 1305; SumSQ.u64 = 1305; Count.u64 = 1305; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 543; SumSQ.u64 = 543; Count.u64 = 543; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 536; SumSQ.u64 = 536; Count.u64 = 536; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 795; SumSQ.u64 = 795; Count.u64 = 795; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 940590; SumSQ.u64 = 8938744; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 15; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_I : Accumulator : Sum.u64 = 1244; SumSQ.u64 = 1244; Count.u64 = 1244; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_S : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_M : Accumulator : Sum.u64 = 447; SumSQ.u64 = 447; Count.u64 = 447; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 994; SumSQ.u64 = 994; Count.u64 = 994; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1476; SumSQ.u64 = 1476; Count.u64 = 1476; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_I : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_I : Accumulator : Sum.u64 = 595; SumSQ.u64 = 595; Count.u64 = 595; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 297; SumSQ.u64 = 297; Count.u64 = 297; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 352; SumSQ.u64 = 352; Count.u64 = 352; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_I : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 1011; SumSQ.u64 = 1011; Count.u64 = 1011; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 879; SumSQ.u64 = 879; Count.u64 = 879; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSX : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 447; SumSQ.u64 = 447; Count.u64 = 447; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 534; SumSQ.u64 = 534; Count.u64 = 534; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 400; SumSQ.u64 = 400; Count.u64 = 400; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1479; SumSQ.u64 = 1479; Count.u64 = 1479; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 1274; SumSQ.u64 = 1274; Count.u64 = 1274; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 48; Count.u64 = 3; Min.u64 = 4; Max.u64 = 4; + l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 449177; SumSQ.u64 = 246615895; Count.u64 = 994; Min.u64 = 15; Max.u64 = 1490; + l2cache2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 391224; SumSQ.u64 = 219813058; Count.u64 = 862; Min.u64 = 23; Max.u64 = 1903; + l2cache2.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 17470; SumSQ.u64 = 8650662; Count.u64 = 43; Min.u64 = 50; Max.u64 = 1203; + l2cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 994; SumSQ.u64 = 994; Count.u64 = 994; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CacheHits : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheMisses : Accumulator : Sum.u64 = 1899; SumSQ.u64 = 1899; Count.u64 = 1899; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_E : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_I : Accumulator : Sum.u64 = 521; SumSQ.u64 = 521; Count.u64 = 521; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_PutE : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 8113; SumSQ.u64 = 8113; Count.u64 = 8113; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1202; SumSQ.u64 = 1202; Count.u64 = 1202; Min.u64 = 1; Max.u64 = 1; + l2cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetS_recv : Accumulator : Sum.u64 = 997; SumSQ.u64 = 997; Count.u64 = 997; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetX_recv : Accumulator : Sum.u64 = 862; SumSQ.u64 = 862; Count.u64 = 862; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSX_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 1476; SumSQ.u64 = 1476; Count.u64 = 1476; Min.u64 = 1; Max.u64 = 1; + l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutS_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutM_recv : Accumulator : Sum.u64 = 597; SumSQ.u64 = 597; Count.u64 = 597; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutE_recv : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Inv_recv : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 539; SumSQ.u64 = 539; Count.u64 = 539; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache2.NACK_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckInv_recv : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckPut_recv : Accumulator : Sum.u64 = 964; SumSQ.u64 = 964; Count.u64 = 964; Min.u64 = 1; Max.u64 = 1; + l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 978907; SumSQ.u64 = 10053505; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 16; + l2cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_I : Accumulator : Sum.u64 = 1356; SumSQ.u64 = 1356; Count.u64 = 1356; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_S : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_M : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1221; SumSQ.u64 = 1221; Count.u64 = 1221; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1511; SumSQ.u64 = 1511; Count.u64 = 1511; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_I : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_I : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 267; SumSQ.u64 = 267; Count.u64 = 267; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 111; SumSQ.u64 = 111; Count.u64 = 111; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_I : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 2067; SumSQ.u64 = 2067; Count.u64 = 2067; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 1271; SumSQ.u64 = 1271; Count.u64 = 1271; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSX : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 426; SumSQ.u64 = 426; Count.u64 = 426; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 1517; SumSQ.u64 = 1517; Count.u64 = 1517; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 262; SumSQ.u64 = 262; Count.u64 = 262; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 1413; SumSQ.u64 = 1413; Count.u64 = 1413; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 16; SumSQ.u64 = 64; Count.u64 = 4; Min.u64 = 4; Max.u64 = 4; + l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 610530; SumSQ.u64 = 379436960; Count.u64 = 1221; Min.u64 = 15; Max.u64 = 1838; + l2cache3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 8; SumSQ.u64 = 32; Count.u64 = 2; Min.u64 = 4; Max.u64 = 4; + l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 338232; SumSQ.u64 = 219510508; Count.u64 = 668; Min.u64 = 23; Max.u64 = 2649; + l2cache3.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 8616; SumSQ.u64 = 4810096; Count.u64 = 19; Min.u64 = 278; Max.u64 = 1177; + l2cache3.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1221; SumSQ.u64 = 1221; Count.u64 = 1221; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 668; SumSQ.u64 = 668; Count.u64 = 668; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CacheHits : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.CacheMisses : Accumulator : Sum.u64 = 1908; SumSQ.u64 = 1908; Count.u64 = 1908; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_E : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_I : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_PutE : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 9573; SumSQ.u64 = 9573; Count.u64 = 9573; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1353; SumSQ.u64 = 1353; Count.u64 = 1353; Min.u64 = 1; Max.u64 = 1; + l2cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetS_recv : Accumulator : Sum.u64 = 1225; SumSQ.u64 = 1225; Count.u64 = 1225; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetX_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 1511; SumSQ.u64 = 1511; Count.u64 = 1511; Min.u64 = 1; Max.u64 = 1; + l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutS_recv : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutM_recv : Accumulator : Sum.u64 = 521; SumSQ.u64 = 521; Count.u64 = 521; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutE_recv : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Inv_recv : Accumulator : Sum.u64 = 378; SumSQ.u64 = 378; Count.u64 = 378; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l2cache3.NACK_recv : Accumulator : Sum.u64 = 1467; SumSQ.u64 = 1467; Count.u64 = 1467; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckInv_recv : Accumulator : Sum.u64 = 256; SumSQ.u64 = 256; Count.u64 = 256; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckPut_recv : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; + l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1108558; SumSQ.u64 = 11265778; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 16; + l2cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 6451; SumSQ.u64 = 6451; Count.u64 = 6451; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 56; SumSQ.u64 = 56; Count.u64 = 56; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2728; SumSQ.u64 = 2728; Count.u64 = 2728; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 108; SumSQ.u64 = 108; Count.u64 = 108; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 1658; SumSQ.u64 = 1658; Count.u64 = 1658; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 2678; SumSQ.u64 = 2678; Count.u64 = 2678; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2881; SumSQ.u64 = 2881; Count.u64 = 2881; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1387; SumSQ.u64 = 1387; Count.u64 = 1387; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 1615; SumSQ.u64 = 1615; Count.u64 = 1615; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 1448; SumSQ.u64 = 1448; Count.u64 = 1448; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1412; SumSQ.u64 = 1412; Count.u64 = 1412; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 116; SumSQ.u64 = 116; Count.u64 = 116; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 1641; SumSQ.u64 = 1641; Count.u64 = 1641; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 3679; SumSQ.u64 = 3679; Count.u64 = 3679; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 1658; SumSQ.u64 = 1658; Count.u64 = 1658; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 1594; SumSQ.u64 = 1594; Count.u64 = 1594; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1977; SumSQ.u64 = 1977; Count.u64 = 1977; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5586; SumSQ.u64 = 5586; Count.u64 = 5586; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1997; SumSQ.u64 = 1997; Count.u64 = 1997; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 1924; SumSQ.u64 = 1924; Count.u64 = 1924; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 32850; SumSQ.u64 = 13651208; Count.u64 = 116; Min.u64 = 5; Max.u64 = 880; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 1811536; SumSQ.u64 = 924157950; Count.u64 = 4336; Min.u64 = 268; Max.u64 = 1509; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 31384; SumSQ.u64 = 16008550; Count.u64 = 106; Min.u64 = 16; Max.u64 = 928; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 1136205; SumSQ.u64 = 578929669; Count.u64 = 2728; Min.u64 = 268; Max.u64 = 1762; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 28900; SumSQ.u64 = 12296856; Count.u64 = 117; Min.u64 = 16; Max.u64 = 1084; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 46158; SumSQ.u64 = 54777864; Count.u64 = 43; Min.u64 = 602; Max.u64 = 2268; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 42527; SumSQ.u64 = 22114731; Count.u64 = 108; Min.u64 = 269; Max.u64 = 1811; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 2704; SumSQ.u64 = 1966344; Count.u64 = 7; Min.u64 = 42; Max.u64 = 1172; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1476; SumSQ.u64 = 1124136; Count.u64 = 2; Min.u64 = 606; Max.u64 = 870; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 4330; SumSQ.u64 = 4330; Count.u64 = 4330; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 2709; SumSQ.u64 = 2709; Count.u64 = 2709; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheHits : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 7217; SumSQ.u64 = 7217; Count.u64 = 7217; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 3534; SumSQ.u64 = 3534; Count.u64 = 3534; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_E : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 75; SumSQ.u64 = 75; Count.u64 = 75; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 2006; SumSQ.u64 = 2006; Count.u64 = 2006; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 587; SumSQ.u64 = 587; Count.u64 = 587; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 93; SumSQ.u64 = 93; Count.u64 = 93; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 32285; SumSQ.u64 = 32285; Count.u64 = 32285; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 8178; SumSQ.u64 = 8178; Count.u64 = 8178; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 5456; SumSQ.u64 = 5456; Count.u64 = 5456; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 3524; SumSQ.u64 = 3524; Count.u64 = 3524; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 1658; SumSQ.u64 = 1658; Count.u64 = 1658; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 5559; SumSQ.u64 = 5559; Count.u64 = 5559; Min.u64 = 1; Max.u64 = 1; + l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l3cache.PutS_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l3cache.PutM_recv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 2042; SumSQ.u64 = 2042; Count.u64 = 2042; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 1660; SumSQ.u64 = 1660; Count.u64 = 1660; Min.u64 = 1; Max.u64 = 1; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 2036; SumSQ.u64 = 2036; Count.u64 = 2036; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 1975; SumSQ.u64 = 1975; Count.u64 = 1975; Min.u64 = 1; Max.u64 = 1; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 524; SumSQ.u64 = 524; Count.u64 = 524; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 1896; SumSQ.u64 = 1896; Count.u64 = 1896; Min.u64 = 1; Max.u64 = 1; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 3534; SumSQ.u64 = 3534; Count.u64 = 3534; Min.u64 = 1; Max.u64 = 1; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 3528679; SumSQ.u64 = 112112303; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 50; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_I : Accumulator : Sum.u64 = 8338; SumSQ.u64 = 8338; Count.u64 = 8338; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IS : Accumulator : Sum.u64 = 2176; SumSQ.u64 = 2176; Count.u64 = 2176; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IM : Accumulator : Sum.u64 = 1330; SumSQ.u64 = 1330; Count.u64 = 1330; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_M : Accumulator : Sum.u64 = 2878; SumSQ.u64 = 2878; Count.u64 = 2878; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_MInv : Accumulator : Sum.u64 = 446; SumSQ.u64 = 446; Count.u64 = 446; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2881; SumSQ.u64 = 2881; Count.u64 = 2881; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1439; SumSQ.u64 = 1439; Count.u64 = 1439; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 7207; SumSQ.u64 = 7207; Count.u64 = 7207; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetS : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetX : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutM : Accumulator : Sum.u64 = 2926; SumSQ.u64 = 2926; Count.u64 = 2926; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAll : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_AckFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1658; SumSQ.u64 = 1658; Count.u64 = 1658; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5559; SumSQ.u64 = 5559; Count.u64 = 5559; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Inv : Accumulator : Sum.u64 = 1660; SumSQ.u64 = 1660; Count.u64 = 1660; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchInv : Accumulator : Sum.u64 = 2036; SumSQ.u64 = 2036; Count.u64 = 2036; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckPut : Accumulator : Sum.u64 = 3534; SumSQ.u64 = 3534; Count.u64 = 3534; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetS_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetS_miss : Accumulator : Sum.u64 = 1763257; SumSQ.u64 = 883654173; Count.u64 = 4336; Min.u64 = 257; Max.u64 = 1498; + l4cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_miss : Accumulator : Sum.u64 = 1135366; SumSQ.u64 = 575372826; Count.u64 = 2771; Min.u64 = 257; Max.u64 = 1738; + l4cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_miss : Accumulator : Sum.u64 = 42466; SumSQ.u64 = 21805360; Count.u64 = 110; Min.u64 = 258; Max.u64 = 1800; + l4cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 2131; SumSQ.u64 = 2131; Count.u64 = 2131; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1378; SumSQ.u64 = 1378; Count.u64 = 1378; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 2205; SumSQ.u64 = 2205; Count.u64 = 2205; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 1393; SumSQ.u64 = 1393; Count.u64 = 1393; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l4cache.CacheHits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CacheMisses : Accumulator : Sum.u64 = 7217; SumSQ.u64 = 7217; Count.u64 = 7217; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_E : Accumulator : Sum.u64 = 4468; SumSQ.u64 = 4468; Count.u64 = 4468; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_EInv : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 1658; SumSQ.u64 = 1658; Count.u64 = 1658; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutE : Accumulator : Sum.u64 = 4281; SumSQ.u64 = 4281; Count.u64 = 4281; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReceived : Accumulator : Sum.u64 = 29542; SumSQ.u64 = 29542; Count.u64 = 29542; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReplayed : Accumulator : Sum.u64 = 14488; SumSQ.u64 = 14488; Count.u64 = 14488; Min.u64 = 1; Max.u64 = 1; + l4cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_recv : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + l4cache.GetX_recv : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + l4cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAll_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXResp_recv : Accumulator : Sum.u64 = 7217; SumSQ.u64 = 7217; Count.u64 = 7217; Min.u64 = 1; Max.u64 = 1; + l4cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAllResp_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.PutM_recv : Accumulator : Sum.u64 = 1487; SumSQ.u64 = 1487; Count.u64 = 1487; Min.u64 = 1; Max.u64 = 1; + l4cache.PutE_recv : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; + l4cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchResp_recv : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; + l4cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForwardFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.AckFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.UnblockFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l4cache.NACK_recv : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; + l4cache.AckInv_recv : Accumulator : Sum.u64 = 1658; SumSQ.u64 = 1658; Count.u64 = 1658; Min.u64 = 1; Max.u64 = 1; + l4cache.AckPut_recv : Accumulator : Sum.u64 = 7207; SumSQ.u64 = 7207; Count.u64 = 7207; Min.u64 = 1; Max.u64 = 1; + l4cache.MSHR_occupancy : Accumulator : Sum.u64 = 3203981; SumSQ.u64 = 94288783; Count.u64 = 175811; Min.u64 = 0; Max.u64 = 47; + l4cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 132612; SumSQ.u64 = 75309086; Count.u64 = 7338; Min.u64 = 2; Max.u64 = 1214; + directory.get_request_latency : Accumulator : Sum.u64 = 1258309; SumSQ.u64 = 220255689; Count.u64 = 7217; Min.u64 = 165; Max.u64 = 216; + directory.directory_cache_hits : Accumulator : Sum.u64 = 14424; SumSQ.u64 = 14424; Count.u64 = 14424; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 2926; SumSQ.u64 = 2926; Count.u64 = 2926; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 4281; SumSQ.u64 = 4281; Count.u64 = 4281; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 7217; SumSQ.u64 = 7217; Count.u64 = 7217; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckFlush_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 4336; SumSQ.u64 = 4336; Count.u64 = 4336; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 2771; SumSQ.u64 = 2771; Count.u64 = 2771; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 2926; SumSQ.u64 = 2926; Count.u64 = 2926; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 7217; SumSQ.u64 = 7217; Count.u64 = 7217; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 7207; SumSQ.u64 = 7207; Count.u64 = 7207; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 1336590; SumSQ.u64 = 24487504; Count.u64 = 117082; Min.u64 = 0; Max.u64 = 34; +Simulation is complete, simulated time: 58.5451 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case2_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case2_mesi.out new file mode 100644 index 0000000000..ad17e5d39c --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case2_mesi.out @@ -0,0 +1,1529 @@ +l2cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l4cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 2891907; SumSQ.u64 = 46202263; Count.u64 = 181463; Min.u64 = 0; Max.u64 = 16; + core0.reads : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 760; SumSQ.u64 = 760; Count.u64 = 760; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 3872492; SumSQ.u64 = 61801222; Count.u64 = 243283; Min.u64 = 0; Max.u64 = 16; + core1.reads : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + core2.pendCycle : Accumulator : Sum.u64 = 3853006; SumSQ.u64 = 61582532; Count.u64 = 241320; Min.u64 = 0; Max.u64 = 16; + core2.reads : Accumulator : Sum.u64 = 1069; SumSQ.u64 = 1069; Count.u64 = 1069; Min.u64 = 1; Max.u64 = 1; + core2.writes : Accumulator : Sum.u64 = 846; SumSQ.u64 = 846; Count.u64 = 846; Min.u64 = 1; Max.u64 = 1; + core2.flushcaches : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + core2.llsc : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + core2.llsc_success : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + core3.pendCycle : Accumulator : Sum.u64 = 4321503; SumSQ.u64 = 69096113; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 16; + core3.reads : Accumulator : Sum.u64 = 1255; SumSQ.u64 = 1255; Count.u64 = 1255; Min.u64 = 1; Max.u64 = 1; + core3.writes : Accumulator : Sum.u64 = 660; SumSQ.u64 = 660; Count.u64 = 660; Min.u64 = 1; Max.u64 = 1; + core3.flushcaches : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + core3.llsc : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + core3.llsc_success : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1148; SumSQ.u64 = 1148; Count.u64 = 1148; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 403; SumSQ.u64 = 403; Count.u64 = 403; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 767; SumSQ.u64 = 767; Count.u64 = 767; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 222; SumSQ.u64 = 222; Count.u64 = 222; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 443; SumSQ.u64 = 443; Count.u64 = 443; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1473; SumSQ.u64 = 1473; Count.u64 = 1473; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 996; SumSQ.u64 = 996; Count.u64 = 996; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2172; SumSQ.u64 = 2172; Count.u64 = 2172; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 22037; SumSQ.u64 = 37212217; Count.u64 = 31; Min.u64 = 2; Max.u64 = 3638; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 1675564; SumSQ.u64 = 3471226064; Count.u64 = 1148; Min.u64 = 21; Max.u64 = 5104; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 28080; SumSQ.u64 = 55085280; Count.u64 = 24; Min.u64 = 2; Max.u64 = 4174; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 1066437; SumSQ.u64 = 2207523353; Count.u64 = 734; Min.u64 = 19; Max.u64 = 5380; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 16461; SumSQ.u64 = 32188707; Count.u64 = 10; Min.u64 = 605; Max.u64 = 2847; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 36250; SumSQ.u64 = 71216876; Count.u64 = 23; Min.u64 = 545; Max.u64 = 4185; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 859; SumSQ.u64 = 859; Count.u64 = 859; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 289; SumSQ.u64 = 289; Count.u64 = 289; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 1915; SumSQ.u64 = 1915; Count.u64 = 1915; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 240; SumSQ.u64 = 240; Count.u64 = 240; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 7163; SumSQ.u64 = 7163; Count.u64 = 7163; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 2093; Count.u64 = 2093; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1179; SumSQ.u64 = 1179; Count.u64 = 1179; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 745; SumSQ.u64 = 745; Count.u64 = 745; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1170; SumSQ.u64 = 1170; Count.u64 = 1170; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 747; SumSQ.u64 = 747; Count.u64 = 747; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 654; SumSQ.u64 = 654; Count.u64 = 654; Min.u64 = 1; Max.u64 = 1; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 1187152; SumSQ.u64 = 14775224; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 15; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1185; SumSQ.u64 = 1185; Count.u64 = 1185; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 666; SumSQ.u64 = 666; Count.u64 = 666; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 451; SumSQ.u64 = 451; Count.u64 = 451; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 700; SumSQ.u64 = 700; Count.u64 = 700; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 441; SumSQ.u64 = 441; Count.u64 = 441; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 2216; SumSQ.u64 = 2216; Count.u64 = 2216; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 1218; SumSQ.u64 = 1218; Count.u64 = 1218; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 515; SumSQ.u64 = 515; Count.u64 = 515; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 706; SumSQ.u64 = 706; Count.u64 = 706; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 2201; SumSQ.u64 = 2201; Count.u64 = 2201; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 516; SumSQ.u64 = 516; Count.u64 = 516; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 248; SumSQ.u64 = 248; Count.u64 = 248; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 28941; SumSQ.u64 = 121377373; Count.u64 = 30; Min.u64 = 2; Max.u64 = 9418; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 2221455; SumSQ.u64 = 7714467221; Count.u64 = 1185; Min.u64 = 31; Max.u64 = 13146; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 15057; SumSQ.u64 = 29217031; Count.u64 = 19; Min.u64 = 2; Max.u64 = 4213; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 1331314; SumSQ.u64 = 4944692302; Count.u64 = 666; Min.u64 = 17; Max.u64 = 12886; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 14422; SumSQ.u64 = 45409034; Count.u64 = 7; Min.u64 = 328; Max.u64 = 5431; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 49014; SumSQ.u64 = 127864978; Count.u64 = 27; Min.u64 = 284; Max.u64 = 4323; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 146; SumSQ.u64 = 146; Count.u64 = 146; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 1885; SumSQ.u64 = 1885; Count.u64 = 1885; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 226; SumSQ.u64 = 226; Count.u64 = 226; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 283; SumSQ.u64 = 283; Count.u64 = 283; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 210; SumSQ.u64 = 210; Count.u64 = 210; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8143; SumSQ.u64 = 8143; Count.u64 = 8143; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2028; SumSQ.u64 = 2028; Count.u64 = 2028; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1215; SumSQ.u64 = 1215; Count.u64 = 1215; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 706; SumSQ.u64 = 706; Count.u64 = 706; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 1151; SumSQ.u64 = 1151; Count.u64 = 1151; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 722; SumSQ.u64 = 722; Count.u64 = 722; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 802; SumSQ.u64 = 802; Count.u64 = 802; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 1715; SumSQ.u64 = 1715; Count.u64 = 1715; Min.u64 = 1; Max.u64 = 1; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 711; SumSQ.u64 = 711; Count.u64 = 711; Min.u64 = 1; Max.u64 = 1; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1514609; SumSQ.u64 = 18218391; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 15; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1043; SumSQ.u64 = 1043; Count.u64 = 1043; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 832; SumSQ.u64 = 832; Count.u64 = 832; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 508; SumSQ.u64 = 508; Count.u64 = 508; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 871; SumSQ.u64 = 871; Count.u64 = 871; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 141; SumSQ.u64 = 141; Count.u64 = 141; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 381; SumSQ.u64 = 381; Count.u64 = 381; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 437; SumSQ.u64 = 437; Count.u64 = 437; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 4432; SumSQ.u64 = 4432; Count.u64 = 4432; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 3125; SumSQ.u64 = 3125; Count.u64 = 3125; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 452; SumSQ.u64 = 452; Count.u64 = 452; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 95; SumSQ.u64 = 95; Count.u64 = 95; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 630; SumSQ.u64 = 630; Count.u64 = 630; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1069; SumSQ.u64 = 1069; Count.u64 = 1069; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 881; SumSQ.u64 = 881; Count.u64 = 881; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_I : Accumulator : Sum.u64 = 2122; SumSQ.u64 = 2122; Count.u64 = 2122; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_S : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_M : Accumulator : Sum.u64 = 419; SumSQ.u64 = 419; Count.u64 = 419; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IS : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IM : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 35396; SumSQ.u64 = 80260566; Count.u64 = 26; Min.u64 = 2; Max.u64 = 4544; + l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 2026403; SumSQ.u64 = 5809118793; Count.u64 = 1043; Min.u64 = 39; Max.u64 = 8040; + l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 27021; SumSQ.u64 = 67851597; Count.u64 = 25; Min.u64 = 2; Max.u64 = 4903; + l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 1622931; SumSQ.u64 = 4664595433; Count.u64 = 832; Min.u64 = 36; Max.u64 = 8326; + l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 8579; SumSQ.u64 = 14433973; Count.u64 = 6; Min.u64 = 857; Max.u64 = 2705; + l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 2033; SumSQ.u64 = 3202069; Count.u64 = 2; Min.u64 = 263; Max.u64 = 1770; + l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 68466; SumSQ.u64 = 213997186; Count.u64 = 33; Min.u64 = 285; Max.u64 = 5738; + l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 842; SumSQ.u64 = 842; Count.u64 = 842; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 219; SumSQ.u64 = 219; Count.u64 = 219; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheHits : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheMisses : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 150; SumSQ.u64 = 150; Count.u64 = 150; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 179; SumSQ.u64 = 179; Count.u64 = 179; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_E : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 12278; SumSQ.u64 = 12278; Count.u64 = 12278; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 2018; SumSQ.u64 = 2018; Count.u64 = 2018; Min.u64 = 1; Max.u64 = 1; + l1cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_recv : Accumulator : Sum.u64 = 1069; SumSQ.u64 = 1069; Count.u64 = 1069; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_recv : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_recv : Accumulator : Sum.u64 = 881; SumSQ.u64 = 881; Count.u64 = 881; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 535; SumSQ.u64 = 535; Count.u64 = 535; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1379; SumSQ.u64 = 1379; Count.u64 = 1379; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.Inv_recv : Accumulator : Sum.u64 = 528; SumSQ.u64 = 528; Count.u64 = 528; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Fetch_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 760; SumSQ.u64 = 760; Count.u64 = 760; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache2.NACK_recv : Accumulator : Sum.u64 = 5904; SumSQ.u64 = 5904; Count.u64 = 5904; Min.u64 = 1; Max.u64 = 1; + l1cache2.AckPut_recv : Accumulator : Sum.u64 = 907; SumSQ.u64 = 907; Count.u64 = 907; Min.u64 = 1; Max.u64 = 1; + l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 2038524; SumSQ.u64 = 26424554; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 15; + l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1231; SumSQ.u64 = 1231; Count.u64 = 1231; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 641; SumSQ.u64 = 641; Count.u64 = 641; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 671; SumSQ.u64 = 671; Count.u64 = 671; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 128; SumSQ.u64 = 128; Count.u64 = 128; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 322; SumSQ.u64 = 322; Count.u64 = 322; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 246; SumSQ.u64 = 246; Count.u64 = 246; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 6400; SumSQ.u64 = 6400; Count.u64 = 6400; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 3258; SumSQ.u64 = 3258; Count.u64 = 3258; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 371; SumSQ.u64 = 371; Count.u64 = 371; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1255; SumSQ.u64 = 1255; Count.u64 = 1255; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 686; SumSQ.u64 = 686; Count.u64 = 686; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_I : Accumulator : Sum.u64 = 2097; SumSQ.u64 = 2097; Count.u64 = 2097; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_S : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_M : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IS : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IM : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 31397; SumSQ.u64 = 100800987; Count.u64 = 24; Min.u64 = 2; Max.u64 = 5246; + l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 2699813; SumSQ.u64 = 10682827733; Count.u64 = 1231; Min.u64 = 32; Max.u64 = 14986; + l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 25034; SumSQ.u64 = 73640782; Count.u64 = 24; Min.u64 = 2; Max.u64 = 5404; + l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 1376797; SumSQ.u64 = 5449454303; Count.u64 = 641; Min.u64 = 32; Max.u64 = 10849; + l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 9188; SumSQ.u64 = 29896978; Count.u64 = 4; Min.u64 = 601; Max.u64 = 4160; + l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 53030; SumSQ.u64 = 152465992; Count.u64 = 26; Min.u64 = 284; Max.u64 = 4693; + l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 962; SumSQ.u64 = 962; Count.u64 = 962; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 494; SumSQ.u64 = 494; Count.u64 = 494; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheHits : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheMisses : Accumulator : Sum.u64 = 1902; SumSQ.u64 = 1902; Count.u64 = 1902; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1195; SumSQ.u64 = 1195; Count.u64 = 1195; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 655; SumSQ.u64 = 655; Count.u64 = 655; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_E : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 14336; SumSQ.u64 = 14336; Count.u64 = 14336; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 2349; SumSQ.u64 = 2349; Count.u64 = 2349; Min.u64 = 1; Max.u64 = 1; + l1cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_recv : Accumulator : Sum.u64 = 1255; SumSQ.u64 = 1255; Count.u64 = 1255; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_recv : Accumulator : Sum.u64 = 686; SumSQ.u64 = 686; Count.u64 = 686; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 459; SumSQ.u64 = 459; Count.u64 = 459; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache3.Inv_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Fetch_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 476; SumSQ.u64 = 476; Count.u64 = 476; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l1cache3.NACK_recv : Accumulator : Sum.u64 = 8039; SumSQ.u64 = 8039; Count.u64 = 8039; Min.u64 = 1; Max.u64 = 1; + l1cache3.AckPut_recv : Accumulator : Sum.u64 = 1195; SumSQ.u64 = 1195; Count.u64 = 1195; Min.u64 = 1; Max.u64 = 1; + l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 2463368; SumSQ.u64 = 32005370; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 15; + l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 4134; SumSQ.u64 = 4134; Count.u64 = 4134; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 2740; Count.u64 = 2740; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 800023; SumSQ.u64 = 16138545; Count.u64 = 90041; Min.u64 = 0; Max.u64 = 103; + memory.latency_GetS : Accumulator : Sum.u64 = 340122; SumSQ.u64 = 28021300; Count.u64 = 4134; Min.u64 = 81; Max.u64 = 120; + memory.latency_GetSX : Accumulator : Sum.u64 = 8392; SumSQ.u64 = 699642; Count.u64 = 101; Min.u64 = 81; Max.u64 = 118; + memory.latency_GetX : Accumulator : Sum.u64 = 211581; SumSQ.u64 = 17468581; Count.u64 = 2567; Min.u64 = 81; Max.u64 = 119; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 239928; SumSQ.u64 = 21135800; Count.u64 = 2740; Min.u64 = 81; Max.u64 = 124; + memory.cycles_with_issue : Accumulator : Sum.u64 = 9542; SumSQ.u64 = 9542; Count.u64 = 9542; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 90041; SumSQ.u64 = 8107381681; Count.u64 = 1; Min.u64 = 90041; Max.u64 = 90041; + l2cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_I : Accumulator : Sum.u64 = 9540; SumSQ.u64 = 9540; Count.u64 = 9540; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IS : Accumulator : Sum.u64 = 3643; SumSQ.u64 = 3643; Count.u64 = 3643; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IM : Accumulator : Sum.u64 = 2454; SumSQ.u64 = 2454; Count.u64 = 2454; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_M : Accumulator : Sum.u64 = 4286; SumSQ.u64 = 4286; Count.u64 = 4286; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.evict_MInv : Accumulator : Sum.u64 = 1021; SumSQ.u64 = 1021; Count.u64 = 1021; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_MInvX : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4519; SumSQ.u64 = 4519; Count.u64 = 4519; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 23; SumSQ.u64 = 23; Count.u64 = 23; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4519; SumSQ.u64 = 4519; Count.u64 = 4519; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2953; SumSQ.u64 = 2953; Count.u64 = 2953; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 874; SumSQ.u64 = 874; Count.u64 = 874; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 474; SumSQ.u64 = 474; Count.u64 = 474; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1607; SumSQ.u64 = 1607; Count.u64 = 1607; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 7459; SumSQ.u64 = 7459; Count.u64 = 7459; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_GetS : Accumulator : Sum.u64 = 4519; SumSQ.u64 = 4519; Count.u64 = 4519; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetX : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSX : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutM : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 2992; Count.u64 = 2992; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAll : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 460; SumSQ.u64 = 460; Count.u64 = 460; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 460; SumSQ.u64 = 460; Count.u64 = 460; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_NACK : Accumulator : Sum.u64 = 16561; SumSQ.u64 = 16561; Count.u64 = 16561; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetSResp : Accumulator : Sum.u64 = 2473; SumSQ.u64 = 2473; Count.u64 = 2473; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5143; SumSQ.u64 = 5143; Count.u64 = 5143; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Inv : Accumulator : Sum.u64 = 2451; SumSQ.u64 = 2451; Count.u64 = 2451; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Fetch : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInv : Accumulator : Sum.u64 = 2836; SumSQ.u64 = 2836; Count.u64 = 2836; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckPut : Accumulator : Sum.u64 = 3589; SumSQ.u64 = 3589; Count.u64 = 3589; Min.u64 = 1; Max.u64 = 1; + l2cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetS_hit : Accumulator : Sum.u64 = 30617; SumSQ.u64 = 18463749; Count.u64 = 88; Min.u64 = 4; Max.u64 = 1173; + l2cache.latency_GetS_miss : Accumulator : Sum.u64 = 2038343; SumSQ.u64 = 1244512563; Count.u64 = 4519; Min.u64 = 26; Max.u64 = 1883; + l2cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_hit : Accumulator : Sum.u64 = 14471; SumSQ.u64 = 7159439; Count.u64 = 54; Min.u64 = 4; Max.u64 = 879; + l2cache.latency_GetX_miss : Accumulator : Sum.u64 = 1287003; SumSQ.u64 = 791521481; Count.u64 = 2846; Min.u64 = 26; Max.u64 = 2265; + l2cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_hit : Accumulator : Sum.u64 = 67; SumSQ.u64 = 2245; Count.u64 = 2; Min.u64 = 33; Max.u64 = 34; + l2cache.latency_GetSX_miss : Accumulator : Sum.u64 = 47983; SumSQ.u64 = 32492139; Count.u64 = 107; Min.u64 = 26; Max.u64 = 2039; + l2cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Arrival : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSHit_Blocked : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXHit_Blocked : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 1519; SumSQ.u64 = 1519; Count.u64 = 1519; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 975; SumSQ.u64 = 975; Count.u64 = 975; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 3000; SumSQ.u64 = 3000; Count.u64 = 3000; Min.u64 = 1; Max.u64 = 1; + l2cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 1871; SumSQ.u64 = 1871; Count.u64 = 1871; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheHits : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; + l2cache.CacheMisses : Accumulator : Sum.u64 = 7472; SumSQ.u64 = 7472; Count.u64 = 7472; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_E : Accumulator : Sum.u64 = 6435; SumSQ.u64 = 6435; Count.u64 = 6435; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_ED : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInv : Accumulator : Sum.u64 = 1453; SumSQ.u64 = 1453; Count.u64 = 1453; Min.u64 = 1; Max.u64 = 1; + l2cache.evict_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 690; SumSQ.u64 = 690; Count.u64 = 690; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 1361; SumSQ.u64 = 1361; Count.u64 = 1361; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 655; SumSQ.u64 = 655; Count.u64 = 655; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 1702; SumSQ.u64 = 1702; Count.u64 = 1702; Min.u64 = 1; Max.u64 = 1; + l2cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.eventSent_PutE : Accumulator : Sum.u64 = 4467; SumSQ.u64 = 4467; Count.u64 = 4467; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReceived : Accumulator : Sum.u64 = 47713; SumSQ.u64 = 47713; Count.u64 = 47713; Min.u64 = 1; Max.u64 = 1; + l2cache.TotalEventsReplayed : Accumulator : Sum.u64 = 22250; SumSQ.u64 = 22250; Count.u64 = 22250; Min.u64 = 1; Max.u64 = 1; + l2cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetS_recv : Accumulator : Sum.u64 = 14521; SumSQ.u64 = 14521; Count.u64 = 14521; Min.u64 = 1; Max.u64 = 1; + l2cache.GetX_recv : Accumulator : Sum.u64 = 8597; SumSQ.u64 = 8597; Count.u64 = 8597; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSX_recv : Accumulator : Sum.u64 = 316; SumSQ.u64 = 316; Count.u64 = 316; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAll_recv : Accumulator : Sum.u64 = 424; SumSQ.u64 = 424; Count.u64 = 424; Min.u64 = 1; Max.u64 = 1; + l2cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.GetXResp_recv : Accumulator : Sum.u64 = 7472; SumSQ.u64 = 7472; Count.u64 = 7472; Min.u64 = 1; Max.u64 = 1; + l2cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FlushAllResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache.PutS_recv : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; + l2cache.PutM_recv : Accumulator : Sum.u64 = 1422; SumSQ.u64 = 1422; Count.u64 = 1422; Min.u64 = 1; Max.u64 = 1; + l2cache.PutE_recv : Accumulator : Sum.u64 = 1611; SumSQ.u64 = 1611; Count.u64 = 1611; Min.u64 = 1; Max.u64 = 1; + l2cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchInv_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.FetchResp_recv : Accumulator : Sum.u64 = 2292; SumSQ.u64 = 2292; Count.u64 = 2292; Min.u64 = 1; Max.u64 = 1; + l2cache.FetchXResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache.ForwardFlush_recv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; + l2cache.AckFlush_recv : Accumulator : Sum.u64 = 460; SumSQ.u64 = 460; Count.u64 = 460; Min.u64 = 1; Max.u64 = 1; + l2cache.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l2cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.AckInv_recv : Accumulator : Sum.u64 = 1753; SumSQ.u64 = 1753; Count.u64 = 1753; Min.u64 = 1; Max.u64 = 1; + l2cache.AckPut_recv : Accumulator : Sum.u64 = 7459; SumSQ.u64 = 7459; Count.u64 = 7459; Min.u64 = 1; Max.u64 = 1; + l2cache.MSHR_occupancy : Accumulator : Sum.u64 = 3852899; SumSQ.u64 = 70271797; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 23; + l2cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_I : Accumulator : Sum.u64 = 4837; SumSQ.u64 = 4837; Count.u64 = 4837; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_M : Accumulator : Sum.u64 = 1088; SumSQ.u64 = 1088; Count.u64 = 1088; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4518; SumSQ.u64 = 4518; Count.u64 = 4518; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4518; SumSQ.u64 = 4518; Count.u64 = 4518; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2953; SumSQ.u64 = 2953; Count.u64 = 2953; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 2945; SumSQ.u64 = 2945; Count.u64 = 2945; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetS : Accumulator : Sum.u64 = 4518; SumSQ.u64 = 4518; Count.u64 = 4518; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetX : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_GetSX : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutM : Accumulator : Sum.u64 = 2991; SumSQ.u64 = 2991; Count.u64 = 2991; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 7472; SumSQ.u64 = 7472; Count.u64 = 7472; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 7459; SumSQ.u64 = 7459; Count.u64 = 7459; Min.u64 = 1; Max.u64 = 1; + l3cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetS_hit : Accumulator : Sum.u64 = 8; SumSQ.u64 = 64; Count.u64 = 1; Min.u64 = 8; Max.u64 = 8; + l3cache.latency_GetS_miss : Accumulator : Sum.u64 = 1142120; SumSQ.u64 = 313115786; Count.u64 = 4518; Min.u64 = 19; Max.u64 = 781; + l3cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_miss : Accumulator : Sum.u64 = 710891; SumSQ.u64 = 194778127; Count.u64 = 2846; Min.u64 = 19; Max.u64 = 699; + l3cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_miss : Accumulator : Sum.u64 = 28014; SumSQ.u64 = 7730794; Count.u64 = 107; Min.u64 = 19; Max.u64 = 382; + l3cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 4507; SumSQ.u64 = 4507; Count.u64 = 4507; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 2842; SumSQ.u64 = 2842; Count.u64 = 2842; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CacheHits : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.CacheMisses : Accumulator : Sum.u64 = 7471; SumSQ.u64 = 7471; Count.u64 = 7471; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_E : Accumulator : Sum.u64 = 1576; SumSQ.u64 = 1576; Count.u64 = 1576; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 4456; SumSQ.u64 = 4456; Count.u64 = 4456; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_PutE : Accumulator : Sum.u64 = 4466; SumSQ.u64 = 4466; Count.u64 = 4466; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReceived : Accumulator : Sum.u64 = 23226; SumSQ.u64 = 23226; Count.u64 = 23226; Min.u64 = 1; Max.u64 = 1; + l3cache.TotalEventsReplayed : Accumulator : Sum.u64 = 718; SumSQ.u64 = 718; Count.u64 = 718; Min.u64 = 1; Max.u64 = 1; + l3cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetS_recv : Accumulator : Sum.u64 = 4519; SumSQ.u64 = 4519; Count.u64 = 4519; Min.u64 = 1; Max.u64 = 1; + l3cache.GetX_recv : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.GetXResp_recv : Accumulator : Sum.u64 = 7471; SumSQ.u64 = 7471; Count.u64 = 7471; Min.u64 = 1; Max.u64 = 1; + l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.PutM_recv : Accumulator : Sum.u64 = 2992; SumSQ.u64 = 2992; Count.u64 = 2992; Min.u64 = 1; Max.u64 = 1; + l3cache.PutE_recv : Accumulator : Sum.u64 = 4467; SumSQ.u64 = 4467; Count.u64 = 4467; Min.u64 = 1; Max.u64 = 1; + l3cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l3cache.NACK_recv : Accumulator : Sum.u64 = 249; SumSQ.u64 = 249; Count.u64 = 249; Min.u64 = 1; Max.u64 = 1; + l3cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.MSHR_occupancy : Accumulator : Sum.u64 = 2243329; SumSQ.u64 = 22836019; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 17; + l3cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_I : Accumulator : Sum.u64 = 6622; SumSQ.u64 = 6622; Count.u64 = 6622; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_M : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 2740; Count.u64 = 2740; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4134; SumSQ.u64 = 4134; Count.u64 = 4134; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4134; SumSQ.u64 = 4134; Count.u64 = 4134; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2668; SumSQ.u64 = 2668; Count.u64 = 2668; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 2764; SumSQ.u64 = 2764; Count.u64 = 2764; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetS : Accumulator : Sum.u64 = 4134; SumSQ.u64 = 4134; Count.u64 = 4134; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetX : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetSX : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutM : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 2740; Count.u64 = 2740; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAll : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetXResp : Accumulator : Sum.u64 = 7471; SumSQ.u64 = 7471; Count.u64 = 7471; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_AckFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetS_hit : Accumulator : Sum.u64 = 3072; SumSQ.u64 = 24576; Count.u64 = 384; Min.u64 = 8; Max.u64 = 8; + l4cache.latency_GetS_miss : Accumulator : Sum.u64 = 1086035; SumSQ.u64 = 285666603; Count.u64 = 4134; Min.u64 = 257; Max.u64 = 376; + l4cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_hit : Accumulator : Sum.u64 = 2233; SumSQ.u64 = 17873; Count.u64 = 279; Min.u64 = 8; Max.u64 = 9; + l4cache.latency_GetX_miss : Accumulator : Sum.u64 = 675514; SumSQ.u64 = 178038186; Count.u64 = 2567; Min.u64 = 257; Max.u64 = 373; + l4cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_hit : Accumulator : Sum.u64 = 48; SumSQ.u64 = 384; Count.u64 = 6; Min.u64 = 8; Max.u64 = 8; + l4cache.latency_GetSX_miss : Accumulator : Sum.u64 = 26789; SumSQ.u64 = 7127049; Count.u64 = 101; Min.u64 = 257; Max.u64 = 371; + l4cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Arrival : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXHit_Arrival : Accumulator : Sum.u64 = 279; SumSQ.u64 = 279; Count.u64 = 279; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 4132; SumSQ.u64 = 4132; Count.u64 = 4132; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CacheHits : Accumulator : Sum.u64 = 669; SumSQ.u64 = 669; Count.u64 = 669; Min.u64 = 1; Max.u64 = 1; + l4cache.CacheMisses : Accumulator : Sum.u64 = 6802; SumSQ.u64 = 6802; Count.u64 = 6802; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 6784; SumSQ.u64 = 6784; Count.u64 = 6784; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_E : Accumulator : Sum.u64 = 4044; SumSQ.u64 = 4044; Count.u64 = 4044; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 237; SumSQ.u64 = 237; Count.u64 = 237; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 181; SumSQ.u64 = 181; Count.u64 = 181; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 4319; SumSQ.u64 = 4319; Count.u64 = 4319; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 147; SumSQ.u64 = 147; Count.u64 = 147; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 227; SumSQ.u64 = 227; Count.u64 = 227; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutE : Accumulator : Sum.u64 = 4044; SumSQ.u64 = 4044; Count.u64 = 4044; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReceived : Accumulator : Sum.u64 = 29089; SumSQ.u64 = 29089; Count.u64 = 29089; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReplayed : Accumulator : Sum.u64 = 6836; SumSQ.u64 = 6836; Count.u64 = 6836; Min.u64 = 1; Max.u64 = 1; + l4cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_recv : Accumulator : Sum.u64 = 4518; SumSQ.u64 = 4518; Count.u64 = 4518; Min.u64 = 1; Max.u64 = 1; + l4cache.GetX_recv : Accumulator : Sum.u64 = 2846; SumSQ.u64 = 2846; Count.u64 = 2846; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSX_recv : Accumulator : Sum.u64 = 107; SumSQ.u64 = 107; Count.u64 = 107; Min.u64 = 1; Max.u64 = 1; + l4cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAll_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXResp_recv : Accumulator : Sum.u64 = 6802; SumSQ.u64 = 6802; Count.u64 = 6802; Min.u64 = 1; Max.u64 = 1; + l4cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAllResp_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.PutM_recv : Accumulator : Sum.u64 = 2991; SumSQ.u64 = 2991; Count.u64 = 2991; Min.u64 = 1; Max.u64 = 1; + l4cache.PutE_recv : Accumulator : Sum.u64 = 4466; SumSQ.u64 = 4466; Count.u64 = 4466; Min.u64 = 1; Max.u64 = 1; + l4cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForwardFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.AckFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.UnblockFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + l4cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckPut_recv : Accumulator : Sum.u64 = 6784; SumSQ.u64 = 6784; Count.u64 = 6784; Min.u64 = 1; Max.u64 = 1; + l4cache.MSHR_occupancy : Accumulator : Sum.u64 = 2158558; SumSQ.u64 = 21560786; Count.u64 = 270396; Min.u64 = 0; Max.u64 = 17; + l4cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 272422; SumSQ.u64 = 174572832; Count.u64 = 6899; Min.u64 = 2; Max.u64 = 2235; + directory.get_request_latency : Accumulator : Sum.u64 = 1144102; SumSQ.u64 = 192729790; Count.u64 = 6802; Min.u64 = 165; Max.u64 = 244; + directory.directory_cache_hits : Accumulator : Sum.u64 = 13586; SumSQ.u64 = 13586; Count.u64 = 13586; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 4134; SumSQ.u64 = 4134; Count.u64 = 4134; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 2740; Count.u64 = 2740; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 4044; SumSQ.u64 = 4044; Count.u64 = 4044; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 6802; SumSQ.u64 = 6802; Count.u64 = 6802; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckFlush_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 4134; SumSQ.u64 = 4134; Count.u64 = 4134; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 2567; SumSQ.u64 = 2567; Count.u64 = 2567; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 2740; SumSQ.u64 = 2740; Count.u64 = 2740; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 6802; SumSQ.u64 = 6802; Count.u64 = 6802; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 6784; SumSQ.u64 = 6784; Count.u64 = 6784; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 115; SumSQ.u64 = 115; Count.u64 = 115; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 1261913; SumSQ.u64 = 11898953; Count.u64 = 180076; Min.u64 = 0; Max.u64 = 16; +Simulation is complete, simulated time: 90.0419 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case3_mesi.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case3_mesi.out new file mode 100644 index 0000000000..d43a9ec31e --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_coherence_4core_5level_case3_mesi.out @@ -0,0 +1,2887 @@ +l2cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache2: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l2cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache0: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache1: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache2: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l3cache3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. +l4cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to 2 cycles. + core0.pendCycle : Accumulator : Sum.u64 = 2426882; SumSQ.u64 = 38731322; Count.u64 = 152619; Min.u64 = 0; Max.u64 = 16; + core0.reads : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + core0.writes : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; + core0.flushcaches : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + core0.llsc : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + core0.llsc_success : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + core1.pendCycle : Accumulator : Sum.u64 = 2945783; SumSQ.u64 = 47081557; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 16; + core1.reads : Accumulator : Sum.u64 = 1181; SumSQ.u64 = 1181; Count.u64 = 1181; Min.u64 = 1; Max.u64 = 1; + core1.writes : Accumulator : Sum.u64 = 688; SumSQ.u64 = 688; Count.u64 = 688; Min.u64 = 1; Max.u64 = 1; + core1.flushcaches : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + core1.llsc : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + core1.llsc_success : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + core2.pendCycle : Accumulator : Sum.u64 = 2556338; SumSQ.u64 = 40835064; Count.u64 = 160477; Min.u64 = 0; Max.u64 = 16; + core2.reads : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + core2.writes : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; + core2.flushcaches : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + core2.llsc : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + core2.llsc_success : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + core3.pendCycle : Accumulator : Sum.u64 = 2808992; SumSQ.u64 = 44869958; Count.u64 = 176165; Min.u64 = 0; Max.u64 = 16; + core3.reads : Accumulator : Sum.u64 = 1300; SumSQ.u64 = 1300; Count.u64 = 1300; Min.u64 = 1; Max.u64 = 1; + core3.writes : Accumulator : Sum.u64 = 642; SumSQ.u64 = 642; Count.u64 = 642; Min.u64 = 1; Max.u64 = 1; + core3.flushcaches : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + core3.llsc : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + core3.llsc_success : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 720; SumSQ.u64 = 720; Count.u64 = 720; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 554; SumSQ.u64 = 554; Count.u64 = 554; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 775; SumSQ.u64 = 775; Count.u64 = 775; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 255; SumSQ.u64 = 255; Count.u64 = 255; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_GetS : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetX : Accumulator : Sum.u64 = 730; SumSQ.u64 = 730; Count.u64 = 730; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutM : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 786; SumSQ.u64 = 786; Count.u64 = 786; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_I : Accumulator : Sum.u64 = 2047; SumSQ.u64 = 2047; Count.u64 = 2047; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_S : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_M : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IS : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_IM : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetS_hit : Accumulator : Sum.u64 = 22432; SumSQ.u64 = 34762362; Count.u64 = 22; Min.u64 = 2; Max.u64 = 3508; + l1cache0.latency_GetS_miss : Accumulator : Sum.u64 = 1394998; SumSQ.u64 = 2173873586; Count.u64 = 1130; Min.u64 = 61; Max.u64 = 4813; + l1cache0.latency_GetX_hit : Accumulator : Sum.u64 = 13319; SumSQ.u64 = 13365117; Count.u64 = 19; Min.u64 = 28; Max.u64 = 1617; + l1cache0.latency_GetX_miss : Accumulator : Sum.u64 = 889732; SumSQ.u64 = 1350430166; Count.u64 = 720; Min.u64 = 9; Max.u64 = 4334; + l1cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 13352; SumSQ.u64 = 19643928; Count.u64 = 10; Min.u64 = 593; Max.u64 = 2092; + l1cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 55724; SumSQ.u64 = 77019334; Count.u64 = 45; Min.u64 = 287; Max.u64 = 2986; + l1cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 923; SumSQ.u64 = 923; Count.u64 = 923; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 573; SumSQ.u64 = 573; Count.u64 = 573; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 34; SumSQ.u64 = 34; Count.u64 = 34; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 157; SumSQ.u64 = 157; Count.u64 = 157; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheHits : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; + l1cache0.CacheMisses : Accumulator : Sum.u64 = 1905; SumSQ.u64 = 1905; Count.u64 = 1905; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_PutS : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l1cache0.eventSent_PutE : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; + l1cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache0.evict_E : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReceived : Accumulator : Sum.u64 = 4949; SumSQ.u64 = 4949; Count.u64 = 4949; Min.u64 = 1; Max.u64 = 1; + l1cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 2210; SumSQ.u64 = 2210; Count.u64 = 2210; Min.u64 = 1; Max.u64 = 1; + l1cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetS_recv : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.GetSX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l1cache0.Write_recv : Accumulator : Sum.u64 = 786; SumSQ.u64 = 786; Count.u64 = 786; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; + l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 1329; SumSQ.u64 = 1329; Count.u64 = 1329; Min.u64 = 1; Max.u64 = 1; + l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache0.Inv_recv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; + l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 961268; SumSQ.u64 = 11435772; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 15; + l1cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1156; SumSQ.u64 = 1156; Count.u64 = 1156; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 677; SumSQ.u64 = 677; Count.u64 = 677; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 708; SumSQ.u64 = 708; Count.u64 = 708; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 709; SumSQ.u64 = 709; Count.u64 = 709; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_GetS : Accumulator : Sum.u64 = 1156; SumSQ.u64 = 1156; Count.u64 = 1156; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetX : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSX : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutM : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 1181; SumSQ.u64 = 1181; Count.u64 = 1181; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_I : Accumulator : Sum.u64 = 1948; SumSQ.u64 = 1948; Count.u64 = 1948; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_S : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_M : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IS : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_IM : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_GetS_hit : Accumulator : Sum.u64 = 16224; SumSQ.u64 = 23132358; Count.u64 = 25; Min.u64 = 2; Max.u64 = 3424; + l1cache1.latency_GetS_miss : Accumulator : Sum.u64 = 1675967; SumSQ.u64 = 3784116073; Count.u64 = 1156; Min.u64 = 8; Max.u64 = 6677; + l1cache1.latency_GetX_hit : Accumulator : Sum.u64 = 7038; SumSQ.u64 = 7078172; Count.u64 = 14; Min.u64 = 2; Max.u64 = 1996; + l1cache1.latency_GetX_miss : Accumulator : Sum.u64 = 1030166; SumSQ.u64 = 2451059380; Count.u64 = 677; Min.u64 = 12; Max.u64 = 7022; + l1cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 6450; SumSQ.u64 = 10609730; Count.u64 = 4; Min.u64 = 1316; Max.u64 = 1843; + l1cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 594; SumSQ.u64 = 352836; Count.u64 = 1; Min.u64 = 594; Max.u64 = 594; + l1cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 42754; SumSQ.u64 = 93604766; Count.u64 = 28; Min.u64 = 286; Max.u64 = 4260; + l1cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 926; SumSQ.u64 = 926; Count.u64 = 926; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 559; SumSQ.u64 = 559; Count.u64 = 559; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 230; SumSQ.u64 = 230; Count.u64 = 230; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 122; SumSQ.u64 = 122; Count.u64 = 122; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheHits : Accumulator : Sum.u64 = 40; SumSQ.u64 = 40; Count.u64 = 40; Min.u64 = 1; Max.u64 = 1; + l1cache1.CacheMisses : Accumulator : Sum.u64 = 1865; SumSQ.u64 = 1865; Count.u64 = 1865; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_PutS : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l1cache1.eventSent_PutE : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache1.evict_E : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReceived : Accumulator : Sum.u64 = 4766; SumSQ.u64 = 4766; Count.u64 = 4766; Min.u64 = 1; Max.u64 = 1; + l1cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 2255; SumSQ.u64 = 2255; Count.u64 = 2255; Min.u64 = 1; Max.u64 = 1; + l1cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetS_recv : Accumulator : Sum.u64 = 1181; SumSQ.u64 = 1181; Count.u64 = 1181; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.GetSX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l1cache1.Write_recv : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 1417; SumSQ.u64 = 1417; Count.u64 = 1417; Min.u64 = 1; Max.u64 = 1; + l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache1.Inv_recv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1148334; SumSQ.u64 = 13063854; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 15; + l1cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 828; SumSQ.u64 = 828; Count.u64 = 828; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 583; SumSQ.u64 = 583; Count.u64 = 583; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_GetS : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetX : Accumulator : Sum.u64 = 835; SumSQ.u64 = 835; Count.u64 = 835; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_PutM : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckInv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_I : Accumulator : Sum.u64 = 2063; SumSQ.u64 = 2063; Count.u64 = 2063; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_S : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_M : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IS : Accumulator : Sum.u64 = 290; SumSQ.u64 = 290; Count.u64 = 290; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_IM : Accumulator : Sum.u64 = 272; SumSQ.u64 = 272; Count.u64 = 272; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetS_hit : Accumulator : Sum.u64 = 11636; SumSQ.u64 = 14992446; Count.u64 = 12; Min.u64 = 2; Max.u64 = 1814; + l1cache2.latency_GetS_miss : Accumulator : Sum.u64 = 1330481; SumSQ.u64 = 2130239155; Count.u64 = 1037; Min.u64 = 16; Max.u64 = 5960; + l1cache2.latency_GetX_hit : Accumulator : Sum.u64 = 19092; SumSQ.u64 = 30062898; Count.u64 = 26; Min.u64 = 2; Max.u64 = 4077; + l1cache2.latency_GetX_miss : Accumulator : Sum.u64 = 1087356; SumSQ.u64 = 1789515874; Count.u64 = 828; Min.u64 = 62; Max.u64 = 5724; + l1cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 12960; SumSQ.u64 = 25119648; Count.u64 = 7; Min.u64 = 909; Max.u64 = 2142; + l1cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 53160; SumSQ.u64 = 87843266; Count.u64 = 42; Min.u64 = 325; Max.u64 = 3471; + l1cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 851; SumSQ.u64 = 851; Count.u64 = 851; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 674; SumSQ.u64 = 674; Count.u64 = 674; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheHits : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l1cache2.CacheMisses : Accumulator : Sum.u64 = 1914; SumSQ.u64 = 1914; Count.u64 = 1914; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.eventSent_PutS : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l1cache2.eventSent_PutE : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 544; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; + l1cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache2.evict_E : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 544; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReceived : Accumulator : Sum.u64 = 4888; SumSQ.u64 = 4888; Count.u64 = 4888; Min.u64 = 1; Max.u64 = 1; + l1cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 2274; SumSQ.u64 = 2274; Count.u64 = 2274; Min.u64 = 1; Max.u64 = 1; + l1cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetS_recv : Accumulator : Sum.u64 = 1049; SumSQ.u64 = 1049; Count.u64 = 1049; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.GetSX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l1cache2.Write_recv : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAll_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetSResp_recv : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l1cache2.GetXResp_recv : Accumulator : Sum.u64 = 1460; SumSQ.u64 = 1460; Count.u64 = 1460; Min.u64 = 1; Max.u64 = 1; + l1cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l1cache2.Inv_recv : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.FetchInv_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache2.FetchInvX_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l1cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.MSHR_occupancy : Accumulator : Sum.u64 = 1072537; SumSQ.u64 = 12712131; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 15; + l1cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1270; SumSQ.u64 = 1270; Count.u64 = 1270; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 628; SumSQ.u64 = 628; Count.u64 = 628; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 847; SumSQ.u64 = 847; Count.u64 = 847; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 185; SumSQ.u64 = 185; Count.u64 = 185; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_GetS : Accumulator : Sum.u64 = 1270; SumSQ.u64 = 1270; Count.u64 = 1270; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetX : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_PutM : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckInv : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 1300; SumSQ.u64 = 1300; Count.u64 = 1300; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_I : Accumulator : Sum.u64 = 2072; SumSQ.u64 = 2072; Count.u64 = 2072; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_S : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_M : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IS : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_IM : Accumulator : Sum.u64 = 200; SumSQ.u64 = 200; Count.u64 = 200; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetS_hit : Accumulator : Sum.u64 = 22867; SumSQ.u64 = 28745545; Count.u64 = 30; Min.u64 = 2; Max.u64 = 2581; + l1cache3.latency_GetS_miss : Accumulator : Sum.u64 = 1777747; SumSQ.u64 = 3425689967; Count.u64 = 1270; Min.u64 = 55; Max.u64 = 7234; + l1cache3.latency_GetX_hit : Accumulator : Sum.u64 = 10654; SumSQ.u64 = 11989344; Count.u64 = 13; Min.u64 = 2; Max.u64 = 1600; + l1cache3.latency_GetX_miss : Accumulator : Sum.u64 = 889219; SumSQ.u64 = 1778177815; Count.u64 = 628; Min.u64 = 60; Max.u64 = 6943; + l1cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 4143; SumSQ.u64 = 4333577; Count.u64 = 4; Min.u64 = 859; Max.u64 = 1116; + l1cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 17452; SumSQ.u64 = 40944388; Count.u64 = 11; Min.u64 = 387; Max.u64 = 3752; + l1cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 506; SumSQ.u64 = 506; Count.u64 = 506; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 236; SumSQ.u64 = 236; Count.u64 = 236; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheHits : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l1cache3.CacheMisses : Accumulator : Sum.u64 = 1913; SumSQ.u64 = 1913; Count.u64 = 1913; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.eventSent_PutS : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache3.eventSent_PutE : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l1cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l1cache3.evict_E : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReceived : Accumulator : Sum.u64 = 4779; SumSQ.u64 = 4779; Count.u64 = 4779; Min.u64 = 1; Max.u64 = 1; + l1cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 2418; SumSQ.u64 = 2418; Count.u64 = 2418; Min.u64 = 1; Max.u64 = 1; + l1cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetS_recv : Accumulator : Sum.u64 = 1300; SumSQ.u64 = 1300; Count.u64 = 1300; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.GetSX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l1cache3.Write_recv : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAll_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetSResp_recv : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l1cache3.GetXResp_recv : Accumulator : Sum.u64 = 1490; SumSQ.u64 = 1490; Count.u64 = 1490; Min.u64 = 1; Max.u64 = 1; + l1cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l1cache3.Inv_recv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.FetchInv_recv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l1cache3.FetchInvX_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l1cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l1cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1239883; SumSQ.u64 = 14382359; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 15; + l1cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_GetS : Accumulator : Sum.u64 = 4394; SumSQ.u64 = 4394; Count.u64 = 4394; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetSX : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_GetX : Accumulator : Sum.u64 = 2756; SumSQ.u64 = 2756; Count.u64 = 2756; Min.u64 = 1; Max.u64 = 1; + memory.requests_received_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.requests_received_PutM : Accumulator : Sum.u64 = 2960; SumSQ.u64 = 2960; Count.u64 = 2960; Min.u64 = 1; Max.u64 = 1; + memory.outstanding_requests : Accumulator : Sum.u64 = 866435; SumSQ.u64 = 19734525; Count.u64 = 61443; Min.u64 = 0; Max.u64 = 50; + memory.latency_GetS : Accumulator : Sum.u64 = 376498; SumSQ.u64 = 32398088; Count.u64 = 4394; Min.u64 = 81; Max.u64 = 104; + memory.latency_GetSX : Accumulator : Sum.u64 = 10532; SumSQ.u64 = 905434; Count.u64 = 123; Min.u64 = 81; Max.u64 = 103; + memory.latency_GetX : Accumulator : Sum.u64 = 236038; SumSQ.u64 = 20298654; Count.u64 = 2756; Min.u64 = 81; Max.u64 = 104; + memory.latency_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.latency_PutM : Accumulator : Sum.u64 = 243367; SumSQ.u64 = 20016205; Count.u64 = 2960; Min.u64 = 81; Max.u64 = 93; + memory.cycles_with_issue : Accumulator : Sum.u64 = 10233; SumSQ.u64 = 10233; Count.u64 = 10233; Min.u64 = 1; Max.u64 = 1; + memory.cycles_attempted_issue_but_rejected : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + memory.total_cycles : Accumulator : Sum.u64 = 61443; SumSQ.u64 = 3775242249; Count.u64 = 1; Min.u64 = 61443; Max.u64 = 61443; + l2cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_I : Accumulator : Sum.u64 = 1860; SumSQ.u64 = 1860; Count.u64 = 1860; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_S : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_M : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 551; SumSQ.u64 = 551; Count.u64 = 551; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 201; SumSQ.u64 = 201; Count.u64 = 201; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 457; SumSQ.u64 = 457; Count.u64 = 457; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 390; SumSQ.u64 = 390; Count.u64 = 390; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 370; SumSQ.u64 = 370; Count.u64 = 370; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetS : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetX : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutS : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_PutM : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 532; SumSQ.u64 = 532; Count.u64 = 532; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckInv : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 576; SumSQ.u64 = 576; Count.u64 = 576; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1329; SumSQ.u64 = 1329; Count.u64 = 1329; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Inv : Accumulator : Sum.u64 = 394; SumSQ.u64 = 394; Count.u64 = 394; Min.u64 = 1; Max.u64 = 1; + l2cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetS_hit : Accumulator : Sum.u64 = 22; SumSQ.u64 = 98; Count.u64 = 5; Min.u64 = 4; Max.u64 = 5; + l2cache0.latency_GetS_miss : Accumulator : Sum.u64 = 426937; SumSQ.u64 = 194883407; Count.u64 = 1125; Min.u64 = 50; Max.u64 = 1195; + l2cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 48; Count.u64 = 3; Min.u64 = 4; Max.u64 = 4; + l2cache0.latency_GetX_miss : Accumulator : Sum.u64 = 283211; SumSQ.u64 = 137127515; Count.u64 = 717; Min.u64 = 54; Max.u64 = 1456; + l2cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 6742; SumSQ.u64 = 4712832; Count.u64 = 10; Min.u64 = 585; Max.u64 = 873; + l2cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 16551; SumSQ.u64 = 6803071; Count.u64 = 45; Min.u64 = 277; Max.u64 = 652; + l2cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CacheHits : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache0.CacheMisses : Accumulator : Sum.u64 = 1897; SumSQ.u64 = 1897; Count.u64 = 1897; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_E : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; + l2cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 492; SumSQ.u64 = 492; Count.u64 = 492; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 55; SumSQ.u64 = 55; Count.u64 = 55; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.eventSent_PutE : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8152; SumSQ.u64 = 8152; Count.u64 = 8152; Min.u64 = 1; Max.u64 = 1; + l2cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1862; SumSQ.u64 = 1862; Count.u64 = 1862; Min.u64 = 1; Max.u64 = 1; + l2cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.GetS_recv : Accumulator : Sum.u64 = 1130; SumSQ.u64 = 1130; Count.u64 = 1130; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetX_recv : Accumulator : Sum.u64 = 730; SumSQ.u64 = 730; Count.u64 = 730; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l2cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAll_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetSResp_recv : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l2cache0.GetXResp_recv : Accumulator : Sum.u64 = 1323; SumSQ.u64 = 1323; Count.u64 = 1323; Min.u64 = 1; Max.u64 = 1; + l2cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutS_recv : Accumulator : Sum.u64 = 215; SumSQ.u64 = 215; Count.u64 = 215; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutM_recv : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutE_recv : Accumulator : Sum.u64 = 518; SumSQ.u64 = 518; Count.u64 = 518; Min.u64 = 1; Max.u64 = 1; + l2cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Inv_recv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.Fetch_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInv_recv : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchResp_recv : Accumulator : Sum.u64 = 323; SumSQ.u64 = 323; Count.u64 = 323; Min.u64 = 1; Max.u64 = 1; + l2cache0.FetchXResp_recv : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.AckInv_recv : Accumulator : Sum.u64 = 380; SumSQ.u64 = 380; Count.u64 = 380; Min.u64 = 1; Max.u64 = 1; + l2cache0.AckPut_recv : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l2cache0.MSHR_occupancy : Accumulator : Sum.u64 = 849296; SumSQ.u64 = 8736932; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 16; + l2cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_I : Accumulator : Sum.u64 = 1815; SumSQ.u64 = 1815; Count.u64 = 1815; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_S : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_M : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 702; SumSQ.u64 = 702; Count.u64 = 702; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 706; SumSQ.u64 = 706; Count.u64 = 706; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 276; SumSQ.u64 = 276; Count.u64 = 276; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 175; SumSQ.u64 = 175; Count.u64 = 175; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 273; SumSQ.u64 = 273; Count.u64 = 273; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetS : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetX : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetSX : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutS : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_PutM : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckInv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1417; SumSQ.u64 = 1417; Count.u64 = 1417; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 232; SumSQ.u64 = 232; Count.u64 = 232; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Inv : Accumulator : Sum.u64 = 294; SumSQ.u64 = 294; Count.u64 = 294; Min.u64 = 1; Max.u64 = 1; + l2cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetS_hit : Accumulator : Sum.u64 = 24; SumSQ.u64 = 96; Count.u64 = 6; Min.u64 = 4; Max.u64 = 4; + l2cache1.latency_GetS_miss : Accumulator : Sum.u64 = 507975; SumSQ.u64 = 282596885; Count.u64 = 1150; Min.u64 = 51; Max.u64 = 1752; + l2cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_hit : Accumulator : Sum.u64 = 12; SumSQ.u64 = 48; Count.u64 = 3; Min.u64 = 4; Max.u64 = 4; + l2cache1.latency_GetX_miss : Accumulator : Sum.u64 = 303602; SumSQ.u64 = 170989060; Count.u64 = 673; Min.u64 = 51; Max.u64 = 1751; + l2cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 3831; SumSQ.u64 = 3028561; Count.u64 = 5; Min.u64 = 598; Max.u64 = 883; + l2cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 11653; SumSQ.u64 = 6084963; Count.u64 = 28; Min.u64 = 61; Max.u64 = 950; + l2cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CacheHits : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.CacheMisses : Accumulator : Sum.u64 = 1856; SumSQ.u64 = 1856; Count.u64 = 1856; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_E : Accumulator : Sum.u64 = 580; SumSQ.u64 = 580; Count.u64 = 580; Min.u64 = 1; Max.u64 = 1; + l2cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 636; SumSQ.u64 = 636; Count.u64 = 636; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.eventSent_PutE : Accumulator : Sum.u64 = 580; SumSQ.u64 = 580; Count.u64 = 580; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8067; SumSQ.u64 = 8067; Count.u64 = 8067; Min.u64 = 1; Max.u64 = 1; + l2cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1832; SumSQ.u64 = 1832; Count.u64 = 1832; Min.u64 = 1; Max.u64 = 1; + l2cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.GetS_recv : Accumulator : Sum.u64 = 1156; SumSQ.u64 = 1156; Count.u64 = 1156; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetX_recv : Accumulator : Sum.u64 = 681; SumSQ.u64 = 681; Count.u64 = 681; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l2cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAll_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetSResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l2cache1.GetXResp_recv : Accumulator : Sum.u64 = 1408; SumSQ.u64 = 1408; Count.u64 = 1408; Min.u64 = 1; Max.u64 = 1; + l2cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutS_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutM_recv : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutE_recv : Accumulator : Sum.u64 = 651; SumSQ.u64 = 651; Count.u64 = 651; Min.u64 = 1; Max.u64 = 1; + l2cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Inv_recv : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.Fetch_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInv_recv : Accumulator : Sum.u64 = 395; SumSQ.u64 = 395; Count.u64 = 395; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchResp_recv : Accumulator : Sum.u64 = 229; SumSQ.u64 = 229; Count.u64 = 229; Min.u64 = 1; Max.u64 = 1; + l2cache1.FetchXResp_recv : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.AckInv_recv : Accumulator : Sum.u64 = 277; SumSQ.u64 = 277; Count.u64 = 277; Min.u64 = 1; Max.u64 = 1; + l2cache1.AckPut_recv : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l2cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1021155; SumSQ.u64 = 9972861; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 16; + l2cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_I : Accumulator : Sum.u64 = 1869; SumSQ.u64 = 1869; Count.u64 = 1869; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_S : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_M : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 827; SumSQ.u64 = 827; Count.u64 = 827; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 582; SumSQ.u64 = 582; Count.u64 = 582; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 876; SumSQ.u64 = 876; Count.u64 = 876; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 562; SumSQ.u64 = 562; Count.u64 = 562; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 405; SumSQ.u64 = 405; Count.u64 = 405; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_GetS : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetX : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetSX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_PutS : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_PutM : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 519; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckInv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1460; SumSQ.u64 = 1460; Count.u64 = 1460; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 19; SumSQ.u64 = 19; Count.u64 = 19; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Inv : Accumulator : Sum.u64 = 320; SumSQ.u64 = 320; Count.u64 = 320; Min.u64 = 1; Max.u64 = 1; + l2cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetS_hit : Accumulator : Sum.u64 = 9; SumSQ.u64 = 41; Count.u64 = 2; Min.u64 = 4; Max.u64 = 5; + l2cache2.latency_GetS_miss : Accumulator : Sum.u64 = 446800; SumSQ.u64 = 230574198; Count.u64 = 1035; Min.u64 = 51; Max.u64 = 1200; + l2cache2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_hit : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + l2cache2.latency_GetX_miss : Accumulator : Sum.u64 = 342891; SumSQ.u64 = 172693649; Count.u64 = 827; Min.u64 = 54; Max.u64 = 1519; + l2cache2.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 5125; SumSQ.u64 = 3900805; Count.u64 = 7; Min.u64 = 597; Max.u64 = 916; + l2cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 17484; SumSQ.u64 = 8703840; Count.u64 = 42; Min.u64 = 278; Max.u64 = 888; + l2cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CacheHits : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.CacheMisses : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_E : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l2cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 523; SumSQ.u64 = 523; Count.u64 = 523; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 20; SumSQ.u64 = 20; Count.u64 = 20; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 92; SumSQ.u64 = 92; Count.u64 = 92; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.eventSent_PutE : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReceived : Accumulator : Sum.u64 = 8186; SumSQ.u64 = 8186; Count.u64 = 8186; Min.u64 = 1; Max.u64 = 1; + l2cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1926; SumSQ.u64 = 1926; Count.u64 = 1926; Min.u64 = 1; Max.u64 = 1; + l2cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.GetS_recv : Accumulator : Sum.u64 = 1037; SumSQ.u64 = 1037; Count.u64 = 1037; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetX_recv : Accumulator : Sum.u64 = 835; SumSQ.u64 = 835; Count.u64 = 835; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l2cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAll_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetSResp_recv : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l2cache2.GetXResp_recv : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; + l2cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutS_recv : Accumulator : Sum.u64 = 160; SumSQ.u64 = 160; Count.u64 = 160; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutM_recv : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutE_recv : Accumulator : Sum.u64 = 544; SumSQ.u64 = 544; Count.u64 = 544; Min.u64 = 1; Max.u64 = 1; + l2cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Inv_recv : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.Fetch_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInv_recv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; + l2cache2.FetchXResp_recv : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; + l2cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache2.AckInv_recv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; + l2cache2.AckPut_recv : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l2cache2.MSHR_occupancy : Accumulator : Sum.u64 = 937269; SumSQ.u64 = 9575471; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 16; + l2cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_I : Accumulator : Sum.u64 = 1871; SumSQ.u64 = 1871; Count.u64 = 1871; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_S : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_M : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 628; SumSQ.u64 = 628; Count.u64 = 628; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 846; SumSQ.u64 = 846; Count.u64 = 846; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 643; SumSQ.u64 = 643; Count.u64 = 643; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 439; SumSQ.u64 = 439; Count.u64 = 439; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 385; SumSQ.u64 = 385; Count.u64 = 385; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 22; SumSQ.u64 = 22; Count.u64 = 22; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_Fetch_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 261; SumSQ.u64 = 261; Count.u64 = 261; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 187; SumSQ.u64 = 187; Count.u64 = 187; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 284; SumSQ.u64 = 284; Count.u64 = 284; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_GetS : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetX : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetSX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_PutS : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_PutM : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckInv : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 1490; SumSQ.u64 = 1490; Count.u64 = 1490; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 245; SumSQ.u64 = 245; Count.u64 = 245; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Inv : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; + l2cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetS_hit : Accumulator : Sum.u64 = 4; SumSQ.u64 = 16; Count.u64 = 1; Min.u64 = 4; Max.u64 = 4; + l2cache3.latency_GetS_miss : Accumulator : Sum.u64 = 603584; SumSQ.u64 = 350064888; Count.u64 = 1269; Min.u64 = 51; Max.u64 = 1490; + l2cache3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_miss : Accumulator : Sum.u64 = 292585; SumSQ.u64 = 167673255; Count.u64 = 628; Min.u64 = 31; Max.u64 = 1487; + l2cache3.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 2619; SumSQ.u64 = 1776629; Count.u64 = 4; Min.u64 = 577; Max.u64 = 870; + l2cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 5396; SumSQ.u64 = 3088528; Count.u64 = 11; Min.u64 = 311; Max.u64 = 928; + l2cache3.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CacheHits : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.CacheMisses : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_E : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; + l2cache3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_E : Accumulator : Sum.u64 = 791; SumSQ.u64 = 791; Count.u64 = 791; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_M : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInvX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInvX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_ForceInv_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l2cache3.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.eventSent_PutE : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReceived : Accumulator : Sum.u64 = 8196; SumSQ.u64 = 8196; Count.u64 = 8196; Min.u64 = 1; Max.u64 = 1; + l2cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1951; SumSQ.u64 = 1951; Count.u64 = 1951; Min.u64 = 1; Max.u64 = 1; + l2cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.GetS_recv : Accumulator : Sum.u64 = 1270; SumSQ.u64 = 1270; Count.u64 = 1270; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetX_recv : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l2cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAll_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetSResp_recv : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l2cache3.GetXResp_recv : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l2cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutS_recv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutM_recv : Accumulator : Sum.u64 = 445; SumSQ.u64 = 445; Count.u64 = 445; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutE_recv : Accumulator : Sum.u64 = 798; SumSQ.u64 = 798; Count.u64 = 798; Min.u64 = 1; Max.u64 = 1; + l2cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Inv_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.Fetch_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInv_recv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchResp_recv : Accumulator : Sum.u64 = 239; SumSQ.u64 = 239; Count.u64 = 239; Min.u64 = 1; Max.u64 = 1; + l2cache3.FetchXResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; + l2cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l2cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache3.AckInv_recv : Accumulator : Sum.u64 = 288; SumSQ.u64 = 288; Count.u64 = 288; Min.u64 = 1; Max.u64 = 1; + l2cache3.AckPut_recv : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l2cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1070203; SumSQ.u64 = 10505659; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 16; + l2cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_I : Accumulator : Sum.u64 = 859; SumSQ.u64 = 859; Count.u64 = 859; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_S : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_M : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_I : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetX_I : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSX_I : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1323; SumSQ.u64 = 1323; Count.u64 = 1323; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_I : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_I : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutM_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_I : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 532; SumSQ.u64 = 532; Count.u64 = 532; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_I : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_GetS : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetX : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSX : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutS : Accumulator : Sum.u64 = 46; SumSQ.u64 = 46; Count.u64 = 46; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_PutM : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 538; SumSQ.u64 = 538; Count.u64 = 538; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_AckInv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 1323; SumSQ.u64 = 1323; Count.u64 = 1323; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Fetch : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInv : Accumulator : Sum.u64 = 509; SumSQ.u64 = 509; Count.u64 = 509; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_FetchInvX : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Inv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckPut : Accumulator : Sum.u64 = 870; SumSQ.u64 = 870; Count.u64 = 870; Min.u64 = 1; Max.u64 = 1; + l3cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetS_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetS_miss : Accumulator : Sum.u64 = 419062; SumSQ.u64 = 188961414; Count.u64 = 1125; Min.u64 = 43; Max.u64 = 1188; + l3cache0.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_miss : Accumulator : Sum.u64 = 284864; SumSQ.u64 = 137816628; Count.u64 = 727; Min.u64 = 47; Max.u64 = 1449; + l3cache0.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_miss : Accumulator : Sum.u64 = 16236; SumSQ.u64 = 6573562; Count.u64 = 45; Min.u64 = 270; Max.u64 = 645; + l3cache0.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSMiss_Arrival : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXMiss_Arrival : Accumulator : Sum.u64 = 717; SumSQ.u64 = 717; Count.u64 = 717; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Arrival : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetXMiss_Blocked : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CacheHits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CacheMisses : Accumulator : Sum.u64 = 1897; SumSQ.u64 = 1897; Count.u64 = 1897; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_AckPut_I : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_E : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l3cache0.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_I : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache0.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.eventSent_PutE : Accumulator : Sum.u64 = 454; SumSQ.u64 = 454; Count.u64 = 454; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReceived : Accumulator : Sum.u64 = 8161; SumSQ.u64 = 8161; Count.u64 = 8161; Min.u64 = 1; Max.u64 = 1; + l3cache0.TotalEventsReplayed : Accumulator : Sum.u64 = 1128; SumSQ.u64 = 1128; Count.u64 = 1128; Min.u64 = 1; Max.u64 = 1; + l3cache0.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.GetS_recv : Accumulator : Sum.u64 = 1125; SumSQ.u64 = 1125; Count.u64 = 1125; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetX_recv : Accumulator : Sum.u64 = 727; SumSQ.u64 = 727; Count.u64 = 727; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSX_recv : Accumulator : Sum.u64 = 45; SumSQ.u64 = 45; Count.u64 = 45; Min.u64 = 1; Max.u64 = 1; + l3cache0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAll_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetSResp_recv : Accumulator : Sum.u64 = 574; SumSQ.u64 = 574; Count.u64 = 574; Min.u64 = 1; Max.u64 = 1; + l3cache0.GetXResp_recv : Accumulator : Sum.u64 = 1323; SumSQ.u64 = 1323; Count.u64 = 1323; Min.u64 = 1; Max.u64 = 1; + l3cache0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutS_recv : Accumulator : Sum.u64 = 54; SumSQ.u64 = 54; Count.u64 = 54; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutM_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutE_recv : Accumulator : Sum.u64 = 455; SumSQ.u64 = 455; Count.u64 = 455; Min.u64 = 1; Max.u64 = 1; + l3cache0.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Inv_recv : Accumulator : Sum.u64 = 530; SumSQ.u64 = 530; Count.u64 = 530; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.Fetch_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchInv_recv : Accumulator : Sum.u64 = 510; SumSQ.u64 = 510; Count.u64 = 510; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchInvX_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchResp_recv : Accumulator : Sum.u64 = 532; SumSQ.u64 = 532; Count.u64 = 532; Min.u64 = 1; Max.u64 = 1; + l3cache0.FetchXResp_recv : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; + l3cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache0.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache0.AckInv_recv : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; + l3cache0.AckPut_recv : Accumulator : Sum.u64 = 857; SumSQ.u64 = 857; Count.u64 = 857; Min.u64 = 1; Max.u64 = 1; + l3cache0.MSHR_occupancy : Accumulator : Sum.u64 = 850293; SumSQ.u64 = 8756031; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 17; + l3cache0.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_I : Accumulator : Sum.u64 = 1030; SumSQ.u64 = 1030; Count.u64 = 1030; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_S : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_M : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_I : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetX_I : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSX_I : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1408; SumSQ.u64 = 1408; Count.u64 = 1408; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_I : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutM_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_I : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_I : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_GetS : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetX : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSX : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutS : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_PutM : Accumulator : Sum.u64 = 410; SumSQ.u64 = 410; Count.u64 = 410; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_AckInv : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 1408; SumSQ.u64 = 1408; Count.u64 = 1408; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Fetch : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInv : Accumulator : Sum.u64 = 395; SumSQ.u64 = 395; Count.u64 = 395; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_FetchInvX : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Inv : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckPut : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; + l3cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetS_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetS_miss : Accumulator : Sum.u64 = 499925; SumSQ.u64 = 275541585; Count.u64 = 1150; Min.u64 = 44; Max.u64 = 1745; + l3cache1.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_miss : Accumulator : Sum.u64 = 302687; SumSQ.u64 = 169746781; Count.u64 = 678; Min.u64 = 44; Max.u64 = 1744; + l3cache1.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_miss : Accumulator : Sum.u64 = 11457; SumSQ.u64 = 5923193; Count.u64 = 28; Min.u64 = 54; Max.u64 = 943; + l3cache1.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSMiss_Arrival : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXMiss_Arrival : Accumulator : Sum.u64 = 673; SumSQ.u64 = 673; Count.u64 = 673; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetXMiss_Blocked : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CacheHits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CacheMisses : Accumulator : Sum.u64 = 1856; SumSQ.u64 = 1856; Count.u64 = 1856; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_E : Accumulator : Sum.u64 = 577; SumSQ.u64 = 577; Count.u64 = 577; Min.u64 = 1; Max.u64 = 1; + l3cache1.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_I : Accumulator : Sum.u64 = 580; SumSQ.u64 = 580; Count.u64 = 580; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache1.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.eventSent_PutE : Accumulator : Sum.u64 = 577; SumSQ.u64 = 577; Count.u64 = 577; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReceived : Accumulator : Sum.u64 = 8073; SumSQ.u64 = 8073; Count.u64 = 8073; Min.u64 = 1; Max.u64 = 1; + l3cache1.TotalEventsReplayed : Accumulator : Sum.u64 = 1295; SumSQ.u64 = 1295; Count.u64 = 1295; Min.u64 = 1; Max.u64 = 1; + l3cache1.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.GetS_recv : Accumulator : Sum.u64 = 1150; SumSQ.u64 = 1150; Count.u64 = 1150; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetX_recv : Accumulator : Sum.u64 = 678; SumSQ.u64 = 678; Count.u64 = 678; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSX_recv : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; + l3cache1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAll_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetSResp_recv : Accumulator : Sum.u64 = 448; SumSQ.u64 = 448; Count.u64 = 448; Min.u64 = 1; Max.u64 = 1; + l3cache1.GetXResp_recv : Accumulator : Sum.u64 = 1408; SumSQ.u64 = 1408; Count.u64 = 1408; Min.u64 = 1; Max.u64 = 1; + l3cache1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutS_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutM_recv : Accumulator : Sum.u64 = 414; SumSQ.u64 = 414; Count.u64 = 414; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutE_recv : Accumulator : Sum.u64 = 580; SumSQ.u64 = 580; Count.u64 = 580; Min.u64 = 1; Max.u64 = 1; + l3cache1.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Inv_recv : Accumulator : Sum.u64 = 418; SumSQ.u64 = 418; Count.u64 = 418; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.Fetch_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchInv_recv : Accumulator : Sum.u64 = 398; SumSQ.u64 = 398; Count.u64 = 398; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchInvX_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchResp_recv : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; + l3cache1.FetchXResp_recv : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; + l3cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache1.AckInv_recv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l3cache1.AckPut_recv : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; + l3cache1.MSHR_occupancy : Accumulator : Sum.u64 = 1019310; SumSQ.u64 = 9963976; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 17; + l3cache1.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_I : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_S : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_M : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetS_I : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetX_I : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetSX_I : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_I : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_I : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_PutM_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Inv_I : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Fetch_I : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 504; SumSQ.u64 = 504; Count.u64 = 504; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 519; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_AckInv_I : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_GetS : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetX : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetSX : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_PutS : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_PutM : Accumulator : Sum.u64 = 461; SumSQ.u64 = 461; Count.u64 = 461; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushAll : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchResp : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchXResp : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_AckInv : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetSResp : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_GetXResp : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_Fetch : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchInv : Accumulator : Sum.u64 = 503; SumSQ.u64 = 503; Count.u64 = 503; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_FetchInvX : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_Inv : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckPut : Accumulator : Sum.u64 = 1001; SumSQ.u64 = 1001; Count.u64 = 1001; Min.u64 = 1; Max.u64 = 1; + l3cache2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetS_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetS_miss : Accumulator : Sum.u64 = 439555; SumSQ.u64 = 224369713; Count.u64 = 1035; Min.u64 = 44; Max.u64 = 1193; + l3cache2.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetX_miss : Accumulator : Sum.u64 = 342178; SumSQ.u64 = 171763096; Count.u64 = 834; Min.u64 = 47; Max.u64 = 1512; + l3cache2.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetSX_miss : Accumulator : Sum.u64 = 17190; SumSQ.u64 = 8461122; Count.u64 = 42; Min.u64 = 271; Max.u64 = 881; + l3cache2.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSMiss_Arrival : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXMiss_Arrival : Accumulator : Sum.u64 = 827; SumSQ.u64 = 827; Count.u64 = 827; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSXMiss_Arrival : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetXMiss_Blocked : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.CacheHits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.CacheMisses : Accumulator : Sum.u64 = 1911; SumSQ.u64 = 1911; Count.u64 = 1911; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_AckPut_I : Accumulator : Sum.u64 = 987; SumSQ.u64 = 987; Count.u64 = 987; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_E : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; + l3cache2.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutE_I : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache2.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.eventSent_PutE : Accumulator : Sum.u64 = 484; SumSQ.u64 = 484; Count.u64 = 484; Min.u64 = 1; Max.u64 = 1; + l3cache2.TotalEventsReceived : Accumulator : Sum.u64 = 8197; SumSQ.u64 = 8197; Count.u64 = 8197; Min.u64 = 1; Max.u64 = 1; + l3cache2.TotalEventsReplayed : Accumulator : Sum.u64 = 1259; SumSQ.u64 = 1259; Count.u64 = 1259; Min.u64 = 1; Max.u64 = 1; + l3cache2.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.GetS_recv : Accumulator : Sum.u64 = 1035; SumSQ.u64 = 1035; Count.u64 = 1035; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetX_recv : Accumulator : Sum.u64 = 834; SumSQ.u64 = 834; Count.u64 = 834; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSX_recv : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l3cache2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAll_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetSResp_recv : Accumulator : Sum.u64 = 453; SumSQ.u64 = 453; Count.u64 = 453; Min.u64 = 1; Max.u64 = 1; + l3cache2.GetXResp_recv : Accumulator : Sum.u64 = 1458; SumSQ.u64 = 1458; Count.u64 = 1458; Min.u64 = 1; Max.u64 = 1; + l3cache2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.FlushAllResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; + l3cache2.PutS_recv : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; + l3cache2.PutM_recv : Accumulator : Sum.u64 = 466; SumSQ.u64 = 466; Count.u64 = 466; Min.u64 = 1; Max.u64 = 1; + l3cache2.PutE_recv : Accumulator : Sum.u64 = 485; SumSQ.u64 = 485; Count.u64 = 485; Min.u64 = 1; Max.u64 = 1; + l3cache2.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.Inv_recv : Accumulator : Sum.u64 = 420; SumSQ.u64 = 420; Count.u64 = 420; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.Fetch_recv : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchInv_recv : Accumulator : Sum.u64 = 505; SumSQ.u64 = 505; Count.u64 = 505; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchInvX_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchResp_recv : Accumulator : Sum.u64 = 519; SumSQ.u64 = 519; Count.u64 = 519; Min.u64 = 1; Max.u64 = 1; + l3cache2.FetchXResp_recv : Accumulator : Sum.u64 = 26; SumSQ.u64 = 26; Count.u64 = 26; Min.u64 = 1; Max.u64 = 1; + l3cache2.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache2.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache2.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache2.AckInv_recv : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; + l3cache2.AckPut_recv : Accumulator : Sum.u64 = 987; SumSQ.u64 = 987; Count.u64 = 987; Min.u64 = 1; Max.u64 = 1; + l3cache2.MSHR_occupancy : Accumulator : Sum.u64 = 936663; SumSQ.u64 = 9568387; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 16; + l3cache2.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_I : Accumulator : Sum.u64 = 1142; SumSQ.u64 = 1142; Count.u64 = 1142; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_S : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_M : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetS_I : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetX_I : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetSX_I : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetSResp_I : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_GetXResp_I : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutS_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutM_I : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_PutM_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Inv_I : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInvX_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Fetch_I : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Fetch_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchResp_I : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchXResp_I : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_AckInv_I : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_GetS : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_GetX : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_GetSX : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_PutS : Accumulator : Sum.u64 = 35; SumSQ.u64 = 35; Count.u64 = 35; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_PutM : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushAll : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_FetchResp : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_FetchXResp : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_AckInv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_GetSResp : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_GetXResp : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_Fetch : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_FetchInv : Accumulator : Sum.u64 = 373; SumSQ.u64 = 373; Count.u64 = 373; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_FetchInvX : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_Inv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_AckPut : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; + l3cache3.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetS_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetS_miss : Accumulator : Sum.u64 = 594701; SumSQ.u64 = 341676893; Count.u64 = 1269; Min.u64 = 44; Max.u64 = 1483; + l3cache3.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetX_miss : Accumulator : Sum.u64 = 290780; SumSQ.u64 = 165347996; Count.u64 = 632; Min.u64 = 24; Max.u64 = 1480; + l3cache3.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetSX_miss : Accumulator : Sum.u64 = 5319; SumSQ.u64 = 3013523; Count.u64 = 11; Min.u64 = 304; Max.u64 = 921; + l3cache3.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSMiss_Arrival : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetXMiss_Arrival : Accumulator : Sum.u64 = 628; SumSQ.u64 = 628; Count.u64 = 628; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetSXMiss_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetXMiss_Blocked : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.CacheHits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.CacheMisses : Accumulator : Sum.u64 = 1912; SumSQ.u64 = 1912; Count.u64 = 1912; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_AckPut_I : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_E : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; + l3cache3.evict_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutS_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutE_I : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_PutE_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutM_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_PutX_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l3cache3.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.eventSent_PutE : Accumulator : Sum.u64 = 739; SumSQ.u64 = 739; Count.u64 = 739; Min.u64 = 1; Max.u64 = 1; + l3cache3.TotalEventsReceived : Accumulator : Sum.u64 = 8206; SumSQ.u64 = 8206; Count.u64 = 8206; Min.u64 = 1; Max.u64 = 1; + l3cache3.TotalEventsReplayed : Accumulator : Sum.u64 = 1411; SumSQ.u64 = 1411; Count.u64 = 1411; Min.u64 = 1; Max.u64 = 1; + l3cache3.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.GetS_recv : Accumulator : Sum.u64 = 1269; SumSQ.u64 = 1269; Count.u64 = 1269; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetX_recv : Accumulator : Sum.u64 = 632; SumSQ.u64 = 632; Count.u64 = 632; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetSX_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; + l3cache3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushAll_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetSResp_recv : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l3cache3.GetXResp_recv : Accumulator : Sum.u64 = 1489; SumSQ.u64 = 1489; Count.u64 = 1489; Min.u64 = 1; Max.u64 = 1; + l3cache3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.FlushAllResp_recv : Accumulator : Sum.u64 = 36; SumSQ.u64 = 36; Count.u64 = 36; Min.u64 = 1; Max.u64 = 1; + l3cache3.PutS_recv : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l3cache3.PutM_recv : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; + l3cache3.PutE_recv : Accumulator : Sum.u64 = 741; SumSQ.u64 = 741; Count.u64 = 741; Min.u64 = 1; Max.u64 = 1; + l3cache3.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.Inv_recv : Accumulator : Sum.u64 = 397; SumSQ.u64 = 397; Count.u64 = 397; Min.u64 = 1; Max.u64 = 1; + l3cache3.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.Fetch_recv : Accumulator : Sum.u64 = 13; SumSQ.u64 = 13; Count.u64 = 13; Min.u64 = 1; Max.u64 = 1; + l3cache3.FetchInv_recv : Accumulator : Sum.u64 = 376; SumSQ.u64 = 376; Count.u64 = 376; Min.u64 = 1; Max.u64 = 1; + l3cache3.FetchInvX_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache3.FetchResp_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; + l3cache3.FetchXResp_recv : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; + l3cache3.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache3.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache3.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l3cache3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache3.AckInv_recv : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l3cache3.AckPut_recv : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; + l3cache3.MSHR_occupancy : Accumulator : Sum.u64 = 1067442; SumSQ.u64 = 10472948; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 17; + l3cache3.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_I : Accumulator : Sum.u64 = 8305; SumSQ.u64 = 8305; Count.u64 = 8305; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IS : Accumulator : Sum.u64 = 2096; SumSQ.u64 = 2096; Count.u64 = 2096; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IM : Accumulator : Sum.u64 = 1328; SumSQ.u64 = 1328; Count.u64 = 1328; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_M : Accumulator : Sum.u64 = 2677; SumSQ.u64 = 2677; Count.u64 = 2677; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.evict_MInv : Accumulator : Sum.u64 = 417; SumSQ.u64 = 417; Count.u64 = 417; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_MInvX : Accumulator : Sum.u64 = 10; SumSQ.u64 = 10; Count.u64 = 10; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 4394; SumSQ.u64 = 4394; Count.u64 = 4394; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetS_IA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 83; SumSQ.u64 = 83; Count.u64 = 83; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 2756; SumSQ.u64 = 2756; Count.u64 = 2756; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 42; SumSQ.u64 = 42; Count.u64 = 42; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 4394; SumSQ.u64 = 4394; Count.u64 = 4394; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 2879; SumSQ.u64 = 2879; Count.u64 = 2879; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetXResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_M : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutS_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_M : Accumulator : Sum.u64 = 1580; SumSQ.u64 = 1580; Count.u64 = 1580; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_MInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Inv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_SA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_MInv : Accumulator : Sum.u64 = 1402; SumSQ.u64 = 1402; Count.u64 = 1402; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FetchResp_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_MD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SBD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchXResp_MInvX : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_AckInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_MInv : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_AckInv_SInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SMInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckInv_SBInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 7261; SumSQ.u64 = 7261; Count.u64 = 7261; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FlushLine_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLine_SMD : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_MB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetS : Accumulator : Sum.u64 = 4394; SumSQ.u64 = 4394; Count.u64 = 4394; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetX : Accumulator : Sum.u64 = 2756; SumSQ.u64 = 2756; Count.u64 = 2756; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetSX : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutM : Accumulator : Sum.u64 = 2960; SumSQ.u64 = 2960; Count.u64 = 2960; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAll : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_AckFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_GetSResp : Accumulator : Sum.u64 = 1898; SumSQ.u64 = 1898; Count.u64 = 1898; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_GetXResp : Accumulator : Sum.u64 = 5678; SumSQ.u64 = 5678; Count.u64 = 5678; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Inv : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Fetch : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1789; SumSQ.u64 = 1789; Count.u64 = 1789; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_FetchInvX : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckPut : Accumulator : Sum.u64 = 4012; SumSQ.u64 = 4012; Count.u64 = 4012; Min.u64 = 1; Max.u64 = 1; + l4cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomReq : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetS_hit : Accumulator : Sum.u64 = 59265; SumSQ.u64 = 28340721; Count.u64 = 185; Min.u64 = 32; Max.u64 = 1170; + l4cache.latency_GetS_miss : Accumulator : Sum.u64 = 1810903; SumSQ.u64 = 929028093; Count.u64 = 4394; Min.u64 = 257; Max.u64 = 1711; + l4cache.latency_GetS_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_hit : Accumulator : Sum.u64 = 35192; SumSQ.u64 = 16273544; Count.u64 = 115; Min.u64 = 8; Max.u64 = 911; + l4cache.latency_GetX_miss : Accumulator : Sum.u64 = 1133695; SumSQ.u64 = 583107689; Count.u64 = 2756; Min.u64 = 257; Max.u64 = 1714; + l4cache.latency_GetX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_hit : Accumulator : Sum.u64 = 635; SumSQ.u64 = 178549; Count.u64 = 3; Min.u64 = 41; Max.u64 = 312; + l4cache.latency_GetSX_miss : Accumulator : Sum.u64 = 47351; SumSQ.u64 = 21974309; Count.u64 = 123; Min.u64 = 257; Max.u64 = 915; + l4cache.latency_GetSX_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSHit_Blocked : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXHit_Blocked : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 2379; SumSQ.u64 = 2379; Count.u64 = 2379; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 1495; SumSQ.u64 = 1495; Count.u64 = 1495; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 2015; SumSQ.u64 = 2015; Count.u64 = 2015; Min.u64 = 1; Max.u64 = 1; + l4cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 1261; SumSQ.u64 = 1261; Count.u64 = 1261; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; + l4cache.CacheHits : Accumulator : Sum.u64 = 303; SumSQ.u64 = 303; Count.u64 = 303; Min.u64 = 1; Max.u64 = 1; + l4cache.CacheMisses : Accumulator : Sum.u64 = 7273; SumSQ.u64 = 7273; Count.u64 = 7273; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_E : Accumulator : Sum.u64 = 4006; SumSQ.u64 = 4006; Count.u64 = 4006; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_ED : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_EInv : Accumulator : Sum.u64 = 638; SumSQ.u64 = 638; Count.u64 = 638; Min.u64 = 1; Max.u64 = 1; + l4cache.evict_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutS_E : Accumulator : Sum.u64 = 101; SumSQ.u64 = 101; Count.u64 = 101; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutS_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_ED : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutS_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_MInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutE_E : Accumulator : Sum.u64 = 2253; SumSQ.u64 = 2253; Count.u64 = 2253; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutE_EInv : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutE_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutX_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_E : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_PutM_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_PutM_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInvX_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_Fetch_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EA : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_ForceInv_EInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_EInv : Accumulator : Sum.u64 = 385; SumSQ.u64 = 385; Count.u64 = 385; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FetchResp_EInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FetchResp_ED : Accumulator : Sum.u64 = 88; SumSQ.u64 = 88; Count.u64 = 88; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FetchXResp_EInvX : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_AckInv_EInv : Accumulator : Sum.u64 = 1663; SumSQ.u64 = 1663; Count.u64 = 1663; Min.u64 = 1; Max.u64 = 1; + l4cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.stateEvent_FlushLineInv_EB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.eventSent_PutE : Accumulator : Sum.u64 = 4301; SumSQ.u64 = 4301; Count.u64 = 4301; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReceived : Accumulator : Sum.u64 = 30994; SumSQ.u64 = 30994; Count.u64 = 30994; Min.u64 = 1; Max.u64 = 1; + l4cache.TotalEventsReplayed : Accumulator : Sum.u64 = 14321; SumSQ.u64 = 14321; Count.u64 = 14321; Min.u64 = 1; Max.u64 = 1; + l4cache.Put_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Get_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckMove_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetS_recv : Accumulator : Sum.u64 = 4579; SumSQ.u64 = 4579; Count.u64 = 4579; Min.u64 = 1; Max.u64 = 1; + l4cache.GetX_recv : Accumulator : Sum.u64 = 2871; SumSQ.u64 = 2871; Count.u64 = 2871; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSX_recv : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; + l4cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAll_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.GetXResp_recv : Accumulator : Sum.u64 = 7273; SumSQ.u64 = 7273; Count.u64 = 7273; Min.u64 = 1; Max.u64 = 1; + l4cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FlushAllResp_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.PutS_recv : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; + l4cache.PutM_recv : Accumulator : Sum.u64 = 1593; SumSQ.u64 = 1593; Count.u64 = 1593; Min.u64 = 1; Max.u64 = 1; + l4cache.PutE_recv : Accumulator : Sum.u64 = 2254; SumSQ.u64 = 2254; Count.u64 = 2254; Min.u64 = 1; Max.u64 = 1; + l4cache.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.FetchResp_recv : Accumulator : Sum.u64 = 1875; SumSQ.u64 = 1875; Count.u64 = 1875; Min.u64 = 1; Max.u64 = 1; + l4cache.FetchXResp_recv : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; + l4cache.ForwardFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.AckFlush_recv : Accumulator : Sum.u64 = 568; SumSQ.u64 = 568; Count.u64 = 568; Min.u64 = 1; Max.u64 = 1; + l4cache.UnblockFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + l4cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.AckInv_recv : Accumulator : Sum.u64 = 1765; SumSQ.u64 = 1765; Count.u64 = 1765; Min.u64 = 1; Max.u64 = 1; + l4cache.AckPut_recv : Accumulator : Sum.u64 = 7261; SumSQ.u64 = 7261; Count.u64 = 7261; Min.u64 = 1; Max.u64 = 1; + l4cache.MSHR_occupancy : Accumulator : Sum.u64 = 3433306; SumSQ.u64 = 106032138; Count.u64 = 184516; Min.u64 = 0; Max.u64 = 57; + l4cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.replacement_request_latency : Accumulator : Sum.u64 = 123240; SumSQ.u64 = 83545076; Count.u64 = 7403; Min.u64 = 2; Max.u64 = 1207; + directory.get_request_latency : Accumulator : Sum.u64 = 1275013; SumSQ.u64 = 224480409; Count.u64 = 7273; Min.u64 = 165; Max.u64 = 212; + directory.directory_cache_hits : Accumulator : Sum.u64 = 14534; SumSQ.u64 = 14534; Count.u64 = 14534; Min.u64 = 1; Max.u64 = 1; + directory.mshr_hits : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetX_recv : Accumulator : Sum.u64 = 2756; SumSQ.u64 = 2756; Count.u64 = 2756; Min.u64 = 1; Max.u64 = 1; + directory.GetS_recv : Accumulator : Sum.u64 = 4394; SumSQ.u64 = 4394; Count.u64 = 4394; Min.u64 = 1; Max.u64 = 1; + directory.GetSX_recv : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + directory.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutM_recv : Accumulator : Sum.u64 = 2960; SumSQ.u64 = 2960; Count.u64 = 2960; Min.u64 = 1; Max.u64 = 1; + directory.PutX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.PutE_recv : Accumulator : Sum.u64 = 4301; SumSQ.u64 = 4301; Count.u64 = 4301; Min.u64 = 1; Max.u64 = 1; + directory.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetXResp_recv : Accumulator : Sum.u64 = 7273; SumSQ.u64 = 7273; Count.u64 = 7273; Min.u64 = 1; Max.u64 = 1; + directory.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.AckFlush_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + directory.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.FlushAll_recv : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + directory.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.GetSResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.WriteResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomReq_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetS : Accumulator : Sum.u64 = 4394; SumSQ.u64 = 4394; Count.u64 = 4394; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetX : Accumulator : Sum.u64 = 2756; SumSQ.u64 = 2756; Count.u64 = 2756; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_GetSX : Accumulator : Sum.u64 = 123; SumSQ.u64 = 123; Count.u64 = 123; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_PutM : Accumulator : Sum.u64 = 2960; SumSQ.u64 = 2960; Count.u64 = 2960; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_Inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_ForwardFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetSResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_GetXResp : Accumulator : Sum.u64 = 7273; SumSQ.u64 = 7273; Count.u64 = 7273; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_AckPut : Accumulator : Sum.u64 = 7261; SumSQ.u64 = 7261; Count.u64 = 7261; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_FlushAllResp : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_UnblockFlush : Accumulator : Sum.u64 = 142; SumSQ.u64 = 142; Count.u64 = 142; Min.u64 = 1; Max.u64 = 1; + directory.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.MSHR_occupancy : Accumulator : Sum.u64 = 1361817; SumSQ.u64 = 24973537; Count.u64 = 122880; Min.u64 = 0; Max.u64 = 34; +Simulation is complete, simulated time: 61.4438 us diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out index d95c6c1be3..3064dd7e12 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl2_1.out @@ -71,13 +71,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1449; SumSQ.u64 = 1449; Count.u64 = 1449; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 948; SumSQ.u64 = 948; Count.u64 = 948; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -85,7 +88,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -104,6 +107,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1419; SumSQ.u64 = 1419; Count.u64 = 1419; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 916; SumSQ.u64 = 916; Count.u64 = 916; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; @@ -141,20 +145,24 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.Write_recv : Accumulator : Sum.u64 = 948; SumSQ.u64 = 948; Count.u64 = 948; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSResp_recv : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.MSHR_occupancy : Accumulator : Sum.u64 = 17745; SumSQ.u64 = 251289; Count.u64 = 3430; Min.u64 = 0; Max.u64 = 16; l1cache.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -262,8 +270,11 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -272,6 +283,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -296,6 +310,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 8; SumSQ.u64 = 8; Count.u64 = 8; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -331,10 +346,12 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -346,6 +363,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out index 1ebd73cebc..c4a09d40fd 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_1.out @@ -71,13 +71,16 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 325; SumSQ.u64 = 325; Count.u64 = 325; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 30; SumSQ.u64 = 30; Count.u64 = 30; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 1719; SumSQ.u64 = 1719; Count.u64 = 1719; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 113; SumSQ.u64 = 113; Count.u64 = 113; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 1168; SumSQ.u64 = 1168; Count.u64 = 1168; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -85,7 +88,7 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.mesi.evict_I : Accumulator : Sum.u64 = 716; SumSQ.u64 = 716; Count.u64 = 716; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.evict_I : Accumulator : Sum.u64 = 720; SumSQ.u64 = 720; Count.u64 = 720; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.evict_S : Accumulator : Sum.u64 = 421; SumSQ.u64 = 421; Count.u64 = 421; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.evict_M : Accumulator : Sum.u64 = 599; SumSQ.u64 = 599; Count.u64 = 599; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.evict_IS : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; @@ -104,6 +107,7 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 404; SumSQ.u64 = 404; Count.u64 = 404; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; @@ -150,14 +154,18 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache0.mesi.Write_recv : Accumulator : Sum.u64 = 1168; SumSQ.u64 = 1168; Count.u64 = 1168; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.GetSResp_recv : Accumulator : Sum.u64 = 282; SumSQ.u64 = 282; Count.u64 = 282; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.GetXResp_recv : Accumulator : Sum.u64 = 1344; SumSQ.u64 = 1344; Count.u64 = 1344; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Inv_recv : Accumulator : Sum.u64 = 58; SumSQ.u64 = 58; Count.u64 = 58; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.FetchInv_recv : Accumulator : Sum.u64 = 139; SumSQ.u64 = 139; Count.u64 = 139; Min.u64 = 1; Max.u64 = 1; l1cache0.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 551; SumSQ.u64 = 551; Count.u64 = 551; Min.u64 = 1; Max.u64 = 1; + l1cache0.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 260630; SumSQ.u64 = 3848492; Count.u64 = 17932; Min.u64 = 0; Max.u64 = 16; @@ -232,13 +240,16 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 118; SumSQ.u64 = 118; Count.u64 = 118; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 104; SumSQ.u64 = 104; Count.u64 = 104; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 2437; SumSQ.u64 = 2437; Count.u64 = 2437; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -246,7 +257,7 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.mesi.evict_I : Accumulator : Sum.u64 = 765; SumSQ.u64 = 765; Count.u64 = 765; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.evict_I : Accumulator : Sum.u64 = 776; SumSQ.u64 = 776; Count.u64 = 776; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.evict_S : Accumulator : Sum.u64 = 458; SumSQ.u64 = 458; Count.u64 = 458; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.evict_M : Accumulator : Sum.u64 = 356; SumSQ.u64 = 356; Count.u64 = 356; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.evict_IS : Accumulator : Sum.u64 = 464; SumSQ.u64 = 464; Count.u64 = 464; Min.u64 = 1; Max.u64 = 1; @@ -265,6 +276,7 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 521; SumSQ.u64 = 521; Count.u64 = 521; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,20 +323,24 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l1cache1.mesi.Write_recv : Accumulator : Sum.u64 = 563; SumSQ.u64 = 563; Count.u64 = 563; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.GetSResp_recv : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.GetXResp_recv : Accumulator : Sum.u64 = 1218; SumSQ.u64 = 1218; Count.u64 = 1218; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Inv_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.FetchInv_recv : Accumulator : Sum.u64 = 235; SumSQ.u64 = 235; Count.u64 = 235; Min.u64 = 1; Max.u64 = 1; l1cache1.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; + l1cache1.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 256368; SumSQ.u64 = 3772802; Count.u64 = 17932; Min.u64 = 0; Max.u64 = 16; l1cache1.mesi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l2cache.mesi.inclus.evict_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -432,8 +448,11 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache.mesi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -442,6 +461,9 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache.mesi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2562; SumSQ.u64 = 2562; Count.u64 = 2562; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 374; SumSQ.u64 = 374; Count.u64 = 374; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -466,6 +488,7 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache.mesi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 2115; SumSQ.u64 = 2115; Count.u64 = 2115; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 1004; SumSQ.u64 = 1004; Count.u64 = 1004; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; @@ -536,10 +559,12 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache.mesi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.PutS_recv : Accumulator : Sum.u64 = 877; SumSQ.u64 = 877; Count.u64 = 877; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.PutM_recv : Accumulator : Sum.u64 = 955; SumSQ.u64 = 955; Count.u64 = 955; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.PutE_recv : Accumulator : Sum.u64 = 833; SumSQ.u64 = 833; Count.u64 = 833; Min.u64 = 1; Max.u64 = 1; @@ -551,6 +576,9 @@ l2cache.mesi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...int l2cache.mesi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 556; SumSQ.u64 = 556; Count.u64 = 556; Min.u64 = 1; Max.u64 = 1; + l2cache.mesi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.mesi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.mesi.inclus.AckInv_recv : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; l2cache.mesi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out index 4a039adb54..00d2f224dd 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_2.out @@ -73,13 +73,16 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 80; SumSQ.u64 = 80; Count.u64 = 80; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1604; SumSQ.u64 = 1604; Count.u64 = 1604; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -87,7 +90,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 1101; SumSQ.u64 = 1101; Count.u64 = 1101; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 854; SumSQ.u64 = 854; Count.u64 = 854; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 921; SumSQ.u64 = 921; Count.u64 = 921; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 428; SumSQ.u64 = 428; Count.u64 = 428; Min.u64 = 1; Max.u64 = 1; @@ -106,6 +109,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 212; SumSQ.u64 = 212; Count.u64 = 212; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; @@ -143,14 +147,18 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 1066; SumSQ.u64 = 1066; Count.u64 = 1066; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 1108; SumSQ.u64 = 1108; Count.u64 = 1108; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 163; SumSQ.u64 = 163; Count.u64 = 163; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 205; SumSQ.u64 = 205; Count.u64 = 205; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 301164; SumSQ.u64 = 4451430; Count.u64 = 20647; Min.u64 = 0; Max.u64 = 16; @@ -227,13 +235,16 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 68; SumSQ.u64 = 68; Count.u64 = 68; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_AckInv : Accumulator : Sum.u64 = 114; SumSQ.u64 = 114; Count.u64 = 114; Min.u64 = 1; Max.u64 = 1; + l1cache.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1853; SumSQ.u64 = 1853; Count.u64 = 1853; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1096; SumSQ.u64 = 1096; Count.u64 = 1096; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -241,7 +252,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.msi.evict_I : Accumulator : Sum.u64 = 1203; SumSQ.u64 = 1203; Count.u64 = 1203; Min.u64 = 1; Max.u64 = 1; + l1cache.msi.evict_I : Accumulator : Sum.u64 = 1206; SumSQ.u64 = 1206; Count.u64 = 1206; Min.u64 = 1; Max.u64 = 1; l1cache.msi.evict_S : Accumulator : Sum.u64 = 1029; SumSQ.u64 = 1029; Count.u64 = 1029; Min.u64 = 1; Max.u64 = 1; l1cache.msi.evict_M : Accumulator : Sum.u64 = 800; SumSQ.u64 = 800; Count.u64 = 800; Min.u64 = 1; Max.u64 = 1; l1cache.msi.evict_IS : Accumulator : Sum.u64 = 549; SumSQ.u64 = 549; Count.u64 = 549; Min.u64 = 1; Max.u64 = 1; @@ -260,6 +271,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 225; SumSQ.u64 = 225; Count.u64 = 225; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -297,20 +309,24 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.Write_recv : Accumulator : Sum.u64 = 1096; SumSQ.u64 = 1096; Count.u64 = 1096; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSResp_recv : Accumulator : Sum.u64 = 1246; SumSQ.u64 = 1246; Count.u64 = 1246; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXResp_recv : Accumulator : Sum.u64 = 953; SumSQ.u64 = 953; Count.u64 = 953; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Inv_recv : Accumulator : Sum.u64 = 231; SumSQ.u64 = 231; Count.u64 = 231; Min.u64 = 1; Max.u64 = 1; l1cache.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInv_recv : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FetchInvX_recv : Accumulator : Sum.u64 = 161; SumSQ.u64 = 161; Count.u64 = 161; Min.u64 = 1; Max.u64 = 1; + l1cache.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.MSHR_occupancy : Accumulator : Sum.u64 = 298951; SumSQ.u64 = 4413725; Count.u64 = 20647; Min.u64 = 0; Max.u64 = 16; l1cache.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; @@ -418,8 +434,11 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -428,6 +447,9 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2061; SumSQ.u64 = 2061; Count.u64 = 2061; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 312; SumSQ.u64 = 312; Count.u64 = 312; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -452,6 +474,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1181; SumSQ.u64 = 70539; Count.u64 = 24; Min.u64 = 30; Max.u64 = 78; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1042; SumSQ.u64 = 1042; Count.u64 = 1042; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 614; SumSQ.u64 = 614; Count.u64 = 614; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 37; SumSQ.u64 = 37; Count.u64 = 37; Min.u64 = 1; Max.u64 = 1; @@ -487,10 +510,12 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 1171; SumSQ.u64 = 1171; Count.u64 = 1171; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 1877; SumSQ.u64 = 1877; Count.u64 = 1877; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 1720; SumSQ.u64 = 1720; Count.u64 = 1720; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -502,13 +527,16 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 148; SumSQ.u64 = 148; Count.u64 = 148; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 211; SumSQ.u64 = 211; Count.u64 = 211; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 130264; SumSQ.u64 = 1057044; Count.u64 = 20647; Min.u64 = 0; Max.u64 = 27; l2cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -616,8 +644,11 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -626,6 +657,9 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 1335; SumSQ.u64 = 1335; Count.u64 = 1335; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -650,6 +684,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 71; SumSQ.u64 = 5041; Count.u64 = 1; Min.u64 = 71; Max.u64 = 71; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1139; SumSQ.u64 = 1139; Count.u64 = 1139; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 1234; SumSQ.u64 = 1234; Count.u64 = 1234; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 53; SumSQ.u64 = 53; Count.u64 = 53; Min.u64 = 1; Max.u64 = 1; @@ -685,10 +720,12 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 653; SumSQ.u64 = 653; Count.u64 = 653; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 1312; SumSQ.u64 = 1312; Count.u64 = 1312; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -700,13 +737,16 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 46383; SumSQ.u64 = 697579; Count.u64 = 82588; Min.u64 = 0; Max.u64 = 24; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l4cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 47; SumSQ.u64 = 47; Count.u64 = 47; Min.u64 = 1; Max.u64 = 1; + l4cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l4cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -814,8 +854,11 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l4cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -824,6 +867,9 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l4cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l4cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -848,6 +894,7 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l4cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; l4cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -883,10 +930,12 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l4cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 48; SumSQ.u64 = 48; Count.u64 = 48; Min.u64 = 1; Max.u64 = 1; l4cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -898,6 +947,9 @@ l4cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l4cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l4cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l4cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out index 507ad190cc..481cc42fed 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl3_3.out @@ -69,13 +69,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1191; SumSQ.u64 = 1191; Count.u64 = 1191; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -83,7 +86,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -102,6 +105,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 169; SumSQ.u64 = 169; Count.u64 = 169; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -139,14 +143,18 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 809; SumSQ.u64 = 809; Count.u64 = 809; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 204; SumSQ.u64 = 204; Count.u64 = 204; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 146490; SumSQ.u64 = 2136662; Count.u64 = 10409; Min.u64 = 0; Max.u64 = 16; @@ -221,13 +229,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1229; SumSQ.u64 = 1229; Count.u64 = 1229; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 771; SumSQ.u64 = 771; Count.u64 = 771; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -235,7 +246,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -254,6 +265,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 580; SumSQ.u64 = 580; Count.u64 = 580; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -291,20 +303,24 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 771; SumSQ.u64 = 771; Count.u64 = 771; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 193; SumSQ.u64 = 193; Count.u64 = 193; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 184; SumSQ.u64 = 184; Count.u64 = 184; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 198; SumSQ.u64 = 198; Count.u64 = 198; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 143807; SumSQ.u64 = 2101939; Count.u64 = 10409; Min.u64 = 0; Max.u64 = 16; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 21; SumSQ.u64 = 21; Count.u64 = 21; Min.u64 = 1; Max.u64 = 1; - l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -412,8 +428,11 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -422,6 +441,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 783; SumSQ.u64 = 783; Count.u64 = 783; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -446,6 +468,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 624; SumSQ.u64 = 624; Count.u64 = 624; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -481,10 +504,12 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -496,6 +521,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out index dae551ea3e..f423b88104 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_1.out @@ -69,13 +69,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1286; SumSQ.u64 = 1286; Count.u64 = 1286; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 714; SumSQ.u64 = 714; Count.u64 = 714; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -83,7 +86,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -102,6 +105,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 619; SumSQ.u64 = 619; Count.u64 = 619; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -139,14 +143,18 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 714; SumSQ.u64 = 714; Count.u64 = 714; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 182; SumSQ.u64 = 182; Count.u64 = 182; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 197; SumSQ.u64 = 197; Count.u64 = 197; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 146086; SumSQ.u64 = 2073612; Count.u64 = 10763; Min.u64 = 0; Max.u64 = 16; @@ -221,13 +229,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1320; SumSQ.u64 = 1320; Count.u64 = 1320; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -235,7 +246,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -254,6 +265,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 633; SumSQ.u64 = 633; Count.u64 = 633; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 140; SumSQ.u64 = 140; Count.u64 = 140; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -291,20 +303,24 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 680; SumSQ.u64 = 680; Count.u64 = 680; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 203; SumSQ.u64 = 203; Count.u64 = 203; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 341; SumSQ.u64 = 341; Count.u64 = 341; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 207; SumSQ.u64 = 207; Count.u64 = 207; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 189; SumSQ.u64 = 189; Count.u64 = 189; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 142553; SumSQ.u64 = 2019351; Count.u64 = 10763; Min.u64 = 0; Max.u64 = 16; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 24; SumSQ.u64 = 24; Count.u64 = 24; Min.u64 = 1; Max.u64 = 1; - l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -412,8 +428,11 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -422,6 +441,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 704; SumSQ.u64 = 704; Count.u64 = 704; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -446,6 +468,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 589; SumSQ.u64 = 589; Count.u64 = 589; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -481,10 +504,12 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -496,6 +521,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 307; SumSQ.u64 = 307; Count.u64 = 307; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 386; SumSQ.u64 = 386; Count.u64 = 386; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 389; SumSQ.u64 = 389; Count.u64 = 389; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out index 506e16730f..0b533c83ae 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl4_2.out @@ -69,13 +69,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2258; SumSQ.u64 = 2258; Count.u64 = 2258; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -83,7 +86,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -102,6 +105,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1391; SumSQ.u64 = 1391; Count.u64 = 1391; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -139,14 +143,18 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 742; SumSQ.u64 = 742; Count.u64 = 742; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 348; SumSQ.u64 = 348; Count.u64 = 348; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 495; SumSQ.u64 = 495; Count.u64 = 495; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 329; SumSQ.u64 = 329; Count.u64 = 329; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 318; SumSQ.u64 = 318; Count.u64 = 318; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 162925; SumSQ.u64 = 1135839; Count.u64 = 24845; Min.u64 = 0; Max.u64 = 8; @@ -221,13 +229,16 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2236; SumSQ.u64 = 2236; Count.u64 = 2236; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 764; SumSQ.u64 = 764; Count.u64 = 764; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -235,7 +246,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -254,6 +265,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1426; SumSQ.u64 = 1426; Count.u64 = 1426; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -291,20 +303,24 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 764; SumSQ.u64 = 764; Count.u64 = 764; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 326; SumSQ.u64 = 326; Count.u64 = 326; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 497; SumSQ.u64 = 497; Count.u64 = 497; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 334; SumSQ.u64 = 334; Count.u64 = 334; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 158; SumSQ.u64 = 158; Count.u64 = 158; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 160340; SumSQ.u64 = 1117822; Count.u64 = 24845; Min.u64 = 0; Max.u64 = 8; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; - l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -412,8 +428,11 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -422,6 +441,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 992; SumSQ.u64 = 992; Count.u64 = 992; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -446,6 +468,7 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 660; SumSQ.u64 = 660; Count.u64 = 660; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -481,10 +504,12 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -496,6 +521,9 @@ l2cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 324; SumSQ.u64 = 324; Count.u64 = 324; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 657; SumSQ.u64 = 657; Count.u64 = 657; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 663; SumSQ.u64 = 663; Count.u64 = 663; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out index 10b809f318..10e37fac03 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl5_1.out @@ -73,13 +73,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1769; SumSQ.u64 = 1769; Count.u64 = 1769; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -87,7 +90,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -106,6 +109,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 355; SumSQ.u64 = 355; Count.u64 = 355; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 67; SumSQ.u64 = 67; Count.u64 = 67; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; @@ -143,14 +147,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 1147; SumSQ.u64 = 1147; Count.u64 = 1147; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 558; SumSQ.u64 = 558; Count.u64 = 558; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 710; SumSQ.u64 = 710; Count.u64 = 710; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 682; SumSQ.u64 = 682; Count.u64 = 682; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 291; SumSQ.u64 = 291; Count.u64 = 291; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1043160; SumSQ.u64 = 16188208; Count.u64 = 67866; Min.u64 = 0; Max.u64 = 16; @@ -227,13 +235,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1647; SumSQ.u64 = 1647; Count.u64 = 1647; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1253; SumSQ.u64 = 1253; Count.u64 = 1253; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -241,7 +252,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache1.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -260,6 +271,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 357; SumSQ.u64 = 357; Count.u64 = 357; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 74; SumSQ.u64 = 74; Count.u64 = 74; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; @@ -297,20 +309,24 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 1253; SumSQ.u64 = 1253; Count.u64 = 1253; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 499; SumSQ.u64 = 499; Count.u64 = 499; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 670; SumSQ.u64 = 670; Count.u64 = 670; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 396; SumSQ.u64 = 396; Count.u64 = 396; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1034043; SumSQ.u64 = 16029179; Count.u64 = 67866; Min.u64 = 0; Max.u64 = 16; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -418,8 +434,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache0.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 541; SumSQ.u64 = 541; Count.u64 = 541; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 364; SumSQ.u64 = 364; Count.u64 = 364; Min.u64 = 1; Max.u64 = 1; @@ -428,6 +447,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache0.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 1441; SumSQ.u64 = 1441; Count.u64 = 1441; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 804; SumSQ.u64 = 804; Count.u64 = 804; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -452,6 +474,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache0.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 23771; SumSQ.u64 = 13452379; Count.u64 = 45; Min.u64 = 343; Max.u64 = 1000; l2cache0.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 214; SumSQ.u64 = 214; Count.u64 = 214; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 174; SumSQ.u64 = 174; Count.u64 = 174; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 14; SumSQ.u64 = 14; Count.u64 = 14; Min.u64 = 1; Max.u64 = 1; @@ -487,10 +510,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache0.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 369; SumSQ.u64 = 369; Count.u64 = 369; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 892; SumSQ.u64 = 892; Count.u64 = 892; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -502,6 +527,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache0.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 804; SumSQ.u64 = 804; Count.u64 = 804; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 626; SumSQ.u64 = 626; Count.u64 = 626; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 1352; SumSQ.u64 = 1352; Count.u64 = 1352; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -579,13 +607,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1699; SumSQ.u64 = 1699; Count.u64 = 1699; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1201; SumSQ.u64 = 1201; Count.u64 = 1201; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -593,7 +624,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache2.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -612,6 +643,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -649,14 +681,18 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 1201; SumSQ.u64 = 1201; Count.u64 = 1201; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 514; SumSQ.u64 = 514; Count.u64 = 514; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 743; SumSQ.u64 = 743; Count.u64 = 743; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 679; SumSQ.u64 = 679; Count.u64 = 679; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 407; SumSQ.u64 = 407; Count.u64 = 407; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 335; SumSQ.u64 = 335; Count.u64 = 335; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1031249; SumSQ.u64 = 15989195; Count.u64 = 67866; Min.u64 = 0; Max.u64 = 16; @@ -733,13 +769,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 691; SumSQ.u64 = 691; Count.u64 = 691; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1716; SumSQ.u64 = 1716; Count.u64 = 1716; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 85; SumSQ.u64 = 85; Count.u64 = 85; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1199; SumSQ.u64 = 1199; Count.u64 = 1199; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -747,7 +786,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache3.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -766,6 +805,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 62; SumSQ.u64 = 62; Count.u64 = 62; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -803,20 +843,24 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 1199; SumSQ.u64 = 1199; Count.u64 = 1199; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 527; SumSQ.u64 = 527; Count.u64 = 527; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 731; SumSQ.u64 = 731; Count.u64 = 731; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 691; SumSQ.u64 = 691; Count.u64 = 691; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 401; SumSQ.u64 = 401; Count.u64 = 401; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 330; SumSQ.u64 = 330; Count.u64 = 330; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1026483; SumSQ.u64 = 15916217; Count.u64 = 67866; Min.u64 = 0; Max.u64 = 16; l1cache3.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -924,8 +968,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 546; SumSQ.u64 = 546; Count.u64 = 546; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 339; SumSQ.u64 = 339; Count.u64 = 339; Min.u64 = 1; Max.u64 = 1; @@ -934,6 +981,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 1474; SumSQ.u64 = 1474; Count.u64 = 1474; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -958,6 +1008,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 25727; SumSQ.u64 = 15020671; Count.u64 = 47; Min.u64 = 343; Max.u64 = 935; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 213; SumSQ.u64 = 213; Count.u64 = 213; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 190; SumSQ.u64 = 190; Count.u64 = 190; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 17; SumSQ.u64 = 17; Count.u64 = 17; Min.u64 = 1; Max.u64 = 1; @@ -993,10 +1044,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 905; SumSQ.u64 = 905; Count.u64 = 905; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1008,13 +1061,16 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 808; SumSQ.u64 = 808; Count.u64 = 808; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 665; SumSQ.u64 = 665; Count.u64 = 665; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 1370; SumSQ.u64 = 1370; Count.u64 = 1370; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 1029871; SumSQ.u64 = 16289059; Count.u64 = 67866; Min.u64 = 0; Max.u64 = 24; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.default_stat : Accumulator : Sum.u64 = 27; SumSQ.u64 = 27; Count.u64 = 27; Min.u64 = 1; Max.u64 = 1; - l3cache.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1122,8 +1178,11 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1132,6 +1191,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.eventSent_GetXResp : Accumulator : Sum.u64 = 1797; SumSQ.u64 = 1797; Count.u64 = 1797; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.eventSent_FetchInv : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; l3cache.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1156,6 +1218,7 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSHit_Arrival : Accumulator : Sum.u64 = 693; SumSQ.u64 = 693; Count.u64 = 693; Min.u64 = 1; Max.u64 = 1; l3cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1330; SumSQ.u64 = 1330; Count.u64 = 1330; Min.u64 = 1; Max.u64 = 1; l3cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; @@ -1191,10 +1254,12 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1206,6 +1271,9 @@ l3cache: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated to l3cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.FetchResp_recv : Accumulator : Sum.u64 = 1087; SumSQ.u64 = 1087; Count.u64 = 1087; Min.u64 = 1; Max.u64 = 1; l3cache.FetchXResp_recv : Accumulator : Sum.u64 = 696; SumSQ.u64 = 696; Count.u64 = 696; Min.u64 = 1; Max.u64 = 1; + l3cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.AckInv_recv : Accumulator : Sum.u64 = 703; SumSQ.u64 = 703; Count.u64 = 703; Min.u64 = 1; Max.u64 = 1; l3cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out index 3be693cf7e..c360f3633f 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_1.out @@ -72,13 +72,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5720; SumSQ.u64 = 5720; Count.u64 = 5720; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 299; SumSQ.u64 = 299; Count.u64 = 299; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 3981; SumSQ.u64 = 3981; Count.u64 = 3981; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 168; SumSQ.u64 = 168; Count.u64 = 168; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; @@ -142,14 +146,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.Write_recv : Accumulator : Sum.u64 = 3981; SumSQ.u64 = 3981; Count.u64 = 3981; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSResp_recv : Accumulator : Sum.u64 = 5507; SumSQ.u64 = 5507; Count.u64 = 5507; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXResp_recv : Accumulator : Sum.u64 = 3900; SumSQ.u64 = 3900; Count.u64 = 3900; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.MSHR_occupancy : Accumulator : Sum.u64 = 17645086; SumSQ.u64 = 280502148; Count.u64 = 1111628; Min.u64 = 0; Max.u64 = 16; @@ -263,8 +271,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 3062; SumSQ.u64 = 3062; Count.u64 = 3062; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 3087; SumSQ.u64 = 3087; Count.u64 = 3087; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -273,6 +284,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3900; SumSQ.u64 = 3900; Count.u64 = 3900; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -297,6 +311,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 101190; SumSQ.u64 = 296307356; Count.u64 = 49; Min.u64 = 168; Max.u64 = 3831; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1581; SumSQ.u64 = 1581; Count.u64 = 1581; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 522; SumSQ.u64 = 522; Count.u64 = 522; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 43; SumSQ.u64 = 43; Count.u64 = 43; Min.u64 = 1; Max.u64 = 1; @@ -332,10 +347,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 3926; SumSQ.u64 = 3926; Count.u64 = 3926; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3335; SumSQ.u64 = 3335; Count.u64 = 3335; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5375; SumSQ.u64 = 5375; Count.u64 = 5375; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3880; SumSQ.u64 = 3880; Count.u64 = 3880; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -347,15 +364,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 15877451; SumSQ.u64 = 228659393; Count.u64 = 1111628; Min.u64 = 0; Max.u64 = 16; l2cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 701792; SumSQ.u64 = 63863072; Count.u64 = 7712; Min.u64 = 91; Max.u64 = 91; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 1433600; SumSQ.u64 = 633208832; Count.u64 = 7712; Min.u64 = 64; Max.u64 = 576; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 28466500000; Count.u64 = 2; Min.u64 = 60500; Max.u64 = 157500; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 701792; SumSQ.u64 = 63863072; Count.u64 = 7712; Min.u64 = 91; Max.u64 = 91; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 1433600; SumSQ.u64 = 633208832; Count.u64 = 7712; Min.u64 = 64; Max.u64 = 576; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 28466500000; Count.u64 = 2; Min.u64 = 60500; Max.u64 = 157500; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -465,8 +485,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 1083; SumSQ.u64 = 1083; Count.u64 = 1083; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1836; SumSQ.u64 = 1836; Count.u64 = 1836; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -475,6 +498,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3335; SumSQ.u64 = 3335; Count.u64 = 3335; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -499,6 +525,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 209063; SumSQ.u64 = 643716893; Count.u64 = 70; Min.u64 = 1757; Max.u64 = 3897; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1632; SumSQ.u64 = 1632; Count.u64 = 1632; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 773; SumSQ.u64 = 773; Count.u64 = 773; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 63; SumSQ.u64 = 63; Count.u64 = 63; Min.u64 = 1; Max.u64 = 1; @@ -534,10 +561,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 2294; SumSQ.u64 = 2294; Count.u64 = 2294; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 2499; SumSQ.u64 = 2499; Count.u64 = 2499; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 3062; SumSQ.u64 = 3062; Count.u64 = 3062; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3087; SumSQ.u64 = 3087; Count.u64 = 3087; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -549,15 +578,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 2919; SumSQ.u64 = 2919; Count.u64 = 2919; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 15027092; SumSQ.u64 = 205239368; Count.u64 = 1111628; Min.u64 = 0; Max.u64 = 16; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 1025696; SumSQ.u64 = 136417568; Count.u64 = 7712; Min.u64 = 133; Max.u64 = 133; - directory.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 3452416; SumSQ.u64 = 1925251072; Count.u64 = 7712; Min.u64 = 64; Max.u64 = 576; - directory.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.idle_time : Accumulator : Sum.u64 = 353000; SumSQ.u64 = 88069000000; Count.u64 = 2; Min.u64 = 63000; Max.u64 = 290000; + directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 1025696; SumSQ.u64 = 136417568; Count.u64 = 7712; Min.u64 = 133; Max.u64 = 133; + directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 3452416; SumSQ.u64 = 1925251072; Count.u64 = 7712; Min.u64 = 64; Max.u64 = 576; + directory.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi:highlink.idle_time : Accumulator : Sum.u64 = 353000; SumSQ.u64 = 88069000000; Count.u64 = 2; Min.u64 = 63000; Max.u64 = 290000; directory.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.replacement_request_latency : Accumulator : Sum.u64 = 5838; SumSQ.u64 = 11676; Count.u64 = 2919; Min.u64 = 2; Max.u64 = 2; directory.msi.get_request_latency : Accumulator : Sum.u64 = 494575; SumSQ.u64 = 61612775; Count.u64 = 4793; Min.u64 = 2; Max.u64 = 125; @@ -580,8 +612,10 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -600,6 +634,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2294; SumSQ.u64 = 2294; Count.u64 = 2294; Min.u64 = 1; Max.u64 = 1; directory.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 2499; SumSQ.u64 = 2499; Count.u64 = 2499; Min.u64 = 1; Max.u64 = 1; @@ -610,6 +645,8 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.MSHR_occupancy : Accumulator : Sum.u64 = 484989; SumSQ.u64 = 577809; Count.u64 = 555607; Min.u64 = 0; Max.u64 = 2; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out index 3275bd48df..d629807a63 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_3.out @@ -73,13 +73,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 89; SumSQ.u64 = 89; Count.u64 = 89; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 134; SumSQ.u64 = 134; Count.u64 = 134; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 120; SumSQ.u64 = 120; Count.u64 = 120; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2855; SumSQ.u64 = 2855; Count.u64 = 2855; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 2014; Count.u64 = 2014; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -106,6 +109,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 91; SumSQ.u64 = 91; Count.u64 = 91; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 49; SumSQ.u64 = 49; Count.u64 = 49; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -143,14 +147,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 2014; Count.u64 = 2014; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 2739; SumSQ.u64 = 2739; Count.u64 = 2739; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 1980; SumSQ.u64 = 1980; Count.u64 = 1980; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 94; SumSQ.u64 = 94; Count.u64 = 94; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 35771754; SumSQ.u64 = 571065328; Count.u64 = 2249700; Min.u64 = 0; Max.u64 = 16; @@ -227,13 +235,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 135; SumSQ.u64 = 135; Count.u64 = 135; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2845; SumSQ.u64 = 2845; Count.u64 = 2845; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 154; SumSQ.u64 = 154; Count.u64 = 154; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2001; SumSQ.u64 = 2001; Count.u64 = 2001; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -260,6 +271,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 57; SumSQ.u64 = 57; Count.u64 = 57; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -297,20 +309,24 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 2001; SumSQ.u64 = 2001; Count.u64 = 2001; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 2753; SumSQ.u64 = 2753; Count.u64 = 2753; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 1967; SumSQ.u64 = 1967; Count.u64 = 1967; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 144; SumSQ.u64 = 144; Count.u64 = 144; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 138; SumSQ.u64 = 138; Count.u64 = 138; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 35815862; SumSQ.u64 = 571733732; Count.u64 = 2249700; Min.u64 = 0; Max.u64 = 16; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 1601; SumSQ.u64 = 1601; Count.u64 = 1601; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 1602; SumSQ.u64 = 1602; Count.u64 = 1602; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_S : Accumulator : Sum.u64 = 3132; SumSQ.u64 = 3132; Count.u64 = 3132; Min.u64 = 1; Max.u64 = 1; @@ -418,8 +434,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 3132; SumSQ.u64 = 3132; Count.u64 = 3132; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1993; SumSQ.u64 = 1993; Count.u64 = 1993; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 496; SumSQ.u64 = 496; Count.u64 = 496; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 773; SumSQ.u64 = 773; Count.u64 = 773; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 687; SumSQ.u64 = 687; Count.u64 = 687; Min.u64 = 1; Max.u64 = 1; @@ -428,6 +447,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3947; SumSQ.u64 = 3947; Count.u64 = 3947; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 194; SumSQ.u64 = 194; Count.u64 = 194; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -452,6 +474,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 469601; SumSQ.u64 = 6610664623; Count.u64 = 47; Min.u64 = 208; Max.u64 = 26398; l2cache0.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1440; SumSQ.u64 = 1440; Count.u64 = 1440; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 416; SumSQ.u64 = 416; Count.u64 = 416; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 29; SumSQ.u64 = 29; Count.u64 = 29; Min.u64 = 1; Max.u64 = 1; @@ -487,10 +510,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 4007; SumSQ.u64 = 4007; Count.u64 = 4007; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3475; SumSQ.u64 = 3475; Count.u64 = 3475; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5328; SumSQ.u64 = 5328; Count.u64 = 5328; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3440; SumSQ.u64 = 3440; Count.u64 = 3440; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -502,6 +527,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 773; SumSQ.u64 = 773; Count.u64 = 773; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 269; SumSQ.u64 = 269; Count.u64 = 269; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 263; SumSQ.u64 = 263; Count.u64 = 263; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -579,13 +607,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2901; SumSQ.u64 = 2901; Count.u64 = 2901; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -612,6 +643,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 52; SumSQ.u64 = 52; Count.u64 = 52; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -649,14 +681,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 1950; SumSQ.u64 = 1950; Count.u64 = 1950; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 2796; SumSQ.u64 = 2796; Count.u64 = 2796; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 1922; SumSQ.u64 = 1922; Count.u64 = 1922; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 151; SumSQ.u64 = 151; Count.u64 = 151; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 71; SumSQ.u64 = 71; Count.u64 = 71; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 35684735; SumSQ.u64 = 569585769; Count.u64 = 2249700; Min.u64 = 0; Max.u64 = 16; @@ -733,13 +769,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 96; SumSQ.u64 = 96; Count.u64 = 96; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 121; SumSQ.u64 = 121; Count.u64 = 121; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 130; SumSQ.u64 = 130; Count.u64 = 130; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2818; SumSQ.u64 = 2818; Count.u64 = 2818; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 149; SumSQ.u64 = 149; Count.u64 = 149; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2033; SumSQ.u64 = 2033; Count.u64 = 2033; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -766,6 +805,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 86; SumSQ.u64 = 86; Count.u64 = 86; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 50; SumSQ.u64 = 50; Count.u64 = 50; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -803,14 +843,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 2033; SumSQ.u64 = 2033; Count.u64 = 2033; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 2712; SumSQ.u64 = 2712; Count.u64 = 2712; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 2000; SumSQ.u64 = 2000; Count.u64 = 2000; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 133; SumSQ.u64 = 133; Count.u64 = 133; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 125; SumSQ.u64 = 125; Count.u64 = 125; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 35908891; SumSQ.u64 = 573501587; Count.u64 = 2249700; Min.u64 = 0; Max.u64 = 16; @@ -924,8 +968,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 3108; SumSQ.u64 = 3108; Count.u64 = 3108; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1965; SumSQ.u64 = 1965; Count.u64 = 1965; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 538; SumSQ.u64 = 538; Count.u64 = 538; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 704; SumSQ.u64 = 704; Count.u64 = 704; Min.u64 = 1; Max.u64 = 1; @@ -934,6 +981,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3922; SumSQ.u64 = 3922; Count.u64 = 3922; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 171; SumSQ.u64 = 171; Count.u64 = 171; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -958,6 +1008,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 510597; SumSQ.u64 = 6873460207; Count.u64 = 61; Min.u64 = 208; Max.u64 = 22534; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1430; SumSQ.u64 = 1430; Count.u64 = 1430; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 412; SumSQ.u64 = 412; Count.u64 = 412; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 25; SumSQ.u64 = 25; Count.u64 = 25; Min.u64 = 1; Max.u64 = 1; @@ -993,10 +1044,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 4033; SumSQ.u64 = 4033; Count.u64 = 4033; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3465; SumSQ.u64 = 3465; Count.u64 = 3465; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5312; SumSQ.u64 = 5312; Count.u64 = 5312; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3453; SumSQ.u64 = 3453; Count.u64 = 3453; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1008,17 +1061,20 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 166; SumSQ.u64 = 166; Count.u64 = 166; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 250; SumSQ.u64 = 250; Count.u64 = 250; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 275; SumSQ.u64 = 275; Count.u64 = 275; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 65194282; SumSQ.u64 = 1899838472; Count.u64 = 2249700; Min.u64 = 0; Max.u64 = 33; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 1420965; SumSQ.u64 = 129307815; Count.u64 = 15615; Min.u64 = 91; Max.u64 = 91; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 3114432; SumSQ.u64 = 1417605120; Count.u64 = 15615; Min.u64 = 64; Max.u64 = 576; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 33146500000; Count.u64 = 2; Min.u64 = 40500; Max.u64 = 177500; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 1420965; SumSQ.u64 = 129307815; Count.u64 = 15615; Min.u64 = 91; Max.u64 = 91; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 3114432; SumSQ.u64 = 1417605120; Count.u64 = 15615; Min.u64 = 64; Max.u64 = 576; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 33146500000; Count.u64 = 2; Min.u64 = 40500; Max.u64 = 177500; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 1023; SumSQ.u64 = 1023; Count.u64 = 1023; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 1024; SumSQ.u64 = 1024; Count.u64 = 1024; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 2258; SumSQ.u64 = 2258; Count.u64 = 2258; Min.u64 = 1; Max.u64 = 1; @@ -1126,8 +1182,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 2258; SumSQ.u64 = 2258; Count.u64 = 2258; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 4131; SumSQ.u64 = 4131; Count.u64 = 4131; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1136,6 +1195,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 6940; SumSQ.u64 = 6940; Count.u64 = 6940; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1160,6 +1222,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 1803952; SumSQ.u64 = 25131477202; Count.u64 = 134; Min.u64 = 7859; Max.u64 = 28419; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 3426; SumSQ.u64 = 3426; Count.u64 = 3426; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 1923; SumSQ.u64 = 1923; Count.u64 = 1923; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; @@ -1195,10 +1258,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 4417; SumSQ.u64 = 4417; Count.u64 = 4417; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 4809; SumSQ.u64 = 4809; Count.u64 = 4809; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 6240; SumSQ.u64 = 6240; Count.u64 = 6240; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3958; SumSQ.u64 = 3958; Count.u64 = 3958; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1210,15 +1275,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1034; SumSQ.u64 = 1034; Count.u64 = 1034; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 1510; SumSQ.u64 = 1510; Count.u64 = 1510; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 1391; SumSQ.u64 = 1391; Count.u64 = 1391; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 6389; SumSQ.u64 = 6389; Count.u64 = 6389; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 126469137; SumSQ.u64 = 7142946351; Count.u64 = 2249700; Min.u64 = 0; Max.u64 = 63; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 1764495; SumSQ.u64 = 199387935; Count.u64 = 15615; Min.u64 = 113; Max.u64 = 113; - directory.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 6909888; SumSQ.u64 = 3846696960; Count.u64 = 15615; Min.u64 = 64; Max.u64 = 576; - directory.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.idle_time : Accumulator : Sum.u64 = 373000; SumSQ.u64 = 90989000000; Count.u64 = 2; Min.u64 = 83000; Max.u64 = 290000; + directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 1764495; SumSQ.u64 = 199387935; Count.u64 = 15615; Min.u64 = 113; Max.u64 = 113; + directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 6909888; SumSQ.u64 = 3846696960; Count.u64 = 15615; Min.u64 = 64; Max.u64 = 576; + directory.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi:highlink.idle_time : Accumulator : Sum.u64 = 373000; SumSQ.u64 = 90989000000; Count.u64 = 2; Min.u64 = 83000; Max.u64 = 290000; directory.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.replacement_request_latency : Accumulator : Sum.u64 = 12778; SumSQ.u64 = 25556; Count.u64 = 6389; Min.u64 = 2; Max.u64 = 2; directory.msi.get_request_latency : Accumulator : Sum.u64 = 930251; SumSQ.u64 = 115835377; Count.u64 = 9226; Min.u64 = 2; Max.u64 = 125; @@ -1241,8 +1309,10 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1261,6 +1331,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 4417; SumSQ.u64 = 4417; Count.u64 = 4417; Min.u64 = 1; Max.u64 = 1; directory.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 4809; SumSQ.u64 = 4809; Count.u64 = 4809; Min.u64 = 1; Max.u64 = 1; @@ -1271,6 +1342,8 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.MSHR_occupancy : Accumulator : Sum.u64 = 911799; SumSQ.u64 = 1005537; Count.u64 = 1124623; Min.u64 = 0; Max.u64 = 2; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out index c87ffd14b0..7541eb00d4 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl8_4.out @@ -73,13 +73,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 760; SumSQ.u64 = 760; Count.u64 = 760; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2868; SumSQ.u64 = 2868; Count.u64 = 2868; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1979; SumSQ.u64 = 1979; Count.u64 = 1979; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -87,7 +90,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache0.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -106,6 +109,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 351; SumSQ.u64 = 351; Count.u64 = 351; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 69; SumSQ.u64 = 69; Count.u64 = 69; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; @@ -143,14 +147,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 1979; SumSQ.u64 = 1979; Count.u64 = 1979; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 569; SumSQ.u64 = 569; Count.u64 = 569; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 888; SumSQ.u64 = 888; Count.u64 = 888; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 760; SumSQ.u64 = 760; Count.u64 = 760; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 550; SumSQ.u64 = 550; Count.u64 = 550; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 338; SumSQ.u64 = 338; Count.u64 = 338; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2215615; SumSQ.u64 = 68884561; Count.u64 = 72920; Min.u64 = 0; Max.u64 = 32; @@ -227,13 +235,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2873; SumSQ.u64 = 2873; Count.u64 = 2873; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 165; SumSQ.u64 = 165; Count.u64 = 165; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1962; SumSQ.u64 = 1962; Count.u64 = 1962; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -241,7 +252,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -260,6 +271,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 402; SumSQ.u64 = 402; Count.u64 = 402; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 65; SumSQ.u64 = 65; Count.u64 = 65; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; @@ -297,20 +309,24 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 1962; SumSQ.u64 = 1962; Count.u64 = 1962; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 546; SumSQ.u64 = 546; Count.u64 = 546; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 902; SumSQ.u64 = 902; Count.u64 = 902; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 737; SumSQ.u64 = 737; Count.u64 = 737; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 545; SumSQ.u64 = 545; Count.u64 = 545; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 346; SumSQ.u64 = 346; Count.u64 = 346; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2256637; SumSQ.u64 = 70251591; Count.u64 = 72920; Min.u64 = 0; Max.u64 = 32; l1cache1.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -418,8 +434,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 734; SumSQ.u64 = 734; Count.u64 = 734; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 365; SumSQ.u64 = 365; Count.u64 = 365; Min.u64 = 1; Max.u64 = 1; @@ -428,6 +447,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 1790; SumSQ.u64 = 1790; Count.u64 = 1790; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1095; SumSQ.u64 = 1095; Count.u64 = 1095; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -452,6 +474,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 35422; SumSQ.u64 = 22866546; Count.u64 = 58; Min.u64 = 343; Max.u64 = 927; l2cache0.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 132; SumSQ.u64 = 132; Count.u64 = 132; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 110; SumSQ.u64 = 110; Count.u64 = 110; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; @@ -487,10 +510,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 367; SumSQ.u64 = 367; Count.u64 = 367; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 1098; SumSQ.u64 = 1098; Count.u64 = 1098; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -502,6 +527,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache0.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 353; SumSQ.u64 = 353; Count.u64 = 353; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1095; SumSQ.u64 = 1095; Count.u64 = 1095; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 684; SumSQ.u64 = 684; Count.u64 = 684; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -579,13 +607,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 520; SumSQ.u64 = 520; Count.u64 = 520; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2855; SumSQ.u64 = 2855; Count.u64 = 2855; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 153; SumSQ.u64 = 153; Count.u64 = 153; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -593,7 +624,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache2.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -612,6 +643,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 427; SumSQ.u64 = 427; Count.u64 = 427; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 64; SumSQ.u64 = 64; Count.u64 = 64; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; @@ -649,14 +681,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 1992; SumSQ.u64 = 1992; Count.u64 = 1992; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 553; SumSQ.u64 = 553; Count.u64 = 553; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 886; SumSQ.u64 = 886; Count.u64 = 886; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 772; SumSQ.u64 = 772; Count.u64 = 772; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 520; SumSQ.u64 = 520; Count.u64 = 520; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 363; SumSQ.u64 = 363; Count.u64 = 363; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2247026; SumSQ.u64 = 69943786; Count.u64 = 72920; Min.u64 = 0; Max.u64 = 32; @@ -733,13 +769,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 2847; SumSQ.u64 = 2847; Count.u64 = 2847; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 2001; SumSQ.u64 = 2001; Count.u64 = 2001; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -747,7 +786,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache3.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -766,6 +805,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 70; SumSQ.u64 = 70; Count.u64 = 70; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; @@ -803,20 +843,24 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 2001; SumSQ.u64 = 2001; Count.u64 = 2001; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 562; SumSQ.u64 = 562; Count.u64 = 562; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 867; SumSQ.u64 = 867; Count.u64 = 867; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 750; SumSQ.u64 = 750; Count.u64 = 750; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 336; SumSQ.u64 = 336; Count.u64 = 336; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2200046; SumSQ.u64 = 68405064; Count.u64 = 72920; Min.u64 = 0; Max.u64 = 32; l1cache3.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache1.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -924,8 +968,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 740; SumSQ.u64 = 740; Count.u64 = 740; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 354; SumSQ.u64 = 354; Count.u64 = 354; Min.u64 = 1; Max.u64 = 1; @@ -934,6 +981,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 1753; SumSQ.u64 = 1753; Count.u64 = 1753; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -958,6 +1008,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 32575; SumSQ.u64 = 24912627; Count.u64 = 50; Min.u64 = 343; Max.u64 = 1898; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 137; SumSQ.u64 = 137; Count.u64 = 137; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 84; SumSQ.u64 = 84; Count.u64 = 84; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 12; SumSQ.u64 = 12; Count.u64 = 12; Min.u64 = 1; Max.u64 = 1; @@ -993,10 +1044,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 358; SumSQ.u64 = 358; Count.u64 = 358; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 1104; SumSQ.u64 = 1104; Count.u64 = 1104; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1008,17 +1061,20 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 361; SumSQ.u64 = 361; Count.u64 = 361; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1051; SumSQ.u64 = 1051; Count.u64 = 1051; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 699; SumSQ.u64 = 699; Count.u64 = 699; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 1522; SumSQ.u64 = 1522; Count.u64 = 1522; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 1522450; SumSQ.u64 = 32817964; Count.u64 = 72920; Min.u64 = 0; Max.u64 = 31; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 190463; Count.u64 = 23; Min.u64 = 91; Max.u64 = 91; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 1472; SumSQ.u64 = 94208; Count.u64 = 23; Min.u64 = 64; Max.u64 = 64; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 33146500000; Count.u64 = 2; Min.u64 = 40500; Max.u64 = 177500; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 2093; SumSQ.u64 = 190463; Count.u64 = 23; Min.u64 = 91; Max.u64 = 91; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 1472; SumSQ.u64 = 94208; Count.u64 = 23; Min.u64 = 64; Max.u64 = 64; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 218000; SumSQ.u64 = 33146500000; Count.u64 = 2; Min.u64 = 40500; Max.u64 = 177500; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1126,8 +1182,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1136,6 +1195,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 2202; SumSQ.u64 = 2202; Count.u64 = 2202; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 1474; SumSQ.u64 = 1474; Count.u64 = 1474; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1160,6 +1222,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 3325; SumSQ.u64 = 5560837; Count.u64 = 2; Min.u64 = 1534; Max.u64 = 1791; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 707; SumSQ.u64 = 707; Count.u64 = 707; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 1523; SumSQ.u64 = 1523; Count.u64 = 1523; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 126; SumSQ.u64 = 126; Count.u64 = 126; Min.u64 = 1; Max.u64 = 1; @@ -1195,10 +1258,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1210,15 +1275,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 1474; SumSQ.u64 = 1474; Count.u64 = 1474; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 714; SumSQ.u64 = 714; Count.u64 = 714; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 719; SumSQ.u64 = 719; Count.u64 = 719; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 1115158; SumSQ.u64 = 17926852; Count.u64 = 72920; Min.u64 = 0; Max.u64 = 32; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 2599; SumSQ.u64 = 293687; Count.u64 = 23; Min.u64 = 113; Max.u64 = 113; - directory.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 9664; SumSQ.u64 = 5337088; Count.u64 = 23; Min.u64 = 64; Max.u64 = 576; - directory.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.idle_time : Accumulator : Sum.u64 = 34607000; SumSQ.u64 = 1177740589000000; Count.u64 = 2; Min.u64 = 290000; Max.u64 = 34317000; + directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 2599; SumSQ.u64 = 293687; Count.u64 = 23; Min.u64 = 113; Max.u64 = 113; + directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 9664; SumSQ.u64 = 5337088; Count.u64 = 23; Min.u64 = 64; Max.u64 = 576; + directory.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi:highlink.idle_time : Accumulator : Sum.u64 = 34607000; SumSQ.u64 = 1177740589000000; Count.u64 = 2; Min.u64 = 290000; Max.u64 = 34317000; directory.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.get_request_latency : Accumulator : Sum.u64 = 2014; SumSQ.u64 = 250028; Count.u64 = 23; Min.u64 = 2; Max.u64 = 125; @@ -1241,8 +1309,10 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1261,6 +1331,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; directory.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; @@ -1271,6 +1342,8 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr directory.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1968; SumSQ.u64 = 3498; Count.u64 = 1876; Min.u64 = 0; Max.u64 = 2; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out index a2c34a930f..2a2c8078fa 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_1.out @@ -74,13 +74,16 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5684; SumSQ.u64 = 5684; Count.u64 = 5684; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 293; SumSQ.u64 = 293; Count.u64 = 293; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 4023; SumSQ.u64 = 4023; Count.u64 = 4023; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -107,6 +110,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 143; SumSQ.u64 = 143; Count.u64 = 143; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 41; SumSQ.u64 = 41; Count.u64 = 41; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; @@ -144,14 +148,18 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l1cache.msi.Write_recv : Accumulator : Sum.u64 = 3861; SumSQ.u64 = 3861; Count.u64 = 3861; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSResp_recv : Accumulator : Sum.u64 = 5214; SumSQ.u64 = 5214; Count.u64 = 5214; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXResp_recv : Accumulator : Sum.u64 = 3794; SumSQ.u64 = 3794; Count.u64 = 3794; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2991579; SumSQ.u64 = 88794617; Count.u64 = 101320; Min.u64 = 0; Max.u64 = 32; @@ -265,8 +273,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 2849; SumSQ.u64 = 2849; Count.u64 = 2849; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 2943; SumSQ.u64 = 2943; Count.u64 = 2943; Min.u64 = 1; Max.u64 = 1; + l2cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -275,6 +286,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3794; SumSQ.u64 = 3794; Count.u64 = 3794; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -299,6 +313,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 6552; SumSQ.u64 = 1100736; Count.u64 = 39; Min.u64 = 168; Max.u64 = 168; l2cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1528; SumSQ.u64 = 1528; Count.u64 = 1528; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 531; SumSQ.u64 = 531; Count.u64 = 531; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 51; SumSQ.u64 = 51; Count.u64 = 51; Min.u64 = 1; Max.u64 = 1; @@ -334,10 +349,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 3686; SumSQ.u64 = 3686; Count.u64 = 3686; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3212; SumSQ.u64 = 3212; Count.u64 = 3212; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 5072; SumSQ.u64 = 5072; Count.u64 = 5072; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 3763; SumSQ.u64 = 3763; Count.u64 = 3763; Min.u64 = 1; Max.u64 = 1; l2cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -349,6 +366,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l2cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -463,8 +483,11 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 901; SumSQ.u64 = 901; Count.u64 = 901; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 1652; SumSQ.u64 = 1652; Count.u64 = 1652; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -473,6 +496,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 3212; SumSQ.u64 = 3212; Count.u64 = 3212; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -497,6 +523,7 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 1607; SumSQ.u64 = 1607; Count.u64 = 1607; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 1595; SumSQ.u64 = 1595; Count.u64 = 1595; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 119; SumSQ.u64 = 119; Count.u64 = 119; Min.u64 = 1; Max.u64 = 1; @@ -532,10 +559,12 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 3577; SumSQ.u64 = 3577; Count.u64 = 3577; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 2849; SumSQ.u64 = 2849; Count.u64 = 2849; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 2943; SumSQ.u64 = 2943; Count.u64 = 2943; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -547,6 +576,9 @@ l3cache.msi.inclus: No MSHR lookup latency provided (mshr_latency_cycles)...intr l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out index 8ddf2ce51d..9410c9a650 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl9_2.out @@ -72,13 +72,16 @@ l1cache0.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1122; SumSQ.u64 = 1122; Count.u64 = 1122; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3385; SumSQ.u64 = 3385; Count.u64 = 3385; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5768; SumSQ.u64 = 5768; Count.u64 = 5768; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 270; SumSQ.u64 = 270; Count.u64 = 270; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 3962; SumSQ.u64 = 3962; Count.u64 = 3962; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -105,6 +108,7 @@ l1cache0.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1447; SumSQ.u64 = 1447; Count.u64 = 1447; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 382; SumSQ.u64 = 382; Count.u64 = 382; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; @@ -142,14 +146,18 @@ l1cache0.msi.Write_recv : Accumulator : Sum.u64 = 2999; SumSQ.u64 = 2999; Count.u64 = 2999; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.GetSResp_recv : Accumulator : Sum.u64 = 2608; SumSQ.u64 = 2608; Count.u64 = 2608; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.GetXResp_recv : Accumulator : Sum.u64 = 2566; SumSQ.u64 = 2566; Count.u64 = 2566; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Inv_recv : Accumulator : Sum.u64 = 3385; SumSQ.u64 = 3385; Count.u64 = 3385; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.FetchInv_recv : Accumulator : Sum.u64 = 1122; SumSQ.u64 = 1122; Count.u64 = 1122; Min.u64 = 1; Max.u64 = 1; l1cache0.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1444; SumSQ.u64 = 1444; Count.u64 = 1444; Min.u64 = 1; Max.u64 = 1; + l1cache0.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2656524; SumSQ.u64 = 16228918; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 28; @@ -226,13 +234,16 @@ l1cache1.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_AckInv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5678; SumSQ.u64 = 5678; Count.u64 = 5678; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 332; SumSQ.u64 = 332; Count.u64 = 332; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 3990; SumSQ.u64 = 3990; Count.u64 = 3990; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -240,7 +251,7 @@ l1cache1.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache1.msi.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -259,6 +270,7 @@ l1cache1.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 3634; SumSQ.u64 = 3634; Count.u64 = 3634; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 2283; SumSQ.u64 = 2283; Count.u64 = 2283; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 195; SumSQ.u64 = 195; Count.u64 = 195; Min.u64 = 1; Max.u64 = 1; @@ -296,14 +308,18 @@ l1cache1.msi.Write_recv : Accumulator : Sum.u64 = 3990; SumSQ.u64 = 3990; Count.u64 = 3990; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.GetSResp_recv : Accumulator : Sum.u64 = 186; SumSQ.u64 = 186; Count.u64 = 186; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.GetXResp_recv : Accumulator : Sum.u64 = 525; SumSQ.u64 = 525; Count.u64 = 525; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Inv_recv : Accumulator : Sum.u64 = 145; SumSQ.u64 = 145; Count.u64 = 145; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.FetchInv_recv : Accumulator : Sum.u64 = 223; SumSQ.u64 = 223; Count.u64 = 223; Min.u64 = 1; Max.u64 = 1; l1cache1.msi.FetchInvX_recv : Accumulator : Sum.u64 = 298; SumSQ.u64 = 298; Count.u64 = 298; Min.u64 = 1; Max.u64 = 1; + l1cache1.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2034645; SumSQ.u64 = 61862529; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 32; @@ -382,13 +398,16 @@ l1cache2.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1167; SumSQ.u64 = 1167; Count.u64 = 1167; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1424; SumSQ.u64 = 1424; Count.u64 = 1424; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3230; SumSQ.u64 = 3230; Count.u64 = 3230; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5715; SumSQ.u64 = 5715; Count.u64 = 5715; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 268; SumSQ.u64 = 268; Count.u64 = 268; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 4017; SumSQ.u64 = 4017; Count.u64 = 4017; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -415,6 +434,7 @@ l1cache2.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1523; SumSQ.u64 = 1523; Count.u64 = 1523; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 387; SumSQ.u64 = 387; Count.u64 = 387; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; @@ -452,14 +472,18 @@ l1cache2.msi.Write_recv : Accumulator : Sum.u64 = 3071; SumSQ.u64 = 3071; Count.u64 = 3071; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.GetSResp_recv : Accumulator : Sum.u64 = 2506; SumSQ.u64 = 2506; Count.u64 = 2506; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.GetXResp_recv : Accumulator : Sum.u64 = 2591; SumSQ.u64 = 2591; Count.u64 = 2591; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Inv_recv : Accumulator : Sum.u64 = 3230; SumSQ.u64 = 3230; Count.u64 = 3230; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.FetchInv_recv : Accumulator : Sum.u64 = 1167; SumSQ.u64 = 1167; Count.u64 = 1167; Min.u64 = 1; Max.u64 = 1; l1cache2.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1424; SumSQ.u64 = 1424; Count.u64 = 1424; Min.u64 = 1; Max.u64 = 1; + l1cache2.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache2.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache2.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2692867; SumSQ.u64 = 18029731; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 29; @@ -538,13 +562,16 @@ l1cache3.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1166; SumSQ.u64 = 1166; Count.u64 = 1166; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1393; SumSQ.u64 = 1393; Count.u64 = 1393; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3182; SumSQ.u64 = 3182; Count.u64 = 3182; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5744; SumSQ.u64 = 5744; Count.u64 = 5744; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 264; SumSQ.u64 = 264; Count.u64 = 264; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 3992; SumSQ.u64 = 3992; Count.u64 = 3992; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -571,6 +598,7 @@ l1cache3.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1442; SumSQ.u64 = 1442; Count.u64 = 1442; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 38; SumSQ.u64 = 38; Count.u64 = 38; Min.u64 = 1; Max.u64 = 1; @@ -608,20 +636,24 @@ l1cache3.msi.Write_recv : Accumulator : Sum.u64 = 3059; SumSQ.u64 = 3059; Count.u64 = 3059; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.GetSResp_recv : Accumulator : Sum.u64 = 2504; SumSQ.u64 = 2504; Count.u64 = 2504; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.GetXResp_recv : Accumulator : Sum.u64 = 2571; SumSQ.u64 = 2571; Count.u64 = 2571; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Inv_recv : Accumulator : Sum.u64 = 3182; SumSQ.u64 = 3182; Count.u64 = 3182; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.FetchInv_recv : Accumulator : Sum.u64 = 1166; SumSQ.u64 = 1166; Count.u64 = 1166; Min.u64 = 1; Max.u64 = 1; l1cache3.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1393; SumSQ.u64 = 1393; Count.u64 = 1393; Min.u64 = 1; Max.u64 = 1; + l1cache3.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache3.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache3.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2662247; SumSQ.u64 = 18134339; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 29; l1cache3.msi.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -729,8 +761,11 @@ l2cache0.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 2842; SumSQ.u64 = 2842; Count.u64 = 2842; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2561; SumSQ.u64 = 2561; Count.u64 = 2561; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 3034; SumSQ.u64 = 3034; Count.u64 = 3034; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 3504; SumSQ.u64 = 3504; Count.u64 = 3504; Min.u64 = 1; Max.u64 = 1; @@ -739,6 +774,9 @@ l2cache0.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 8253; SumSQ.u64 = 8253; Count.u64 = 8253; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 2842; SumSQ.u64 = 2842; Count.u64 = 2842; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 3678; SumSQ.u64 = 3678; Count.u64 = 3678; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -763,6 +801,7 @@ l2cache0.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 166912; SumSQ.u64 = 716715410; Count.u64 = 270; Min.u64 = 331; Max.u64 = 17719; l2cache0.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 3235; SumSQ.u64 = 3235; Count.u64 = 3235; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 1792; SumSQ.u64 = 1792; Count.u64 = 1792; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; @@ -798,10 +837,12 @@ l2cache0.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 3359; SumSQ.u64 = 3359; Count.u64 = 3359; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 5611; SumSQ.u64 = 5611; Count.u64 = 5611; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -813,6 +854,9 @@ l2cache0.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 3034; SumSQ.u64 = 3034; Count.u64 = 3034; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 3678; SumSQ.u64 = 3678; Count.u64 = 3678; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 4559; SumSQ.u64 = 4559; Count.u64 = 4559; Min.u64 = 1; Max.u64 = 1; + l2cache0.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache0.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache0.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 9942; SumSQ.u64 = 9942; Count.u64 = 9942; Min.u64 = 1; Max.u64 = 1; l2cache0.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -892,13 +936,16 @@ l1cache4.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1159; SumSQ.u64 = 1159; Count.u64 = 1159; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3469; SumSQ.u64 = 3469; Count.u64 = 3469; Min.u64 = 1; Max.u64 = 1; + l1cache4.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5730; SumSQ.u64 = 5730; Count.u64 = 5730; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 321; SumSQ.u64 = 321; Count.u64 = 321; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 3949; SumSQ.u64 = 3949; Count.u64 = 3949; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -925,6 +972,7 @@ l1cache4.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1295; SumSQ.u64 = 1295; Count.u64 = 1295; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 347; SumSQ.u64 = 347; Count.u64 = 347; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 33; SumSQ.u64 = 33; Count.u64 = 33; Min.u64 = 1; Max.u64 = 1; @@ -962,14 +1010,18 @@ l1cache4.msi.Write_recv : Accumulator : Sum.u64 = 3062; SumSQ.u64 = 3062; Count.u64 = 3062; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.GetSResp_recv : Accumulator : Sum.u64 = 2671; SumSQ.u64 = 2671; Count.u64 = 2671; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.GetXResp_recv : Accumulator : Sum.u64 = 2656; SumSQ.u64 = 2656; Count.u64 = 2656; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.Inv_recv : Accumulator : Sum.u64 = 3469; SumSQ.u64 = 3469; Count.u64 = 3469; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.FetchInv_recv : Accumulator : Sum.u64 = 1159; SumSQ.u64 = 1159; Count.u64 = 1159; Min.u64 = 1; Max.u64 = 1; l1cache4.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1497; SumSQ.u64 = 1497; Count.u64 = 1497; Min.u64 = 1; Max.u64 = 1; + l1cache4.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache4.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache4.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2469578; SumSQ.u64 = 14145206; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 27; @@ -1048,13 +1100,16 @@ l1cache5.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1511; SumSQ.u64 = 1511; Count.u64 = 1511; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3308; SumSQ.u64 = 3308; Count.u64 = 3308; Min.u64 = 1; Max.u64 = 1; + l1cache5.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5722; SumSQ.u64 = 5722; Count.u64 = 5722; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 287; SumSQ.u64 = 287; Count.u64 = 287; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 3991; SumSQ.u64 = 3991; Count.u64 = 3991; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1081,6 +1136,7 @@ l1cache5.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1479; SumSQ.u64 = 1479; Count.u64 = 1479; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 368; SumSQ.u64 = 368; Count.u64 = 368; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 18; SumSQ.u64 = 18; Count.u64 = 18; Min.u64 = 1; Max.u64 = 1; @@ -1118,14 +1174,18 @@ l1cache5.msi.Write_recv : Accumulator : Sum.u64 = 3079; SumSQ.u64 = 3079; Count.u64 = 3079; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.GetSResp_recv : Accumulator : Sum.u64 = 2544; SumSQ.u64 = 2544; Count.u64 = 2544; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.GetXResp_recv : Accumulator : Sum.u64 = 2647; SumSQ.u64 = 2647; Count.u64 = 2647; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.Inv_recv : Accumulator : Sum.u64 = 3308; SumSQ.u64 = 3308; Count.u64 = 3308; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.FetchInv_recv : Accumulator : Sum.u64 = 1136; SumSQ.u64 = 1136; Count.u64 = 1136; Min.u64 = 1; Max.u64 = 1; l1cache5.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1511; SumSQ.u64 = 1511; Count.u64 = 1511; Min.u64 = 1; Max.u64 = 1; + l1cache5.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache5.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache5.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2483333; SumSQ.u64 = 15776561; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 27; @@ -1204,13 +1264,16 @@ l1cache6.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1160; SumSQ.u64 = 1160; Count.u64 = 1160; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3255; SumSQ.u64 = 3255; Count.u64 = 3255; Min.u64 = 1; Max.u64 = 1; + l1cache6.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5699; SumSQ.u64 = 5699; Count.u64 = 5699; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 260; SumSQ.u64 = 260; Count.u64 = 260; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 4041; SumSQ.u64 = 4041; Count.u64 = 4041; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1237,6 +1300,7 @@ l1cache6.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1495; SumSQ.u64 = 1495; Count.u64 = 1495; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 408; SumSQ.u64 = 408; Count.u64 = 408; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; @@ -1274,14 +1338,18 @@ l1cache6.msi.Write_recv : Accumulator : Sum.u64 = 3069; SumSQ.u64 = 3069; Count.u64 = 3069; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.GetSResp_recv : Accumulator : Sum.u64 = 2511; SumSQ.u64 = 2511; Count.u64 = 2511; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.GetXResp_recv : Accumulator : Sum.u64 = 2603; SumSQ.u64 = 2603; Count.u64 = 2603; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.Inv_recv : Accumulator : Sum.u64 = 3255; SumSQ.u64 = 3255; Count.u64 = 3255; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.FetchInv_recv : Accumulator : Sum.u64 = 1160; SumSQ.u64 = 1160; Count.u64 = 1160; Min.u64 = 1; Max.u64 = 1; l1cache6.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1443; SumSQ.u64 = 1443; Count.u64 = 1443; Min.u64 = 1; Max.u64 = 1; + l1cache6.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache6.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache6.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2473862; SumSQ.u64 = 16167584; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 29; @@ -1360,13 +1428,16 @@ l1cache7.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 1457; SumSQ.u64 = 1457; Count.u64 = 1457; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.eventSent_AckInv : Accumulator : Sum.u64 = 3301; SumSQ.u64 = 3301; Count.u64 = 3301; Min.u64 = 1; Max.u64 = 1; + l1cache7.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 5656; SumSQ.u64 = 5656; Count.u64 = 5656; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 301; SumSQ.u64 = 301; Count.u64 = 301; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 4043; SumSQ.u64 = 4043; Count.u64 = 4043; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1393,6 +1464,7 @@ l1cache7.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1418; SumSQ.u64 = 1418; Count.u64 = 1418; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 384; SumSQ.u64 = 384; Count.u64 = 384; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 28; SumSQ.u64 = 28; Count.u64 = 28; Min.u64 = 1; Max.u64 = 1; @@ -1430,14 +1502,18 @@ l1cache7.msi.Write_recv : Accumulator : Sum.u64 = 3056; SumSQ.u64 = 3056; Count.u64 = 3056; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.GetSResp_recv : Accumulator : Sum.u64 = 2540; SumSQ.u64 = 2540; Count.u64 = 2540; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.GetXResp_recv : Accumulator : Sum.u64 = 2609; SumSQ.u64 = 2609; Count.u64 = 2609; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.Inv_recv : Accumulator : Sum.u64 = 3301; SumSQ.u64 = 3301; Count.u64 = 3301; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.FetchInv_recv : Accumulator : Sum.u64 = 1152; SumSQ.u64 = 1152; Count.u64 = 1152; Min.u64 = 1; Max.u64 = 1; l1cache7.msi.FetchInvX_recv : Accumulator : Sum.u64 = 1457; SumSQ.u64 = 1457; Count.u64 = 1457; Min.u64 = 1; Max.u64 = 1; + l1cache7.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache7.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache7.msi.MSHR_occupancy : Accumulator : Sum.u64 = 2435491; SumSQ.u64 = 14250563; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 27; @@ -1551,8 +1627,11 @@ l2cache1.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 3758; SumSQ.u64 = 3758; Count.u64 = 3758; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 2718; SumSQ.u64 = 2718; Count.u64 = 2718; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 3349; SumSQ.u64 = 3349; Count.u64 = 3349; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 2888; SumSQ.u64 = 2888; Count.u64 = 2888; Min.u64 = 1; Max.u64 = 1; @@ -1561,6 +1640,9 @@ l2cache1.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 10515; SumSQ.u64 = 10515; Count.u64 = 10515; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 3758; SumSQ.u64 = 3758; Count.u64 = 3758; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 4607; SumSQ.u64 = 4607; Count.u64 = 4607; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1585,6 +1667,7 @@ l2cache1.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 171594; SumSQ.u64 = 115861904; Count.u64 = 351; Min.u64 = 331; Max.u64 = 5827; l2cache1.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 5378; SumSQ.u64 = 5378; Count.u64 = 5378; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 3071; SumSQ.u64 = 3071; Count.u64 = 3071; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 317; SumSQ.u64 = 317; Count.u64 = 317; Min.u64 = 1; Max.u64 = 1; @@ -1620,10 +1703,12 @@ l2cache1.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 3042; SumSQ.u64 = 3042; Count.u64 = 3042; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 6067; SumSQ.u64 = 6067; Count.u64 = 6067; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1635,17 +1720,20 @@ l2cache1.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 3349; SumSQ.u64 = 3349; Count.u64 = 3349; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 4607; SumSQ.u64 = 4607; Count.u64 = 4607; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 5908; SumSQ.u64 = 5908; Count.u64 = 5908; Min.u64 = 1; Max.u64 = 1; + l2cache1.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache1.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 13333; SumSQ.u64 = 13333; Count.u64 = 13333; Min.u64 = 1; Max.u64 = 1; l2cache1.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache1.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 6942389; SumSQ.u64 = 47302751; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 44; l2cache1.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.packet_latency : Accumulator : Sum.u64 = 1534872; SumSQ.u64 = 142743096; Count.u64 = 16504; Min.u64 = 93; Max.u64 = 93; - l3cache.msi.inclus:memlink.send_bit_count : Accumulator : Sum.u64 = 1267456; SumSQ.u64 = 101392384; Count.u64 = 16504; Min.u64 = 64; Max.u64 = 96; - l3cache.msi.inclus:memlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus:memlink.idle_time : Accumulator : Sum.u64 = 146000; SumSQ.u64 = 14442500000; Count.u64 = 2; Min.u64 = 29500; Max.u64 = 116500; + l3cache.msi.inclus:lowlink.packet_latency : Accumulator : Sum.u64 = 1534872; SumSQ.u64 = 142743096; Count.u64 = 16504; Min.u64 = 93; Max.u64 = 93; + l3cache.msi.inclus:lowlink.send_bit_count : Accumulator : Sum.u64 = 1267456; SumSQ.u64 = 101392384; Count.u64 = 16504; Min.u64 = 64; Max.u64 = 96; + l3cache.msi.inclus:lowlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus:lowlink.idle_time : Accumulator : Sum.u64 = 146000; SumSQ.u64 = 14442500000; Count.u64 = 2; Min.u64 = 29500; Max.u64 = 116500; l3cache.msi.inclus.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 15; SumSQ.u64 = 15; Count.u64 = 15; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.evict_I : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1753,8 +1841,11 @@ l3cache.msi.inclus.eventSent_Write : Accumulator : Sum.u64 = 6600; SumSQ.u64 = 6600; Count.u64 = 6600; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_PutM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckPut : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1763,6 +1854,9 @@ l3cache.msi.inclus.eventSent_GetXResp : Accumulator : Sum.u64 = 11678; SumSQ.u64 = 11678; Count.u64 = 11678; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_WriteResp : Accumulator : Sum.u64 = 6600; SumSQ.u64 = 6600; Count.u64 = 6600; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_Fetch : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.eventSent_FetchInv : Accumulator : Sum.u64 = 5279; SumSQ.u64 = 5279; Count.u64 = 5279; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1787,6 +1881,7 @@ l3cache.msi.inclus.latency_GetSX_upgrade : Accumulator : Sum.u64 = 14175; SumSQ.u64 = 100642325; Count.u64 = 2; Min.u64 = 6790; Max.u64 = 7385; l3cache.msi.inclus.latency_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSHit_Arrival : Accumulator : Sum.u64 = 6381; SumSQ.u64 = 6381; Count.u64 = 6381; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXHit_Arrival : Accumulator : Sum.u64 = 10184; SumSQ.u64 = 10184; Count.u64 = 10184; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetSXHit_Arrival : Accumulator : Sum.u64 = 991; SumSQ.u64 = 991; Count.u64 = 991; Min.u64 = 1; Max.u64 = 1; @@ -1822,10 +1917,12 @@ l3cache.msi.inclus.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.GetSResp_recv : Accumulator : Sum.u64 = 11; SumSQ.u64 = 11; Count.u64 = 11; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.GetXResp_recv : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.PutE_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1837,15 +1934,18 @@ l3cache.msi.inclus.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.FetchResp_recv : Accumulator : Sum.u64 = 5279; SumSQ.u64 = 5279; Count.u64 = 5279; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.FetchXResp_recv : Accumulator : Sum.u64 = 6383; SumSQ.u64 = 6383; Count.u64 = 6383; Min.u64 = 1; Max.u64 = 1; + l3cache.msi.inclus.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l3cache.msi.inclus.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.AckInv_recv : Accumulator : Sum.u64 = 6392; SumSQ.u64 = 6392; Count.u64 = 6392; Min.u64 = 1; Max.u64 = 1; l3cache.msi.inclus.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l3cache.msi.inclus.MSHR_occupancy : Accumulator : Sum.u64 = 5908369; SumSQ.u64 = 27263623; Count.u64 = 2377533; Min.u64 = 0; Max.u64 = 28; l3cache.msi.inclus.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.packet_latency : Accumulator : Sum.u64 = 1683408; SumSQ.u64 = 171707616; Count.u64 = 16504; Min.u64 = 102; Max.u64 = 102; - directory.msi:cpulink.send_bit_count : Accumulator : Sum.u64 = 1591712; SumSQ.u64 = 157205504; Count.u64 = 16504; Min.u64 = 64; Max.u64 = 576; - directory.msi:cpulink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - directory.msi:cpulink.idle_time : Accumulator : Sum.u64 = 283500; SumSQ.u64 = 51814250000; Count.u64 = 2; Min.u64 = 65500; Max.u64 = 218000; + directory.msi:highlink.packet_latency : Accumulator : Sum.u64 = 1683408; SumSQ.u64 = 171707616; Count.u64 = 16504; Min.u64 = 102; Max.u64 = 102; + directory.msi:highlink.send_bit_count : Accumulator : Sum.u64 = 1591712; SumSQ.u64 = 157205504; Count.u64 = 16504; Min.u64 = 64; Max.u64 = 576; + directory.msi:highlink.output_port_stalls : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi:highlink.idle_time : Accumulator : Sum.u64 = 283500; SumSQ.u64 = 51814250000; Count.u64 = 2; Min.u64 = 65500; Max.u64 = 218000; directory.msi.default_stat : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.replacement_request_latency : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.get_request_latency : Accumulator : Sum.u64 = 2022; SumSQ.u64 = 250044; Count.u64 = 27; Min.u64 = 2; Max.u64 = 125; @@ -1868,8 +1968,10 @@ directory.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.GetS_uncache_recv : Accumulator : Sum.u64 = 9877; SumSQ.u64 = 9877; Count.u64 = 9877; Min.u64 = 1; Max.u64 = 1; directory.msi.Write_uncache_recv : Accumulator : Sum.u64 = 6600; SumSQ.u64 = 6600; Count.u64 = 6600; Min.u64 = 1; Max.u64 = 1; @@ -1888,6 +1990,7 @@ directory.msi.eventSent_FetchInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FetchInvX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_ForceInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 9888; SumSQ.u64 = 9888; Count.u64 = 9888; Min.u64 = 1; Max.u64 = 1; directory.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 16; SumSQ.u64 = 16; Count.u64 = 16; Min.u64 = 1; Max.u64 = 1; @@ -1898,6 +2001,8 @@ directory.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + directory.msi.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_read_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.eventSent_write_directory_entry : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; directory.msi.MSHR_occupancy : Accumulator : Sum.u64 = 1968; SumSQ.u64 = 3396; Count.u64 = 1188557; Min.u64 = 0; Max.u64 = 2; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out index e2285ccba9..a15408e327 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_1.out @@ -70,13 +70,16 @@ l1cache.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1414; SumSQ.u64 = 1414; Count.u64 = 1414; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 98; SumSQ.u64 = 98; Count.u64 = 98; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -103,6 +106,7 @@ l1cache.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 481; SumSQ.u64 = 481; Count.u64 = 481; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 337; SumSQ.u64 = 337; Count.u64 = 337; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; @@ -140,14 +144,18 @@ l1cache.msi.Write_recv : Accumulator : Sum.u64 = 988; SumSQ.u64 = 988; Count.u64 = 988; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetXResp_recv : Accumulator : Sum.u64 = 1187; SumSQ.u64 = 1187; Count.u64 = 1187; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.MSHR_occupancy : Accumulator : Sum.u64 = 5476656; SumSQ.u64 = 87070434; Count.u64 = 345130; Min.u64 = 0; Max.u64 = 16; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out index 51d952cd74..fed213f0b9 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_2.out @@ -70,13 +70,16 @@ l1cache.mesi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_GetSResp : Accumulator : Sum.u64 = 1436; SumSQ.u64 = 1436; Count.u64 = 1436; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_GetXResp : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_WriteResp : Accumulator : Sum.u64 = 962; SumSQ.u64 = 962; Count.u64 = 962; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -84,7 +87,7 @@ l1cache.mesi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.mesi.evict_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache.mesi.evict_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -103,6 +106,7 @@ l1cache.mesi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.GetSHit_Arrival : Accumulator : Sum.u64 = 1404; SumSQ.u64 = 1404; Count.u64 = 1404; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.GetXHit_Arrival : Accumulator : Sum.u64 = 941; SumSQ.u64 = 941; Count.u64 = 941; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.GetSXHit_Arrival : Accumulator : Sum.u64 = 100; SumSQ.u64 = 100; Count.u64 = 100; Min.u64 = 1; Max.u64 = 1; @@ -149,14 +153,18 @@ l1cache.mesi.Write_recv : Accumulator : Sum.u64 = 962; SumSQ.u64 = 962; Count.u64 = 962; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.GetXResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.mesi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.mesi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.mesi.MSHR_occupancy : Accumulator : Sum.u64 = 2620; SumSQ.u64 = 35346; Count.u64 = 1563; Min.u64 = 0; Max.u64 = 16; diff --git a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out index 68041f1d4a..d7af1123c3 100644 --- a/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out +++ b/src/sst/elements/memHierarchy/tests/refFiles/test_memHierarchy_sdl_3.out @@ -70,13 +70,16 @@ l1cache.msi.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_GetSResp : Accumulator : Sum.u64 = 1481; SumSQ.u64 = 1481; Count.u64 = 1481; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_GetXResp : Accumulator : Sum.u64 = 106; SumSQ.u64 = 106; Count.u64 = 106; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_WriteResp : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; l1cache.msi.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -84,7 +87,7 @@ l1cache.msi.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.msi.evict_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache.msi.evict_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.msi.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -103,6 +106,7 @@ l1cache.msi.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSHit_Arrival : Accumulator : Sum.u64 = 1445; SumSQ.u64 = 1445; Count.u64 = 1445; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetXHit_Arrival : Accumulator : Sum.u64 = 896; SumSQ.u64 = 896; Count.u64 = 896; Min.u64 = 1; Max.u64 = 1; l1cache.msi.GetSXHit_Arrival : Accumulator : Sum.u64 = 102; SumSQ.u64 = 102; Count.u64 = 102; Min.u64 = 1; Max.u64 = 1; @@ -140,14 +144,18 @@ l1cache.msi.Write_recv : Accumulator : Sum.u64 = 913; SumSQ.u64 = 913; Count.u64 = 913; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.GetXResp_recv : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.msi.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.msi.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.msi.MSHR_occupancy : Accumulator : Sum.u64 = 4275; SumSQ.u64 = 50821; Count.u64 = 5153; Min.u64 = 0; Max.u64 = 16; diff --git a/src/sst/elements/memHierarchy/tests/sdl-1.py b/src/sst/elements/memHierarchy/tests/sdl-1.py index 7179588a70..3ef49577a7 100644 --- a/src/sst/elements/memHierarchy/tests/sdl-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl-1.py @@ -25,6 +25,7 @@ "llsc_freq" : 4, # 4% LLSC }) iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface") +#iface.addParams({"debug" : 1, "debug_level" : 10}) l1cache = sst.Component("l1cache.msi", "memHierarchy.Cache") l1cache.addParams({ @@ -65,6 +66,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) +link_cache_mem_link = sst.Link("link_cache_mem_link") +link_cache_mem_link.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl-2.py b/src/sst/elements/memHierarchy/tests/sdl-2.py index ad5569dc55..0ade5bf4bf 100644 --- a/src/sst/elements/memHierarchy/tests/sdl-2.py +++ b/src/sst/elements/memHierarchy/tests/sdl-2.py @@ -36,10 +36,6 @@ "cache_size" : "2KiB" }) -# Explicitly set the link subcomponents instead of having cache figure them out based on connected port names -l1toC = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1toM = l1cache.setSubComponent("memlink", "memHierarchy.MemLink") - # Memory controller memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams({ @@ -50,7 +46,6 @@ "debug_level" : DEBUG_LEVEL, "addr_range_end" : 512*1024*1024-1, }) -Mtol1 = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") # Memory model memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") @@ -68,7 +63,7 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "100ps"), (l1toC, "port", "100ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l1toM, "port", "50ps"), (Mtol1, "port", "50ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "100ps"), (l1cache, "highlink", "100ps") ) +link_mem_cache_link = sst.Link("link_mem_cache_link") +link_mem_cache_link.connect( (memctrl, "highlink", "50ps"), (l1cache, "lowlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl-3.py b/src/sst/elements/memHierarchy/tests/sdl-3.py index 59eb35d7d0..e085721e51 100644 --- a/src/sst/elements/memHierarchy/tests/sdl-3.py +++ b/src/sst/elements/memHierarchy/tests/sdl-3.py @@ -37,10 +37,6 @@ # Replacement policy - can declare here or as a parameter (only if part of memHierarchy's core set of policies and using default parameters) l1cache.setSubComponent("replacement", "memHierarchy.replacement.mru") -# Links to core & mem -l1toC = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1toM = l1cache.setSubComponent("memlink", "memHierarchy.MemLink") - memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams({ "debug" : "0", @@ -48,7 +44,6 @@ "request_width" : "64", "addr_range_end" : 512*1024*1024-1, }) -mtol1 = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") memory = memctrl.setSubComponent("backend", "memHierarchy.timingDRAM") memory.addParams({ @@ -86,6 +81,6 @@ # Define the simulation links link_cpu_cache = sst.Link("link_cpu_cache") -link_cpu_cache.connect( (iface, "port", "1000ps"), (l1toC, "port", "1000ps") ) -link_mem_bus = sst.Link("link_mem_bus") -link_mem_bus.connect( (l1toM, "port", "50ps"), (mtol1, "port", "50ps") ) +link_cpu_cache.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) +link_mem_cache = sst.Link("link_mem_cache") +link_mem_cache.connect( (memctrl, "highlink", "50ps"), (l1cache, "lowlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl2-1.py b/src/sst/elements/memHierarchy/tests/sdl2-1.py index 9a59c065c4..3b2b58faf2 100644 --- a/src/sst/elements/memHierarchy/tests/sdl2-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl2-1.py @@ -74,8 +74,8 @@ # Define the simulation links link_cpu_l1cache = sst.Link("link_cpu_l1cache_link") -link_cpu_l1cache.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") ) +link_cpu_l1cache.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) link_l1cache_l2cache = sst.Link("link_l1cache_l2cache_link") -link_l1cache_l2cache.connect( (l1cache, "low_network_0", "10000ps"), (l2cache, "high_network_0", "1000ps") ) -link_mem_bus = sst.Link("link_mem_bus_link") -link_mem_bus.connect( (l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_l1cache_l2cache.connect( (l1cache, "lowlink", "10000ps"), (l2cache, "highlink", "1000ps") ) +link_mem_cache = sst.Link("link_mem_cache_link") +link_mem_cache.connect( (l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl3-1.py b/src/sst/elements/memHierarchy/tests/sdl3-1.py index c0f2a7ce03..6d477e2631 100644 --- a/src/sst/elements/memHierarchy/tests/sdl3-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl3-1.py @@ -88,8 +88,8 @@ "debug" : DEBUG_MEM, "debug_level" : 10, "clock" : "1GHz", - #"cpulink.debug" : 1, - #"cpulink.debug_level" : 10, + #"highlink.debug" : 1, + #"highlink.debug_level" : 10, "addr_range_end" : 512*1024*1024-1, }) @@ -108,14 +108,14 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link") -link_c0_l1_l2_link.connect( (c0_l1cache, "low_network_0", "1000ps"), (bus, "high_network_0", "10000ps") ) +link_c0_l1_l2_link.connect( (c0_l1cache, "lowlink", "1000ps"), (bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link") -link_c1_l1_l2_link.connect( (c1_l1cache, "low_network_0", "1000ps"), (bus, "high_network_1", "10000ps") ) +link_c1_l1_l2_link.connect( (c1_l1cache, "lowlink", "1000ps"), (bus, "highlink1", "10000ps") ) link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (bus, "low_network_0", "10000ps"), (l2cache, "high_network_0", "1000ps") ) +link_bus_l2cache.connect( (bus, "lowlink0", "10000ps"), (l2cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl3-2.py b/src/sst/elements/memHierarchy/tests/sdl3-2.py index 920b599a97..bb46176ca2 100644 --- a/src/sst/elements/memHierarchy/tests/sdl3-2.py +++ b/src/sst/elements/memHierarchy/tests/sdl3-2.py @@ -39,8 +39,6 @@ "debug" : DEBUG_L1 | DEBUG_CORE0, "cache_size" : "1 KB" }) -l1toC0 = c0_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1tol2_0 = c0_l1cache.setSubComponent("memlink", "memHierarchy.MemLink") # Core 1 + L1 cpu1 = sst.Component("core1", "memHierarchy.standardCPU") @@ -71,8 +69,6 @@ "debug" : DEBUG_L1 | DEBUG_CORE1, "cache_size" : "1 KB" }) -l1toC1 = c1_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1tol2_1 = c1_l1cache.setSubComponent("memlink", "memHierarchy.MemLink") # Bus between L1s and L2 bus = sst.Component("bus", "memHierarchy.Bus") @@ -93,8 +89,6 @@ "debug" : DEBUG_L2, "cache_size" : "2 KB" }) -l2tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l2tol3 = l2cache.setSubComponent("memlink", "memHierarchy.MemLink") # L3 l3cache = sst.Component("l3cache.msi.inclus", "memHierarchy.Cache") @@ -107,8 +101,6 @@ "cache_line_size" : 64, "cache_size" : "4KiB" }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3tol4 = l3cache.setSubComponent("memlink", "memHierarchy.MemLink") l4cache = sst.Component("l4cache.msi.inclus", "memHierarchy.Cache") l4cache.addParams({ @@ -120,8 +112,6 @@ "cache_line_size" : 64, "cache_size" : "8KiB" }) -l4tol3 = l4cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l4toM = l4cache.setSubComponent("memlink", "memHierarchy.MemLink") memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams({ @@ -130,7 +120,6 @@ "clock" : "1GHz", "addr_range_end" : 512*1024*1024-1, }) -mtol4 = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") memory.addParams({ @@ -149,24 +138,24 @@ # Define the simulation links # Core 0 to L1 link_cpu0_l1cache = sst.Link("link_cpu0_l1cache") -link_cpu0_l1cache.connect( (iface0, "port", "1000ps"), (l1toC0, "port", "1000ps") ) +link_cpu0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) # Core 1 to L1 link_cpu1_l1cache = sst.Link("link_cpu1_l1cache") -link_cpu1_l1cache.connect( (iface1, "port", "1000ps"), (l1toC1, "port", "1000ps") ) +link_cpu1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) # L1s to bus link_c0_l1_l2 = sst.Link("link_c0_l1_l2") -link_c0_l1_l2.connect( (l1tol2_0, "port", "1000ps"), (bus, "high_network_0", "10000ps") ) +link_c0_l1_l2.connect( (c0_l1cache, "lowlink", "1000ps"), (bus, "highlink0", "10000ps") ) link_c1_l1_l2 = sst.Link("link_c1_l1_l2_link") -link_c1_l1_l2.connect( (l1tol2_1, "port", "1000ps"), (bus, "high_network_1", "10000ps") ) +link_c1_l1_l2.connect( (c1_l1cache, "lowlink", "1000ps"), (bus, "highlink1", "10000ps") ) # Bus to L2 link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (bus, "low_network_0", "10000ps"), (l2tol1, "port", "1000ps") ) +link_bus_l2cache.connect( (bus, "lowlink0", "10000ps"), (l2cache, "highlink", "1000ps") ) # L2 to L3 link_l2_l3 = sst.Link("link_l2_l3") -link_l2_l3.connect( (l2tol3, "port", "100ps"), (l3tol2, "port", "100ps") ) +link_l2_l3.connect( (l2cache, "lowlink", "100ps"), (l3cache, "highlink", "100ps") ) # L3 to L4 link_l3_l4 = sst.Link("link_l3_l4") -link_l3_l4.connect( (l3tol4, "port", "400ps"), (l4tol3, "port", "400ps") ) +link_l3_l4.connect( (l3cache, "lowlink", "400ps"), (l4cache, "highlink", "400ps") ) # L4 to mem link_l4_mem = sst.Link("link_l4_mem") -link_l4_mem.connect( (l4toM, "port", "10000ps"), (mtol4, "port", "10000ps") ) +link_l4_mem.connect( (l4cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl3-3.py b/src/sst/elements/memHierarchy/tests/sdl3-3.py index b9fb6df079..708c138de8 100644 --- a/src/sst/elements/memHierarchy/tests/sdl3-3.py +++ b/src/sst/elements/memHierarchy/tests/sdl3-3.py @@ -101,14 +101,14 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link") -link_c0_l1_l2_link.connect( (c0_l1cache, "low_network_0", "1000ps"), (bus, "high_network_0", "10000ps") ) +link_c0_l1_l2_link.connect( (c0_l1cache, "lowlink", "1000ps"), (bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link") -link_c1_l1_l2_link.connect( (c1_l1cache, "low_network_0", "1000ps"), (bus, "high_network_1", "10000ps") ) +link_c1_l1_l2_link.connect( (c1_l1cache, "lowlink", "1000ps"), (bus, "highlink1", "10000ps") ) link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (bus, "low_network_0", "10000ps"), (l2cache, "high_network_0", "1000ps") ) +link_bus_l2cache.connect( (bus, "lowlink0", "10000ps"), (l2cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl4-1.py b/src/sst/elements/memHierarchy/tests/sdl4-1.py index 351d5e979f..349d2b190c 100644 --- a/src/sst/elements/memHierarchy/tests/sdl4-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl4-1.py @@ -101,14 +101,14 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (comp_c0_l1cache, "highlink", "1000ps") ) link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link") -link_c0_l1_l2_link.connect( (comp_c0_l1cache, "low_network_0", "1000ps"), (comp_bus, "high_network_0", "10000ps") ) +link_c0_l1_l2_link.connect( (comp_c0_l1cache, "lowlink", "1000ps"), (comp_bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (comp_c1_l1cache, "highlink", "1000ps") ) link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link") -link_c1_l1_l2_link.connect( (comp_c1_l1cache, "low_network_0", "1000ps"), (comp_bus, "high_network_1", "10000ps") ) +link_c1_l1_l2_link.connect( (comp_c1_l1cache, "lowlink", "1000ps"), (comp_bus, "highlink1", "10000ps") ) link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (comp_bus, "low_network_0", "10000ps"), (comp_l2cache, "high_network_0", "1000ps") ) +link_bus_l2cache.connect( (comp_bus, "lowlink0", "10000ps"), (comp_l2cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (comp_l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl4-2.py b/src/sst/elements/memHierarchy/tests/sdl4-2.py index 10de01832b..39bd2926ed 100644 --- a/src/sst/elements/memHierarchy/tests/sdl4-2.py +++ b/src/sst/elements/memHierarchy/tests/sdl4-2.py @@ -106,14 +106,14 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link") -link_c0_l1_l2_link.connect( (c0_l1cache, "low_network_0", "1000ps"), (bus, "high_network_0", "10000ps") ) +link_c0_l1_l2_link.connect( (c0_l1cache, "lowlink", "1000ps"), (bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link") -link_c1_l1_l2_link.connect( (c1_l1cache, "low_network_0", "1000ps"), (bus, "high_network_1", "10000ps") ) +link_c1_l1_l2_link.connect( (c1_l1cache, "lowlink", "1000ps"), (bus, "highlink1", "10000ps") ) link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (bus, "low_network_0", "10000ps"), (l2cache, "high_network_0", "1000ps") ) +link_bus_l2cache.connect( (bus, "lowlink0", "10000ps"), (l2cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl5-1.py b/src/sst/elements/memHierarchy/tests/sdl5-1.py index dc17e210a7..09ccf78a68 100644 --- a/src/sst/elements/memHierarchy/tests/sdl5-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl5-1.py @@ -201,30 +201,30 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0_l1cache_l2cache_link = sst.Link("link_c0_l1cache_l2cache_link") -link_c0_l1cache_l2cache_link.connect( (c0_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0_l1cache_l2cache_link.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1_l1cache_l2cache_link = sst.Link("link_c1_l1cache_l2cache_link") -link_c1_l1cache_l2cache_link.connect( (c1_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1_l1cache_l2cache_link.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_n0_bus_l2cache = sst.Link("link_n0_bus_l2cache") -link_n0_bus_l2cache.connect( (n0_bus, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "1000ps") ) +link_n0_bus_l2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "1000ps") ) link_n0_l2cache_l3cache = sst.Link("link_n0_l2cache_l3cache") -link_n0_l2cache_l3cache.connect( (n0_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0_l2cache_l3cache.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_cpu2_l1cache_link = sst.Link("link_cpu2_l1cache_link") -link_cpu2_l1cache_link.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_cpu2_l1cache_link.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2_l1cache_l2cache_link = sst.Link("link_c2_l1cache_l2cache_link") -link_c2_l1cache_l2cache_link.connect( (c2_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2_l1cache_l2cache_link.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_cpu3_l1cache_link = sst.Link("link_cpu3_l1cache_link") -link_cpu3_l1cache_link.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_cpu3_l1cache_link.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3_l1cache_l2cache_link = sst.Link("link_c3_l1cache_l2cache_link") -link_c3_l1cache_l2cache_link.connect( (c3_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3_l1cache_l2cache_link.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) link_n1_bus_l2cache = sst.Link("link_n1_bus_l2cache") -link_n1_bus_l2cache.connect( (n1_bus, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "1000ps") ) +link_n1_bus_l2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "1000ps") ) link_n1_l2cache_l3cache = sst.Link("link_n1_l2cache_l3cache") -link_n1_l2cache_l3cache.connect( (n1_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1_l2cache_l3cache.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3cache, "high_network_0", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l3cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (l3cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl8-1.py b/src/sst/elements/memHierarchy/tests/sdl8-1.py index d0aab50fae..9831a705b5 100644 --- a/src/sst/elements/memHierarchy/tests/sdl8-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl8-1.py @@ -38,8 +38,6 @@ "debug_level" : 10, "verbose" : 2, }) -l1ToC = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1Tol2 = l1cache.setSubComponent("memlink", "memHierarchy.MemLink") l2cache = sst.Component("l2cache.msi.inclus", "memHierarchy.Cache") l2cache.addParams({ @@ -54,8 +52,6 @@ "debug_level" : 10, "verbose" : 2, }) -l2Tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l2Tol3 = l2cache.setSubComponent("memlink", "memHierarchy.MemLink") l3cache = sst.Component("l3cache.msi.inclus", "memHierarchy.Cache") l3cache.addParams({ @@ -70,8 +66,9 @@ "debug_level" : 10, "verbose" : 2, }) -l3Tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") + +# Must use subcomponent slot instead of lowlink port since l3 connects to a network +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ #"debug" : 1, #"debug_level" : 10, @@ -103,7 +100,7 @@ "addr_range_start" : "0x0", "verbose" : 2, }) -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "network_bw" : "25GB/s", "group" : 2, @@ -111,7 +108,6 @@ #"debug" : 1, #"debug_level" : 10, }) -dirMemLink = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") # Not on a network, just a direct link memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams({ @@ -121,7 +117,7 @@ "verbose" : 2, "addr_range_end" : 512*1024*1024-1, }) -memToDir = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") + memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") memory.addParams({ "access_time" : "100 ns", @@ -136,13 +132,13 @@ # Define the simulation links link_cpu_l1cache = sst.Link("link_cpu_l1cache") -link_cpu_l1cache.connect( (iface, "port", "1000ps"), (l1ToC, "port", "1000ps") ) +link_cpu_l1cache.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) link_l1cache_l2cache = sst.Link("link_l1cache_l2cache") -link_l1cache_l2cache.connect( (l1Tol2, "port", "10000ps"), (l2Tol1, "port", "10000ps") ) +link_l1cache_l2cache.connect( (l1cache, "lowlink", "10000ps"), (l2cache, "highlink", "10000ps") ) link_l2cache_l3cache = sst.Link("link_l2cache_l3cache") -link_l2cache_l3cache.connect( (l2Tol3, "port", "10000ps"), (l3Tol2, "port", "10000ps") ) +link_l2cache_l3cache.connect( (l2cache, "lowlink", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net = sst.Link("link_cache_net") link_cache_net.connect( (l3NIC, "port", "10000ps"), (chiprtr, "port1", "2000ps") ) @@ -151,5 +147,5 @@ link_dir_net.connect( (chiprtr, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirMemLink, "port", "10000ps"), (memToDir, "port", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl8-3.py b/src/sst/elements/memHierarchy/tests/sdl8-3.py index be39201d8a..9c12121770 100644 --- a/src/sst/elements/memHierarchy/tests/sdl8-3.py +++ b/src/sst/elements/memHierarchy/tests/sdl8-3.py @@ -44,8 +44,6 @@ "debug" : DEBUG_L1 | DEBUG_CORE0 | DEBUG_NODE0, "debug_level" : 10, }) -l1ToC_0 = c0_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1Tol2_0 = c0_l1cache.setSubComponent("memlink", "memHierarchy.MemLink") # Core 1 cpu1 = sst.Component("core1", "memHierarchy.standardCPU") @@ -78,8 +76,6 @@ "debug" : DEBUG_L1 | DEBUG_CORE1 | DEBUG_NODE0, "debug_level" : 10, }) -l1ToC_1 = c1_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1Tol2_1 = c1_l1cache.setSubComponent("memlink", "memHierarchy.MemLink") # L1/L2 bus 0 n0_bus = sst.Component("bus0", "memHierarchy.Bus") @@ -100,8 +96,6 @@ "debug" : DEBUG_L2 | DEBUG_NODE0, "debug_level" : 10, }) -l2Tol1_0 = n0_l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l2Tol3_0 = n0_l2cache.setSubComponent("memlink", "memHierarchy.MemLink") # Core 2 cpu2 = sst.Component("core2", "memHierarchy.standardCPU") @@ -134,8 +128,6 @@ "debug" : DEBUG_L1 | DEBUG_CORE2 | DEBUG_NODE1, "debug_level" : 10, }) -l1ToC_2 = c2_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1Tol2_2 = c2_l1cache.setSubComponent("memlink", "memHierarchy.MemLink") # Core 3 cpu3 = sst.Component("core3", "memHierarchy.standardCPU") @@ -168,8 +160,6 @@ "debug" : DEBUG_L1 | DEBUG_CORE3 | DEBUG_NODE1, "debug_level" : 10, }) -l1ToC_3 = c3_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1Tol2_3 = c3_l1cache.setSubComponent("memlink", "memHierarchy.MemLink") # L1/L2 bus 1 n1_bus = sst.Component("bus1", "memHierarchy.Bus") @@ -190,8 +180,6 @@ "debug" : DEBUG_L2 | DEBUG_NODE1, "debug_level" : 10, }) -l2Tol1_1 = n1_l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l2Tol3_1 = n1_l2cache.setSubComponent("memlink", "memHierarchy.MemLink") # L2/L3 bus n2_bus = sst.Component("n2.bus", "memHierarchy.Bus") @@ -212,8 +200,7 @@ "debug" : DEBUG_L3, "debug_level" : 10, }) -l3Tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -243,12 +230,11 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0", }) -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "network_bw" : "25GB/s", "group" : 2, }) -dirLink = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") # Memory memctrl = sst.Component("memory", "memHierarchy.MemController") @@ -264,7 +250,6 @@ "access_time" : "100 ns", "mem_size" : "512MiB", }) -memLink = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") # Enable statistics sst.setStatisticLoadLevel(7) @@ -278,46 +263,46 @@ # Cores to L1s link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (l1ToC_0, "port", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (l1ToC_1, "port", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (l1ToC_2, "port", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (l1ToC_3, "port", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) # L1s to buses link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (l1Tol2_0, "port", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (l1Tol2_1, "port", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (l1Tol2_2, "port", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (l1Tol2_3, "port", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) # L1 buses to L2s link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "10000ps"), (l2Tol1_0, "port", "10000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "10000ps"), (l2Tol1_1, "port", "10000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "10000ps") ) # L2s to L3 via bus link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (l2Tol3_0, "port", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (l2Tol3_1, "port", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3Tol2, "port", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) # Network connections - l3 & directory link_cache_net = sst.Link("link_cache_net_0") @@ -327,4 +312,4 @@ # Directory to memory link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirLink, "port", "10000ps"), (memLink, "port", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl8-4.py b/src/sst/elements/memHierarchy/tests/sdl8-4.py index 551492ac7f..cd6b5f2ddc 100644 --- a/src/sst/elements/memHierarchy/tests/sdl8-4.py +++ b/src/sst/elements/memHierarchy/tests/sdl8-4.py @@ -175,8 +175,7 @@ "debug" : DEBUG_L3, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "network_bw" : "25GB/s", "group" : 1, @@ -203,8 +202,7 @@ "addr_range_start" : "0x0", "addr_range_end" : "0x1F000000", }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "network_bw" : "25GB/s", "group" : 2, @@ -216,7 +214,6 @@ "request_width" : "64", "addr_range_end" : 512*1024*1024-1, }) -memtoD = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") memory.addParams({ "access_time" : "100 ns", @@ -231,31 +228,31 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "10000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "10000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "10000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3tol2, "port", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) # Network connections link_cache_net = sst.Link("link_cache_net_0") link_cache_net.connect( (l3NIC, "port", "10000ps"), (chiprtr, "port1", "2000ps") ) @@ -263,4 +260,4 @@ link_dir_net.connect( (chiprtr, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) # Directory to memory link_dir_mem = sst.Link("link_dir_mem_link") -link_dir_mem.connect( (dirtoM, "port", "10000ps"), (memtoD, "port", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl9-1.py b/src/sst/elements/memHierarchy/tests/sdl9-1.py index 954eccc471..77aa4e1411 100644 --- a/src/sst/elements/memHierarchy/tests/sdl9-1.py +++ b/src/sst/elements/memHierarchy/tests/sdl9-1.py @@ -82,10 +82,10 @@ # Define the simulation links link_cpu_l1cache = sst.Link("link_cpu_l1cache") -link_cpu_l1cache.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") ) +link_cpu_l1cache.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) link_l1cache_l2cache = sst.Link("link_l1cache_l2cache") -link_l1cache_l2cache.connect( (l1cache, "low_network_0", "10000ps"), (l2cache, "high_network_0", "10000ps") ) +link_l1cache_l2cache.connect( (l1cache, "lowlink", "10000ps"), (l2cache, "highlink", "10000ps") ) link_l2cache_l3cache = sst.Link("link_l2cache_l3cache") -link_l2cache_l3cache.connect( (l2cache, "low_network_0", "10000ps"), (l3cache, "high_network_0", "10000ps") ) +link_l2cache_l3cache.connect( (l2cache, "lowlink", "10000ps"), (l3cache, "highlink", "10000ps") ) link_mem_bus = sst.Link("link_mem_bus") -link_mem_bus.connect( (l3cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus.connect( (l3cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl9-2.py b/src/sst/elements/memHierarchy/tests/sdl9-2.py index f6e0d18bbb..12bf40dcef 100644 --- a/src/sst/elements/memHierarchy/tests/sdl9-2.py +++ b/src/sst/elements/memHierarchy/tests/sdl9-2.py @@ -298,8 +298,7 @@ "debug" : DEBUG_L3, "debug_level" : "3", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "network_bw" : "25GB/s", "group" : 1, @@ -325,8 +324,7 @@ "addr_range_start" : "0x0", "addr_range_end" : "0x1F000000", }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -354,50 +352,50 @@ # Define the simulation links link_c0l1cache_link = sst.Link("link_c0l1cache_link") -link_c0l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_c0l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0l1cache_bus = sst.Link("link_c0l1cache_bus") -link_c0l1cache_bus.connect( (c0_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_0", "10000ps") ) +link_c0l1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (comp_n0_bus, "highlink0", "10000ps") ) link_c1l1cache_link = sst.Link("link_c1l1cache_link") -link_c1l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_c1l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1l1cache_bus = sst.Link("link_c1l1cache_bus") -link_c1l1cache_bus.connect( (c1_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_1", "10000ps") ) +link_c1l1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (comp_n0_bus, "highlink1", "10000ps") ) link_c2l1cache_link = sst.Link("link_c2l1cache_link") -link_c2l1cache_link.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_c2l1cache_link.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2l1cache_bus = sst.Link("link_c2l1cache_bus") -link_c2l1cache_bus.connect( (c2_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_2", "10000ps") ) +link_c2l1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (comp_n0_bus, "highlink2", "10000ps") ) link_c3l1cache_link = sst.Link("link_c3l1cache_link") -link_c3l1cache_link.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_c3l1cache_link.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3l1cache_bus = sst.Link("link_c3l1cache_bus") -link_c3l1cache_bus.connect( (c3_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_3", "10000ps") ) +link_c3l1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (comp_n0_bus, "highlink3", "10000ps") ) link_n0bus_l2cache = sst.Link("link_n0bus_l2cache") -link_n0bus_l2cache.connect( (comp_n0_bus, "low_network_0", "10000ps"), (comp_n0_l2cache, "high_network_0", "10000ps") ) +link_n0bus_l2cache.connect( (comp_n0_bus, "lowlink0", "10000ps"), (comp_n0_l2cache, "highlink", "10000ps") ) link_n0l2cache_bus = sst.Link("link_n0l2cache_bus") -link_n0l2cache_bus.connect( (comp_n0_l2cache, "low_network_0", "10000ps"), (comp_n2_bus, "high_network_0", "10000ps") ) +link_n0l2cache_bus.connect( (comp_n0_l2cache, "lowlink", "10000ps"), (comp_n2_bus, "highlink0", "10000ps") ) link_c4l1cache_link = sst.Link("link_c4l1cache_link") -link_c4l1cache_link.connect( (iface4, "port", "1000ps"), (c4_l1cache, "high_network_0", "1000ps") ) +link_c4l1cache_link.connect( (iface4, "lowlink", "1000ps"), (c4_l1cache, "highlink", "1000ps") ) link_c4l1cache_bus = sst.Link("link_c4l1cache_bus") -link_c4l1cache_bus.connect( (c4_l1cache, "low_network_0", "10000ps"), (comp_n1_bus, "high_network_0", "10000ps") ) +link_c4l1cache_bus.connect( (c4_l1cache, "lowlink", "10000ps"), (comp_n1_bus, "highlink0", "10000ps") ) link_c5l1cache_link = sst.Link("link_c5l1cache_link") -link_c5l1cache_link.connect( (iface5, "port", "1000ps"), (c5_l1cache, "high_network_0", "1000ps") ) +link_c5l1cache_link.connect( (iface5, "lowlink", "1000ps"), (c5_l1cache, "highlink", "1000ps") ) link_c5l1cache_bus = sst.Link("link_c5l1cache_bus") -link_c5l1cache_bus.connect( (c5_l1cache, "low_network_0", "10000ps"), (comp_n1_bus, "high_network_1", "10000ps") ) +link_c5l1cache_bus.connect( (c5_l1cache, "lowlink", "10000ps"), (comp_n1_bus, "highlink1", "10000ps") ) link_c6l1cache_link = sst.Link("link_c6l1cache_link") -link_c6l1cache_link.connect( (iface6, "port", "1000ps"), (c6_l1cache, "high_network_0", "1000ps") ) +link_c6l1cache_link.connect( (iface6, "lowlink", "1000ps"), (c6_l1cache, "highlink", "1000ps") ) link_c6l1cache_bus = sst.Link("link_c6l1cache_bus") -link_c6l1cache_bus.connect( (c6_l1cache, "low_network_0", "10000ps"), (comp_n1_bus, "high_network_2", "10000ps") ) +link_c6l1cache_bus.connect( (c6_l1cache, "lowlink", "10000ps"), (comp_n1_bus, "highlink2", "10000ps") ) link_c7l1cache_link = sst.Link("link_c7l1cache_link") -link_c7l1cache_link.connect( (iface7, "port", "1000ps"), (c7_l1cache, "high_network_0", "1000ps") ) +link_c7l1cache_link.connect( (iface7, "lowlink", "1000ps"), (c7_l1cache, "highlink", "1000ps") ) link_c7l1cache_bus = sst.Link("link_c7l1cache_bus") -link_c7l1cache_bus.connect( (c7_l1cache, "low_network_0", "10000ps"), (comp_n1_bus, "high_network_3", "10000ps") ) +link_c7l1cache_bus.connect( (c7_l1cache, "lowlink", "10000ps"), (comp_n1_bus, "highlink3", "10000ps") ) link_n1bus_l2cache = sst.Link("link_n1bus_l2cache") -link_n1bus_l2cache.connect( (comp_n1_bus, "low_network_0", "10000ps"), (comp_n1_l2cache, "high_network_0", "10000ps") ) +link_n1bus_l2cache.connect( (comp_n1_bus, "lowlink0", "10000ps"), (comp_n1_l2cache, "highlink", "10000ps") ) link_n1l2cache_bus = sst.Link("link_n1l2cache_bus") -link_n1l2cache_bus.connect( (comp_n1_l2cache, "low_network_0", "10000ps"), (comp_n2_bus, "high_network_1", "10000ps") ) +link_n1l2cache_bus.connect( (comp_n1_l2cache, "lowlink", "10000ps"), (comp_n2_bus, "highlink1", "10000ps") ) link_n2bus_l3cache = sst.Link("link_n2bus_l3cache") -link_n2bus_l3cache.connect( (comp_n2_bus, "low_network_0", "10000ps"), (l3tol2, "port", "10000ps") ) +link_n2bus_l3cache.connect( (comp_n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "10000ps"), (chiprtr, "port1", "2000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (chiprtr, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendChaining.py b/src/sst/elements/memHierarchy/tests/testBackendChaining.py index e0e9ce00ad..03c7811b11 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendChaining.py +++ b/src/sst/elements/memHierarchy/tests/testBackendChaining.py @@ -167,8 +167,7 @@ "debug_level" : DEBUG_LEVEL }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "network_bw" : "40GB/s", "input_buffer_size" : "2KiB", @@ -198,8 +197,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0", }) -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "network_bw" : "40GB/s", "input_buffer_size" : "2KiB", @@ -250,34 +248,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "100ps"), (c0_l1cache, "high_network_0", "100ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "100ps"), (c0_l1cache, "highlink", "100ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "200ps"), (n0_bus, "high_network_0", "200ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "200ps"), (n0_bus, "highlink0", "200ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "100ps"), (c1_l1cache, "high_network_0", "100ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "100ps"), (c1_l1cache, "highlink", "100ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "100ps"), (n0_bus, "high_network_1", "200ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "100ps"), (n0_bus, "highlink1", "200ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "200ps"), (n0_l2cache, "high_network_0", "200ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "200ps"), (n0_l2cache, "highlink", "200ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "200ps"), (n2_bus, "high_network_0", "200ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "200ps"), (n2_bus, "highlink0", "200ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "100ps"), (c2_l1cache, "high_network_0", "100ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "100ps"), (c2_l1cache, "highlink", "100ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "200ps"), (n1_bus, "high_network_0", "200ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "200ps"), (n1_bus, "highlink0", "200ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "100ps"), (c3_l1cache, "high_network_0", "100ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "100ps"), (c3_l1cache, "highlink", "100ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "200ps"), (n1_bus, "high_network_1", "200ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "200ps"), (n1_bus, "highlink1", "200ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "200ps"), (n1_l2cache, "high_network_0", "200ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "200ps"), (n1_l2cache, "highlink", "200ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "200ps"), (n2_bus, "high_network_1", "200ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "200ps"), (n2_bus, "highlink1", "200ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "200ps"), (l3tol2, "port", "200ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "200ps"), (l3cache, "highlink", "200ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "200ps"), (network, "port1", "150ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "150ps"), (dirNIC, "port", "150ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "200ps"), (memctrl, "direct_link", "200ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "200ps"), (memctrl, "highlink", "200ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendCramSim.py b/src/sst/elements/memHierarchy/tests/testBackendCramSim.py index bb5c733b1c..c0e9b9fde3 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendCramSim.py +++ b/src/sst/elements/memHierarchy/tests/testBackendCramSim.py @@ -302,37 +302,37 @@ def setup_config_params(): # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (comp_c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (comp_c0_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (comp_c0_l1cache, "lowlink", "10000ps"), (comp_n0_bus, "highlink0", "10000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (comp_c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (comp_c1_l1cache, "low_network_0", "10000ps"), (comp_n0_bus, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (comp_c1_l1cache, "lowlink", "10000ps"), (comp_n0_bus, "highlink1", "10000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (comp_n0_bus, "low_network_0", "10000ps"), (comp_n0_l2cache, "high_network_0", "10000ps") ) +link_bus_n0L2cache.connect( (comp_n0_bus, "lowlink0", "10000ps"), (comp_n0_l2cache, "highlink", "10000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (comp_n0_l2cache, "low_network_0", "10000ps"), (comp_n2_bus, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (comp_n0_l2cache, "lowlink", "10000ps"), (comp_n2_bus, "highlink0", "10000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (comp_c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (comp_c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (comp_c2_l1cache, "low_network_0", "10000ps"), (comp_n1_bus, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (comp_c2_l1cache, "lowlink", "10000ps"), (comp_n1_bus, "highlink0", "10000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (comp_c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (comp_c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (comp_c3_l1cache, "low_network_0", "10000ps"), (comp_n1_bus, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (comp_c3_l1cache, "lowlink", "10000ps"), (comp_n1_bus, "highlink1", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (comp_n1_bus, "low_network_0", "10000ps"), (comp_n1_l2cache, "high_network_0", "10000ps") ) +link_bus_n1L2cache.connect( (comp_n1_bus, "lowlink0", "10000ps"), (comp_n1_l2cache, "highlink", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (comp_n1_l2cache, "low_network_0", "10000ps"), (comp_n2_bus, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (comp_n1_l2cache, "lowlink", "10000ps"), (comp_n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (comp_n2_bus, "low_network_0", "10000ps"), (l3cache, "high_network_0", "10000ps") ) +link_bus_l3cache.connect( (comp_n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3cache, "directory", "10000ps"), (comp_chiprtr, "port1", "2000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (comp_chiprtr, "port0", "2000ps"), (comp_dirctrl, "network", "2000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (comp_dirctrl, "memory", "10000ps"), (comp_memctrl, "direct_link", "10000ps") ) +link_dir_mem_link.connect( (comp_dirctrl, "memory", "10000ps"), (comp_memctrl, "highlink", "10000ps") ) link_dir_cramsim_link = sst.Link("link_dir_cramsim_link") diff --git a/src/sst/elements/memHierarchy/tests/testBackendDelayBuffer.py b/src/sst/elements/memHierarchy/tests/testBackendDelayBuffer.py index b4b5e19f15..a67fd63a02 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendDelayBuffer.py +++ b/src/sst/elements/memHierarchy/tests/testBackendDelayBuffer.py @@ -157,8 +157,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "network_bw" : "25GB/s", "group" : 1 @@ -183,8 +182,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0", }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "network_bw" : "25GB/s", "group" : 2, @@ -222,34 +220,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "500ps"), (c0_l1cache, "high_network_0", "500ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "500ps"), (c0_l1cache, "highlink", "500ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "1000ps"), (n0_bus, "high_network_0", "1000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "1000ps"), (n0_bus, "highlink0", "1000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "500ps"), (c1_l1cache, "high_network_0", "500ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "500ps"), (c1_l1cache, "highlink", "500ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "1000ps"), (n0_bus, "high_network_1", "1000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "1000ps"), (n0_bus, "highlink1", "1000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "1000ps"), (n0_l2cache, "high_network_0", "1000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "1000ps"), (n0_l2cache, "highlink", "1000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "1000ps"), (n2_bus, "high_network_0", "1000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "1000ps"), (n2_bus, "highlink0", "1000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "500ps"), (c2_l1cache, "high_network_0", "500ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "500ps"), (c2_l1cache, "highlink", "500ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "1000ps"), (n1_bus, "high_network_0", "1000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "1000ps"), (n1_bus, "highlink0", "1000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "500ps"), (c3_l1cache, "high_network_0", "500ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "500ps"), (c3_l1cache, "highlink", "500ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "1000ps"), (n1_bus, "high_network_1", "1000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "1000ps"), (n1_bus, "highlink1", "1000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "1000ps"), (n1_l2cache, "high_network_0", "1000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "1000ps"), (n1_l2cache, "highlink", "1000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "1000ps"), (n2_bus, "high_network_1", "1000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "1000ps"), (n2_bus, "highlink1", "1000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "1000ps"), (l3tol2, "port", "1000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "1000ps"), (l3cache, "highlink", "1000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "1000ps"), (chiprtr, "port1", "1000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (chiprtr, "port0", "1000ps"), (dirNIC, "port", "1000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "1000ps"), (memctrl, "direct_link", "1000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "1000ps"), (memctrl, "highlink", "1000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendDramsim3.py b/src/sst/elements/memHierarchy/tests/testBackendDramsim3.py index 3f87f6b506..82aa4ca095 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendDramsim3.py +++ b/src/sst/elements/memHierarchy/tests/testBackendDramsim3.py @@ -32,8 +32,7 @@ "debug" : "0", "verbose" : 2, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "etwork_bw" : "25GB/s", @@ -79,13 +78,13 @@ # Connect link_cpu_l1 = sst.Link("link_cpu_l1_" + str(i)) - link_cpu_l1.connect( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + link_cpu_l1.connect( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) link_l1_l2 = sst.Link("link_l1_l2_" + str(i)) - link_l1_l2.connect( (l1cache, "low_network_0", "500ps"), (l2cache, "high_network_0", "500ps") ) + link_l1_l2.connect( (l1cache, "lowlink", "500ps"), (l2cache, "highlink", "500ps") ) link_l2_bus = sst.Link("link_l2_bus_" + str(i)) - link_l2_bus.connect( (l2cache, "low_network_0", "1000ps"), (bus, "high_network_" + str(i), "1000ps") ) + link_l2_bus.connect( (l2cache, "lowlink", "1000ps"), (bus, "highlink" + str(i), "1000ps") ) network = sst.Component("network", "merlin.hr_router") @@ -109,8 +108,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -133,14 +131,14 @@ # Do lower memory hierarchy links link_bus_l3 = sst.Link("link_bus_l3") -link_bus_l3.connect( (bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3.connect( (bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_l3_net = sst.Link("link_l3_net") link_l3_net.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net = sst.Link("link_dir_net") link_dir_net.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testBackendGoblinHMC.py b/src/sst/elements/memHierarchy/tests/testBackendGoblinHMC.py index 6f3cd915fd..2e524b7c1f 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendGoblinHMC.py +++ b/src/sst/elements/memHierarchy/tests/testBackendGoblinHMC.py @@ -162,8 +162,7 @@ "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "network_bw" : "25GB/s", "group" : 1, @@ -190,8 +189,7 @@ "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -230,34 +228,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "10000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "10000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "10000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3tol2, "port", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendHBMDramsim.py b/src/sst/elements/memHierarchy/tests/testBackendHBMDramsim.py index 57cbfa14a3..cc99f029af 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendHBMDramsim.py +++ b/src/sst/elements/memHierarchy/tests/testBackendHBMDramsim.py @@ -105,8 +105,7 @@ "debug_level" : 10, "debug" : 0, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "network_bw" : netBW, "group" : 1, @@ -136,8 +135,7 @@ "interleave_size" : "64B", "interleave_step" : "128B", }) -dirtoM0 = dirctrl0.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC0 = dirctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC0 = dirctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC0.addParams({ "group" : 2, "network_bw" : netBW, @@ -155,8 +153,7 @@ "interleave_size" : "64B", "interleave_step" : "128B", }) -dirtoM1 = dirctrl1.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC1 = dirctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC1 = dirctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC1.addParams({ "group" : 2, "network_bw" : netBW, @@ -174,7 +171,6 @@ "interleave_size" : "64B", "interleave_step" : "128B", }) -memtoD1 = memctrl1.setSubComponent("cpulink", "memHierarchy.MemLink") memory1 = memctrl1.setSubComponent("backend", "memHierarchy.dramsim") memory1.addParams({ "mem_size" : "512MiB", @@ -193,7 +189,6 @@ "interleave_size" : "64B", "interleave_step" : "128B", }) -memtoD0 = memctrl0.setSubComponent("cpulink", "memHierarchy.MemLink") memory0 = memctrl0.setSubComponent("backend", "memHierarchy.HBMDRAMSimMemory") memory0.addParams({ "mem_size" : "512MiB", @@ -209,38 +204,38 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "100ps"), (c0_l1cache, "high_network_0", "100ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "100ps"), (c0_l1cache, "highlink", "100ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "500ps"), (n0_bus, "high_network_0", "500ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "500ps"), (n0_bus, "highlink0", "500ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "100ps"), (c1_l1cache, "high_network_0", "100ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "100ps"), (c1_l1cache, "highlink", "100ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "500ps"), (n0_bus, "high_network_1", "500ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "500ps"), (n0_bus, "highlink1", "500ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "500ps"), (n0_l2cache, "high_network_0", "500ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "500ps"), (n0_l2cache, "highlink", "500ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "500ps"), (n2_bus, "high_network_0", "500ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "500ps"), (n2_bus, "highlink0", "500ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "100ps"), (c2_l1cache, "high_network_0", "100ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "100ps"), (c2_l1cache, "highlink", "100ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "500ps"), (n1_bus, "high_network_0", "500ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "500ps"), (n1_bus, "highlink0", "500ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "100ps"), (c3_l1cache, "high_network_0", "100ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "100ps"), (c3_l1cache, "highlink", "100ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "500ps"), (n1_bus, "high_network_1", "500ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "500ps"), (n1_bus, "highlink1", "500ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "500ps"), (n1_l2cache, "high_network_0", "500ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "500ps"), (n1_l2cache, "highlink", "500ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "500ps"), (n2_bus, "high_network_1", "500ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "500ps"), (n2_bus, "highlink1", "500ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "500ps"), (network, "port2", "500ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "200ps"), (dirNIC0, "port", "200ps") ) link_dir0_mem_link = sst.Link("link_dir0_mem_link") -link_dir0_mem_link.connect( (dirtoM0, "port", "500ps"), (memtoD0, "port", "500ps") ) +link_dir0_mem_link.connect( (dirctrl0, "lowlink", "500ps"), (memctrl0, "highlink", "500ps") ) link_dir_net_1 = sst.Link("link_dir_net_1") link_dir_net_1.connect( (network, "port1", "200ps"), (dirNIC1, "port", "200ps") ) link_dir1_mem_link = sst.Link("link_dir1_mem_link") -link_dir1_mem_link.connect( (dirtoM1, "port", "500ps"), (memtoD1, "port", "500ps") ) +link_dir1_mem_link.connect( (dirctrl1, "lowlink", "500ps"), (memctrl1, "highlink", "500ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendHBMPagedMulti.py b/src/sst/elements/memHierarchy/tests/testBackendHBMPagedMulti.py index 1dbfec80e1..8b280f28ff 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendHBMPagedMulti.py +++ b/src/sst/elements/memHierarchy/tests/testBackendHBMPagedMulti.py @@ -137,8 +137,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -163,8 +162,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -202,34 +200,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "500ps"), (c0_l1cache, "high_network_0", "500ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "500ps"), (c0_l1cache, "highlink", "500ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "1000ps"), (n0_bus, "high_network_0", "1000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "1000ps"), (n0_bus, "highlink0", "1000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "500ps"), (c1_l1cache, "high_network_0", "500ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "500ps"), (c1_l1cache, "highlink", "500ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "1000ps"), (n0_bus, "high_network_1", "1000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "1000ps"), (n0_bus, "highlink1", "1000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "1000ps"), (n0_l2cache, "high_network_0", "1000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "1000ps"), (n0_l2cache, "highlink", "1000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "1000ps"), (n2_bus, "high_network_0", "1000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "1000ps"), (n2_bus, "highlink0", "1000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "500ps"), (c2_l1cache, "high_network_0", "500ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "500ps"), (c2_l1cache, "highlink", "500ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "1000ps"), (n1_bus, "high_network_0", "1000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "1000ps"), (n1_bus, "highlink0", "1000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "500ps"), (c3_l1cache, "high_network_0", "500ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "500ps"), (c3_l1cache, "highlink", "500ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "1000ps"), (n1_bus, "high_network_1", "1000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "1000ps"), (n1_bus, "highlink1", "1000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "1000ps"), (n1_l2cache, "high_network_0", "1000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "1000ps"), (n1_l2cache, "highlink", "1000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "1000ps"), (n2_bus, "high_network_1", "1000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "1000ps"), (n2_bus, "highlink1", "1000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "1000ps"), (l3tol2, "port", "1000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "1000ps"), (l3cache, "highlink", "1000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "1000ps"), (network, "port1", "1000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "1000ps"), (dirNIC, "port", "1000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "1000ps"), (memctrl, "direct_link", "1000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "1000ps"), (memctrl, "highlink", "1000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendPagedMulti.py b/src/sst/elements/memHierarchy/tests/testBackendPagedMulti.py index aa7719bcd5..83486c2a9b 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendPagedMulti.py +++ b/src/sst/elements/memHierarchy/tests/testBackendPagedMulti.py @@ -137,8 +137,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -163,8 +162,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -202,34 +200,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "500ps"), (c0_l1cache, "high_network_0", "500ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "500ps"), (c0_l1cache, "highlink", "500ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "1000ps"), (n0_bus, "high_network_0", "1000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "1000ps"), (n0_bus, "highlink0", "1000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "500ps"), (c1_l1cache, "high_network_0", "500ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "500ps"), (c1_l1cache, "highlink", "500ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "1000ps"), (n0_bus, "high_network_1", "1000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "1000ps"), (n0_bus, "highlink1", "1000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "1000ps"), (n0_l2cache, "high_network_0", "1000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "1000ps"), (n0_l2cache, "highlink", "1000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "1000ps"), (n2_bus, "high_network_0", "1000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "1000ps"), (n2_bus, "highlink0", "1000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "500ps"), (c2_l1cache, "high_network_0", "500ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "500ps"), (c2_l1cache, "highlink", "500ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "1000ps"), (n1_bus, "high_network_0", "1000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "1000ps"), (n1_bus, "highlink0", "1000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "500ps"), (c3_l1cache, "high_network_0", "500ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "500ps"), (c3_l1cache, "highlink", "500ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "1000ps"), (n1_bus, "high_network_1", "1000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "1000ps"), (n1_bus, "highlink1", "1000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "1000ps"), (n1_l2cache, "high_network_0", "1000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "1000ps"), (n1_l2cache, "highlink", "1000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "1000ps"), (n2_bus, "high_network_1", "1000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "1000ps"), (n2_bus, "highlink1", "1000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "1000ps"), (l3tol2, "port", "1000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "1000ps"), (l3cache, "highlink", "1000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "1000ps"), (network, "port1", "1000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "1000ps"), (dirNIC, "port", "1000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "1000ps"), (memctrl, "direct_link", "1000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "1000ps"), (memctrl, "highlink", "1000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl4-2-ramulator.py b/src/sst/elements/memHierarchy/tests/testBackendRamulator-1.py similarity index 82% rename from src/sst/elements/memHierarchy/tests/sdl4-2-ramulator.py rename to src/sst/elements/memHierarchy/tests/testBackendRamulator-1.py index ee60f6419e..081d6bd441 100644 --- a/src/sst/elements/memHierarchy/tests/sdl4-2-ramulator.py +++ b/src/sst/elements/memHierarchy/tests/testBackendRamulator-1.py @@ -90,14 +90,14 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0_l1_l2_link = sst.Link("link_c0_l1_l2_link") -link_c0_l1_l2_link.connect( (c0_l1cache, "low_network_0", "1000ps"), (bus, "high_network_0", "10000ps") ) +link_c0_l1_l2_link.connect( (c0_l1cache, "lowlink", "1000ps"), (bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1_l1_l2_link = sst.Link("link_c1_l1_l2_link") -link_c1_l1_l2_link.connect( (c1_l1cache, "low_network_0", "1000ps"), (bus, "high_network_1", "10000ps") ) +link_c1_l1_l2_link.connect( (c1_l1cache, "lowlink", "1000ps"), (bus, "highlink1", "10000ps") ) link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (bus, "low_network_0", "10000ps"), (l2cache, "high_network_0", "1000ps") ) +link_bus_l2cache.connect( (bus, "lowlink0", "10000ps"), (l2cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/sdl5-1-ramulator.py b/src/sst/elements/memHierarchy/tests/testBackendRamulator-2.py similarity index 79% rename from src/sst/elements/memHierarchy/tests/sdl5-1-ramulator.py rename to src/sst/elements/memHierarchy/tests/testBackendRamulator-2.py index 453074a990..dd88550d95 100644 --- a/src/sst/elements/memHierarchy/tests/sdl5-1-ramulator.py +++ b/src/sst/elements/memHierarchy/tests/testBackendRamulator-2.py @@ -179,30 +179,30 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_cpu0_l1cache_link.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0_l1cache_l2cache_link = sst.Link("link_c0_l1cache_l2cache_link") -link_c0_l1cache_l2cache_link.connect( (c0_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0_l1cache_l2cache_link.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_cpu1_l1cache_link.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1_l1cache_l2cache_link = sst.Link("link_c1_l1cache_l2cache_link") -link_c1_l1cache_l2cache_link.connect( (c1_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1_l1cache_l2cache_link.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_n0_bus_l2cache = sst.Link("link_n0_bus_l2cache") -link_n0_bus_l2cache.connect( (n0_bus, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "1000ps") ) +link_n0_bus_l2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "1000ps") ) link_n0_l2cache_l3cache = sst.Link("link_n0_l2cache_l3cache") -link_n0_l2cache_l3cache.connect( (n0_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0_l2cache_l3cache.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_cpu2_l1cache_link = sst.Link("link_cpu2_l1cache_link") -link_cpu2_l1cache_link.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_cpu2_l1cache_link.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2_l1cache_l2cache_link = sst.Link("link_c2_l1cache_l2cache_link") -link_c2_l1cache_l2cache_link.connect( (c2_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2_l1cache_l2cache_link.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_cpu3_l1cache_link = sst.Link("link_cpu3_l1cache_link") -link_cpu3_l1cache_link.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_cpu3_l1cache_link.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3_l1cache_l2cache_link = sst.Link("link_c3_l1cache_l2cache_link") -link_c3_l1cache_l2cache_link.connect( (c3_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3_l1cache_l2cache_link.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) link_n1_bus_l2cache = sst.Link("link_n1_bus_l2cache") -link_n1_bus_l2cache.connect( (n1_bus, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "1000ps") ) +link_n1_bus_l2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "1000ps") ) link_n1_l2cache_l3cache = sst.Link("link_n1_l2cache_l3cache") -link_n1_l2cache_l3cache.connect( (n1_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1_l2cache_l3cache.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3cache, "high_network_0", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l3cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (l3cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendReorderRow.py b/src/sst/elements/memHierarchy/tests/testBackendReorderRow.py index 34c7203b3a..9ba37c68a4 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendReorderRow.py +++ b/src/sst/elements/memHierarchy/tests/testBackendReorderRow.py @@ -131,8 +131,7 @@ "cache_size" : "64KiB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "40GB/s", @@ -160,8 +159,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0", }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "40GB/s", @@ -200,34 +198,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "100ps"), (c0_l1cache, "high_network_0", "100ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "100ps"), (c0_l1cache, "highlink", "100ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "200ps"), (n0_bus, "high_network_0", "200ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "200ps"), (n0_bus, "highlink0", "200ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "100ps"), (c1_l1cache, "high_network_0", "100ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "100ps"), (c1_l1cache, "highlink", "100ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "100ps"), (n0_bus, "high_network_1", "200ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "100ps"), (n0_bus, "highlink1", "200ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "200ps"), (n0_l2cache, "high_network_0", "200ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "200ps"), (n0_l2cache, "highlink", "200ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "200ps"), (n2_bus, "high_network_0", "200ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "200ps"), (n2_bus, "highlink0", "200ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "100ps"), (c2_l1cache, "high_network_0", "100ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "100ps"), (c2_l1cache, "highlink", "100ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "200ps"), (n1_bus, "high_network_0", "200ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "200ps"), (n1_bus, "highlink0", "200ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "100ps"), (c3_l1cache, "high_network_0", "100ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "100ps"), (c3_l1cache, "highlink", "100ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "200ps"), (n1_bus, "high_network_1", "200ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "200ps"), (n1_bus, "highlink1", "200ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "200ps"), (n1_l2cache, "high_network_0", "200ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "200ps"), (n1_l2cache, "highlink", "200ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "200ps"), (n2_bus, "high_network_1", "200ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "200ps"), (n2_bus, "highlink1", "200ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "200ps"), (l3tol2, "port", "200ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "200ps"), (l3cache, "highlink", "200ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "200ps"), (network, "port1", "150ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "150ps"), (dirNIC, "port", "150ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "200ps"), (memctrl, "direct_link", "200ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "200ps"), (memctrl, "highlink", "200ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendReorderSimple.py b/src/sst/elements/memHierarchy/tests/testBackendReorderSimple.py index 8f80444545..387d5c4a7c 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendReorderSimple.py +++ b/src/sst/elements/memHierarchy/tests/testBackendReorderSimple.py @@ -131,8 +131,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -157,8 +156,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -195,34 +193,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "100ps"), (c0_l1cache, "high_network_0", "100ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "100ps"), (c0_l1cache, "highlink", "100ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "500ps"), (n0_bus, "high_network_0", "500ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "500ps"), (n0_bus, "highlink0", "500ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "100ps"), (c1_l1cache, "high_network_0", "100ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "100ps"), (c1_l1cache, "highlink", "100ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "500ps"), (n0_bus, "high_network_1", "500ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "500ps"), (n0_bus, "highlink1", "500ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "500ps"), (n0_l2cache, "high_network_0", "500ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "500ps"), (n0_l2cache, "highlink", "500ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "500ps"), (n2_bus, "high_network_0", "500ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "500ps"), (n2_bus, "highlink0", "500ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "100ps"), (c2_l1cache, "high_network_0", "100ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "100ps"), (c2_l1cache, "highlink", "100ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "500ps"), (n1_bus, "high_network_0", "500ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "500ps"), (n1_bus, "highlink0", "500ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "100ps"), (c3_l1cache, "high_network_0", "100ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "100ps"), (c3_l1cache, "highlink", "100ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "500ps"), (n1_bus, "high_network_1", "500ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "500ps"), (n1_bus, "highlink1", "500ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "500ps"), (n1_l2cache, "high_network_0", "500ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "500ps"), (n1_l2cache, "highlink", "500ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "500ps"), (n2_bus, "high_network_1", "500ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "500ps"), (n2_bus, "highlink1", "500ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "500ps"), (network, "port1", "200ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "200ps"), (dirNIC, "port", "200ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "500ps"), (memctrl, "direct_link", "500ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "500ps"), (memctrl, "highlink", "500ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-1.py b/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-1.py index 370953d3be..6416566dd2 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-1.py +++ b/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-1.py @@ -137,8 +137,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -163,8 +162,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -196,34 +194,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "10000ps"), (bus0, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (bus0, "highlink0", "10000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "10000ps"), (bus0, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (bus0, "highlink1", "10000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (bus0, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "10000ps") ) +link_bus_n0L2cache.connect( (bus0, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "10000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "10000ps"), (bus2, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "10000ps"), (bus2, "highlink0", "10000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "10000ps"), (bus1, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (bus1, "highlink0", "10000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "10000ps"), (bus1, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (bus1, "highlink1", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (bus1, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "10000ps") ) +link_bus_n1L2cache.connect( (bus1, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "10000ps"), (bus2, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "10000ps"), (bus2, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (bus2, "low_network_0", "10000ps"), (l3tol2, "port", "10000ps") ) +link_bus_l3cache.connect( (bus2, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-2.py b/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-2.py index 416818b96f..94152a4de6 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-2.py +++ b/src/sst/elements/memHierarchy/tests/testBackendSimpleDRAM-2.py @@ -155,8 +155,7 @@ "debug" : DEBUG_L3, "debug_level" : DEBUG_LEVEL, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -184,7 +183,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0", }) -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -213,7 +212,7 @@ "row_size" : "8KiB", "row_policy" : "closed", }) -memNIC = memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +memNIC = memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") memNIC.addParams({ "group" : 3, # "debug" : 1, @@ -232,31 +231,31 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "10000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "10000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "10000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3tol2, "port", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") diff --git a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-1.py b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-1.py index 15c954e691..9386baa048 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-1.py +++ b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-1.py @@ -32,8 +32,7 @@ "debug" : "0", "verbose" : 2, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -79,13 +78,13 @@ # Connect link_cpu_l1 = sst.Link("link_cpu_l1_" + str(i)) - link_cpu_l1.connect( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + link_cpu_l1.connect( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) link_l1_l2 = sst.Link("link_l1_l2_" + str(i)) - link_l1_l2.connect( (l1cache, "low_network_0", "500ps"), (l2cache, "high_network_0", "500ps") ) + link_l1_l2.connect( (l1cache, "lowlink", "500ps"), (l2cache, "highlink", "500ps") ) link_l2_bus = sst.Link("link_l2_bus_" + str(i)) - link_l2_bus.connect( (l2cache, "low_network_0", "1000ps"), (bus, "high_network_" + str(i), "1000ps") ) + link_l2_bus.connect( (l2cache, "lowlink", "1000ps"), (bus, "highlink" + str(i), "1000ps") ) network = sst.Component("network", "merlin.hr_router") @@ -109,8 +108,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -153,14 +151,14 @@ # Do lower memory hierarchy links link_bus_l3 = sst.Link("link_bus_l3") -link_bus_l3.connect( (bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3.connect( (bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_l3_net = sst.Link("link_l3_net") link_l3_net.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net = sst.Link("link_dir_net") link_dir_net.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-2.py b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-2.py index a33a8bd6a7..c9ae0f8bd4 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-2.py +++ b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-2.py @@ -32,8 +32,7 @@ "debug" : "0", "verbose" : 2, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "etwork_bw" : "25GB/s", @@ -79,13 +78,13 @@ # Connect link_cpu_l1 = sst.Link("link_cpu_l1_" + str(i)) - link_cpu_l1.connect( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + link_cpu_l1.connect( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) link_l1_l2 = sst.Link("link_l1_l2_" + str(i)) - link_l1_l2.connect( (l1cache, "low_network_0", "500ps"), (l2cache, "high_network_0", "500ps") ) + link_l1_l2.connect( (l1cache, "lowlink", "500ps"), (l2cache, "highlink", "500ps") ) link_l2_bus = sst.Link("link_l2_bus_" + str(i)) - link_l2_bus.connect( (l2cache, "low_network_0", "1000ps"), (bus, "high_network_" + str(i), "1000ps") ) + link_l2_bus.connect( (l2cache, "lowlink", "1000ps"), (bus, "highlink" + str(i), "1000ps") ) network = sst.Component("network", "merlin.hr_router") @@ -109,8 +108,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -153,14 +151,14 @@ # Do lower memory hierarchy links link_bus_l3 = sst.Link("link_bus_l3") -link_bus_l3.connect( (bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3.connect( (bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_l3_net = sst.Link("link_l3_net") link_l3_net.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net = sst.Link("link_dir_net") link_dir_net.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-3.py b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-3.py index a1c7c19705..325529f9c9 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-3.py +++ b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-3.py @@ -32,8 +32,7 @@ "debug" : "0", "verbose" : 2, }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -79,13 +78,13 @@ # Connect link_cpu_l1 = sst.Link("link_cpu_l1_" + str(i)) - link_cpu_l1.connect( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + link_cpu_l1.connect( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) link_l1_l2 = sst.Link("link_l1_l2_" + str(i)) - link_l1_l2.connect( (l1cache, "low_network_0", "500ps"), (l2cache, "high_network_0", "500ps") ) + link_l1_l2.connect( (l1cache, "lowlink", "500ps"), (l2cache, "highlink", "500ps") ) link_l2_bus = sst.Link("link_l2_bus_" + str(i)) - link_l2_bus.connect( (l2cache, "low_network_0", "1000ps"), (bus, "high_network_" + str(i), "1000ps") ) + link_l2_bus.connect( (l2cache, "lowlink", "1000ps"), (bus, "highlink" + str(i), "1000ps") ) network = sst.Component("network", "merlin.hr_router") @@ -109,8 +108,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -152,14 +150,14 @@ # Do lower memory hierarchy links link_bus_l3 = sst.Link("link_bus_l3") -link_bus_l3.connect( (bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3.connect( (bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_l3_net = sst.Link("link_l3_net") link_l3_net.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net = sst.Link("link_dir_net") link_dir_net.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-4.py b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-4.py index 7bb359703c..09b67ef572 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-4.py +++ b/src/sst/elements/memHierarchy/tests/testBackendTimingDRAM-4.py @@ -32,8 +32,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -79,13 +78,13 @@ # Connect link_cpu_l1 = sst.Link("link_cpu_l1_" + str(i)) - link_cpu_l1.connect( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + link_cpu_l1.connect( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) link_l1_l2 = sst.Link("link_l1_l2_" + str(i)) - link_l1_l2.connect( (l1cache, "low_network_0", "500ps"), (l2cache, "high_network_0", "500ps") ) + link_l1_l2.connect( (l1cache, "lowlink", "500ps"), (l2cache, "highlink", "500ps") ) link_l2_bus = sst.Link("link_l2_bus_" + str(i)) - link_l2_bus.connect( (l2cache, "low_network_0", "1000ps"), (bus, "high_network_" + str(i), "1000ps") ) + link_l2_bus.connect( (l2cache, "lowlink", "1000ps"), (bus, "highlink" + str(i), "1000ps") ) network = sst.Component("network", "merlin.hr_router") @@ -109,8 +108,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -152,14 +150,14 @@ # Do lower memory hierarchy links link_bus_l3 = sst.Link("link_bus_l3") -link_bus_l3.connect( (bus, "low_network_0", "500ps"), (l3tol2, "port", "500ps") ) +link_bus_l3.connect( (bus, "lowlink0", "500ps"), (l3cache, "highlink", "500ps") ) link_l3_net = sst.Link("link_l3_net") link_l3_net.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net = sst.Link("link_dir_net") link_dir_net.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem = sst.Link("link_dir_mem") -link_dir_mem.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testBackendVaultSim.py b/src/sst/elements/memHierarchy/tests/testBackendVaultSim.py index efa08b76ee..0ba6723672 100644 --- a/src/sst/elements/memHierarchy/tests/testBackendVaultSim.py +++ b/src/sst/elements/memHierarchy/tests/testBackendVaultSim.py @@ -151,8 +151,7 @@ "cache_size" : "64 KB", "debug" : "0", }) -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : "25GB/s", @@ -177,8 +176,7 @@ "addr_range_end" : "0x1F000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -270,37 +268,37 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (c0_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_0", "10000ps") ) +link_c0L1cache_bus.connect( (c0_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink0", "10000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (c1_l1cache, "low_network_0", "10000ps"), (n0_bus, "high_network_1", "10000ps") ) +link_c1L1cache_bus.connect( (c1_l1cache, "lowlink", "10000ps"), (n0_bus, "highlink1", "10000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (n0_bus, "low_network_0", "10000ps"), (n0_l2cache, "high_network_0", "10000ps") ) +link_bus_n0L2cache.connect( (n0_bus, "lowlink0", "10000ps"), (n0_l2cache, "highlink", "10000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (n0_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_0", "10000ps") ) +link_n0L2cache_bus.connect( (n0_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink0", "10000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (c2_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_0", "10000ps") ) +link_c2L1cache_bus.connect( (c2_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink0", "10000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (c3_l1cache, "low_network_0", "10000ps"), (n1_bus, "high_network_1", "10000ps") ) +link_c3L1cache_bus.connect( (c3_l1cache, "lowlink", "10000ps"), (n1_bus, "highlink1", "10000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (n1_bus, "low_network_0", "10000ps"), (n1_l2cache, "high_network_0", "10000ps") ) +link_bus_n1L2cache.connect( (n1_bus, "lowlink0", "10000ps"), (n1_l2cache, "highlink", "10000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (n1_l2cache, "low_network_0", "10000ps"), (n2_bus, "high_network_1", "10000ps") ) +link_n1L2cache_bus.connect( (n1_l2cache, "lowlink", "10000ps"), (n2_bus, "highlink1", "10000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (n2_bus, "low_network_0", "10000ps"), (l3tol2, "port", "10000ps") ) +link_bus_l3cache.connect( (n2_bus, "lowlink0", "10000ps"), (l3cache, "highlink", "10000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "10000ps"), (network, "port1", "2000ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (network, "port0", "2000ps"), (dirNIC, "port", "2000ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) link_dir_cube_link = sst.Link("link_dir_cube_link") link_dir_cube_link.connect( (memory, "cube_link", "2ns"), (logic_layer, "toCPU", "2ns") ) link_logic_v0 = sst.Link("link_logic_v0") diff --git a/src/sst/elements/memHierarchy/tests/testBridge.py b/src/sst/elements/memHierarchy/tests/testBridge.py index a800bd4aa7..e2459a0790 100644 --- a/src/sst/elements/memHierarchy/tests/testBridge.py +++ b/src/sst/elements/memHierarchy/tests/testBridge.py @@ -64,14 +64,16 @@ def buildCPU(num, network): "associativity" : 4, "cache_line_size": 64, "L1": 1, - "network_bw" : netBW, }) + l1_lowlink = l1.setSubComponent("lowlink", "memHierarchy.MemNIC") + l1_lowlink.addParam("network_bw", netBW) + l1_lowlink.addParam("group", 1) - cpuLink = sst.Link("cpu-cache-%d"%num) - cpuLink.connect( (iface, "port", "500ps"), (l1, "high_network_0", "500ps")) + highlink = sst.Link("cpu_cache_%d"%num) + highlink.connect( (iface, "lowlink", "500ps"), (l1, "highlink", "500ps")) - rtrLink = sst.Link("L1-net-%d"%num) - rtrLink.connect( (l1, "directory", "500ps"), (network.rtr, "port%d"%netPort, "500ps") ) + rtrLink = sst.Link("L1_net_%d"%num) + rtrLink.connect( (l1_lowlink, "port", "500ps"), (network.rtr, "port%d"%netPort, "500ps") ) def buildMem(num, network): @@ -81,7 +83,9 @@ def buildMem(num, network): mem.addParams({ "debug": debug, "debug_level" : debug_level, - "clock" : "1GHz" + "clock" : "1GHz", + "addr_range_start" : num * (mem_size // num_mem), + "addr_range_end" : (num+1) * (mem_size // num_mem) -1, }) memback = mem.setSubComponent("backend", "memHierarchy.simpleMem") memback.addParams({ @@ -98,11 +102,14 @@ def buildMem(num, network): "addr_range_start" : num * (mem_size // num_mem), "addr_range_end" : (num+1) * (mem_size // num_mem) -1, }) + dc_highlink = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_highlink.addParam("network_bw", netBW) + dc_highlink.addParam("group", 2) - memLink = sst.Link("MemDir_%d"%num) - memLink.connect( (dc, "memory", "500ps"), (mem, "direct_link", "500ps") ) + lowlink = sst.Link("MemDir_%d"%num) + lowlink.connect( (dc, "lowlink", "500ps"), (mem, "highlink", "500ps") ) dcLink = sst.Link("DCNet%d"%num) - dcLink.connect( (dc, "network", "500ps"), (network.rtr, "port%d"%netPort, "500ps") ) + dcLink.connect( (dc_highlink, "port", "500ps"), (network.rtr, "port%d"%netPort, "500ps") ) @@ -110,17 +117,17 @@ def buildMem(num, network): def bridge(net0, net1): net0port = net0.getNextPort() net1port = net1.getNextPort() - name = "%s-%s"%(net0.name, net1.name) - bridge = sst.Component("Bridge:%s"%name, "merlin.Bridge") + name = "%s_%s"%(net0.name, net1.name) + bridge = sst.Component("Bridge.%s"%name, "merlin.Bridge") bridge.addParams({ "translator": "memHierarchy.MemNetBridge", "debug": debug, "debug_level" : debug_level, "network_bw" : netBW, }) - link = sst.Link("B0-%s"%name) + link = sst.Link("B0_%s"%name) link.connect( (bridge, "network0", "500ps"), (net0.rtr, "port%d"%net0port, "500ps") ) - link = sst.Link("B1-%s"%name) + link = sst.Link("B1_%s"%name) link.connect( (bridge, "network1", "500ps"), (net1.rtr, "port%d"%net1port, "500ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testCachLineTrack.py b/src/sst/elements/memHierarchy/tests/testCachLineTrack.py index 1933caa5bb..0b9b4ae3cf 100644 --- a/src/sst/elements/memHierarchy/tests/testCachLineTrack.py +++ b/src/sst/elements/memHierarchy/tests/testCachLineTrack.py @@ -79,8 +79,7 @@ #"prefetcher" : "cassini.NextBlockPrefetcher", #"drop_prefetch_mshr_level" : 5, # Drop prefetch when total misses > 5 }) - l2tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2NIC = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2NIC = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2NIC.addParams({ "group" : 1, # MemNIC parameters @@ -90,10 +89,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (comp_l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (comp_l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (comp_l1cache, "low_network_0", "100ps"), (l2tol1, "port", "100ps") ) + l1_l2_link.connect( (comp_l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2NIC, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -115,7 +114,7 @@ "slice_allocation_policy" : "rr", # Round-robin "slice_id" : x, }) - l3NIC = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3NIC = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 2, # MemNIC parameters @@ -140,8 +139,7 @@ "addr_range_start" : x*64, "addr_range_end" : 1024*1024*1024 - ((memories - x) * 64) + 63, }) - dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") - dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 3, # MemNIC parameters @@ -172,7 +170,7 @@ link_directory_network.connect( (dirNIC, "port", "100ps"), (comp_network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (comp_memory, "direct_link", "400ps") ) + link_directory_memory_network.connect( (dirctrl, "lowlink", "400ps"), (comp_memory, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testCoherenceDomains.py b/src/sst/elements/memHierarchy/tests/testCoherenceDomains.py index 17a04ab894..11f10dc16d 100644 --- a/src/sst/elements/memHierarchy/tests/testCoherenceDomains.py +++ b/src/sst/elements/memHierarchy/tests/testCoherenceDomains.py @@ -48,8 +48,7 @@ "debug" : DEBUG_L1 | DEBUG_CORE0 | DEBUG_NODE0, "debug_level" : 10, }) -node0_l1cache0_to_core = node0_l1cache0.setSubComponent("cpulink", "memHierarchy.MemLink") -node0_l1cache0_to_network = node0_l1cache0.setSubComponent("memlink", "memHierarchy.MemNIC") +node0_l1cache0_to_network = node0_l1cache0.setSubComponent("lowlink", "memHierarchy.MemNIC") node0_l1cache0_to_network.addParams({ "group" : 0, "network_bw" : "25GB/s", @@ -89,8 +88,7 @@ "debug" : DEBUG_L1 | DEBUG_CORE1 | DEBUG_NODE0, "debug_level" : 10, }) -node0_l1cache1_to_core = node0_l1cache1.setSubComponent("cpulink", "memHierarchy.MemLink") -node0_l1cache1_to_network = node0_l1cache1.setSubComponent("memlink", "memHierarchy.MemNIC") +node0_l1cache1_to_network = node0_l1cache1.setSubComponent("lowlink", "memHierarchy.MemNIC") node0_l1cache1_to_network.addParams({ "group" : 0, "network_bw" : "25GB/s", @@ -130,8 +128,7 @@ "debug" : DEBUG_L1 | DEBUG_CORE0 | DEBUG_NODE1, "debug_level" : 10, }) -node1_l1cache0_to_core = node1_l1cache0.setSubComponent("cpulink", "memHierarchy.MemLink") -node1_l1cache0_to_network = node1_l1cache0.setSubComponent("memlink", "memHierarchy.MemNIC") +node1_l1cache0_to_network = node1_l1cache0.setSubComponent("lowlink", "memHierarchy.MemNIC") node1_l1cache0_to_network.addParams({ "group" : 0, "network_bw" : "25GB/s", @@ -170,8 +167,7 @@ "debug" : DEBUG_L1 | DEBUG_CORE1 | DEBUG_NODE0, "debug_level" : 10, }) -node1_l1cache1_to_core = node1_l1cache1.setSubComponent("cpulink", "memHierarchy.MemLink") -node1_l1cache1_to_network = node1_l1cache1.setSubComponent("memlink", "memHierarchy.MemNIC") +node1_l1cache1_to_network = node1_l1cache1.setSubComponent("lowlink", "memHierarchy.MemNIC") node1_l1cache1_to_network.addParams({ "group" : 0, "network_bw" : "25GB/s", @@ -237,10 +233,10 @@ "addr_range_start" : 75*1024, }) # Create and parameterize memNIC for each dir -node0_dc0_to_network = node0_dc0.setSubComponent("cpulink", "memHierarchy.MemNIC") -node0_dc1_to_network = node0_dc1.setSubComponent("cpulink", "memHierarchy.MemNIC") -node1_dc0_to_network = node1_dc0.setSubComponent("cpulink", "memHierarchy.MemNIC") -node1_dc1_to_network = node1_dc1.setSubComponent("cpulink", "memHierarchy.MemNIC") +node0_dc0_to_network = node0_dc0.setSubComponent("highlink", "memHierarchy.MemNIC") +node0_dc1_to_network = node0_dc1.setSubComponent("highlink", "memHierarchy.MemNIC") +node1_dc0_to_network = node1_dc0.setSubComponent("highlink", "memHierarchy.MemNIC") +node1_dc1_to_network = node1_dc1.setSubComponent("highlink", "memHierarchy.MemNIC") node0_dc0_to_network.addParams({ "network_bw" : "25GB/s", "group" : 1, @@ -257,11 +253,6 @@ "network_bw" : "25GB/s", "group" : 1, }) -# Create memlink (to memory controller) for each dir -node0_dc0_to_memory = node0_dc0.setSubComponent("memlink", "memHierarchy.MemLink") -node0_dc1_to_memory = node0_dc1.setSubComponent("memlink", "memHierarchy.MemLink") -node1_dc0_to_memory = node1_dc0.setSubComponent("memlink", "memHierarchy.MemLink") -node1_dc1_to_memory = node1_dc1.setSubComponent("memlink", "memHierarchy.MemLink") # Memory controllers node0_mc0 = sst.Component("n0.memory0", "memHierarchy.MemController") @@ -312,11 +303,6 @@ node1_mem0.addParams( { "access_time" : "100 ns", "mem_size" : "50KiB" } ) node1_mem1.addParams( { "access_time" : "100 ns", "mem_size" : "50KiB" } ) -# Create memlink (to directories) for each memory controller -node0_mem0_to_dc = node0_mc0.setSubComponent("cpulink", "memHierarchy.MemLink") -node0_mem1_to_dc = node0_mc1.setSubComponent("cpulink", "memHierarchy.MemLink") -node1_mem0_to_dc = node1_mc0.setSubComponent("cpulink", "memHierarchy.MemLink") -node1_mem1_to_dc = node1_mc1.setSubComponent("cpulink", "memHierarchy.MemLink") #################### # Enable statistics @@ -337,10 +323,10 @@ link_node0_core1 = sst.Link("link_n0_core1") link_node1_core0 = sst.Link("link_n1_core0") link_node1_core1 = sst.Link("link_n1_core1") -link_node0_core0.connect( (node0_core0_iface, "port", "1000ps"), (node0_l1cache0_to_core, "port", "1000ps") ) -link_node0_core1.connect( (node0_core1_iface, "port", "1000ps"), (node0_l1cache1_to_core, "port", "1000ps") ) -link_node1_core0.connect( (node1_core0_iface, "port", "1000ps"), (node1_l1cache0_to_core, "port", "1000ps") ) -link_node1_core1.connect( (node1_core1_iface, "port", "1000ps"), (node1_l1cache1_to_core, "port", "1000ps") ) +link_node0_core0.connect( (node0_core0_iface, "lowlink", "1000ps"), (node0_l1cache0, "highlink", "1000ps") ) +link_node0_core1.connect( (node0_core1_iface, "lowlink", "1000ps"), (node0_l1cache1, "highlink", "1000ps") ) +link_node1_core0.connect( (node1_core0_iface, "lowlink", "1000ps"), (node1_l1cache0, "highlink", "1000ps") ) +link_node1_core1.connect( (node1_core1_iface, "lowlink", "1000ps"), (node1_l1cache1, "highlink", "1000ps") ) # L1s to network @@ -368,10 +354,10 @@ link_node0_dc1_mc1 = sst.Link("link_n0_dc1_m1") link_node1_dc0_mc0 = sst.Link("link_n1_dc0_m0") link_node1_dc1_mc1 = sst.Link("link_n1_dc1_m1") -link_node0_dc0_mc0.connect( (node0_dc0_to_memory, "port", "1000ps"), (node0_mem0_to_dc, "port", "1000ps") ) -link_node0_dc1_mc1.connect( (node0_dc1_to_memory, "port", "1000ps"), (node0_mem1_to_dc, "port", "1000ps") ) -link_node1_dc0_mc0.connect( (node1_dc0_to_memory, "port", "1000ps"), (node1_mem0_to_dc, "port", "1000ps") ) -link_node1_dc1_mc1.connect( (node1_dc1_to_memory, "port", "1000ps"), (node1_mem1_to_dc, "port", "1000ps") ) +link_node0_dc0_mc0.connect( (node0_dc0, "lowlink", "1000ps"), (node0_mc0, "highlink", "1000ps") ) +link_node0_dc1_mc1.connect( (node0_dc1, "lowlink", "1000ps"), (node0_mc1, "highlink", "1000ps") ) +link_node1_dc0_mc0.connect( (node1_dc0, "lowlink", "1000ps"), (node1_mc0, "highlink", "1000ps") ) +link_node1_dc1_mc1.connect( (node1_dc1, "lowlink", "1000ps"), (node1_mc1, "highlink", "1000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-1.py b/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-1.py index 952f3e0cf9..3b41e67d34 100644 --- a/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-1.py +++ b/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-1.py @@ -67,8 +67,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-2.py b/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-2.py index 9a517c4a4c..04fff39367 100644 --- a/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-2.py +++ b/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-2.py @@ -63,8 +63,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-3.py b/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-3.py index 42341cba56..14d0aea00c 100644 --- a/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-3.py +++ b/src/sst/elements/memHierarchy/tests/testCustomCmdGoblin-3.py @@ -45,19 +45,21 @@ l2 = sst.Component("l2cache_%d"%(next_core_id), "memHierarchy.Cache") l2.addParams(config.getL2Params()) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParam("group", 1) connect("cpu_cache_link_%d"%next_core_id, - iface, "port", - l1, "high_network_0", + iface, "lowlink", + l1, "highlink", config.ring_latency).setNoCut() connect("l2cache_%d_link"%next_core_id, - l1, "low_network_0", - l2, "high_network_0", + l1, "lowlink", + l2, "highlink", config.ring_latency).setNoCut() connect("l2_ring_link_%d"%next_core_id, - l2, "directory", + l2_nic, "port", router, "port%d"%next_core_id, config.ring_latency) @@ -69,14 +71,16 @@ dc = sst.Component("dc", "memHierarchy.DirectoryController") dc.addParams(config.getDCParams(0)) +dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") +dc_nic.addParam("group", 2) connect("mem_link_0", - memctrl, "direct_link", - dc, "memory", + memctrl, "highlink", + dc, "lowlink", config.ring_latency) connect("dc_link_0", - dc, "network", + dc_nic, "port", router, "port%d"%config.total_cores, config.ring_latency) diff --git a/src/sst/elements/memHierarchy/tests/testDistributedCaches.py b/src/sst/elements/memHierarchy/tests/testDistributedCaches.py index f367a93bfe..98f39a6a05 100644 --- a/src/sst/elements/memHierarchy/tests/testDistributedCaches.py +++ b/src/sst/elements/memHierarchy/tests/testDistributedCaches.py @@ -62,15 +62,14 @@ "debug" : DEBUG_L1, "debug_level" : 10, }) - l1toC = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l1NIC = l1cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l1NIC = l1cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l1NIC.addParams({ "group" : 1, "network_bw" : network_bw, }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (l1toC, "port", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) l1_network_link = sst.Link("link_l1_network_" + str(x)) l1_network_link.connect( (l1NIC, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -94,7 +93,7 @@ "debug_level" : 10, "verbose" : 2, }) - l2NIC = l2cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l2NIC = l2cache.setSubComponent("highlink", "memHierarchy.MemNIC") l2NIC.addParams({ "group" : 2, "network_bw" : network_bw, @@ -120,7 +119,7 @@ "addr_range_start" : x*64, "addr_range_end" : 1024*1024*1024 - ((memories - x) * 64) + 63, }) - dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 3, "network_bw" : network_bw, @@ -142,7 +141,7 @@ "addr_range_start" : x*64, "addr_range_end" : 1024*1024*1024 - ((memories - x) * 64) + 63, }) - memNIC = memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") + memNIC = memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") memNIC.addParams({ "group" : 4, "network_bw" : network_bw, diff --git a/src/sst/elements/memHierarchy/tests/testFlushes-2.py b/src/sst/elements/memHierarchy/tests/testFlushes-2.py index 4d90bcc108..cdedd47e59 100644 --- a/src/sst/elements/memHierarchy/tests/testFlushes-2.py +++ b/src/sst/elements/memHierarchy/tests/testFlushes-2.py @@ -88,8 +88,7 @@ "debug" : DEBUG_L2, "debug_level" : 10, }) - l2tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2NIC = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2NIC = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2NIC.addParams({ "group" : 1, "network_bw" : network_bw, @@ -98,10 +97,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (comp_l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (comp_l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (comp_l1cache, "low_network_0", "100ps"), (l2tol1, "port", "100ps") ) + l1_l2_link.connect( (comp_l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2NIC, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -128,7 +127,7 @@ "debug_level" : 10, }) - l3NIC = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3NIC = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 2, "network_bw" : network_bw, @@ -157,8 +156,7 @@ "addr_range_end" : 1024*1024*1024 - ((memories - x) * 64) + 63, }) - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") - dirNIC = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirNIC = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 3, "group" : 3, # L2 = 1, L3 = 2, dir = 3 @@ -197,7 +195,7 @@ link_directory_network.connect( (dirNIC, "port", "100ps"), (comp_network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testFlushes.py b/src/sst/elements/memHierarchy/tests/testFlushes.py index 5606ebfa75..40fe031f1f 100644 --- a/src/sst/elements/memHierarchy/tests/testFlushes.py +++ b/src/sst/elements/memHierarchy/tests/testFlushes.py @@ -86,8 +86,7 @@ "debug" : DEBUG_L2, "debug_level" : DEBUG_LEVEL }) - l2tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2NIC = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2NIC = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2NIC.addParams({ "group" : 1, "network_bw" : network_bw, @@ -96,10 +95,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (comp_l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (comp_l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (comp_l1cache, "low_network_0", "100ps"), (l2tol1, "port", "100ps") ) + l1_l2_link.connect( (comp_l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2NIC, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -124,7 +123,7 @@ "debug" : DEBUG_L3, "debug_level" : DEBUG_LEVEL }) - l3NIC = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3NIC = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 2, "network_bw" : network_bw, @@ -152,8 +151,7 @@ "debug_level" : DEBUG_LEVEL }) - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") - dirNIC = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirNIC = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 3, "network_bw" : network_bw, @@ -190,7 +188,7 @@ link_directory_network.connect( (dirNIC, "port", "100ps"), (comp_network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testHashXor.py b/src/sst/elements/memHierarchy/tests/testHashXor.py index 973f1fa26a..f5a949ad08 100644 --- a/src/sst/elements/memHierarchy/tests/testHashXor.py +++ b/src/sst/elements/memHierarchy/tests/testHashXor.py @@ -116,8 +116,7 @@ "debug_level" : 10 }) l3cache.setSubComponent("hash", "memHierarchy.hash.xor") -l3tol2 = l3cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l3NIC = l3cache.setSubComponent("memlink", "memHierarchy.MemNIC") +l3NIC = l3cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 1, "network_bw" : " 25GB/s", @@ -147,8 +146,7 @@ "addr_range_end" : "0x40000000", "addr_range_start" : "0x0" }) -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 2, "network_bw" : "25GB/s", @@ -178,34 +176,34 @@ # Define the simulation links link_c0_l1cache = sst.Link("link_c0_l1cache") -link_c0_l1cache.connect( (iface0, "port", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") ) +link_c0_l1cache.connect( (iface0, "lowlink", "1000ps"), (comp_c0_l1cache, "highlink", "1000ps") ) link_c0L1cache_bus = sst.Link("link_c0L1cache_bus") -link_c0L1cache_bus.connect( (comp_c0_l1cache, "low_network_0", "1000ps"), (comp_n0_bus, "high_network_0", "1000ps") ) +link_c0L1cache_bus.connect( (comp_c0_l1cache, "lowlink", "1000ps"), (comp_n0_bus, "highlink0", "1000ps") ) link_c1_l1cache = sst.Link("link_c1_l1cache") -link_c1_l1cache.connect( (iface1, "port", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") ) +link_c1_l1cache.connect( (iface1, "lowlink", "1000ps"), (comp_c1_l1cache, "highlink", "1000ps") ) link_c1L1cache_bus = sst.Link("link_c1L1cache_bus") -link_c1L1cache_bus.connect( (comp_c1_l1cache, "low_network_0", "1000ps"), (comp_n0_bus, "high_network_1", "1000ps") ) +link_c1L1cache_bus.connect( (comp_c1_l1cache, "lowlink", "1000ps"), (comp_n0_bus, "highlink1", "1000ps") ) link_bus_n0L2cache = sst.Link("link_bus_n0L2cache") -link_bus_n0L2cache.connect( (comp_n0_bus, "low_network_0", "1000ps"), (comp_n0_l2cache, "high_network_0", "1000ps") ) +link_bus_n0L2cache.connect( (comp_n0_bus, "lowlink0", "1000ps"), (comp_n0_l2cache, "highlink", "1000ps") ) link_n0L2cache_bus = sst.Link("link_n0L2cache_bus") -link_n0L2cache_bus.connect( (comp_n0_l2cache, "low_network_0", "1000ps"), (comp_n2_bus, "high_network_0", "1000ps") ) +link_n0L2cache_bus.connect( (comp_n0_l2cache, "lowlink", "1000ps"), (comp_n2_bus, "highlink0", "1000ps") ) link_c2_l1cache = sst.Link("link_c2_l1cache") -link_c2_l1cache.connect( (iface2, "port", "1000ps"), (comp_c2_l1cache, "high_network_0", "1000ps") ) +link_c2_l1cache.connect( (iface2, "lowlink", "1000ps"), (comp_c2_l1cache, "highlink", "1000ps") ) link_c2L1cache_bus = sst.Link("link_c2L1cache_bus") -link_c2L1cache_bus.connect( (comp_c2_l1cache, "low_network_0", "1000ps"), (comp_n1_bus, "high_network_0", "1000ps") ) +link_c2L1cache_bus.connect( (comp_c2_l1cache, "lowlink", "1000ps"), (comp_n1_bus, "highlink0", "1000ps") ) link_c3_l1cache = sst.Link("link_c3_l1cache") -link_c3_l1cache.connect( (iface3, "port", "1000ps"), (comp_c3_l1cache, "high_network_0", "1000ps") ) +link_c3_l1cache.connect( (iface3, "lowlink", "1000ps"), (comp_c3_l1cache, "highlink", "1000ps") ) link_c3L1cache_bus = sst.Link("link_c3L1cache_bus") -link_c3L1cache_bus.connect( (comp_c3_l1cache, "low_network_0", "1000ps"), (comp_n1_bus, "high_network_1", "1000ps") ) +link_c3L1cache_bus.connect( (comp_c3_l1cache, "lowlink", "1000ps"), (comp_n1_bus, "highlink1", "1000ps") ) link_bus_n1L2cache = sst.Link("link_bus_n1L2cache") -link_bus_n1L2cache.connect( (comp_n1_bus, "low_network_0", "1000ps"), (comp_n1_l2cache, "high_network_0", "1000ps") ) +link_bus_n1L2cache.connect( (comp_n1_bus, "lowlink0", "1000ps"), (comp_n1_l2cache, "highlink", "1000ps") ) link_n1L2cache_bus = sst.Link("link_n1L2cache_bus") -link_n1L2cache_bus.connect( (comp_n1_l2cache, "low_network_0", "1000ps"), (comp_n2_bus, "high_network_1", "1000ps") ) +link_n1L2cache_bus.connect( (comp_n1_l2cache, "lowlink", "1000ps"), (comp_n2_bus, "highlink1", "1000ps") ) link_bus_l3cache = sst.Link("link_bus_l3cache") -link_bus_l3cache.connect( (comp_n2_bus, "low_network_0", "1000ps"), (l3tol2, "port", "1000ps") ) +link_bus_l3cache.connect( (comp_n2_bus, "lowlink0", "1000ps"), (l3cache, "highlink", "1000ps") ) link_cache_net_0 = sst.Link("link_cache_net_0") link_cache_net_0.connect( (l3NIC, "port", "1000ps"), (comp_chiprtr, "port1", "100ps") ) link_dir_net_0 = sst.Link("link_dir_net_0") link_dir_net_0.connect( (comp_chiprtr, "port0", "100ps"), (dirNIC, "port", "100ps") ) link_dir_mem_link = sst.Link("link_dir_mem_link") -link_dir_mem_link.connect( (dirtoM, "port", "1000ps"), (memctrl, "direct_link", "1000ps") ) +link_dir_mem_link.connect( (dirctrl, "lowlink", "1000ps"), (memctrl, "highlink", "1000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testIface-nic.py b/src/sst/elements/memHierarchy/tests/testIface-nic.py index fa4210a096..73d3878706 100644 --- a/src/sst/elements/memHierarchy/tests/testIface-nic.py +++ b/src/sst/elements/memHierarchy/tests/testIface-nic.py @@ -19,7 +19,7 @@ }) iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface") iface.addParams(debug_params) -cpu_nic = iface.setSubComponent("memlink", "memHierarchy.MemNIC") +cpu_nic = iface.setSubComponent("lowlink", "memHierarchy.MemNIC") cpu_nic.addParams({"group" : 0, "network_bw" : "25GB/s"}) #cpu_nic.addParams(debug_params) @@ -36,7 +36,7 @@ "debug" : DEBUG_L1, "debug_level" : DEBUG_LEVEL }) -l1_nic = l1cache.setSubComponent("cpulink", "memHierarchy.MemNIC") +l1_nic = l1cache.setSubComponent("highlink", "memHierarchy.MemNIC") l1_nic.addParams({"group" : 1, "network_bw" : "25GB/s"}) #l1_nic.addParams(debug_params) @@ -60,7 +60,7 @@ "clock" : "1GHz", "addr_range_end" : 512*1024*1024-1, }) -mem_nic = memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +mem_nic = memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") mem_nic.addParams({"group" : 2, "network_bw" : "25GB/s"}) #mem_nic.addParams(debug_params) diff --git a/src/sst/elements/memHierarchy/tests/testIncoherent.py b/src/sst/elements/memHierarchy/tests/testIncoherent.py index 9e8ec3e933..9809321fc8 100644 --- a/src/sst/elements/memHierarchy/tests/testIncoherent.py +++ b/src/sst/elements/memHierarchy/tests/testIncoherent.py @@ -72,8 +72,8 @@ # Define the simulation links link_cpu_l1cache_link = sst.Link("link_cpu_l1cache_link") -link_cpu_l1cache_link.connect( (iface, "port", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_l1cache_link.connect( (iface, "lowlink", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_l1cache_l2cache_link = sst.Link("link_l1cache_l2cache_link") -link_l1cache_l2cache_link.connect( (comp_l1cache, "low_network_0", "10000ps"), (comp_l2cache, "high_network_0", "1000ps") ) +link_l1cache_l2cache_link.connect( (comp_l1cache, "lowlink", "10000ps"), (comp_l2cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l2cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus_link.connect( (comp_l2cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testKingsley.py b/src/sst/elements/memHierarchy/tests/testKingsley.py index 3bae484c3c..4009c8cf18 100644 --- a/src/sst/elements/memHierarchy/tests/testKingsley.py +++ b/src/sst/elements/memHierarchy/tests/testKingsley.py @@ -202,7 +202,7 @@ def build(self, nodeID): membk.addParams({ "mem_size" : str(self.mem_capacity // 4) + "B" }) membk.addParams(ddr_backend_params) - memNIC = mem.setSubComponent("cpulink", "memHierarchy.MemNICFour") + memNIC = mem.setSubComponent("highlink", "memHierarchy.MemNICFour") memNIC.addParams(ddr_nic_params) memdata = memNIC.setSubComponent("data", "kingsley.linkcontrol") memreq = memNIC.setSubComponent("req", "kingsley.linkcontrol") @@ -258,7 +258,7 @@ def build(self, nodeID): "interleave_size" : "64B", }) # Create NIC on to interface to NoC from directory - dcNIC = dc.setSubComponent("cpulink", "memHierarchy.MemNICFour") + dcNIC = dc.setSubComponent("highlink", "memHierarchy.MemNICFour") dcNIC.addParams(dc_nic_params) dcdata = dcNIC.setSubComponent("data", "kingsley.linkcontrol") dcreq = dcNIC.setSubComponent("req", "kingsley.linkcontrol") @@ -289,10 +289,8 @@ def build(self, nodeID): # l2 prefetcher l2pre = tileL2cache.setSubComponent("prefetcher", "cassini.StridePrefetcher") l2pre.addParams(l2_prefetch_params) - # l2 bus link - l2tol1 = tileL2cache.setSubComponent("cpulink", "memHierarchy.MemLink") # l2 NIC - l2NIC = tileL2cache.setSubComponent("memlink", "memHierarchy.MemNICFour") + l2NIC = tileL2cache.setSubComponent("lowlink", "memHierarchy.MemNICFour") l2data = l2NIC.setSubComponent("data", "kingsley.linkcontrol") l2req = l2NIC.setSubComponent("req", "kingsley.linkcontrol") l2fwd = l2NIC.setSubComponent("fwd", "kingsley.linkcontrol") @@ -308,8 +306,8 @@ def build(self, nodeID): l2bus.addParams({ "bus_frequency" : core_clock }) l2busLink = sst.Link("l2bus_link_" + str(self.next_tile_id)) - l2busLink.connect( (l2bus, "low_network_0", mesh_link_latency), - (l2tol1, "port", mesh_link_latency)) + l2busLink.connect( (l2bus, "lowlink0", mesh_link_latency), + (tileL2cache, "highlink", mesh_link_latency)) l2busLink.setNoCut() self.next_tile_id = self.next_tile_id + 1 @@ -351,23 +349,23 @@ def build(self, nodeID): }) # Thread 0 - leftSMTCPUlink0 = sst.Link("smt_cpu_" + str(self.next_core_id)) - leftSMTCPUlink0.connect( (mirandaL0, "cache_link", mesh_link_latency), (leftSMT, "thread0", mesh_link_latency) ) + leftSMThighlink0 = sst.Link("smt_cpu_" + str(self.next_core_id)) + leftSMThighlink0.connect( (mirandaL0, "cache_link", mesh_link_latency), (leftSMT, "thread0", mesh_link_latency) ) # Thread 1 - leftSMTCPUlink1 = sst.Link("smt_cpu_" + str(self.next_core_id + 18)) - leftSMTCPUlink1.connect( (mirandaL1, "cache_link", mesh_link_latency), (leftSMT, "thread1", mesh_link_latency) ) + leftSMThighlink1 = sst.Link("smt_cpu_" + str(self.next_core_id + 18)) + leftSMThighlink1.connect( (mirandaL1, "cache_link", mesh_link_latency), (leftSMT, "thread1", mesh_link_latency) ) # SMT Shim <-> L1 leftSMTL1link = sst.Link("l1cache_smt_" + str(self.next_core_id)) - leftSMTL1link.connect( (leftSMT, "cache", mesh_link_latency), (tileLeftL1, "high_network_0", mesh_link_latency) ) + leftSMTL1link.connect( (leftSMT, "cache", mesh_link_latency), (tileLeftL1, "highlink", mesh_link_latency) ) - leftSMTCPUlink0.setNoCut() - leftSMTCPUlink1.setNoCut() + leftSMThighlink0.setNoCut() + leftSMThighlink1.setNoCut() leftSMTL1link.setNoCut() leftL1L2link = sst.Link("l1cache_link_" + str(self.next_core_id)) - leftL1L2link.connect( (l2bus, "high_network_0", mesh_link_latency), - (tileLeftL1, "low_network_0", mesh_link_latency)) + leftL1L2link.connect( (l2bus, "highlink0", mesh_link_latency), + (tileLeftL1, "lowlink", mesh_link_latency)) leftL1L2link.setNoCut() self.next_core_id = self.next_core_id + 1 @@ -409,22 +407,22 @@ def build(self, nodeID): }) # Thread 0 - rightSMTCPUlink0 = sst.Link("smt_cpu_" + str(self.next_core_id)) - rightSMTCPUlink0.connect( (mirandaR0, "cache_link", mesh_link_latency), (rightSMT, "thread0", mesh_link_latency) ) + rightSMThighlink0 = sst.Link("smt_cpu_" + str(self.next_core_id)) + rightSMThighlink0.connect( (mirandaR0, "cache_link", mesh_link_latency), (rightSMT, "thread0", mesh_link_latency) ) # Thread 1 - rightSMTCPUlink1 = sst.Link("smt_cpu_" + str(self.next_core_id + 18)) - rightSMTCPUlink1.connect( (mirandaR1, "cache_link", mesh_link_latency), (rightSMT, "thread1", mesh_link_latency) ) + rightSMThighlink1 = sst.Link("smt_cpu_" + str(self.next_core_id + 18)) + rightSMThighlink1.connect( (mirandaR1, "cache_link", mesh_link_latency), (rightSMT, "thread1", mesh_link_latency) ) # SMT Shim <-> L1 rightSMTL1link = sst.Link("l1cache_smt_" + str(self.next_core_id)) - rightSMTL1link.connect( (rightSMT, "cache", mesh_link_latency), (tileRightL1, "high_network_0", mesh_link_latency) ) + rightSMTL1link.connect( (rightSMT, "cache", mesh_link_latency), (tileRightL1, "highlink", mesh_link_latency) ) - rightSMTCPUlink0.setNoCut() - rightSMTCPUlink1.setNoCut() + rightSMThighlink0.setNoCut() + rightSMThighlink1.setNoCut() rightSMTL1link.setNoCut() rightL1L2link = sst.Link("l1cache_link_" + str(self.next_core_id)) - rightL1L2link.connect( (l2bus, "high_network_1", mesh_link_latency), - (tileRightL1, "low_network_0", mesh_link_latency)) + rightL1L2link.connect( (l2bus, "highlink1", mesh_link_latency), + (tileRightL1, "lowlink", mesh_link_latency)) rightL1L2link.setNoCut() self.next_core_id = self.next_core_id + 1 diff --git a/src/sst/elements/memHierarchy/tests/testMemoryCache.py b/src/sst/elements/memHierarchy/tests/testMemoryCache.py index 6c1ebb2be6..43ca514981 100644 --- a/src/sst/elements/memHierarchy/tests/testMemoryCache.py +++ b/src/sst/elements/memHierarchy/tests/testMemoryCache.py @@ -230,7 +230,7 @@ def build(self, nodeID): }) # Define DDR NIC - mlink = mem.setSubComponent("cpulink", "memHierarchy.MemNICFour") + mlink = mem.setSubComponent("highlink", "memHierarchy.MemNICFour") data = mlink.setSubComponent("data", "kingsley.linkcontrol") req = mlink.setSubComponent("req", "kingsley.linkcontrol") fwd = mlink.setSubComponent("fwd", "kingsley.linkcontrol") @@ -279,7 +279,7 @@ def build(self, nodeID): }) # Define DC NIC - dclink = dc.setSubComponent("cpulink", "memHierarchy.MemNICFour") + dclink = dc.setSubComponent("highlink", "memHierarchy.MemNICFour") data = dclink.setSubComponent("data", "kingsley.linkcontrol") req = dclink.setSubComponent("req", "kingsley.linkcontrol") fwd = dclink.setSubComponent("fwd", "kingsley.linkcontrol") @@ -313,7 +313,7 @@ def build(self, nodeID): membk.addParams(hbm_td_backend_params) membk.addParams({ "mem_size" : str(self.memCapacity // self.hbm_count) + "B" }) - memLink = sst.Link("hbm_link_" + str(self.next_hbm_id)) + lowlink = sst.Link("hbm_link_" + str(self.next_hbm_id)) mem.addParams({ "num_caches" : self.hbm_count, @@ -321,7 +321,7 @@ def build(self, nodeID): }) # Define HBM NIC - mlink = mem.setSubComponent("cpulink", "memHierarchy.MemNICFour") + mlink = mem.setSubComponent("highlink", "memHierarchy.MemNICFour") data = mlink.setSubComponent("data", "kingsley.linkcontrol") req = mlink.setSubComponent("req", "kingsley.linkcontrol") fwd = mlink.setSubComponent("fwd", "kingsley.linkcontrol") @@ -351,8 +351,7 @@ def build(self, nodeID): tileL2cache.addParams(l2_prefetch_params) # Define L2 NIC - l2clink = tileL2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2mlink = tileL2cache.setSubComponent("memlink", "memHierarchy.MemNICFour") + l2mlink = tileL2cache.setSubComponent("lowlink", "memHierarchy.MemNICFour") l2data = l2mlink.setSubComponent("data", "kingsley.linkcontrol") l2req = l2mlink.setSubComponent("req", "kingsley.linkcontrol") l2fwd = l2mlink.setSubComponent("fwd", "kingsley.linkcontrol") @@ -371,7 +370,7 @@ def build(self, nodeID): }) l2busLink = sst.Link("l2bus_link_" + str(self.next_tile_id)) - l2busLink.connect( (l2bus, "low_network_0", mesh_link_latency), (l2clink, "port", mesh_link_latency)) + l2busLink.connect( (l2bus, "lowlink0", mesh_link_latency), (tileL2cache, "highlink", mesh_link_latency)) l2busLink.setNoCut() # L1s @@ -384,8 +383,8 @@ def build(self, nodeID): print("Creating core " + str(self.next_core_id) + " on tile: " + str(self.next_tile_id) + "...") leftL1L2link = sst.Link("l1cache_link_" + str(self.next_core_id)) - leftL1L2link.connect( (l2bus, "high_network_0", mesh_link_latency), - (tileLeftL1, "low_network_0", mesh_link_latency)) + leftL1L2link.connect( (l2bus, "highlink0", mesh_link_latency), + (tileLeftL1, "lowlink", mesh_link_latency)) leftL1L2link.setNoCut() leftCore = sst.Component("core_" + str(self.next_core_id), "miranda.BaseCPU") @@ -399,7 +398,7 @@ def build(self, nodeID): }) leftCoreL1link = sst.Link("core_link_" + str(self.next_core_id)) - leftCoreL1link.connect( (leftCore, "cache_link", mesh_link_latency), (tileLeftL1, "high_network_0", mesh_link_latency) ) + leftCoreL1link.connect( (leftCore, "cache_link", mesh_link_latency), (tileLeftL1, "highlink", mesh_link_latency) ) leftCoreL1link.setNoCut() self.next_core_id = self.next_core_id + 1 @@ -418,15 +417,15 @@ def build(self, nodeID): }) rightCoreL1link = sst.Link("core_link_" + str(self.next_core_id)) - rightCoreL1link.connect( (rightCore, "cache_link", mesh_link_latency), (tileRightL1, "high_network_0", mesh_link_latency) ) + rightCoreL1link.connect( (rightCore, "cache_link", mesh_link_latency), (tileRightL1, "highlink", mesh_link_latency) ) rightCoreL1link.setNoCut() if not quiet: print("Creating core " + str(self.next_core_id) + " on tile: " + str(self.next_tile_id) + "...") rightL1L2link = sst.Link("l1cache_link_" + str(self.next_core_id)) - rightL1L2link.connect( (l2bus, "high_network_1", mesh_link_latency), - (tileRightL1, "low_network_0", mesh_link_latency)) + rightL1L2link.connect( (l2bus, "highlink1", mesh_link_latency), + (tileRightL1, "lowlink", mesh_link_latency)) rightL1L2link.setNoCut() self.next_core_id = self.next_core_id + 1 diff --git a/src/sst/elements/memHierarchy/tests/testNoninclusive-1.py b/src/sst/elements/memHierarchy/tests/testNoninclusive-1.py index a6102c37b1..d846531a05 100644 --- a/src/sst/elements/memHierarchy/tests/testNoninclusive-1.py +++ b/src/sst/elements/memHierarchy/tests/testNoninclusive-1.py @@ -73,8 +73,7 @@ # MemNIC parameters }) - l2tl1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2nic = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2nic = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2nic.addParams({ "group" : 1, "network_bw" : network_bw, @@ -83,10 +82,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (comp_l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (comp_l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (comp_l1cache, "low_network_0", "100ps"), (l2tl1, "port", "100ps") ) + l1_l2_link.connect( (comp_l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2nic, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -107,7 +106,7 @@ "slice_id" : x, }) - l3nic = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3nic.addParams({ "group" : 2, "network_bw" : network_bw, @@ -131,8 +130,7 @@ "interleave_size" : "64B", # Interleave at line granularity between memories "interleave_step" : str(memories * 64) + "B", }) - dirNic = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") + dirNic = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirNic.addParams({ "group" : 3, "network_input_buffer_size" : "2KiB", @@ -167,7 +165,7 @@ link_directory_network.connect( (dirNic, "port", "100ps"), (comp_network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testNoninclusive-2.py b/src/sst/elements/memHierarchy/tests/testNoninclusive-2.py index ba8c5a8d5c..eb8d9475d3 100644 --- a/src/sst/elements/memHierarchy/tests/testNoninclusive-2.py +++ b/src/sst/elements/memHierarchy/tests/testNoninclusive-2.py @@ -83,8 +83,7 @@ "debug_level" : DEBUG_LEV, }) - l2tl1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2nic = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2nic = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2nic.addParams({ "group" : 1, "network_bw" : network_bw, @@ -93,10 +92,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (comp_l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (comp_l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (comp_l1cache, "low_network_0", "100ps"), (l2tl1, "port", "100ps") ) + l1_l2_link.connect( (comp_l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2nic, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -121,7 +120,7 @@ "debug" : DEBUG_L3, "debug_level" : DEBUG_LEV, }) - l3nic = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3nic.addParams({ "group" : 2, "network_bw" : network_bw, @@ -147,8 +146,7 @@ "debug" : DEBUG_DIR, "debug_level" : DEBUG_LEV, }) - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") - dirnic = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirnic = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirnic.addParams({ "group" : 3, "network_bw" : network_bw, @@ -184,7 +182,7 @@ link_directory_network.connect( (dirnic, "port", "100ps"), (comp_network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testPrefetchParams.py b/src/sst/elements/memHierarchy/tests/testPrefetchParams.py index 5aeafd76d3..a559017d95 100644 --- a/src/sst/elements/memHierarchy/tests/testPrefetchParams.py +++ b/src/sst/elements/memHierarchy/tests/testPrefetchParams.py @@ -82,8 +82,7 @@ "debug_level" : 10, }) l2cache.setSubComponent("prefetcher", "cassini.NextBlockPrefetcher") - l2tl1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2nic = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2nic = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2nic.addParams({ "group" : 1, "network_bw" : network_bw, @@ -92,10 +91,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (l1cache, "low_network_0", "100ps"), (l2tl1, "port", "100ps") ) + l1_l2_link.connect( (l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2nic, "port", "100ps"), (network, "port" + str(x), "100ps") ) @@ -120,7 +119,7 @@ #"debug_addr" : "[1152]", "debug_level" : 10, }) - l3nic = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3nic.addParams({ "group" : 2, "network_bw" : network_bw, @@ -147,8 +146,7 @@ #"debug_addr" : "[1152]", "debug_level" : 10, }) - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") - dirnic = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirnic = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirnic.addParams({ "group" : 3, "network_bw" : network_bw, @@ -182,7 +180,7 @@ link_directory_network.connect( (dirnic, "port", "100ps"), (network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testRangeCheck.py b/src/sst/elements/memHierarchy/tests/testRangeCheck.py index 8fc16ba6c3..ed06275d13 100644 --- a/src/sst/elements/memHierarchy/tests/testRangeCheck.py +++ b/src/sst/elements/memHierarchy/tests/testRangeCheck.py @@ -57,7 +57,7 @@ def __init__(self, cpu_num): }) # connect CPU to L1 self.link_cpu_l1 = sst.Link(f"link_cpu_l1_{cpu_num}") - self.link_cpu_l1.connect( (self.comp, "cache_link", "1ns"), (self.l1, "high_network_0", "1ns") ) + self.link_cpu_l1.connect( (self.comp, "cache_link", "1ns"), (self.l1, "highlink", "1ns") ) class CPU_COMPLEX(): @@ -89,11 +89,8 @@ def __init__(self,node): "mshr_latency_cycles" : 16 }) - # L2 Cache interface to cpu bus - self.cpulink = self.l2cache.setSubComponent("cpulink","memHierarchy.MemLink") - # L2 Cache interface to nic - self.nic = self.l2cache.setSubComponent("memlink","memHierarchy.MemNIC") + self.nic = self.l2cache.setSubComponent("lowlink","memHierarchy.MemNIC") self.nic.addParams({ "group" : cpu_group, "network_bw" : "8800GiB/s", @@ -105,16 +102,16 @@ def __init__(self,node): # Connect cpubus to L2 self.link_cpubus_l2 = sst.Link("link_cpubus_l2") self.link_cpubus_l2.connect( - (self.cpubus, "low_network_0", "1ns"), - (self.cpulink, "port", "1ns") ) + (self.cpubus, "lowlink0", "1ns"), + (self.l2cache, "highlink", "1ns") ) # Connect CPUs (L1) to cpubus self.link_l1_cpubus = [] for i in range(NUM_CPUS): self.link_l1_cpubus.append(sst.Link(f"link_l1_{i}_cpubus")) self.link_l1_cpubus[i].connect( - (self.cpu[i].l1, "low_network_0", "1ns"), - (self.cpubus, f"high_network_{i}", "1ns") + (self.cpu[i].l1, "lowlink", "1ns"), + (self.cpubus, f"highlink{i}", "1ns") ) class NODE(): @@ -160,7 +157,7 @@ def __init__(self,node): }) # The memory controller NIC - self.memNIC = self.memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") + self.memNIC = self.memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") self.memNIC.addParams({ "group" : node_group, "sources" : [cpu_group, node_group], diff --git a/src/sst/elements/memHierarchy/tests/testScratchCache-1.py b/src/sst/elements/memHierarchy/tests/testScratchCache-1.py index d7c9136b8a..84d1480b1f 100644 --- a/src/sst/elements/memHierarchy/tests/testScratchCache-1.py +++ b/src/sst/elements/memHierarchy/tests/testScratchCache-1.py @@ -52,8 +52,6 @@ "associativity" : 4, "replacement_policy" : "lru", }) -# The L1 uses default (direct) links to the CPU and scratchpad, so we don't explicitly specify their type -# (e.g., MemLink or MemNIC) ####################################################################################################################### ####################################################################################################################### @@ -75,11 +73,8 @@ scratch0_backend = scratch0_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch0_backend.addParam("access_time", "10ns") -# Scratchpad0 uses a MemLink on its link towards the CPU -scratch0_link_cpu = comp_scratch0.setSubComponent("cpulink", "memHierarchy.MemLink") - # Scratchpad0 uses a MemNIC on its link towards the lower memory system -scratch0_link_mem = comp_scratch0.setSubComponent("memlink", "memHierarchy.MemNIC") +scratch0_link_mem = comp_scratch0.setSubComponent("lowlink", "memHierarchy.MemNIC") scratch0_link_mem.addParam("network_bw", "50GB/s") # We put scratchpads in group 0 and memories in group 1 so that routing is (scratchpads -> memories) scratch0_link_mem.addParam("group", "0") # Sources are 'group - 1' and destinations are 'group + 1' @@ -148,11 +143,8 @@ scratch1_backend = scratch1_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch1_backend.addParam("access_time", "10ns") -# Scratchpad1 uses a MemLink on its link towards the CPU -scratch1_link_cpu = comp_scratch1.setSubComponent("cpulink", "memHierarchy.MemLink") - # Scratchpad1 uses a MemNIC on its link towards the lower memory system -scratch1_link_mem = comp_scratch1.setSubComponent("memlink", "memHierarchy.MemNIC") +scratch1_link_mem = comp_scratch1.setSubComponent("lowlink", "memHierarchy.MemNIC") scratch1_link_mem.addParam("network_bw", "50GB/s") # We put scratchpads in group 0 and memories in group 1 so that routing is (scratchpads -> memories) scratch1_link_mem.addParam("group", "0") # Sources are 'group - 1' and destinations are 'group + 1' @@ -203,7 +195,7 @@ }) # The memory sits directly on the NoC so it uses a MemNIC on its link -memNIC0 = memctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") +memNIC0 = memctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") memNIC0.addParam("network_bw", "50GB/s") # The source for the memory is the scratchpads (group 0) so we are group 0 + 1 = 1 memNIC0.addParam("group", "1") # Sources are 'group - 1' and destinations are 'group + 1' @@ -234,7 +226,7 @@ }) # The memory sits directly on the NoC so it uses a MemNIC on its link -memNIC1 = memctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") +memNIC1 = memctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") memNIC1.addParam("network_bw", "50GB/s") # The source for the memory is the scratchpads (group 0) so we are group 0 + 1 = 1 memNIC1.addParam("group", "1") # Sources are 'group - 1' and destinations are 'group + 1' @@ -257,16 +249,16 @@ ####################################################################################################################### # Connect CPU0 to L1_0 link_cpu0_l1 = sst.Link("link_cpu0_l1") -link_cpu0_l1.connect( (iface0, "port", "100ps"), (comp_l1_0, "high_network_0", "100ps") ) +link_cpu0_l1.connect( (iface0, "lowlink", "100ps"), (comp_l1_0, "highlink", "100ps") ) # Connect CPU1 to L1_1 link_cpu1_l1 = sst.Link("link_cpu1_l1") -link_cpu1_l1.connect( (iface1, "port", "100ps"), (comp_l1_1, "high_network_0", "100ps") ) +link_cpu1_l1.connect( (iface1, "lowlink", "100ps"), (comp_l1_1, "highlink", "100ps") ) # Connect L1_0 to Scratchpad0 link_l1_scratch0 = sst.Link("link_cpu0_scratch0") -link_l1_scratch0.connect( (comp_l1_0, "low_network_0", "100ps"), (scratch0_link_cpu, "port", "100ps") ) +link_l1_scratch0.connect( (comp_l1_0, "lowlink", "100ps"), (comp_scratch0, "highlink", "100ps") ) # Connect L1_1 to Scratchpad1 link_l1_scratch1 = sst.Link("link_cpu1_scratch1") -link_l1_scratch1.connect( (comp_l1_1, "low_network_0", "100ps"), (scratch1_link_cpu, "port", "100ps") ) +link_l1_scratch1.connect( (comp_l1_1, "lowlink", "100ps"), (comp_scratch1, "highlink", "100ps") ) # Connect Scratch0's MemNIC to network link_scratch0_net = sst.Link("link_scratch0_net") link_scratch0_net.connect( (scratch0_link_mem, "port", "100ps"), (comp_net, "port0", "100ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testScratchCache-2.py b/src/sst/elements/memHierarchy/tests/testScratchCache-2.py index dcee1a9ddd..317f438819 100644 --- a/src/sst/elements/memHierarchy/tests/testScratchCache-2.py +++ b/src/sst/elements/memHierarchy/tests/testScratchCache-2.py @@ -63,8 +63,7 @@ scratch0_conv = comp_scratch0.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch0_back = scratch0_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch0_back.addParam("access_time", "10ns") -scratchlink0 = comp_scratch0.setSubComponent("cpulink", "memHierarchy.MemLink") -scratchnic0 = comp_scratch0.setSubComponent("memlink", "memHierarchy.MemNIC") +scratchnic0 = comp_scratch0.setSubComponent("lowlink", "memHierarchy.MemNIC") scratchnic0.addParams({ "network_bw" : "50GB/s", "group" : 0, @@ -124,8 +123,7 @@ scratch1_conv = comp_scratch1.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch1_back = scratch1_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch1_back.addParam("access_time", "10ns") -scratchlink1 = comp_scratch1.setSubComponent("cpulink", "memHierarchy.MemLink") -scratchnic1 = comp_scratch1.setSubComponent("memlink", "memHierarchy.MemNIC") +scratchnic1 = comp_scratch1.setSubComponent("lowlink", "memHierarchy.MemNIC") scratchnic1.addParams({ "network_bw" : "50GB/s", "group" : 0, @@ -159,7 +157,7 @@ "access_time" : "50ns", "mem_size" : "512MiB" }) -memnic0 = memctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic0 = memctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") memnic0.addParams({ "network_bw" : "50GB/s", "group" : 1, @@ -180,7 +178,7 @@ "access_time" : "50ns", "mem_size" : "512MiB" }) -memnic1 = memctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic1 = memctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") memnic1.addParams({ "network_bw" : "50GB/s", "group" : 1, @@ -195,17 +193,17 @@ # Define the simulation links link_cpu0_l1 = sst.Link("link_cpu0_l1") -link_cpu0_l1.connect( (iface0, "port", "100ps"), (comp_l1_0, "high_network_0", "100ps") ) +link_cpu0_l1.connect( (iface0, "lowlink", "100ps"), (comp_l1_0, "highlink", "100ps") ) link_cpu1_l1 = sst.Link("link_cpu1_l1") -link_cpu1_l1.connect( (iface1, "port", "100ps"), (comp_l1_1, "high_network_0", "100ps") ) +link_cpu1_l1.connect( (iface1, "lowlink", "100ps"), (comp_l1_1, "highlink", "100ps") ) link_l1_l2_0 = sst.Link("link_l1_l2_0") -link_l1_l2_0.connect( (comp_l1_0, "low_network_0", "100ps"), (comp_l2_0, "high_network_0", "100ps") ) +link_l1_l2_0.connect( (comp_l1_0, "lowlink", "100ps"), (comp_l2_0, "highlink", "100ps") ) link_l1_l2_1 = sst.Link("link_l1_l2_1") -link_l1_l2_1.connect( (comp_l1_1, "low_network_0", "100ps"), (comp_l2_1, "high_network_0", "100ps") ) +link_l1_l2_1.connect( (comp_l1_1, "lowlink", "100ps"), (comp_l2_1, "highlink", "100ps") ) link_l2_scratch0 = sst.Link("link_cpu0_scratch0") -link_l2_scratch0.connect( (comp_l2_0, "low_network_0", "100ps"), (scratchlink0, "port", "100ps") ) +link_l2_scratch0.connect( (comp_l2_0, "lowlink", "100ps"), (comp_scratch0, "highlink", "100ps") ) link_l2_scratch1 = sst.Link("link_cpu1_scratch1") -link_l2_scratch1.connect( (comp_l2_1, "low_network_0", "100ps"), (scratchlink1, "port", "100ps") ) +link_l2_scratch1.connect( (comp_l2_1, "lowlink", "100ps"), (comp_scratch1, "highlink", "100ps") ) link_scratch0_net = sst.Link("link_scratch0_net") link_scratch0_net.connect( (scratchnic0, "port", "100ps"), (comp_net, "port0", "100ps") ) link_scratch1_net = sst.Link("link_scratch1_net") diff --git a/src/sst/elements/memHierarchy/tests/testScratchCache-3.py b/src/sst/elements/memHierarchy/tests/testScratchCache-3.py index 34fbc20d49..7145b4394a 100644 --- a/src/sst/elements/memHierarchy/tests/testScratchCache-3.py +++ b/src/sst/elements/memHierarchy/tests/testScratchCache-3.py @@ -77,8 +77,7 @@ scratch0_conv = comp_scratch0.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch0_back = scratch0_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch0_back.addParam("access_time", "10ns") -scratchlink0 = comp_scratch0.setSubComponent("cpulink", "memHierarchy.MemLink") -scratchnic0 = comp_scratch0.setSubComponent("memlink", "memHierarchy.MemNIC") +scratchnic0 = comp_scratch0.setSubComponent("lowlink", "memHierarchy.MemNIC") scratchnic0.addParams({ "network_bw" : "50GB/s", "group" : 0 @@ -153,8 +152,7 @@ scratch1_conv = comp_scratch1.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch1_back = scratch1_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch1_back.addParam("access_time", "10ns") -scratchlink1 = comp_scratch1.setSubComponent("cpulink", "memHierarchy.MemLink") -scratchnic1 = comp_scratch1.setSubComponent("memlink", "memHierarchy.MemNIC") +scratchnic1 = comp_scratch1.setSubComponent("lowlink", "memHierarchy.MemNIC") scratchnic1.addParams({ "network_bw" : "50GB/s", "group" : 0 @@ -188,7 +186,7 @@ "access_time" : "50ns", "mem_size" : "512MiB", }) -memnic0 = memctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic0 = memctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") memnic0.addParam("network_bw", "50GB/s") memnic0.addParam("group", "1") @@ -207,7 +205,7 @@ "access_time" : "50ns", "mem_size" : "512MiB", }) -memnic1 = memctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic1 = memctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") memnic1.addParam("network_bw", "50GB/s") memnic1.addParam("group", "1") @@ -221,21 +219,21 @@ # Define the simulation links link_cpu0_l1 = sst.Link("link_cpu0_l1") -link_cpu0_l1.connect( (iface0, "port", "100ps"), (comp_l1_0, "high_network_0", "100ps") ) +link_cpu0_l1.connect( (iface0, "lowlink", "100ps"), (comp_l1_0, "highlink", "100ps") ) link_cpu1_l1 = sst.Link("link_cpu1_l1") -link_cpu1_l1.connect( (iface1, "port", "100ps"), (comp_l1_1, "high_network_0", "100ps") ) +link_cpu1_l1.connect( (iface1, "lowlink", "100ps"), (comp_l1_1, "highlink", "100ps") ) link_l1_l2_0 = sst.Link("link_l1_l2_0") -link_l1_l2_0.connect( (comp_l1_0, "low_network_0", "100ps"), (comp_l2_0, "high_network_0", "100ps") ) +link_l1_l2_0.connect( (comp_l1_0, "lowlink", "100ps"), (comp_l2_0, "highlink", "100ps") ) link_l1_l2_1 = sst.Link("link_l1_l2_1") -link_l1_l2_1.connect( (comp_l1_1, "low_network_0", "100ps"), (comp_l2_1, "high_network_0", "100ps") ) +link_l1_l2_1.connect( (comp_l1_1, "lowlink", "100ps"), (comp_l2_1, "highlink", "100ps") ) link_l2_l3_0 = sst.Link("link_l2_l3_0") -link_l2_l3_0.connect( (comp_l2_0, "low_network_0", "100ps"), (l3_0, "high_network_0", "100ps") ) +link_l2_l3_0.connect( (comp_l2_0, "lowlink", "100ps"), (l3_0, "highlink", "100ps") ) link_l2_l3_1 = sst.Link("link_l2_l3_1") -link_l2_l3_1.connect( (comp_l2_1, "low_network_0", "100ps"), (l3_1, "high_network_0", "100ps") ) +link_l2_l3_1.connect( (comp_l2_1, "lowlink", "100ps"), (l3_1, "highlink", "100ps") ) link_l2_scratch0 = sst.Link("link_cpu0_scratch0") -link_l2_scratch0.connect( (l3_0, "low_network_0", "100ps"), (scratchlink0, "port", "100ps") ) +link_l2_scratch0.connect( (l3_0, "lowlink", "100ps"), (comp_scratch0, "highlink", "100ps") ) link_l2_scratch1 = sst.Link("link_cpu1_scratch1") -link_l2_scratch1.connect( (l3_1, "low_network_0", "100ps"), (scratchlink1, "port", "100ps") ) +link_l2_scratch1.connect( (l3_1, "lowlink", "100ps"), (comp_scratch1, "highlink", "100ps") ) link_scratch0_net = sst.Link("link_scratch0_net") link_scratch0_net.connect( (scratchnic0, "port", "100ps"), (comp_net, "port0", "100ps") ) link_scratch1_net = sst.Link("link_scratch1_net") diff --git a/src/sst/elements/memHierarchy/tests/testScratchCache-4.py b/src/sst/elements/memHierarchy/tests/testScratchCache-4.py index face28cfbf..4b60146695 100644 --- a/src/sst/elements/memHierarchy/tests/testScratchCache-4.py +++ b/src/sst/elements/memHierarchy/tests/testScratchCache-4.py @@ -86,8 +86,7 @@ "associativity" : 8, "replacement_policy" : "mru", }) -l2_link_0 = comp_l2_0.setSubComponent("cpulink", "memHierarchy.MemLink") -l2_nic_0 = comp_l2_0.setSubComponent("memlink", "memHierarchy.MemNIC") +l2_nic_0 = comp_l2_0.setSubComponent("lowlink", "memHierarchy.MemNIC") l2_nic_0.addParams({ "network_bw" : "80GiB/s", "group" : 1, @@ -162,8 +161,7 @@ "associativity" : 8, "replacement_policy" : "nmru", }) -l2_link_1 = comp_l2_1.setSubComponent("cpulink", "memHierarchy.MemLink") -l2_nic_1 = comp_l2_1.setSubComponent("memlink", "memHierarchy.MemNIC") +l2_nic_1 = comp_l2_1.setSubComponent("lowlink", "memHierarchy.MemNIC") l2_nic_1.addParams({ "network_bw" : "80GiB/s", "group" : 1, @@ -177,7 +175,7 @@ "coherence_protocol" : "MESI", "addr_range_start" : 0, }) -dir_nic = comp_dir.setSubComponent("cpulink", "memHierarchy.MemNIC") +dir_nic = comp_dir.setSubComponent("highlink", "memHierarchy.MemNIC") dir_nic.addParams({ "network_bw" : "80GiB/s", "group" : 2, @@ -196,7 +194,7 @@ conv = scratch.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch_backend = conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch_backend.addParam("access_time", "10ns") -scratch_nic = scratch.setSubComponent("cpulink", "memHierarchy.MemNIC") +scratch_nic = scratch.setSubComponent("highlink", "memHierarchy.MemNIC") scratch_nic.addParams({ "network_bw" : "50GB/s", "group" : 3, @@ -227,7 +225,7 @@ "interleave_step" : "256B", }) -memnic0 = memctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic0 = memctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") memnic0.addParams({ "network_bw" : "50GB/s", "group" : 4, @@ -251,7 +249,7 @@ "interleave_step" : "256B", }) -memnic1 = memctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic1 = memctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") memnic1.addParams({ "network_bw" : "50GB/s", "group" : 4, @@ -285,34 +283,34 @@ # Define the simulation links link_cpu0_l1 = sst.Link("link_cpu0_l1") -link_cpu0_l1.connect( (iface0, "port", "100ps"), (comp_l1_0, "high_network_0", "100ps") ) +link_cpu0_l1.connect( (iface0, "lowlink", "100ps"), (comp_l1_0, "highlink", "100ps") ) link_cpu1_l1 = sst.Link("link_cpu1_l1") -link_cpu1_l1.connect( (iface1, "port", "100ps"), (comp_l1_1, "high_network_0", "100ps") ) +link_cpu1_l1.connect( (iface1, "lowlink", "100ps"), (comp_l1_1, "highlink", "100ps") ) link_cpu2_l1 = sst.Link("link_cpu2_l1") -link_cpu2_l1.connect( (iface2, "port", "100ps"), (comp_l1_2, "high_network_0", "100ps") ) +link_cpu2_l1.connect( (iface2, "lowlink", "100ps"), (comp_l1_2, "highlink", "100ps") ) link_cpu3_l1 = sst.Link("link_cpu3_l1") -link_cpu3_l1.connect( (iface3, "port", "100ps"), (comp_l1_3, "high_network_0", "100ps") ) +link_cpu3_l1.connect( (iface3, "lowlink", "100ps"), (comp_l1_3, "highlink", "100ps") ) link_cpu0_bus = sst.Link("link_cpu0_bus") -link_cpu0_bus.connect( (comp_l1_0, "low_network_0", "100ps"), (comp_bus_0, "high_network_0", "100ps") ) +link_cpu0_bus.connect( (comp_l1_0, "lowlink", "100ps"), (comp_bus_0, "highlink0", "100ps") ) link_cpu1_bus = sst.Link("link_cpu1_bus") -link_cpu1_bus.connect( (comp_l1_1, "low_network_0", "100ps"), (comp_bus_0, "high_network_1", "100ps") ) +link_cpu1_bus.connect( (comp_l1_1, "lowlink", "100ps"), (comp_bus_0, "highlink1", "100ps") ) link_cpu2_bus = sst.Link("link_cpu2_bus") -link_cpu2_bus.connect( (comp_l1_2, "low_network_0", "100ps"), (comp_bus_1, "high_network_0", "100ps") ) +link_cpu2_bus.connect( (comp_l1_2, "lowlink", "100ps"), (comp_bus_1, "highlink0", "100ps") ) link_cpu3_bus = sst.Link("link_cpu3_bus") -link_cpu3_bus.connect( (comp_l1_3, "low_network_0", "100ps"), (comp_bus_1, "high_network_1", "100ps") ) +link_cpu3_bus.connect( (comp_l1_3, "lowlink", "100ps"), (comp_bus_1, "highlink1", "100ps") ) link_bus_l2_0 = sst.Link("link_bus_l2_0") -link_bus_l2_0.connect( (comp_bus_0, "low_network_0", "100ps"), (l2_link_0, "port", "100ps") ) +link_bus_l2_0.connect( (comp_bus_0, "lowlink0", "100ps"), (comp_l2_0, "highlink", "100ps") ) link_bus_l2_1 = sst.Link("link_bus_l2_1") -link_bus_l2_1.connect( (comp_bus_1, "low_network_0", "100ps"), (l2_link_1, "port", "100ps") ) +link_bus_l2_1.connect( (comp_bus_1, "lowlink0", "100ps"), (comp_l2_1, "highlink", "100ps") ) link_l2_net0 = sst.Link("link_l2_net_0") link_l2_net0.connect( (l2_nic_0, "port", "100ps"), (comp_net, "port0", "100ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testScratchDirect.py b/src/sst/elements/memHierarchy/tests/testScratchDirect.py index 412f8bfbcf..903317bc20 100644 --- a/src/sst/elements/memHierarchy/tests/testScratchDirect.py +++ b/src/sst/elements/memHierarchy/tests/testScratchDirect.py @@ -60,6 +60,6 @@ # Define the simulation links link_cpu_scratch = sst.Link("link_cpu_scratch") -link_cpu_scratch.connect( (iface, "port", "1000ps"), (comp_scratch, "cpu", "1000ps") ) +link_cpu_scratch.connect( (iface, "lowlink", "1000ps"), (comp_scratch, "highlink", "1000ps") ) link_scratch_mem = sst.Link("link_scratch_mem") -link_scratch_mem.connect( (comp_scratch, "memory", "100ps"), (memctrl, "direct_link", "100ps") ) +link_scratch_mem.connect( (comp_scratch, "lowlink", "100ps"), (memctrl, "highlink", "100ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testScratchNetwork.py b/src/sst/elements/memHierarchy/tests/testScratchNetwork.py index 3e366a0860..0f3d90e5bc 100644 --- a/src/sst/elements/memHierarchy/tests/testScratchNetwork.py +++ b/src/sst/elements/memHierarchy/tests/testScratchNetwork.py @@ -35,8 +35,7 @@ scratch0_conv = comp_scratch0.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch0_back = scratch0_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch0_back.addParams({"access_time" : "10ns"}) -scratch0_link = comp_scratch0.setSubComponent("cpulink", "memHierarchy.MemLink") -scratch0_nic = comp_scratch0.setSubComponent("memlink", "memHierarchy.MemNIC") +scratch0_nic = comp_scratch0.setSubComponent("lowlink", "memHierarchy.MemNIC") scratch0_nic.addParams({"network_bw" : "50GB/s", "group" : 0}) comp_cpu1 = sst.Component("core1", "memHierarchy.ScratchCPU") @@ -67,8 +66,7 @@ scratch1_conv = comp_scratch1.setSubComponent("backendConvertor", "memHierarchy.simpleMemScratchBackendConvertor") scratch1_back = scratch1_conv.setSubComponent("backend", "memHierarchy.simpleMem") scratch1_back.addParams({"access_time" : "10ns"}) -scratch1_link = comp_scratch1.setSubComponent("cpulink", "memHierarchy.MemLink") -scratch1_nic = comp_scratch1.setSubComponent("memlink", "memHierarchy.MemNIC") +scratch1_nic = comp_scratch1.setSubComponent("lowlink", "memHierarchy.MemNIC") scratch1_nic.addParams({"network_bw" : "50GB/s", "group" : 0}) comp_net = sst.Component("network", "merlin.hr_router") @@ -100,7 +98,7 @@ "access_time" : "75ns", "mem_size" : "512MiB", }) -memnic0 = memctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic0 = memctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") memnic0.addParams({ "network_bw" : "50GB/s", "group" : 1 @@ -123,7 +121,7 @@ "access_time" : "75ns", "mem_size" : "512MiB", }) -memnic1 = memctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") +memnic1 = memctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") memnic1.addParams({ "network_bw" : "50GB/s", "group" : 1 @@ -138,9 +136,9 @@ # Define the simulation links link_cpu0_scratch0 = sst.Link("link_cpu0_scratch0") -link_cpu0_scratch0.connect( (iface0, "port", "1000ps"), (scratch0_link, "port", "1000ps") ) +link_cpu0_scratch0.connect( (iface0, "lowlink", "1000ps"), (comp_scratch0, "highlink", "1000ps") ) link_cpu0_scratch1 = sst.Link("link_cpu1_scratch1") -link_cpu0_scratch1.connect( (iface1, "port", "1000ps"), (scratch1_link, "port", "1000ps") ) +link_cpu0_scratch1.connect( (iface1, "lowlink", "1000ps"), (comp_scratch1, "highlink", "1000ps") ) link_scratch0_net = sst.Link("link_scratch0_net") link_scratch0_net.connect( (scratch0_nic, "port", "100ps"), (comp_net, "port0", "100ps") ) link_scratch1_net = sst.Link("link_scratch1_net") diff --git a/src/sst/elements/memHierarchy/tests/testStdMem-flush.py b/src/sst/elements/memHierarchy/tests/testStdMem-flush.py index 435b8a7aad..3c666723d1 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem-flush.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem-flush.py @@ -89,8 +89,7 @@ "debug" : DEBUG_L2, "debug_level" : 10, }) - l2tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2NIC = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2NIC = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2NIC.addParams({ "group" : 1, "network_bw" : network_bw, @@ -99,10 +98,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (comp_l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (comp_l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (comp_l1cache, "low_network_0", "100ps"), (l2tol1, "port", "100ps") ) + l1_l2_link.connect( (comp_l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2NIC, "port", "100ps"), (comp_network, "port" + str(x), "100ps") ) @@ -129,7 +128,7 @@ "debug_level" : 10, }) - l3NIC = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3NIC = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3NIC.addParams({ "group" : 2, "network_bw" : network_bw, @@ -160,12 +159,7 @@ "addr_range_end" : 1024*1024*1024 - ((memories - x) * 64) + 63, }) - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") - dirtoM.addParams({ - "debug" : DEBUG_NOC, - "debug_level" : 10 - }) - dirNIC = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirNIC = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams({ "group" : 3, "group" : 3, # L2 = 1, L3 = 2, dir = 3 @@ -206,7 +200,7 @@ link_directory_network.connect( (dirNIC, "port", "100ps"), (comp_network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/testStdMem-mmio.py b/src/sst/elements/memHierarchy/tests/testStdMem-mmio.py index d61ab30518..1e8005e781 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem-mmio.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem-mmio.py @@ -44,7 +44,7 @@ }) iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface") iface.addParams(debug_params) -cpu_nic = iface.setSubComponent("memlink", "memHierarchy.MemNIC") +cpu_nic = iface.setSubComponent("lowlink", "memHierarchy.MemNIC") cpu_nic.addParams({"group" : core_group, "destinations" : core_dst, "network_bw" : network_bw}) @@ -65,7 +65,7 @@ "debug" : DEBUG_L1, "debug_level" : DEBUG_LEVEL }) -l1_nic = l1cache.setSubComponent("cpulink", "memHierarchy.MemNIC") +l1_nic = l1cache.setSubComponent("highlink", "memHierarchy.MemNIC") l1_nic.addParams({ "group" : l1_group, "sources" : l1_src, "destinations" : l1_dst, @@ -80,7 +80,7 @@ }) mmio_iface = mmio.setSubComponent("iface", "memHierarchy.standardInterface") #mmio_iface.addParams(debug_params) -mmio_nic = mmio_iface.setSubComponent("memlink", "memHierarchy.MemNIC") +mmio_nic = mmio_iface.setSubComponent("lowlink", "memHierarchy.MemNIC") mmio_nic.addParams({"group" : mmio_group, "sources" : mmio_src, "destinations" : mmio_dst, @@ -107,7 +107,7 @@ "clock" : "1GHz", "addr_range_end" : mmio_addr - 1, }) -mem_nic = memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +mem_nic = memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") mem_nic.addParams({"group" : memory_group, "sources" : "[1,2]", # Group 1 = L1, Group 2 = MMIO "network_bw" : network_bw}) diff --git a/src/sst/elements/memHierarchy/tests/testStdMem-mmio2.py b/src/sst/elements/memHierarchy/tests/testStdMem-mmio2.py index 4a2c7156ea..07c5ca3653 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem-mmio2.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem-mmio2.py @@ -55,8 +55,7 @@ "debug" : DEBUG_L1, "debug_level" : DEBUG_LEVEL }) -l1_link = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") # Non-network link -l1_nic = l1cache.setSubComponent("memlink", "memHierarchy.MemNIC") # Network link +l1_nic = l1cache.setSubComponent("lowlink", "memHierarchy.MemNIC") # Network link l1_nic.addParams({ "group" : l1_group, "destinations" : l1_dst, "network_bw" : network_bw}) @@ -72,7 +71,7 @@ }) mmio_iface = mmio.setSubComponent("iface", "memHierarchy.standardInterface") mmio_iface.addParams(debug_params) -mmio_nic = mmio_iface.setSubComponent("memlink", "memHierarchy.MemNIC") +mmio_nic = mmio_iface.setSubComponent("lowlink", "memHierarchy.MemNIC") mmio_nic.addParams({"group" : mmio_group, "sources" : mmio_src, "destinations" : mmio_dst, @@ -90,8 +89,7 @@ "debug_level" : 10, }) -dir_link = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dir_nic = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dir_nic = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dir_nic.addParams({ "group" : dir_group, "sources" : dir_src, @@ -140,7 +138,7 @@ # mmio/mmio_nic - chiprtr - dir_nic/dir/mem # link_cpu_l1 = sst.Link("link_cpu") -link_cpu_l1.connect( (iface, "port", "1000ps"), (l1_link, "port", "1000ps") ) +link_cpu_l1.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) link_l1_rtr = sst.Link("link_l1") link_l1_rtr.connect( (l1_nic, "port", '1000ps'), (chiprtr, "port0", "1000ps") ) @@ -152,4 +150,4 @@ link_dir_rtr.connect( (dir_nic, "port", "1000ps"), (chiprtr, "port2", "1000ps")) link_dir_mem = sst.Link("link_mem") -link_dir_mem.connect( (dir_link, "port", "1000ps"), (memctrl, "direct_link", "1000ps") ) +link_dir_mem.connect( (dirctrl, "lowlink", "1000ps"), (memctrl, "highlink", "1000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testStdMem-mmio3.py b/src/sst/elements/memHierarchy/tests/testStdMem-mmio3.py index ab0038398f..bdedecd445 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem-mmio3.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem-mmio3.py @@ -46,7 +46,7 @@ cpu_iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface") cpu_iface.addParams(debug_params) -cpu_link = cpu_iface.setSubComponent("memlink", "memHierarchy.MemLink") +cpu_link = cpu_iface.setSubComponent("lowlink", "memHierarchy.MemLink") cpu_link.addParams(debug_params) cpu_l1cache = sst.Component("cpu_l1cache", "memHierarchy.Cache") @@ -62,9 +62,9 @@ "debug" : DEBUG_L1, "debug_level" : DEBUG_LEVEL }) -cpu_l1_link = cpu_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") # Non-network link +cpu_l1_link = cpu_l1cache.setSubComponent("highlink", "memHierarchy.MemLink") # Non-network link cpu_l1_link.addParams(debug_params) -cpu_l1_nic = cpu_l1cache.setSubComponent("memlink", "memHierarchy.MemNIC") # Network link +cpu_l1_nic = cpu_l1cache.setSubComponent("lowlink", "memHierarchy.MemNIC") # Network link cpu_l1_nic.addParams({ "group" : core_group, "destinations" : l1_dst, "network_bw" : network_bw}) @@ -81,7 +81,7 @@ mmio_iface = mmio.setSubComponent("iface", "memHierarchy.standardInterface") mmio_iface.addParams(debug_params) -mmio_link = mmio_iface.setSubComponent("memlink", "memHierarchy.MemLink") +mmio_link = mmio_iface.setSubComponent("lowlink", "memHierarchy.MemLink") mmio_link.addParams(debug_params) mmio_l1cache = sst.Component("mmio_l1", "memHierarchy.Cache") @@ -98,9 +98,9 @@ "debug_level" : DEBUG_LEVEL }) -mmio_l1_link = mmio_l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") # Non-network link from device to device's L1 +mmio_l1_link = mmio_l1cache.setSubComponent("highlink", "memHierarchy.MemLink") # Non-network link from device to device's L1 mmio_l1_link.addParams(debug_params) -mmio_l1_nic = mmio_l1cache.setSubComponent("memlink", "memHierarchy.MemNIC") # Network link +mmio_l1_nic = mmio_l1cache.setSubComponent("lowlink", "memHierarchy.MemNIC") # Network link mmio_l1_nic.addParams({"group" : mmio_group, "sources" : mmio_src, @@ -118,7 +118,7 @@ "debug_level" : 10, }) -dir_nic = dir.setSubComponent("cpulink", "memHierarchy.MemNIC") +dir_nic = dir.setSubComponent("highlink", "memHierarchy.MemNIC") dir_nic.addParams({ "group" : dir_group, "sources" : dir_src, @@ -143,7 +143,7 @@ "mem_size" : "512MiB" }) -mem_nic = memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +mem_nic = memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") mem_nic.addParams(debug_params) mem_nic.addParams({ "group" : mem_group, @@ -178,19 +178,19 @@ # | # mmio/l1/mmio_l1_nic - chiprtr - dir_nic/dir/mem # -# Connect CPU to CPU L1 via the CPU's interface and the L1's cpulink handler +# Connect CPU to CPU L1 via the CPU's interface and the L1's highlink handler link_cpu_l1 = sst.Link("link_cpu") link_cpu_l1.connect( (cpu_link, "port", "1000ps"), (cpu_l1_link, "port", "1000ps") ) -# Connect the CPU L1 to the network via the L1's memlink NIC handler +# Connect the CPU L1 to the network via the L1's lowlink NIC handler link_core_rtr = sst.Link("link_core") link_core_rtr.connect( (cpu_l1_nic, "port", '1000ps'), (chiprtr, "port0", "1000ps") ) -# Connect MMIO to MMIO L1 via the MMIO's interface and the L1's cpulink handler +# Connect MMIO to MMIO L1 via the MMIO's interface and the L1's highlink handler link_mmio_l1 = sst.Link("link_mmio") link_mmio_l1.connect( (mmio_link, "port", "500ps"), (mmio_l1_link, "port", "500ps") ) -# Connect the MMIO L1 to the network via the L1's memlink NIC handler +# Connect the MMIO L1 to the network via the L1's lowlink NIC handler link_device_rtr = sst.Link("link_device") link_device_rtr.connect( (mmio_l1_nic, "port", "500ps"), (chiprtr, "port1", "500ps")) diff --git a/src/sst/elements/memHierarchy/tests/testStdMem-nic.py b/src/sst/elements/memHierarchy/tests/testStdMem-nic.py index fb51ed118a..256924226d 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem-nic.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem-nic.py @@ -18,7 +18,7 @@ "llsc_freq" : 10, }) iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface") -cpu_nic = iface.setSubComponent("memlink", "memHierarchy.MemNIC") +cpu_nic = iface.setSubComponent("lowlink", "memHierarchy.MemNIC") cpu_nic.addParams({"group" : 0, "network_bw" : "25GB/s"}) #cpu_nic.addParams(debug_params) @@ -35,7 +35,7 @@ "debug" : DEBUG_L1, "debug_level" : DEBUG_LEVEL }) -l1_nic = l1cache.setSubComponent("cpulink", "memHierarchy.MemNIC") +l1_nic = l1cache.setSubComponent("highlink", "memHierarchy.MemNIC") l1_nic.addParams({"group" : 1, "network_bw" : "25GB/s"}) #l1_nic.addParams(debug_params) @@ -59,7 +59,7 @@ "clock" : "1GHz", "addr_range_end" : 512*1024*1024-1, }) -mem_nic = memctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +mem_nic = memctrl.setSubComponent("highlink", "memHierarchy.MemNIC") mem_nic.addParams({"group" : 2, "network_bw" : "25GB/s"}) #mem_nic.addParams(debug_params) diff --git a/src/sst/elements/memHierarchy/tests/testStdMem-noninclusive.py b/src/sst/elements/memHierarchy/tests/testStdMem-noninclusive.py index babbc989c6..5ce585e14c 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem-noninclusive.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem-noninclusive.py @@ -76,10 +76,10 @@ # Define the simulation links link_cpu_l1cache = sst.Link("link_cpu_l1cache") -link_cpu_l1cache.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") ) +link_cpu_l1cache.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) link_l1cache_l2cache = sst.Link("link_l1cache_l2cache") -link_l1cache_l2cache.connect( (l1cache, "low_network_0", "10000ps"), (l2cache, "high_network_0", "10000ps") ) +link_l1cache_l2cache.connect( (l1cache, "lowlink", "10000ps"), (l2cache, "highlink", "10000ps") ) link_l2cache_l3cache = sst.Link("link_l2cache_l3cache") -link_l2cache_l3cache.connect( (l2cache, "low_network_0", "10000ps"), (l3cache, "high_network_0", "10000ps") ) +link_l2cache_l3cache.connect( (l2cache, "lowlink", "10000ps"), (l3cache, "highlink", "10000ps") ) link_mem_bus = sst.Link("link_mem_bus") -link_mem_bus.connect( (l3cache, "low_network_0", "10000ps"), (memctrl, "direct_link", "10000ps") ) +link_mem_bus.connect( (l3cache, "lowlink", "10000ps"), (memctrl, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testStdMem.py b/src/sst/elements/memHierarchy/tests/testStdMem.py index 9c40d79ce8..5e879331f4 100644 --- a/src/sst/elements/memHierarchy/tests/testStdMem.py +++ b/src/sst/elements/memHierarchy/tests/testStdMem.py @@ -59,6 +59,6 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (iface, "port", "1000ps"), (l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (iface, "lowlink", "1000ps"), (l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l1cache, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testThroughputThrottling.py b/src/sst/elements/memHierarchy/tests/testThroughputThrottling.py index eefb1230aa..53c0a975dc 100644 --- a/src/sst/elements/memHierarchy/tests/testThroughputThrottling.py +++ b/src/sst/elements/memHierarchy/tests/testThroughputThrottling.py @@ -93,8 +93,7 @@ "debug_level" : DEBUG_LEVEL, }) l2cache.setSubComponent("prefetcher", "cassini.NextBlockPrefetcher") - l2tol1 = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l2nic = l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2nic = l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2nic.addParams({ "group" : 1, "min_packet_size" : "10B", # control message size @@ -104,10 +103,10 @@ }) cpu_l1_link = sst.Link("link_cpu_cache_" + str(x)) - cpu_l1_link.connect ( (iface, "port", "500ps"), (l1cache, "high_network_0", "500ps") ) + cpu_l1_link.connect ( (iface, "lowlink", "500ps"), (l1cache, "highlink", "500ps") ) l1_l2_link = sst.Link("link_l1_l2_" + str(x)) - l1_l2_link.connect( (l1cache, "low_network_0", "100ps"), (l2tol1, "port", "100ps") ) + l1_l2_link.connect( (l1cache, "lowlink", "100ps"), (l2cache, "highlink", "100ps") ) l2_network_link = sst.Link("link_l2_network_" + str(x)) l2_network_link.connect( (l2nic, "port", "100ps"), (network, "port" + str(x), "100ps") ) @@ -133,7 +132,7 @@ "debug" : DEBUG_L3, "debug_level" : DEBUG_LEVEL, }) - l3nic = l3cache.setSubComponent("cpulink", "memHierarchy.MemNIC") + l3nic = l3cache.setSubComponent("highlink", "memHierarchy.MemNIC") l3nic.addParams({ "group" : 2, "min_packet_size" : "4B", # control message size @@ -160,8 +159,7 @@ "debug" : DEBUG_DIR, "debug_level" : DEBUG_LEVEL, }) - dirtoM = directory.setSubComponent("memlink", "memHierarchy.MemLink") - dirnic = directory.setSubComponent("cpulink", "memHierarchy.MemNIC") + dirnic = directory.setSubComponent("highlink", "memHierarchy.MemNIC") dirnic.addParams({ "group" : 3, "network_bw" : network_bw, @@ -198,7 +196,7 @@ link_directory_network.connect( (dirnic, "port", "100ps"), (network, "port" + str(portid), "100ps") ) link_directory_memory_network = sst.Link("link_directory_memory_" + str(x)) - link_directory_memory_network.connect( (dirtoM, "port", "400ps"), (memctrl, "direct_link", "400ps") ) + link_directory_memory_network.connect( (directory, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) # Enable statistics sst.setStatisticLoadLevel(7) diff --git a/src/sst/elements/memHierarchy/tests/test_coherence_1core.py b/src/sst/elements/memHierarchy/tests/test_coherence_1core.py new file mode 100644 index 0000000000..98350ee95d --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/test_coherence_1core.py @@ -0,0 +1,194 @@ +import sst +import sys +from mhlib import componentlist + +# Part of test set that tests all combinations of coherence protocols +# with each other and as last-level and not and as distributed and not +# +# Covers test cases with a zero, one or two-level hierarchy +# (no caches, L1 only, L1+all combos of next level, and L1+L2+L3 for a specific case that only works as a private hierarchy) + +## Options +# 0: L1 +# 1: L1 + L2 (inclusive) +# 2: L1 + L2 (noninclusive/no tag dir) +# 3: L1 + L2 (noninclusive w/ tag dir) +# 4: L1 + Directory +# 5: L1 + L2 (noninclusive/no tag dir) + L3 (noninclusive/no tag dir) +# 6: No caches + +# Define the simulation components +verbose = 2 + +DEBUG_L1 = 0 +DEBUG_L2 = 0 +DEBUG_MEM = 0 +DEBUG_LEVEL = 10 + +option = 0 + +if len(sys.argv) != 4: + print("Argument count is incorrect. Required: ") + +option = int(sys.argv[1]) +cpu_seed = int(sys.argv[2]) +protocol = sys.argv[3] + +cpu = sst.Component("core", "memHierarchy.standardCPU") +cpu.addParams({ + "memFreq" : 2, + "memSize" : "5KiB", + "verbose" : 0, + "clock" : "3.5GHz", + "rngseed" : cpu_seed, + "maxOutstanding" : 16, + "opCount" : 2500, + "reqsPerIssue" : 3, + "write_freq" : 36, # 36% writes + "read_freq" : 58, # 60% reads + "llsc_freq" : 3, # 3% LLSC + "flushcache_freq" : 3 +}) +iface = cpu.setSubComponent("memory", "memHierarchy.standardInterface") + +if option != 6: + l1cache = sst.Component("l1cache", "memHierarchy.Cache") + l1cache.addParams({ + "access_latency_cycles" : "3", + "cache_frequency" : "3.5Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : protocol, + "associativity" : "4", + "cache_line_size" : "64", + "debug" : DEBUG_L1, + "debug_level" : DEBUG_LEVEL, + "verbose" : verbose, + "L1" : "1", + "cache_size" : "2KiB" + }) + + # Link core & l1cache + link_cpu_l1 = sst.Link("link_cpu_l1") + link_cpu_l1.connect( (iface, "lowlink", "400ps"), (l1cache, "highlink", "400ps") ) + + +memctrl = sst.Component("memory", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : DEBUG_LEVEL, + "clock" : "1GHz", + "verbose" : verbose, + "addr_range_end" : 512*1024*1024-1, +}) + +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "access_time" : "1000ns", + "mem_size" : "512MiB" +}) + + +## Base L2 params +l2cache_params = { + "cache_size" : "1KiB", + "associativity" : 8, + "access_latency_cycles" : 11, + "cache_frequency" : "2.4GHz", + "replacement_policy" : "nmru", + "coherence_protocol" : protocol, + "cache_line_size" : 64, + "debug" : DEBUG_L2, + "debug_level" : DEBUG_LEVEL + } + +### Options for level between l1 & memory, default is none + +if option == 0: # L1 <-> Mem + link_l1_mem = sst.Link("link_l1_mem") + link_l1_mem.connect( (l1cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) + +elif option == 1: # L1 <-> L2/inclusive <-> Mem + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(l2cache_params) + l2cache.addParam("cache_size", "2KiB") # override base param since cache is inclusive + + link_l1_l2 = sst.Link("link_l1_l2") + link_l1_l2.connect( (l1cache, "lowlink", "50ps"), (l2cache, "highlink", "50ps") ) + + link_l2_mem = sst.Link("link_l2_mem") + link_l2_mem.connect( (l2cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) + +elif option == 2: # L1 <-> L2/priv noninclusive <-> Mem + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(l2cache_params) + l2cache.addParam("cache_type", "noninclusive") + + link_l1_l2 = sst.Link("link_l1_l2") + link_l1_l2.connect( (l1cache, "lowlink", "50ps"), (l2cache, "highlink", "50ps") ) + + link_l2_mem = sst.Link("link_l2_mem") + link_l2_mem.connect( (l2cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) + +elif option == 3: # L1 <-> L2/shr noninclusive <-> Mem + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(l2cache_params) + l2cache.addParams({"cache_type" : "noninclusive_with_directory", "noninclusive_directory_entries" : 40, "noninclusive_directory_associativity" : 4}) + + link_l1_l2 = sst.Link("link_l1_l2") + link_l1_l2.connect( (l1cache, "lowlink", "50ps"), (l2cache, "highlink", "50ps") ) + + link_l2_mem = sst.Link("link_l2_mem") + link_l2_mem.connect( (l2cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) + +elif option == 4: # L1 <-> DC <-> Mem + directory = sst.Component("directory", "memHierarchy.DirectoryController") + directory.addParams({ + "clock" : "2.4GHz", + "entry_cache_size" : 48, + "coherence_protocol" : protocol, + "mshr_num_entries" : 8, + "access_latency_cycles" : 2, + "mshr_latency_cycles" : 1, + "max_requests_per_cycle" : 2, + "debug_level" : DEBUG_LEVEL, + "debug" : DEBUG_L2 + }) + + link_l1_dc = sst.Link("link_l1_dc") + link_l1_dc.connect( (l1cache, "lowlink", "50ps"), (directory, "highlink", "50ps") ) + + link_dc_mem = sst.Link("link_dc_mem") + link_dc_mem.connect( (directory, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) + +elif option == 5: ## L1 <-> L2/priv noninclusive <-> 3/priv noninclusive <-> Mem + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(l2cache_params) + l2cache.addParam("cache_type", "noninclusive") + + link_l1_l2 = sst.Link("link_l1_l2") + link_l1_l2.connect( (l1cache, "lowlink", "50ps"), (l2cache, "highlink", "50ps") ) + + l3cache = sst.Component("l3cache", "memHierarchy.Cache") + l3cache.addParams(l2cache_params) + l3cache.addParam("cache_type", "noninclusive") + + link_l2_l3 = sst.Link("link_l2_l3") + link_l2_l3.connect( (l2cache, "lowlink", "50ps"), (l3cache, "highlink", "50ps") ) + + link_l3_mem = sst.Link("link_l3_mem") + link_l3_mem.connect( (l3cache, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) + +elif option == 6: ## Core <-> Mem + link_cpu_mem = sst.Link("link_cpu_mem") + link_cpu_mem.connect( (iface, "lowlink", "400ps"), (memctrl, "highlink", "400ps") ) + +else: + print("Error, option=%d is not valid. Options 0-5 are allowed\n"%option) + sys.exit(-1) + +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +for a in componentlist: + sst.enableAllStatisticsForComponentType(a) + diff --git a/src/sst/elements/memHierarchy/tests/test_coherence_2core_3level.py b/src/sst/elements/memHierarchy/tests/test_coherence_2core_3level.py new file mode 100644 index 0000000000..e6e612e69f --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/test_coherence_2core_3level.py @@ -0,0 +1,469 @@ +import sst +import sys +from mhlib import componentlist +from mhlib import Bus + +# Part of test set that tests all combinations of coherence protocols +# with each other and as last-level and not and as distributed and not +# +# Covers test cases with a three-level hierarchy (3 cache levels or 2 cache levels + directory) + +################## +## Options +## 0. L2 (inclusive/private) + L3 (inclusive/shared) +## 1. L2 (inclusive/shared/distributed) + L3 (inclusive/shared/distributed) +## 2. L2 (noninclusive/no tag dir) + L3 inclusive/shared) +## 3. L2 (noninclusive w/ tag dir) + L3 (inclusive/shared) +## 4. L2 (inclusive/shared) + L3 (noninclusive/no tag dir) +## 5. L2 (inclusive/private) + L3 (noninclusive w/ tag dir/distributed) +## 6. L2 (inclusive/private) + directory +## 7. L2 (noninclusive w/ tag dir) + L3 (noninclusive/no tag dir/distributed) +## 8. L2 (noninclusive/no tag dir) + directory (distributed) +## 9. L2 (noninclusive/no tag dir) + L3 (noninclusive w/tag dir) +## 10. L2 (noninclusive w/ tag dir/distributed + L3 (noninclusive w/ tag dir) +## 11. L2 (noninclusive w/ tag dir/distributed + directory + +DEBUG_L1 = 0 +DEBUG_L2 = 0 +DEBUG_L3 = 0 +DEBUG_MEM = 0 + +option = 0; +if len(sys.argv) != 5: + print("Argument count is incorrect. Required: ") + +option = int(sys.argv[1]) +seeds = [int(sys.argv[2]), int(sys.argv[3])] +protocol = sys.argv[4] + +cpu_params = { + "memFreq" : 1, + "memSize" : "16KiB", + "verbose" : 0, + "clock" : "3GHz", + "maxOutstanding" : 8, + "opCount" : 3000, + "reqsPerIssue" : 4, +} +# Core 0 +cpu0 = sst.Component("core0", "memHierarchy.standardCPU") +cpu0.addParams(cpu_params) +cpu0.addParams({ + "rngseed" : seeds[0], + "write_freq" : 38, # 38% writes + "read_freq" : 58, # 58% reads + "llsc_freq" : 2, # 2% LLSC + "flushcache_freq" : 2, # 2% FlushAll +}) +cpu0_iface = cpu0.setSubComponent("memory", "memHierarchy.standardInterface") + +# Core 1 +cpu1 = sst.Component("core1", "memHierarchy.standardCPU") +cpu1.addParams(cpu_params) +cpu1.addParams({ + "rngseed" : seeds[1], + "write_freq" : 34, # 34% writes + "read_freq" : 62, # 62% reads + "llsc_freq" : 1, # 2% LLSC + "flushcache_freq" : 3, +}) +cpu1_iface = cpu1.setSubComponent("memory", "memHierarchy.standardInterface") + +# L1s +l1cache_params = { + "access_latency_cycles" : 2, + "cache_frequency" : "3Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : protocol, + "associativity" : 4, + "mshr_num_entries" : 8, + "cache_line_size" : "64", + "debug_level" : "10", + "debug" : DEBUG_L1, + "L1" : "1", + "cache_size" : "1 KiB" +} + +l1cache0 = sst.Component("l1cache0", "memHierarchy.Cache") +l1cache0.addParams(l1cache_params) +l1cache1 = sst.Component("l1cache1", "memHierarchy.Cache") +l1cache1.addParams(l1cache_params) + +link0_cpu_l1 = sst.Link("link0_cpu_l1") +link0_cpu_l1.connect( (cpu0_iface, "lowlink", "100ps"), (l1cache0, "highlink", "100ps") ) +link1_cpu_l1 = sst.Link("link1_cpu_l1") +link1_cpu_l1.connect( (cpu1_iface, "lowlink", "100ps"), (l1cache1, "highlink", "100ps") ) + +# Memory +memctrl = sst.Component("memory", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : 10, + "clock" : "1GHz", + "addr_range_end" : 512*1024*1024-1, +}) + +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "mem_size" : "512MiB", + "access_time" : "80ns", +}) + + +## Some parameter sets used below +cache_distributed_params = { + "num_cache_slices" : 2, + "slice_allocation_policy" : "rr" +} + +cache_noninclusive_private_params = { + "cache_type" : "noninclusive" +} + +l2cache_noninclusive_shared_params = { + "cache_type" : "noninclusive_with_directory", + "noninclusive_directory_entries" : 128, # Cover 2x 1KiB L1 + 1x 2KiB L2 (or 2x 2KiB L2) + "noninclusive_directory_associativity" : 4 +} + +l3cache_noninclusive_shared_params = { + "cache_type" : "noninclusive_with_directory", + "noninclusive_directory_entries" : 128, + "noninclusive_directory_associativity" : 4 +} + +bus_params = {"bus_frequency" : "3GHz"} + + +######################### +## Construct L2 level +######################### + +l2cache_base_params = { + "access_latency_cycles" : "11", + "cache_frequency" : "3GHz", + "replacement_policy" : "lru", + "coherence_protocol" : protocol, + "associativity" : "8", + "mshr_num_entries" : 16, + "cache_line_size" : "64", + "debug_level" : "10", + "debug" : DEBUG_L2, +} +l2cache_size_full = {"cache_size" : "4KiB"} # Single (shared) inclusive cache +l2cache_size_half = {"cache_size" : "2KiB"} # Multiple (private or shared/distributed) caches, single shared noninclusive +l2cache_size_quarter = {"cache_size" : "1KiB"} # Distributed shared noninclusive + +l2_bus = None # Only need an L2 bus if we have multiple L2s and/or multiple L3s + +if option == 0 or option == 5 or option == 6: ## L2 inclusive/private/single + params = dict(l2cache_base_params) + params.update(l2cache_size_half) + + l2cache0 = sst.Component("l2cache0", "memHierarchy.Cache") + l2cache0.addParams(params) + + l2cache1 = sst.Component("l2cache1", "memHierarchy.Cache") + l2cache1.addParams(params) + + # Connect L1<->L2 + link0_l1_l2 = sst.Link("link0_l1_l2") + link1_l1_l2 = sst.Link("link1_l1_l2") + link0_l1_l2.connect((l1cache0, "lowlink", "100ps"), (l2cache0, "highlink", "100ps")) + link1_l1_l2.connect((l1cache1, "lowlink", "100ps"), (l2cache1, "highlink", "100ps")) + + # Create L2 bus and connect L2s. Will connect L3(s) or directory(s) later. + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache0, l2cache1]) + +elif option == 1: ## L2 inclusive/shared/distributed + params = dict(l2cache_base_params) + params.update(l2cache_size_half) + params.update(cache_distributed_params) + + l2cache0 = sst.Component("l2cache0", "memHierarchy.Cache") + l2cache0.addParams(params) + l2cache0.addParam("slice_id", 0) + + l2cache1 = sst.Component("l2cache1", "memHierarchy.Cache") + l2cache1.addParams(params) + l2cache1.addParam("slice_id", 1) + + # Create L1 bus and connect L1s to L2s + Bus("l1bus", bus_params, "100ps", [l1cache0, l1cache1], [l2cache0, l2cache1]) + + # Create L2 bus and connect L2s. Will connect L3(s) or directory(s) later. + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache0, l2cache1]) + +elif option == 4: ## L2 inclusive/shared-single + params = dict(l2cache_base_params) + params.update(l2cache_size_full) + + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(params) + + # Create L1 bus and connect L1s to L2 + Bus("l1bus", bus_params, "100ps", [l1cache0, l1cache1], [l2cache]) + +elif option == 2 or option == 8 or option == 9: ## L2 noninclusive/private + params = dict(l2cache_base_params) + params.update(l2cache_size_half) + params.update(cache_noninclusive_private_params) + + l2cache0 = sst.Component("l2cache0", "memHierarchy.Cache") + l2cache0.addParams(params) + + l2cache1 = sst.Component("l2cache1", "memHierarchy.Cache") + l2cache1.addParams(params) + + # Connect L1<->L2 + link0_l1_l2 = sst.Link("link0_l1_l2") + link1_l1_l2 = sst.Link("link1_l1_l2") + link0_l1_l2.connect((l1cache0, "lowlink", "100ps"), (l2cache0, "highlink", "100ps")) + link1_l1_l2.connect((l1cache1, "lowlink", "100ps"), (l2cache1, "highlink", "100ps")) + + # Create L2 bus and connect L2s. Will connect L3(s) or directory(s) later. + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache0, l2cache1]) + +elif option == 3 or option == 7: ## L2 noninclusive/shared-single + params = dict(l2cache_base_params) + params.update(l2cache_size_half) + params.update(l2cache_noninclusive_shared_params) + + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(params) + + # Create L1 bus and connect L1s to L2 + Bus("l1bus", bus_params, "100ps", [l1cache0, l1cache1], [l2cache]) + + +elif option == 10 or option == 11: ## L2 noninclusive/shared-distributed + params = dict(l2cache_base_params) + params.update(l2cache_size_quarter) + params.update(cache_distributed_params) + params.update(l2cache_noninclusive_shared_params) + + l2cache0 = sst.Component("l2cache0", "memHierarchy.Cache") + l2cache0.addParams(params) + l2cache0.addParam("slice_id", 0) + + l2cache1 = sst.Component("l2cache1", "memHierarchy.Cache") + l2cache1.addParams(params) + l2cache1.addParam("slice_id", 1) + + # Create L1 bus and connect L1s to L2s + Bus("l1bus", bus_params, "100ps", [l1cache0, l1cache1], [l2cache0, l2cache1]) + + # Create L2 bus and connect L2s. Will connect L3(s) or directory(s) later. + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache0, l2cache1]) + + +else: + print("Error, option=%d is not valid. Options 0-11 are allowed\n"%option) + sys.exit(-1) + + +######################### +## Construct L3 level +######################### +l3cache_base_params = { + "access_latency_cycles" : "18", + "cache_frequency" : "3 Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : protocol, + "associativity" : "12", + "cache_line_size" : "64", + "mshr_num_entries" : 32, + "debug_level" : "10", + "debug" : DEBUG_L2, +} + +l3cache_size_full = {"cache_size" : "6KiB"} # Single (shared) cache +l3cache_size_half = {"cache_size" : "3KiB"} # Multiple (private or shared/distributed) caches +l3cache_size_quarter = {"cache_size" : "1.5KiB"} # Multiple distributed noninclusive caches + + +if option == 0 or option == 2 or option == 3: ## L3 inclusive/shared/single + l3cache = sst.Component("l3cache", "memHierarchy.Cache") + l3cache.addParams(l3cache_base_params) + l3cache.addParams(l3cache_size_full) + + # Connect l3cache to l2bus + if l2_bus: + l2_bus.connect(lowcomps=[l3cache]) + else: + link = sst.Link("link_l2_l3") + link.connect( (l2cache, "lowlink", "100ps"), (l3cache, "highlink", "100ps") ) + + link = sst.Link("link_l3_memory") + link.connect( (l3cache, "lowlink", "100ps"), (memctrl, "highlink", "100ps") ) + +elif option == 1: ## L3 inclusive/shared/distributed + params = dict(l3cache_base_params) + params.update(cache_distributed_params) + params.update(l3cache_size_half) + + l3cache0 = sst.Component("l3cache0", "memHierarchy.Cache") + l3cache0.addParams(params) + l3cache0.addParam("slice_id", 0) + + l3cache1 = sst.Component("l3cache1", "memHierarchy.Cache") + l3cache1.addParams(params) + l3cache1.addParam("slice_id", 1) + + # Connect l2 <-> l3 via a bus + if l2_bus: + l2_bus.connect(lowcomps=[l3cache0,l3cache1]) + else: + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache], [l3cache0, l3cache1]) + + # Connect l3 <-> memory controller via a bus + mem_bus = Bus("membus", bus_params, "100ps", [l3cache0, l3cache1], [memctrl]) + +elif option == 4: ## 4. L3 noninclusive/private/single + params = dict(l3cache_base_params) + params.update(l3cache_size_half) + params.update(cache_noninclusive_private_params) + + l3cache = sst.Component("l3cache", "memHierarchy.Cache") + l3cache.addParams(params) + + if l2_bus: + l2_bus.connect(lowcomps=[l3cache]) + else: + link = sst.Link("link_l2_l3") + link.connect( (l2cache, "lowlink", "100ps"), (l3cache, "highlink", "100ps") ) + + link = sst.Link("link_l3_memory") + link.connect( (l3cache, "lowlink", "100ps"), (memctrl, "highlink", "100ps") ) + +elif option == 5: ## L3 noninclusive/shared/distributed + params = dict(l3cache_base_params) + params.update(l3cache_size_quarter) + params.update(l3cache_noninclusive_shared_params) + params.update(cache_distributed_params) + + l3cache0 = sst.Component("l3cache0", "memHierarchy.Cache") + l3cache0.addParams(params) + l3cache0.addParam("slice_id", 0) + + l3cache1 = sst.Component("l3cache1", "memHierarchy.Cache") + l3cache1.addParams(params) + l3cache1.addParam("slice_id", 1) + + # Connect l2 <-> l3 via a bus + if l2_bus: + l2_bus.connect(lowcomps=[l3cache0,l3cache1]) + else: + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache], [l3cache0, l3cache1]) + + # Connect l3 <-> memory controller via a bus + mem_bus = Bus("membus", bus_params, "100ps", [l3cache0, l3cache1], [memctrl]) + +elif option == 6 or option == 11: ## directory/single + directory = sst.Component("directory", "memHierarchy.DirectoryController") + directory.addParams({ + "clock" : "2GHz", + "entry_cache_size" : 256, + "coherence_protocol" : protocol, + "mshr_num_entries" : 32, + "access_latency_cycles" : 1, + "mshr_latency_cycles" : 1, + "max_requests_per_cycle" : 2, + "debug_level" : "10", + "debug" : DEBUG_L3, + }) + + # Connect l2 <-> l3 via a bus + if l2_bus: + l2_bus.connect(lowcomps=[directory]) + else: + link = sst.Link("link_l2_dir") + link.connect( (l2cache, "lowlink", "100ps"), (directory, "highlink", "100ps") ) + + # Connect directory <-> memory controller + link = sst.Link("link_dir_mem") + link.connect( (directory, "lowlink", "100ps"), (memctrl, "highlink", "100ps") ) + +elif option == 7: ## L3 noninclusive/private/distributed + params = dict(l3cache_base_params) + params.update(l3cache_size_quarter) + params.update(cache_noninclusive_private_params) + params.update(cache_distributed_params) + + l3cache0 = sst.Component("l3cache0", "memHierarchy.Cache") + l3cache0.addParams(params) + l3cache0.addParam("slice_id", 0) + + l3cache1 = sst.Component("l3cache1", "memHierarchy.Cache") + l3cache1.addParams(params) + l3cache1.addParam("slice_id", 1) + + # Connect l2 <-> l3 via a bus + if l2_bus: + l2_bus.connect(lowcomps=[l3cache0,l3cache1]) + else: + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache], [l3cache0, l3cache1]) + + # Connect l3 <-> memory controller via a bus + mem_bus = Bus("membus", bus_params, "100ps", [l3cache0, l3cache1], [memctrl]) + +elif option == 8: ## 8. directory/distributed + params = { + "clock" : "2GHz", + "entry_cache_size" : 256, + "coherence_protocol" : protocol, + "mshr_num_entries" : 32, + "access_latency_cycles" : 1, + "mshr_latency_cycles" : 1, + "max_requests_per_cycle" : 2, + "debug_level" : "10", + "debug" : DEBUG_L3, + "interleave_step" : "256B", + "interleave_size" : "128B", # interleave 128B chunks (2 cachelines) + } + + directory0 = sst.Component("directory0", "memHierarchy.DirectoryController") + directory0.addParams(params) + directory0.addParam("addr_range_start", 0) + + directory1 = sst.Component("directory1", "memHierarchy.DirectoryController") + directory1.addParams(params) + directory1.addParam("addr_range_start", 128) + + # Connect l2 <-> l3 via a bus + if l2_bus: + l2_bus.connect(lowcomps=[directory0, directory1]) + else: + Bus("l2bus", bus_params, "100ps", [l2cache], [directory0, directory1]) + + # Connect directory <-> memory controller + mem_bus = Bus("membus", bus_params, "100ps", [directory0, directory1], [memctrl]) + +elif option == 9 or option == 10: ## L3 noninclusive/shared/single + params = dict(l3cache_base_params) + params.update(l3cache_size_half) + params.update(l3cache_noninclusive_shared_params) + + l3cache = sst.Component("l3cache", "memHierarchy.Cache") + l3cache.addParams(params) + + # Connect l3cache to l2bus + if l2_bus: + l2_bus.connect(lowcomps=[l3cache]) + else: + link = sst.Link("link_l2_l3") + link.connect( (l2cache, "lowlink", "100ps"), (l3cache, "highlink", "100ps") ) + + link = sst.Link("link_l3_memory") + link.connect( (l3cache, "lowlink", "100ps"), (memctrl, "highlink", "100ps") ) + +else: + print("Error, option=%d is not valid. Options 0-11 are allowed\n"%option) + sys.exit(-1) + +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +for a in componentlist: + sst.enableAllStatisticsForComponentType(a) + diff --git a/src/sst/elements/memHierarchy/tests/test_coherence_4core_5level.py b/src/sst/elements/memHierarchy/tests/test_coherence_4core_5level.py new file mode 100644 index 0000000000..35131d33a2 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/test_coherence_4core_5level.py @@ -0,0 +1,400 @@ +import sst +import sys +from mhlib import componentlist +from mhlib import Bus + +# Part of test set that tests all combinations of coherence protocols +# with each other and as last-level and not and as distributed and not +# +# Covers test cases with a five-level hierarchy (4 cache levels + directory) + +################## +## Options +## 0. L2 inclusive/private + L3 inclusive/shared + L4 noninclusive/private + directory +## 1. L2 noninclusive/private + L3 inclusive/shared + L4 noninclusive/shared + directory +## 2. L2 noninclusive/shared + L3 noninclusive/shared + L4 inclusive/shared + directory +## 3. L2 noninclusive/private + L3 noninclusive/private + L4 noninclusive/shared + directory + +DEBUG_L1 = 0 +DEBUG_L2 = 0 +DEBUG_L3 = 0 +DEBUG_L4 = 0 +DEBUG_DC = 0 +DEBUG_MEM = 0 + +option = 0; +if len(sys.argv) != 7: + print("Argument count is incorrect. Required: ") + +option = int(sys.argv[1]) +seeds = [int(sys.argv[2]), int(sys.argv[3]), int(sys.argv[4]), int(sys.argv[5])] +protocol = sys.argv[6] + +cpu_params = { + "memFreq" : 1, + "memSize" : "24KiB", + "verbose" : 0, + "clock" : "3GHz", + "maxOutstanding" : 16, + "opCount" : 2000, + "reqsPerIssue" : 4, +} +# Core 0 +cpu0 = sst.Component("core0", "memHierarchy.standardCPU") +cpu0.addParams(cpu_params) +cpu0.addParams({ + "rngseed" : seeds[0], + "write_freq" : 38, # 38% writes + "read_freq" : 59, # 59% reads + "llsc_freq" : 2, # 2% LLSC + "flushcache_freq" : 1, # 2% FlushAll +}) +cpu0_iface = cpu0.setSubComponent("memory", "memHierarchy.standardInterface") + +# Core 1 +cpu1 = sst.Component("core1", "memHierarchy.standardCPU") +cpu1.addParams(cpu_params) +cpu1.addParams({ + "rngseed" : seeds[1], + "write_freq" : 34, # 34% writes + "read_freq" : 62, # 62% reads + "llsc_freq" : 1, # 2% LLSC + "flushcache_freq" : 3, +}) +cpu1_iface = cpu1.setSubComponent("memory", "memHierarchy.standardInterface") + +# Core 2 +cpu2 = sst.Component("core2", "memHierarchy.standardCPU") +cpu2.addParams(cpu_params) +cpu2.addParams({ + "rngseed" : seeds[2], + "write_freq" : 43, # 43% writes + "read_freq" : 54, # 54% reads + "llsc_freq" : 2, # 2% LLSC + "flushcache_freq" : 1, +}) +cpu2_iface = cpu2.setSubComponent("memory", "memHierarchy.standardInterface") + +# Core 3 +cpu3 = sst.Component("core3", "memHierarchy.standardCPU") +cpu3.addParams(cpu_params) +cpu3.addParams({ + "rngseed" : seeds[3], + "write_freq" : 33, # 33% writes + "read_freq" : 64, # 64% reads + "llsc_freq" : 1, # 1% LLSC + "flushcache_freq" : 2, +}) +cpu3_iface = cpu3.setSubComponent("memory", "memHierarchy.standardInterface") + + +# L1s +l1cache_params = { + "access_latency_cycles" : 1, + "cache_frequency" : "3Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MESI", + "associativity" : 4, + "cache_line_size" : "64", + "mshr_num_entries" : 16, + "debug_level" : "10", + "debug" : DEBUG_L1, + "L1" : "1", + "cache_size" : "1 KiB" +} + +l1cache0 = sst.Component("l1cache0", "memHierarchy.Cache") +l1cache0.addParams(l1cache_params) +l1cache1 = sst.Component("l1cache1", "memHierarchy.Cache") +l1cache1.addParams(l1cache_params) +l1cache2 = sst.Component("l1cache2", "memHierarchy.Cache") +l1cache2.addParams(l1cache_params) +l1cache3 = sst.Component("l1cache3", "memHierarchy.Cache") +l1cache3.addParams(l1cache_params) + +link0_cpu_l1 = sst.Link("link0_cpu_l1") +link0_cpu_l1.connect( (cpu0_iface, "lowlink", "100ps"), (l1cache0, "highlink", "100ps") ) +link1_cpu_l1 = sst.Link("link1_cpu_l1") +link1_cpu_l1.connect( (cpu1_iface, "lowlink", "100ps"), (l1cache1, "highlink", "100ps") ) +link2_cpu_l1 = sst.Link("link2_cpu_l1") +link2_cpu_l1.connect( (cpu2_iface, "lowlink", "100ps"), (l1cache2, "highlink", "100ps") ) +link3_cpu_l1 = sst.Link("link3_cpu_l1") +link3_cpu_l1.connect( (cpu3_iface, "lowlink", "100ps"), (l1cache3, "highlink", "100ps") ) + +# Memory +memctrl = sst.Component("memory", "memHierarchy.MemController") +memctrl.addParams({ + "debug" : DEBUG_MEM, + "debug_level" : 10, + "clock" : "1GHz", + "addr_range_end" : 512*1024*1024-1, +}) + +memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") +memory.addParams({ + "mem_size" : "512MiB", + "access_time" : "80ns", +}) + +################## +## Options +## 0. L2 inclusive/private + L3 inclusive/shared + L4 noninclusive/private + directory +## 1. L2 noninclusive/private + L3 inclusive/shared + L4 noninclusive/shared + directory +## 2. L2 noninclusive/shared + L3 noninclusive/shared + L4 inclusive/shared + directory +## 3. L2 noninclusive/private + L3 noninclusive/private + L4 noninclusive/shared + directory + +## Some parameter sets used below +cache_distributed_params = { + "num_cache_slices" : 2, + "slice_allocation_policy" : "rr" +} + +cache_noninclusive_private_params = { + "cache_type" : "noninclusive" +} + +l2cache_noninclusive_shared_params = { + "cache_type" : "noninclusive_with_directory", + "noninclusive_directory_entries" : 64, # 4KiB data covered + "noninclusive_directory_associativity" : 4 +} + +l3cache_noninclusive_shared_params = { + "cache_type" : "noninclusive_with_directory", + "noninclusive_directory_entries" : 128, + "noninclusive_directory_associativity" : 4 +} + +l4cache_noninclusive_shared_params = { + "cache_type" : "noninclusive_with_directory", + "noninclusive_directory_entries" : 320, + "noninclusive_directory_associativity" : 8 +} + +bus_params = {"bus_frequency" : "3GHz"} + + +######################### +## Construct L2 level +######################### + +l2cache_base_params = { + "access_latency_cycles" : 3, + "cache_frequency" : "3GHz", + "replacement_policy" : "lru", + "coherence_protocol" : "MESI", + "associativity" : "8", + "cache_line_size" : "64", + "mshr_num_entries" : 24, + "debug_level" : "10", + "debug" : DEBUG_L2, +} +l2cache_size_full = {"cache_size" : "2KiB"} # Inclusive +l2cache_size_half = {"cache_size" : "1KiB"} # Noninclusive + +l2_bus = None # Only need an L2 bus if we have multiple L2s and/or multiple L3s + +## 0. L2 inclusive/private + L3 inclusive/shared + L4 noninclusive/private + directory +## L2=2KiB +## L3=12KiB +## L4=4KiB +## 1. L2 noninclusive/private + L3 inclusive/shared + L4 noninclusive/shared + directory +## L2=1KiB +## L3=12KiB +## L4=4KiB, 16KiB tag +## 2. L2 noninclusive/shared + L3 noninclusive/shared + L4 inclusive/shared + directory +## L2=1KiB, 4KiB tag +## L3=2KiB, 8KiB tag +## L4=12KiB +## 3. L2 noninclusive/private + L3 noninclusive/private + L4 noninclusive/shared + directory +## L2=2KiB +## L3=2KiB +## L4=4KiB, 20KiB tag + +if option == 0 or option == 1 or option == 3: ## L2 inclusive/private or noninclusive/private + params = dict(l2cache_base_params) + if option == 1: + params.update(l2cache_size_half) + params.update(cache_noninclusive_private_params) + else: + params.update(l2cache_size_full) + + l2cache0 = sst.Component("l2cache0", "memHierarchy.Cache") + l2cache0.addParams(params) + + l2cache1 = sst.Component("l2cache1", "memHierarchy.Cache") + l2cache1.addParams(params) + + l2cache2 = sst.Component("l2cache2", "memHierarchy.Cache") + l2cache2.addParams(params) + + l2cache3 = sst.Component("l2cache3", "memHierarchy.Cache") + l2cache3.addParams(params) + + link0_l1_l2 = sst.Link("link0_l1_l2") + link1_l1_l2 = sst.Link("link1_l1_l2") + link2_l1_l2 = sst.Link("link2_l1_l2") + link3_l1_l2 = sst.Link("link3_l1_l2") + link0_l1_l2.connect((l1cache0, "lowlink", "100ps"), (l2cache0, "highlink", "100ps")) + link1_l1_l2.connect((l1cache1, "lowlink", "100ps"), (l2cache1, "highlink", "100ps")) + link2_l1_l2.connect((l1cache2, "lowlink", "100ps"), (l2cache2, "highlink", "100ps")) + link3_l1_l2.connect((l1cache3, "lowlink", "100ps"), (l2cache3, "highlink", "100ps")) + + if option != 3: + l2_bus = Bus("l2bus", bus_params, "100ps", [l2cache0, l2cache1, l2cache2, l2cache3]) + +elif option == 2: ## L2 noninclusive/shared + params = dict(l2cache_base_params) + params.update(l2cache_noninclusive_shared_params) + params.update(l2cache_size_half) + + l2cache = sst.Component("l2cache", "memHierarchy.Cache") + l2cache.addParams(params) + + l1_bus = Bus("l1bus", bus_params, "100ps", [l1cache0, l1cache1, l1cache2, l1cache3], [l2cache]) + +else: + print("Error, option=%d is not valid. Options 0-3 are allowed\n"%option) + sys.exit(-1) + + +######################### +## Construct L3 level +######################### +l3cache_base_params = { + "access_latency_cycles" : 7, + "cache_frequency" : "3 Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MESI", + "associativity" : "8", + "mshr_num_entries" : 48, + "cache_line_size" : "64", + "debug_level" : "10", + "debug" : DEBUG_L3, +} + +l3cache_size_inclus = {"cache_size" : "12KiB"} # Inclusive cache, to cover upper levels +l3cache_size_noninclus = {"cache_size" : "2KiB"} # Noninclusive cache + +l3_bus = None # Only need an L3 bus if we have multiple L3s + +if option != 3: ## L3 inclusive/shared or noninclusive/shared + params = dict(l3cache_base_params) + if option != 2: + params.update(l3cache_size_inclus) + else: + params.update(l3cache_size_noninclus) + params.update(l3cache_noninclusive_shared_params) + + l3cache = sst.Component("l3cache", "memHierarchy.Cache") + l3cache.addParams(params) + + if l2_bus: + l2_bus.connect(lowcomps=[l3cache]) + else: + link = sst.Link("link_l2_l3") + link.connect( (l2cache, "lowlink", "100ps"), (l3cache, "highlink", "100ps") ) + +else: ## option == 3: L3 noninclusive/private + params = dict(l3cache_base_params) + params.update(cache_noninclusive_private_params) + params.update(l3cache_size_noninclus) + + l3cache0 = sst.Component("l3cache0", "memHierarchy.Cache") + l3cache0.addParams(params) + + l3cache1 = sst.Component("l3cache1", "memHierarchy.Cache") + l3cache1.addParams(params) + + l3cache2 = sst.Component("l3cache2", "memHierarchy.Cache") + l3cache2.addParams(params) + + l3cache3 = sst.Component("l3cache3", "memHierarchy.Cache") + l3cache3.addParams(params) + + link0_l2_l3 = sst.Link("link0_l2_l3") + link1_l2_l3 = sst.Link("link1_l2_l3") + link2_l2_l3 = sst.Link("link2_l2_l3") + link3_l2_l3 = sst.Link("link3_l2_l3") + link0_l2_l3.connect( (l2cache0, "lowlink", "100ps"), (l3cache0, "highlink", "100ps") ) + link1_l2_l3.connect( (l2cache1, "lowlink", "100ps"), (l3cache1, "highlink", "100ps") ) + link2_l2_l3.connect( (l2cache2, "lowlink", "100ps"), (l3cache2, "highlink", "100ps") ) + link3_l2_l3.connect( (l2cache3, "lowlink", "100ps"), (l3cache3, "highlink", "100ps") ) + + l3_bus = Bus("l3bus", bus_params, "100ps", [l3cache0, l3cache1, l3cache2, l3cache3]) + +######################### +## Construct L4 level +######################### +l4cache_base_params = { + "access_latency_cycles" : 7, + "cache_frequency" : "3 Ghz", + "replacement_policy" : "lru", + "coherence_protocol" : "MESI", + "associativity" : "8", + "mshr_num_entries" : 128, + "cache_line_size" : "64", + "debug_level" : "10", + "debug" : DEBUG_L4, +} + +l4cache_size_inclus = { "cache_size" : "12KiB" } +l4cache_size_noninclus = { "cache_size" : "4KiB" } + +## 0. L2 inclusive/private + L3 inclusive/shared + L4 noninclusive/private + directory +## L4=4KiB +## 1. L2 noninclusive/private + L3 inclusive/shared + L4 noninclusive/shared + directory +## L4=4KiB, 16KiB tag +## 2. L2 noninclusive/shared + L3 noninclusive/shared + L4 inclusive/shared + directory +## L4=12KiB +## 3. L2 noninclusive/private + L3 noninclusive/private + L4 noninclusive/shared + directory +## L4=4KiB, 20KiB tag + +params = dict(l4cache_base_params) +if option == 0: + params.update(l4cache_size_noninclus) + params.update(cache_noninclusive_private_params) +elif option == 1 or option == 3: + params.update(l4cache_size_noninclus) + params.update(l4cache_noninclusive_shared_params) +else: # option == 2: + params.update(l4cache_size_inclus) + +l4cache = sst.Component("l4cache", "memHierarchy.Cache") +l4cache.addParams(params) + +directory = sst.Component("directory", "memHierarchy.DirectoryController") +directory.addParams({ + "clock" : "2GHz", + "entry_cache_size" : 512, + "coherence_protocol" : "MESI", + "mshr_num_entries" : 256, + "access_latency_cycles" : 1, + "mshr_latency_cycles" : 1, + "max_requests_per_cycle" : 2, + "debug_level" : "10", + "debug" : DEBUG_DC, +}) + +# Connect l3cache(s) <-> l4cache +if l3_bus: + l3_bus.connect(lowcomps=[l4cache]) +else: + link = sst.Link("link_l3_l4") + link.connect( (l3cache, "lowlink", "100ps"), (l4cache, "highlink", "100ps") ) + +# Connect l4cache <-> directory +link = sst.Link("link_l4_dir") +link.connect( (l4cache, "lowlink", "100ps"), (directory, "highlink", "100ps") ) + +# Connect directory <-> memory controller +link = sst.Link("link_dir_mem") +link.connect( (directory, "lowlink", "100ps"), (memctrl, "highlink", "100ps") ) + + +# Enable statistics +sst.setStatisticLoadLevel(7) +sst.setStatisticOutput("sst.statOutputConsole") +for a in componentlist: + sst.enableAllStatisticsForComponentType(a) + diff --git a/src/sst/elements/memHierarchy/tests/test_hybridsim.py b/src/sst/elements/memHierarchy/tests/test_hybridsim.py index 247393f2ec..6687f574b4 100644 --- a/src/sst/elements/memHierarchy/tests/test_hybridsim.py +++ b/src/sst/elements/memHierarchy/tests/test_hybridsim.py @@ -1,6 +1,8 @@ import sst import os +from mhlib import Bus + # Define SST core options sst.setProgramOption("stop-at", "100000ns") @@ -51,10 +53,11 @@ "L1" : "1", "debug" : "0" }) -comp_bus = sst.Component("bus", "memHierarchy.Bus") -comp_bus.addParams({ - "bus_frequency" : "2 Ghz" -}) + +bus_params = { "bus_frequency" : "2GHz" } + +comp_bus = Bus("bus", bus_params, "10000ps") + comp_l2cache = sst.Component("l2cache", "memHierarchy.Cache") comp_l2cache.addParams({ "access_latency_cycles" : "8", @@ -88,14 +91,11 @@ # Define the simulation links link_cpu0_l1cache_link = sst.Link("link_cpu0_l1cache_link") -link_cpu0_l1cache_link.connect( (subcomp_iface0, "port", "1000ps"), (comp_c0_l1cache, "high_network_0", "1000ps") ) -link_c0_l1cache_bus_link = sst.Link("link_c0_l1cache_bus_link") -link_c0_l1cache_bus_link.connect( (comp_c0_l1cache, "low_network_0", "10000ps"), (comp_bus, "high_network_0", "10000ps") ) +link_cpu0_l1cache_link.connect( (subcomp_iface0, "lowlink", "1000ps"), (comp_c0_l1cache, "highlink", "1000ps") ) link_cpu1_l1cache_link = sst.Link("link_cpu1_l1cache_link") -link_cpu1_l1cache_link.connect( (subcomp_iface1, "port", "1000ps"), (comp_c1_l1cache, "high_network_0", "1000ps") ) -link_c1_l1cache_bus_link = sst.Link("link_c1_l1cache_bus_link") -link_c1_l1cache_bus_link.connect( (comp_c1_l1cache, "low_network_0", "10000ps"), (comp_bus, "high_network_1", "10000ps") ) -link_bus_l2cache = sst.Link("link_bus_l2cache") -link_bus_l2cache.connect( (comp_bus, "low_network_0", "10000ps"), (comp_l2cache, "high_network_0", "10000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l2cache, "low_network_0", "10000ps"), (comp_memory, "direct_link", "10000ps") ) +link_cpu1_l1cache_link.connect( (subcomp_iface1, "lowlink", "1000ps"), (comp_c1_l1cache, "highlink", "1000ps") ) + +comp_bus.connect(highcomps=[comp_c0_l1cache,comp_c1_l1cache], lowcomps=[comp_l2cache]) + +link_mem = sst.Link("link_mem_link") +link_mem.connect( (comp_l2cache, "lowlink", "10000ps"), (comp_memory, "highlink", "10000ps") ) diff --git a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_coherence.py b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_coherence.py new file mode 100644 index 0000000000..990c71dc30 --- /dev/null +++ b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_coherence.py @@ -0,0 +1,292 @@ +# -*- coding: utf-8 -*- + +from sst_unittest import * +from sst_unittest_support import * +import os.path +import re + + +################################################################################ +################################################################################ + +class testcase_memHierarchy_coherence(SSTTestCase): + + def setUp(self): + super(type(self), self).setUp() + # Put test based setup code here. it is called once before every test + + def tearDown(self): + # Put test based teardown code here. it is called once after every test + super(type(self), self).tearDown() + +##### + # Run all test_coherence_1core.py tests with different seeds + def test_coherence_single_core_case0_mesi(self): + self.memHA_Template("1core", 0, [1571], "mesi") + + def test_coherence_single_core_case1_mesi(self): + self.memHA_Template("1core", 1, [893], "mesi") + + def test_coherence_single_core_case2_mesi(self): + self.memHA_Template("1core", 2, [922], "mesi") + + def test_coherence_single_core_case3_mesi(self): + self.memHA_Template("1core", 3, [24856], "mesi") + + def test_coherence_single_core_case4_mesi(self): + self.memHA_Template("1core", 4, [11], "mesi") + + def test_coherence_single_core_case5_mesi(self): + self.memHA_Template("1core", 5, [4836], "mesi") + + def test_coherence_single_core_case6_mesi(self): + self.memHA_Template("1core", 6, [323], "mesi") # Protocol doesn't matter but required param + + # Run all test_coherence_2core_3level.py tets with different seeds + def test_coherence_two_core_case0_mesi(self): + self.memHA_Template("2core_3level", 0, [9067, 935], "mesi") + + def test_coherence_two_core_case1_mesi(self): + self.memHA_Template("2core_3level", 1, [515, 49], "mesi") + + def test_coherence_two_core_case2_mesi(self): + self.memHA_Template("2core_3level", 2, [9873, 5768], "mesi") + + def test_coherence_two_core_case3_mesi(self): + self.memHA_Template("2core_3level", 3, [2315, 4623], "mesi") + + def test_coherence_two_core_case4(self): + self.memHA_Template("2core_3level", 4, [235, 157], "mesi") + + def test_coherence_two_core_case5(self): + self.memHA_Template("2core_3level", 5, [653, 5674], "mesi") + + def test_coherence_two_core_case6(self): + self.memHA_Template("2core_3level", 6, [573, 1736], "mesi") + + def test_coherence_two_core_case7(self): + self.memHA_Template("2core_3level", 7, [3475, 9774], "mesi") + + def test_coherence_two_core_case8(self): + self.memHA_Template("2core_3level", 8, [475, 4632], "mesi") + + def test_coherence_two_core_case9(self): + self.memHA_Template("2core_3level", 9, [583, 173], "mesi") + + def test_coherence_two_core_case10(self): + self.memHA_Template("2core_3level", 10, [183, 586], "mesi") + + def test_coherence_two_core_case11(self): + self.memHA_Template("2core_3level", 11, [86, 68], "mesi") + + def test_coherence_four_core_case0_mesi(self): + self.memHA_Template("4core_5level", 0, [1047, 3254, 5371, 4553], "mesi") + + def test_coherence_four_core_case1_mesi(self): + self.memHA_Template("4core_5level", 1, [0, 484, 55, 1823], "mesi") + + def test_coherence_four_core_case2_mesi(self): + self.memHA_Template("4core_5level", 2, [966, 5957, 885, 443], "mesi") + + def test_coherence_four_core_case3_mesi(self): + self.memHA_Template("4core_5level", 3, [5399, 2533, 433, 1834], "mesi") +##### + + def memHA_Template(self, testcase, testnum, cpu_seeds, protocol, + ignore_err_file=False, testtimeout=240): + + # Get the path to the test files + test_path = self.get_testsuite_dir() + outdir = self.get_test_output_run_dir() + tmpdir = self.get_test_output_tmp_dir() + + # Set file paths + test_name = "test_memHierarchy_coherence_{0}_case{1}_{2}".format(testcase, testnum, protocol) + sdlfile = "{0}/test_coherence_{1}.py".format(test_path, testcase) + reffile = "{0}/refFiles/{1}.out".format(test_path, test_name) + tmpfile = "{0}/{1}.tmp".format(outdir, test_name) + outfile = "{0}/{1}.out".format(outdir, test_name) + errfile = "{0}/{1}.err".format(outdir, test_name) + mpi_outfile = "{0}/{1}.testfile".format(outdir, test_name) + + # Create test arguments + args = '--model-options="{0}'.format(testnum) + for x in cpu_seeds: + args = args + " " + str(x) + args = args + " " + protocol + '"' + + ## Output only in debug mode + log_debug("testcase = {0}".format(test_name)) + log_debug("sdl file = {0}".format(sdlfile)) + log_debug("ref file = {0}".format(reffile)) + + # Run SST in the tests directory + self.run_sst(sdlfile, outfile, errfile, other_args=args, set_cwd=test_path, + timeout_sec=testtimeout, mpi_out_files=mpi_outfile) + + # Lines to ignore + # This is generated by SST when the number of ranks/threads > # of components + ignore_lines = ["WARNING: No components are assigned to"] + #These are warnings/info generated by SST/memH in debug mode + ignore_lines.append("Notice: memory controller's region is larger than the backend's mem_size") + ignore_lines.append("Region: start=") + + # Statistics that count occupancy on each cycle sometimes diff in parallel execution + # due to the synchronization interval sometimes allowing the clock to run ahead a cycle or so + tol_stats = { "outstanding_requests" : [0, 0, 20, 0, 0], # Only diffs in number of cycles + "total_cycles" : [20, 'X', 20, 20, 20], # This stat is set once at the end of sim. May vary in all fields + "MSHR_occupancy" : [0, 0, 20, 0, 0] } # Only diffs in number of cycles + + filesAreTheSame, statDiffs, othDiffs = testing_stat_output_diff(outfile, reffile, ignore_lines, tol_stats, True) + + # Perform the tests + if ignore_err_file is False: + if os_test_file(errfile, "-s"): + log_testing_note("memHA test {0} has a Non-Empty Error File {1}".format(testDataFileName, errfile)) + + if filesAreTheSame: + log_debug(" -- Output file {0} passed check against the Reference File {1}".format(outfile, reffile)) + else: + diffdata = self._prettyPrintDiffs(statDiffs, othDiffs) + log_failure(diffdata) + self.assertTrue(filesAreTheSame, "Output file {0} does not pass check against the Reference File {1} ".format(outfile, reffile)) + +### + # Remove lines containing any string found in 'remove_strs' from in_file + # If out_file != None, output is out_file + # Otherwise, in_file is overwritten + def _remove_lines_cleanup_file(self, remove_strs, in_file, out_file = None): + with open(in_file, 'r') as fp: + lines = fp.readlines() + + if out_file == None: + out_file = in_file + + with open(out_file, 'w') as fp: + fp.truncate(0) + for line in lines: + skip = False + for search in remove_strs: + if search in line: + skip = True + continue + if not skip: + fp.write(line) + + #################################### + # TODO move these two functions to the Core test frameworks utilities once they have matured + # These are used to diff statistic output files with some extra checking abilities + #################################### + + + # Return a parsed statistic or 'None' if the line is not a statistic + # Currently handles console output format only and integer statistic formats + # Stats are parsed into [component_name, stat_name, sum, sumSQ, count, min, max] + def _is_stat(self, line): + cons_accum = re.compile(r' ([\w.]+)\.(\w+) : Accumulator : Sum.(\w+) = (\d+); SumSQ.\w+ = (\d+); Count.\w+ = (\d+); Min.\w+ = (\d+); Max.\w+ = (\d+);') + m = cons_accum.match(line) + if m == None: + return None + stat = [m.group(1), m.group(2)] + if 'u' in m.group(3) or 'i' in m.group(3): + stat.append(int(m.group(4))) + stat.append(int(m.group(5))) + stat.append(int(m.group(6))) + stat.append(int(m.group(7))) + stat.append(int(m.group(8))) + else: + print("Stat parsing is not supported for datatype " + m.group(3)) + sys.exit(1) + return stat + + # Diff 'ref' against 'out' with special handling based on the other input options + # Input: ref - Reference filename + # Input: out - Output filename to diff against + # Input: ignore_lines - list of strings to ignore in the ref and out files. Any line that contains one of these strings will be ignored. + # Input: tol_stats - statistics to diff within a tolerance. + # A map of statistic name to a list of tolerances on each field (sum, sumSq, count, min, max). + # 'X' indicates don't care. All others are treated as a +/- on the ref value + # Input: new_stats - if True, the diff will ignore any new statistics in the out file that don't exist in the ref file + # Ouput: pass - whether the test passed (no diffs) or not + # Output: stat_diffs - list of diffs on statistics with '<' indicating ref file lines and '>' indicating out file lines + # Output: oth_diffs - list of diffs on non-statistic lines with '<' indicating ref file lines and '>' indicating out file lines + def _diffStatFiles(self, ref, out, ignore_lines, tol_stats, new_stats): + with open(ref, 'r') as fp: + ref_lines = fp.read().splitlines() + + with open(out, 'r') as fp: + out_lines = fp.read().splitlines() + + # Sort by stat/not stat + ref_stats = [] + ref_oth = [] + out_stats = [] + out_oth = [] + + for line in ref_lines: + stat = self._is_stat(line) + if stat != None: + ref_stats.append(stat) + elif not any(x in line for x in ignore_lines): + ref_oth.append(line) + + for line in out_lines: + stat = self._is_stat(line) + if stat == None: + if line in ref_oth: + ref_oth.remove(line) # Didn't diff + elif not any(x in line for x in ignore_lines): + out_oth.append(line) # Will diff + else: + # Filter out exact matches immediately + if stat in ref_stats: + ref_stats.remove(stat) + # Filter out new statistics (stats not in ref file) if requested + elif not new_stats or any((row[0] == stat[0] and row[1] == stat[1]) for row in ref_stats): + # Check for diff within tolerances + if stat[1] in tol_stats: + found = False + for s in ref_stats: + if s[0] == stat[0] and s[1] == stat[1]: + ref = s + found = True + break + if found: + diffs = False + tol = tol_stats[stat[1]] + for i, t in enumerate(tol): + if t != 'X' and ((ref[2+i] - t) > stat[2+i] or (ref[2+i] + t) < stat[2+i]): + diffs = True + out_stats.append(stat) + break + if not diffs: + ref_stats.remove(ref) + else: # Tolerance on stat but doesn't match a stat in ref + out_stats.append(stat) + else: # No tolerance on stat and doesn't match a stat in ref + out_stats.append(stat) + + stat_diffs = [ ['<',x[0],x[1],x[2],x[3],x[4],x[5],x[6]] for x in ref_stats ] + stat_diffs += [ ['>',x[0],x[1],x[2],x[3],x[4],x[5],x[6]] for x in out_stats ] + + oth_diffs = [ ['<',x] for x in ref_oth ] + oth_diffs += [ ['>',x] for x in out_oth ] + + if len(stat_diffs) > 0 or len(oth_diffs) > 0: + return False, stat_diffs, oth_diffs + else: + return True, stat_diffs, oth_diffs + + def _prettyPrintDiffs(self, stat_diff, oth_diff): + out = "" + if len(stat_diff) != 0: + out = "Statistic diffs:\n" + for x in stat_diff: + out += (x[0] + " " + ",".join(str(y) for y in x[1:]) + "\n") + + if len(oth_diff) != 0: + out += "Non-statistic diffs:\n" + for x in oth_diff: + out += x[0] + " " + x[1] + "\n" + + return out diff --git a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_hybridsim.py b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_hybridsim.py index e96370ec55..5f9a4b9f26 100644 --- a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_hybridsim.py +++ b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_hybridsim.py @@ -31,7 +31,7 @@ def hybridsim_Template(self, testcase, testtimeout=120): # Set the Path of the HybridSim Lib into the Env so that the SDL file # can pull it - lib_dir = sstsimulator_conf_get_value_str("HYBRIDSIM", "LIBDIR", "LIBDIR_UNDEFINED") + lib_dir = sstsimulator_conf_get_value("HYBRIDSIM", "LIBDIR", str, "LIBDIR_UNDEFINED") os.environ['SST_HYBRIDSIM_LIB_DIR'] = lib_dir # Set the various file paths diff --git a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_memHA.py b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_memHA.py index ffe0b33772..9e36ac021c 100644 --- a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_memHA.py +++ b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_memHA.py @@ -95,6 +95,14 @@ def test_memHA_CustomCmdGoblin_2(self): @skip_on_sstsimulator_conf_empty_str("GOBLIN_HMCSIM", "LIBDIR", "GOBLIN_HMCSIM is not included as part of this build") def test_memHA_CustomCmdGoblin_3(self): self.memHA_Template("CustomCmdGoblin_3") + + @skip_on_sstsimulator_conf_empty_str("RAMULATOR", "LIBDIR", "RAMULATOR is not included as part of this build") + def test_memHierarchy_BackendRamulator_1(self): + self.memHA_Template("BackendRamulator_1") + + @skip_on_sstsimulator_conf_empty_str("RAMULATOR", "LIBDIR", "RAMULATOR is not included as part of this build") + def test_memHierarchy_BackendRamulator_2(self): + self.memHA_Template("BackendRamulator_2") def test_memHA_BackendTimingDRAM_1(self): self.memHA_Template("BackendTimingDRAM_1") diff --git a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_sdl.py b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_sdl.py index cb4e7290bb..f13f427b9d 100644 --- a/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_sdl.py +++ b/src/sst/elements/memHierarchy/tests/testsuite_default_memHierarchy_sdl.py @@ -18,27 +18,21 @@ def tearDown(self): ##### def test_memHierarchy_sdl_1(self): - # sdl-1 Simple CPU + 1 level cache + Memory self.memHierarchy_Template("sdl-1") def test_memHierarchy_sdl_2(self): - # sdl-2 Simple CPU + 1 level cache + DRAMSim Memory self.memHierarchy_Template("sdl-2") def test_memHierarchy_sdl_3(self): - # sdl-3 Simple CPU + 1 level cache + DRAMSim Memory (alternate block size) self.memHierarchy_Template("sdl-3") def test_memHierarchy_sdl2_1(self): - # sdl2-1 Simple CPU + 2 levels cache + Memory self.memHierarchy_Template("sdl2-1") def test_memHierarchy_sdl3_1(self): - # sdl3-1 2 Simple CPUs + 2 levels cache + Memory self.memHierarchy_Template("sdl3-1") def test_memHierarchy_sdl3_2(self): - # sdl3-2 2 Simple CPUs + 2 levels cache + DRAMSim Memory self.memHierarchy_Template("sdl3-2") def test_memHierarchy_sdl3_3(self): @@ -48,18 +42,10 @@ def test_memHierarchy_sdl4_1(self): self.memHierarchy_Template("sdl4-1") def test_memHierarchy_sdl4_2(self): - self.memHierarchy_Template("sdl4-2", ignore_err_file=True) - - @skip_on_sstsimulator_conf_empty_str("RAMULATOR", "LIBDIR", "RAMULATOR is not included as part of this build") - def test_memHierarchy_sdl4_2_ramulator(self): - self.memHierarchy_Template("sdl4-2-ramulator") + self.memHierarchy_Template("sdl4-2") def test_memHierarchy_sdl5_1(self): - self.memHierarchy_Template("sdl5-1", ignore_err_file=True) - - @skip_on_sstsimulator_conf_empty_str("RAMULATOR", "LIBDIR", "RAMULATOR is not included as part of this build") - def test_memHierarchy_sdl5_1_ramulator(self): - self.memHierarchy_Template("sdl5-1-ramulator") + self.memHierarchy_Template("sdl5-1") def test_memHierarchy_sdl8_1(self): self.memHierarchy_Template("sdl8-1") @@ -84,7 +70,7 @@ def memHierarchy_Template(self, testcase, ignore_err_file=False): outdir = self.get_test_output_run_dir() tmpdir = self.get_test_output_tmp_dir() - # Some tweeking of file names are due to inconsistencys with testcase name + # Some tweeking of file names are due to inconsistencies with testcase name testcasename_sdl = testcase.replace("_MC", "") testcasename_out = testcase.replace("-", "_") diff --git a/src/sst/elements/memHierarchy/util.h b/src/sst/elements/memHierarchy/util.h index 54dfdccaa0..f47678500e 100644 --- a/src/sst/elements/memHierarchy/util.h +++ b/src/sst/elements/memHierarchy/util.h @@ -19,6 +19,7 @@ #include #include #include +#include using namespace std; @@ -49,18 +50,11 @@ namespace MemHierarchy { #define _L11_ CALL_INFO,11,0 //Data values #define _L20_ CALL_INFO,20,0 //Debug at function call granularity -// Type conversions - TODO are these used anywhere? -const unsigned int kibi = 1024; -const unsigned int mebi = kibi * 1024; -const unsigned int gibi = mebi * 1024; -const unsigned int tebi = gibi * 1024; -const unsigned int pebi = tebi * 1024; -const unsigned int exbi = pebi * 1024; - typedef uint64_t Addr; #ifndef PRI_ADDR #define PRI_ADDR PRIx64 #endif +#define NO_ADDR std::numeric_limits::max(); // Event attributes /* diff --git a/src/sst/elements/mercury/components/nic.cc b/src/sst/elements/mercury/components/nic.cc index 9ab8eb9794..9749f400be 100644 --- a/src/sst/elements/mercury/components/nic.cc +++ b/src/sst/elements/mercury/components/nic.cc @@ -48,7 +48,8 @@ NIC::NIC(uint32_t id, SST::Params& params, NodeBase* parent) : ack_queue_.resize(1); // FIXME needs to be a parameter - mtu_ = 2048; + mtu_ = params.find("mtu", 4096); + out_->debug(CALL_INFO, 1, 0, "setting mtu to %d\n", mtu_); } std::string @@ -188,7 +189,6 @@ NIC::sendWhatYouCan(int vn) { bool NIC::sendWhatYouCan(int vn, Pending& p) { - int seqnum = 0; uint64_t next_bytes = std::min(uint64_t(mtu_), p.bytesLeft); uint32_t next_bits = next_bytes * 8; //this is fine for 32-bits while (link_control_->spaceToSend(vn, next_bits)){ diff --git a/src/sst/elements/mercury/libraries/compute/instruction_processor.cc b/src/sst/elements/mercury/libraries/compute/instruction_processor.cc index 2f0ac9af42..917e11deaa 100644 --- a/src/sst/elements/mercury/libraries/compute/instruction_processor.cc +++ b/src/sst/elements/mercury/libraries/compute/instruction_processor.cc @@ -28,7 +28,7 @@ mem_(mem), nodeCL_(node) double parallelism = params.find("parallelism", 1.0); - freq_ = params.find("frequency", "2.1 GHz").getValue().toDouble(); + freq_ = params.find("frequency", "2.0 GHz").getValue().toDouble(); mem_freq_ = freq_; tflop_ = TimeDelta(1.0 / freq_ / parallelism); diff --git a/src/sst/elements/mercury/libraries/compute/memory_model.cc b/src/sst/elements/mercury/libraries/compute/memory_model.cc index 600577686c..ea142800b0 100644 --- a/src/sst/elements/mercury/libraries/compute/memory_model.cc +++ b/src/sst/elements/mercury/libraries/compute/memory_model.cc @@ -30,7 +30,7 @@ MemoryModel::MemoryModel(SST::Params ¶ms, NodeCL* parent) : { flow_mtu_ = params.find("flow_mtu", "512").getRoundedValue(); - auto max_bw = params.find("channel_bandwidth", "10.0 GB/s"); + auto max_bw = params.find("channel_bandwidth", "12.0 GB/s"); channel_byte_delay_ = TimeDelta(max_bw.getValue().inverse().toDouble()); int num_channels = params.find("num_channels",4); diff --git a/src/sst/elements/mercury/pymercury.py b/src/sst/elements/mercury/pymercury.py index d35e4d375d..327fecac04 100644 --- a/src/sst/elements/mercury/pymercury.py +++ b/src/sst/elements/mercury/pymercury.py @@ -74,7 +74,9 @@ def build(self,nid,lid,nranks): class HgNIC(TemplateBase): def __init__(self): TemplateBase.__init__(self) - self._declareParams("params",["verbose",]) + self._declareParams("params",["verbose", + "mtu", + ]) self._subscribeToPlatformParamSet("nic") def build(self,comp,slot): @@ -104,6 +106,9 @@ def __init__(self): "rdma_pin_latency", "rdma_page_delay", "rdma_page_size", + "max_vshort_msg_size", + "max_eager_msg_size", + "use_put_window", "compute_library_access_width", "compute_library_loop_overhead", ], diff --git a/src/sst/elements/merlin/interfaces/linkControl.h b/src/sst/elements/merlin/interfaces/linkControl.h index 8b97c1dd72..5a278cc345 100644 --- a/src/sst/elements/merlin/interfaces/linkControl.h +++ b/src/sst/elements/merlin/interfaces/linkControl.h @@ -64,7 +64,7 @@ class LinkControl : public SST::Interfaces::SimpleNetwork { {"output_buf_size", "Size of output buffers specified in b or B (can include SI prefix)."}, // {"network_inspectors", "Comma separated list of network inspectors to put on output ports.", ""}, {"job_id", "ID of the job this enpoint is part of.", "" }, - {"Job_size", "Number of nodes in the job this endpoint is part of.",""}, + {"job_size", "Number of nodes in the job this endpoint is part of.",""}, {"logical_nid", "My logical NID", "" }, {"use_nid_remap", "If true, will remap logical nids in job to physical ids", "false" }, {"nid_map_name", "Base name of shared region where my NID map will be located. If empty, no NID map will be used.",""}, diff --git a/src/sst/elements/messier/tests/gupsgen.py b/src/sst/elements/messier/tests/gupsgen.py index c7a23e8618..20788a040f 100644 --- a/src/sst/elements/messier/tests/gupsgen.py +++ b/src/sst/elements/messier/tests/gupsgen.py @@ -106,8 +106,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (nvm_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (nvm_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/messier/tests/gupsgen_2RANKS.py b/src/sst/elements/messier/tests/gupsgen_2RANKS.py index f533569184..aeaf4e19b2 100644 --- a/src/sst/elements/messier/tests/gupsgen_2RANKS.py +++ b/src/sst/elements/messier/tests/gupsgen_2RANKS.py @@ -105,8 +105,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (nvm_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (nvm_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/messier/tests/gupsgen_fastNVM.py b/src/sst/elements/messier/tests/gupsgen_fastNVM.py index 083020651b..475aab7727 100644 --- a/src/sst/elements/messier/tests/gupsgen_fastNVM.py +++ b/src/sst/elements/messier/tests/gupsgen_fastNVM.py @@ -107,8 +107,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (nvm_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (nvm_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen.out b/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen.out index a9effb32ba..8bab997f58 100644 --- a/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen.out +++ b/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen.out @@ -89,13 +89,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,6 +125,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9747; SumSQ.u64 = 9747; Count.u64 = 9747; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -170,14 +174,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 15154; SumSQ.u64 = 15154; Count.u64 = 15154; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 164075692; SumSQ.u64 = 4035098210; Count.u64 = 6686222; Min.u64 = 0; Max.u64 = 32; diff --git a/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out b/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out index 670aa10621..69cfa62860 100644 --- a/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out +++ b/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_2RANKS.out @@ -89,13 +89,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,6 +125,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9743; SumSQ.u64 = 9743; Count.u64 = 9743; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -170,14 +174,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 15169; SumSQ.u64 = 15169; Count.u64 = 15169; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 162660643; SumSQ.u64 = 4006957219; Count.u64 = 6617276; Min.u64 = 0; Max.u64 = 32; diff --git a/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out b/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out index 96b133b591..d0d00c538c 100644 --- a/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out +++ b/src/sst/elements/messier/tests/refFiles/test_Messier_gupsgen_fastNVM.out @@ -89,13 +89,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,6 +125,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9739; SumSQ.u64 = 9739; Count.u64 = 9739; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -170,14 +174,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 15160; SumSQ.u64 = 15160; Count.u64 = 15160; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 33903656; SumSQ.u64 = 832396136; Count.u64 = 1384124; Min.u64 = 0; Max.u64 = 33; diff --git a/src/sst/elements/messier/tests/refFiles/test_Messier_stencil3dbench_messier.out b/src/sst/elements/messier/tests/refFiles/test_Messier_stencil3dbench_messier.out index 1e4c77195d..957a268dee 100644 --- a/src/sst/elements/messier/tests/refFiles/test_Messier_stencil3dbench_messier.out +++ b/src/sst/elements/messier/tests/refFiles/test_Messier_stencil3dbench_messier.out @@ -89,13 +89,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 108864; SumSQ.u64 = 108864; Count.u64 = 108864; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -103,7 +106,7 @@ After initialization l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 399; SumSQ.u64 = 399; Count.u64 = 399; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,6 +125,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 104885; SumSQ.u64 = 104885; Count.u64 = 104885; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1589; SumSQ.u64 = 1589; Count.u64 = 1589; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -170,14 +174,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 5085671; SumSQ.u64 = 85988825; Count.u64 = 321244; Min.u64 = 0; Max.u64 = 35; diff --git a/src/sst/elements/messier/tests/refFiles/test_Messier_streambench_messier.out b/src/sst/elements/messier/tests/refFiles/test_Messier_streambench_messier.out index a0757aa9b2..06e2d24b80 100644 --- a/src/sst/elements/messier/tests/refFiles/test_Messier_streambench_messier.out +++ b/src/sst/elements/messier/tests/refFiles/test_Messier_streambench_messier.out @@ -89,13 +89,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -103,7 +106,7 @@ After initialization l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 2313; SumSQ.u64 = 2313; Count.u64 = 2313; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,6 +125,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 1027; SumSQ.u64 = 1027; Count.u64 = 1027; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 3972; SumSQ.u64 = 3972; Count.u64 = 3972; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -170,14 +174,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 7501; SumSQ.u64 = 7501; Count.u64 = 7501; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 35014267; SumSQ.u64 = 783382045; Count.u64 = 1613536; Min.u64 = 0; Max.u64 = 37; diff --git a/src/sst/elements/messier/tests/stencil3dbench_messier.py b/src/sst/elements/messier/tests/stencil3dbench_messier.py index bd4c4097e9..79bd3d832e 100644 --- a/src/sst/elements/messier/tests/stencil3dbench_messier.py +++ b/src/sst/elements/messier/tests/stencil3dbench_messier.py @@ -100,8 +100,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (nvm_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (nvm_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/messier/tests/streambench_messier.py b/src/sst/elements/messier/tests/streambench_messier.py index 97b4ff15cb..64683affbc 100644 --- a/src/sst/elements/messier/tests/streambench_messier.py +++ b/src/sst/elements/messier/tests/streambench_messier.py @@ -99,8 +99,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (nvm_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (nvm_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/copybench.py b/src/sst/elements/miranda/tests/copybench.py index 33fcfd0f3f..c79c35362e 100644 --- a/src/sst/elements/miranda/tests/copybench.py +++ b/src/sst/elements/miranda/tests/copybench.py @@ -54,8 +54,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream1-trace-map.py b/src/sst/elements/miranda/tests/goblin_singlestream1-trace-map.py index 35ad2840db..ed40bdbe7f 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream1-trace-map.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream1-trace-map.py @@ -60,8 +60,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream1-trace.py b/src/sst/elements/miranda/tests/goblin_singlestream1-trace.py index 8e71aa1e92..cb3b339437 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream1-trace.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream1-trace.py @@ -58,8 +58,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream1.py b/src/sst/elements/miranda/tests/goblin_singlestream1.py index 580470e9c2..1face79bbe 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream1.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream1.py @@ -55,8 +55,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream2-trace.py b/src/sst/elements/miranda/tests/goblin_singlestream2-trace.py index 7717d874de..9e65d1c952 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream2-trace.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream2-trace.py @@ -67,8 +67,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream2.py b/src/sst/elements/miranda/tests/goblin_singlestream2.py index 1f199bd15e..48b1aeaeb6 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream2.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream2.py @@ -62,8 +62,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream3-trace.py b/src/sst/elements/miranda/tests/goblin_singlestream3-trace.py index d808b39119..753e97e502 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream3-trace.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream3-trace.py @@ -68,8 +68,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_singlestream3.py b/src/sst/elements/miranda/tests/goblin_singlestream3.py index 6431f32e50..387919f90e 100644 --- a/src/sst/elements/miranda/tests/goblin_singlestream3.py +++ b/src/sst/elements/miranda/tests/goblin_singlestream3.py @@ -63,8 +63,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/goblin_streambench_customcmd.py b/src/sst/elements/miranda/tests/goblin_streambench_customcmd.py index 1f3c2039f2..c8da61ff98 100644 --- a/src/sst/elements/miranda/tests/goblin_streambench_customcmd.py +++ b/src/sst/elements/miranda/tests/goblin_streambench_customcmd.py @@ -59,8 +59,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/gupsgen.py b/src/sst/elements/miranda/tests/gupsgen.py index 5f97e7291a..03f2b237a6 100644 --- a/src/sst/elements/miranda/tests/gupsgen.py +++ b/src/sst/elements/miranda/tests/gupsgen.py @@ -53,8 +53,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/hbm_singlestream1-trace.py b/src/sst/elements/miranda/tests/hbm_singlestream1-trace.py index 7c0d5f7f92..3cc6a71e01 100644 --- a/src/sst/elements/miranda/tests/hbm_singlestream1-trace.py +++ b/src/sst/elements/miranda/tests/hbm_singlestream1-trace.py @@ -58,8 +58,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/hbm_singlestream1.py b/src/sst/elements/miranda/tests/hbm_singlestream1.py index 26746f49e3..5db3d9afad 100644 --- a/src/sst/elements/miranda/tests/hbm_singlestream1.py +++ b/src/sst/elements/miranda/tests/hbm_singlestream1.py @@ -58,8 +58,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/inorderstream.py b/src/sst/elements/miranda/tests/inorderstream.py index 600f96da99..6f51898cf2 100644 --- a/src/sst/elements/miranda/tests/inorderstream.py +++ b/src/sst/elements/miranda/tests/inorderstream.py @@ -54,8 +54,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/randomgen.py b/src/sst/elements/miranda/tests/randomgen.py index 3601112255..df94767545 100644 --- a/src/sst/elements/miranda/tests/randomgen.py +++ b/src/sst/elements/miranda/tests/randomgen.py @@ -54,8 +54,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out index 75e8a65371..fee25439cd 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_copybench.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 65536; SumSQ.u64 = 65536; Count.u64 = 65536; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 65536; SumSQ.u64 = 65536; Count.u64 = 65536; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -101,7 +104,7 @@ l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 8176; SumSQ.u64 = 8176; Count.u64 = 8176; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 9453; SumSQ.u64 = 9453; Count.u64 = 9453; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9192; SumSQ.u64 = 9192; Count.u64 = 9192; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 65536; SumSQ.u64 = 65536; Count.u64 = 65536; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 16384; SumSQ.u64 = 16384; Count.u64 = 16384; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 212221252; SumSQ.u64 = 5472454654; Count.u64 = 8604201; Min.u64 = 0; Max.u64 = 32; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out index 802c5e1276..be681e0ec8 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_gupsgen.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9738; SumSQ.u64 = 9738; Count.u64 = 9738; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 15216; SumSQ.u64 = 15216; Count.u64 = 15216; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 30777174; SumSQ.u64 = 748714514; Count.u64 = 1267822; Min.u64 = 0; Max.u64 = 31; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out index 1ce2480af1..a2f955c015 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_inorderstream.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -101,7 +104,7 @@ l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 1239; SumSQ.u64 = 1239; Count.u64 = 1239; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 469; SumSQ.u64 = 469; Count.u64 = 469; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 3752; SumSQ.u64 = 3752; Count.u64 = 3752; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 60230526; SumSQ.u64 = 1588359544; Count.u64 = 2307052; Min.u64 = 0; Max.u64 = 35; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out index 8eba8546df..9ea2d6121c 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_randomgen.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 250060; SumSQ.u64 = 250060; Count.u64 = 250060; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 249940; SumSQ.u64 = 249940; Count.u64 = 249940; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 5644; SumSQ.u64 = 5644; Count.u64 = 5644; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 3936; SumSQ.u64 = 3936; Count.u64 = 3936; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 249940; SumSQ.u64 = 249940; Count.u64 = 249940; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 615156; SumSQ.u64 = 615156; Count.u64 = 615156; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1234028690; SumSQ.u64 = 1726883806; Count.u64 = 991748945; Min.u64 = 0; Max.u64 = 2; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out index dea44af2ac..63c3dd9dc9 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_revsinglestream.out @@ -91,13 +91,16 @@ ReverseSingleStreamGenerator[build]: Stride: 8 l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 8192; SumSQ.u64 = 8192; Count.u64 = 8192; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -124,6 +127,7 @@ ReverseSingleStreamGenerator[build]: Stride: 8 l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -172,14 +176,18 @@ ReverseSingleStreamGenerator[build]: Stride: 8 l1cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 8192; SumSQ.u64 = 8192; Count.u64 = 8192; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 280756; SumSQ.u64 = 4809140; Count.u64 = 16412; Min.u64 = 0; Max.u64 = 20; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out index 96a91ff948..8b07987270 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_singlestream.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 562500; SumSQ.u64 = 562500; Count.u64 = 562500; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -101,7 +104,7 @@ l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 31; SumSQ.u64 = 31; Count.u64 = 31; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 32; SumSQ.u64 = 32; Count.u64 = 32; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 46873; SumSQ.u64 = 46873; Count.u64 = 46873; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 62510; SumSQ.u64 = 62510; Count.u64 = 62510; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1047135343; SumSQ.u64 = 17483267405; Count.u64 = 62908266; Min.u64 = 0; Max.u64 = 17; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out index 5cae2ade0c..fd175c4051 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_stencil3dbench.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 108864; SumSQ.u64 = 108864; Count.u64 = 108864; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -101,7 +104,7 @@ l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 399; SumSQ.u64 = 399; Count.u64 = 399; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 104409; SumSQ.u64 = 104409; Count.u64 = 104409; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 1813; SumSQ.u64 = 1813; Count.u64 = 1813; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1303; SumSQ.u64 = 1303; Count.u64 = 1303; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1312589; SumSQ.u64 = 18361385; Count.u64 = 115412; Min.u64 = 0; Max.u64 = 34; diff --git a/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out b/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out index 1e82e503fe..137d8eea2f 100644 --- a/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out +++ b/src/sst/elements/miranda/tests/refFiles/test_miranda_streambench.out @@ -87,13 +87,16 @@ l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -101,7 +104,7 @@ l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 2313; SumSQ.u64 = 2313; Count.u64 = 2313; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -120,6 +123,7 @@ l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 103; SumSQ.u64 = 103; Count.u64 = 103; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -168,14 +172,18 @@ l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 7500; SumSQ.u64 = 7500; Count.u64 = 7500; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 7190639; SumSQ.u64 = 199111497; Count.u64 = 264438; Min.u64 = 0; Max.u64 = 33; diff --git a/src/sst/elements/miranda/tests/revsinglestream.py b/src/sst/elements/miranda/tests/revsinglestream.py index eec05f65cc..3c7bd8fac3 100644 --- a/src/sst/elements/miranda/tests/revsinglestream.py +++ b/src/sst/elements/miranda/tests/revsinglestream.py @@ -55,8 +55,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/singlestream.py b/src/sst/elements/miranda/tests/singlestream.py index defe3e195b..b7115ce491 100644 --- a/src/sst/elements/miranda/tests/singlestream.py +++ b/src/sst/elements/miranda/tests/singlestream.py @@ -54,8 +54,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/spmvgen.py b/src/sst/elements/miranda/tests/spmvgen.py index dadf2f755a..d0207901ca 100644 --- a/src/sst/elements/miranda/tests/spmvgen.py +++ b/src/sst/elements/miranda/tests/spmvgen.py @@ -91,17 +91,17 @@ # Define the simulation links cpu0_cache_link = sst.Link("cpu0_cache_link") cpu1_cache_link = sst.Link("cpu1_cache_link") -cpu0_cache_link.connect( (cpu0, "cache_link", "1000ps"), (l1cache0, "high_network_0", "1000ps") ) -cpu1_cache_link.connect( (cpu1, "cache_link", "1000ps"), (l1cache1, "high_network_0", "1000ps") ) +cpu0_cache_link.connect( (cpu0, "cache_link", "1000ps"), (l1cache0, "highlink", "1000ps") ) +cpu1_cache_link.connect( (cpu1, "cache_link", "1000ps"), (l1cache1, "highlink", "1000ps") ) cpu0_cache_link.setNoCut() cpu1_cache_link.setNoCut() l1cache0_bus_link = sst.Link("l1cache0_bus_link") l1cache1_bus_link = sst.Link("l1cache1_bus_link") -l1cache0_bus_link.connect( (l1cache0, "low_network_0", "50ps"), (bus, "high_network_0", "50ps") ) -l1cache1_bus_link.connect( (l1cache1, "low_network_0", "50ps"), (bus, "high_network_1", "50ps") ) +l1cache0_bus_link.connect( (l1cache0, "lowlink", "50ps"), (bus, "highlink", "50ps") ) +l1cache1_bus_link.connect( (l1cache1, "lowlink", "50ps"), (bus, "high_network_1", "50ps") ) bus_l2cache_link = sst.Link("bus_l2cache_link") -bus_l2cache_link.connect( (bus, "low_network_0", "50ps"), (l2cache, "high_network_0", "50ps") ) +bus_l2cache_link.connect( (bus, "lowlink", "50ps"), (l2cache, "highlink", "50ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (l2cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (l2cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/stencil3dbench.py b/src/sst/elements/miranda/tests/stencil3dbench.py index 83e7a94fd2..c9ece0db11 100644 --- a/src/sst/elements/miranda/tests/stencil3dbench.py +++ b/src/sst/elements/miranda/tests/stencil3dbench.py @@ -55,8 +55,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/streambench.py b/src/sst/elements/miranda/tests/streambench.py index f58b8882c1..b6e31a3954 100644 --- a/src/sst/elements/miranda/tests/streambench.py +++ b/src/sst/elements/miranda/tests/streambench.py @@ -54,8 +54,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/miranda/tests/test_subcomp.py b/src/sst/elements/miranda/tests/test_subcomp.py index cb1bc1a277..31a6906a5b 100644 --- a/src/sst/elements/miranda/tests/test_subcomp.py +++ b/src/sst/elements/miranda/tests/test_subcomp.py @@ -55,8 +55,8 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_cpu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +ink_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/opal/tests/basic_1node_1smp.py b/src/sst/elements/opal/tests/basic_1node_1smp.py index cd3cf44586..ec8ce8ddd2 100644 --- a/src/sst/elements/opal/tests/basic_1node_1smp.py +++ b/src/sst/elements/opal/tests/basic_1node_1smp.py @@ -211,18 +211,18 @@ def getNextPort(self): l1 = sst.Component("l1cache_" + str(next_core), "memHierarchy.Cache") l1.addParams(l1_params) - l1_cpulink = l1.setSubComponent("cpulink", "memHierarchy.MemLink") - l1_memlink = l1.setSubComponent("memlink", "memHierarchy.MemLink") - l1_cpulink.addParams(link_params) - l1_memlink.addParams(link_params) + l1_highlink = l1.setSubComponent("highlink", "memHierarchy.MemLink") + l1_lowlink = l1.setSubComponent("lowlink", "memHierarchy.MemLink") + l1_highlink.addParams(link_params) + l1_lowlink.addParams(link_params) l2 = sst.Component("l2cache_" + str(next_core), "memHierarchy.Cache") l2.addParams(l2_params) - l2_cpulink = l2.setSubComponent("cpulink", "memHierarchy.MemLink") - l2_memlink = l2.setSubComponent("memlink", "Opal.OpalMemNIC") - l2_cpulink.addParams(link_params) - l2_memlink.addParams(nic_params) - l2_memlink.addParams({ "group" : 1}) + l2_highlink = l2.setSubComponent("highlink", "memHierarchy.MemLink") + l2_lowlink = l2.setSubComponent("lowlink", "Opal.OpalMemNIC") + l2_highlink.addParams(link_params) + l2_lowlink.addParams(nic_params) + l2_lowlink.addParams({ "group" : 1}) arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core)) @@ -233,22 +233,22 @@ def getNextPort(self): if next_core < cores//2: arielMMULink.connect((ariel, "cache_link_%d"%next_core, "300ps"), (mmu, "cpu_to_mmu%d"%next_core, "300ps")) ArielOpalLink.connect((memmgr, "opal_link_%d"%next_core, "300ps"), (opal, "coreLink%d"%(next_core), "300ps")) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core, "300ps"), (l1_cpulink, "port", "300ps")) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core, "300ps"), (l1_highlink, "port", "300ps")) PTWOpalLink.connect( (pagefaulthandler, "opal_link_%d"%next_core, "300ps"), (opal, "mmuLink%d"%(next_core), "300ps") ) else: - PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core-cores//2), "300ps"), (l1_cpulink, "port", "300ps")) + PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core-cores//2), "300ps"), (l1_highlink, "port", "300ps")) l2_core_link = sst.Link("l2cache_" + str(next_core) + "_link") - l2_core_link.connect((l1_memlink, "port", "300ps"), (l2_cpulink, "port", "300ps")) + l2_core_link.connect((l1_lowlink, "port", "300ps"), (l2_highlink, "port", "300ps")) l2_ring_link = sst.Link("l2_ring_link_" + str(next_core)) - l2_ring_link.connect((l2_memlink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) + l2_ring_link.connect((l2_lowlink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) l3cache = sst.Component("l3cache", "memHierarchy.Cache") l3cache.addParams(l3_params) -l3_link = l3cache.setSubComponent("cpulink", "Opal.OpalMemNIC") +l3_link = l3cache.setSubComponent("highlink", "Opal.OpalMemNIC") l3cache.addParams({ "slice_id" : 0 }) l3_link.addParams(nic_params) l3_link.addParams({ @@ -286,7 +286,7 @@ def getNextPort(self): "backend.channel.rank.bank.transactionQ" : "memHierarchy.fifoTransactionQ", "backend.channel.rank.bank.pagePolicy.close" : 1, }) -mem_link = mem.setSubComponent("cpulink", "memHierarchy.MemLink") +mem_link = mem.setSubComponent("highlink", "memHierarchy.MemLink") mem_link.addParams({ "shared_memory": 1, "node" : 0 @@ -300,11 +300,11 @@ def getNextPort(self): #"debug_level" : 10, }) -dc_cpulink = dc.setSubComponent("cpulink", "Opal.OpalMemNIC") -dc_memlink = dc.setSubComponent("memlink", "memHierarchy.MemLink") -dc_memlink.addParams(link_params) -dc_cpulink.addParams(nic_params) -dc_cpulink.addParams({ +dc_highlink = dc.setSubComponent("highlink", "Opal.OpalMemNIC") +dc_lowlink = dc.setSubComponent("lowlink", "memHierarchy.MemLink") +dc_lowlink.addParams(link_params) +dc_highlink.addParams(nic_params) +dc_highlink.addParams({ "group" : 3, "addr_range_start" : 0, "addr_range_end" : (local_memory_capacity*1024*1024)-1, @@ -316,10 +316,10 @@ def getNextPort(self): }) memLink = sst.Link("mem_link") -memLink.connect((mem_link, "port", "300ps"), (dc_memlink, "port", "300ps")) +memLink.connect((mem_link, "port", "300ps"), (dc_lowlink, "port", "300ps")) netLink = sst.Link("dc_link") -netLink.connect((dc_cpulink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) +netLink.connect((dc_highlink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) @@ -345,7 +345,7 @@ def getNextPort(self): "clock" : clock, }) -ext_mem_link = ext_mem.setSubComponent("cpulink", "memHierarchy.MemLink") +ext_mem_link = ext_mem.setSubComponent("highlink", "memHierarchy.MemLink") ext_mem_link.addParams({ "node" : 9999, }) ## does not belong to any node ext_dc = sst.Component("ExtMemDc", "memHierarchy.DirectoryController") @@ -353,9 +353,9 @@ def getNextPort(self): "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize "clock": "1GHz", }) -ext_dc_cpulink = ext_dc.setSubComponent("cpulink", "Opal.OpalMemNIC") -ext_dc_memlink = ext_dc.setSubComponent("memlink", "memHierarchy.MemLink") -ext_dc_cpulink.addParams({ +ext_dc_highlink = ext_dc.setSubComponent("highlink", "Opal.OpalMemNIC") +ext_dc_lowlink = ext_dc.setSubComponent("lowlink", "memHierarchy.MemLink") +ext_dc_highlink.addParams({ "network_bw": "80GiB/s", "addr_range_start" : (local_memory_capacity*1024*1024), "addr_range_end" : (local_memory_capacity*1024*1024) + (shared_memory_capacity*1024*1024) -1, @@ -385,10 +385,10 @@ def getNextPort(self): link_nvm_bus_link.connect( (messier, "bus", "50ps"), (ext_memory, "nvm_link", "50ps") ) extmemLink = sst.Link("External_mem_dc_link") -extmemLink.connect( (ext_dc_memlink, "port", "500ps"), (ext_mem_link, "port", "500ps") ) +extmemLink.connect( (ext_dc_lowlink, "port", "500ps"), (ext_mem_link, "port", "500ps") ) ext_dcLink = sst.Link("External_mem_link") -ext_dcLink.connect( (ext_dc_cpulink, "port", "500ps"), (external_network.rtr, "port%d"%port, "500ps") ) +ext_dcLink.connect( (ext_dc_highlink, "port", "500ps"), (external_network.rtr, "port%d"%port, "500ps") ) diff --git a/src/sst/elements/opal/tests/basic_2node_1smp.py b/src/sst/elements/opal/tests/basic_2node_1smp.py index 32dc35d3c6..8d2bab839f 100644 --- a/src/sst/elements/opal/tests/basic_2node_1smp.py +++ b/src/sst/elements/opal/tests/basic_2node_1smp.py @@ -223,22 +223,22 @@ def getNextPort(self): l1 = sst.Component("node"+str(node)+"_l1cache_" + str(next_core), "memHierarchy.Cache") l1.addParams(l1_params) - l1_cpulink = l1.setSubComponent("cpulink", "memHierarchy.MemLink") - l1_memlink = l1.setSubComponent("memlink", "memHierarchy.MemLink") - l1_cpulink.addParams(link_params) - l1_memlink.addParams(link_params) - l1_cpulink.addParams({"node": node,}) - l1_memlink.addParams({"node": node,}) + l1_highlink = l1.setSubComponent("highlink", "memHierarchy.MemLink") + l1_lowlink = l1.setSubComponent("lowlink", "memHierarchy.MemLink") + l1_highlink.addParams(link_params) + l1_lowlink.addParams(link_params) + l1_highlink.addParams({"node": node,}) + l1_lowlink.addParams({"node": node,}) l2 = sst.Component("node"+str(node)+"_l2cache_" + str(next_core), "memHierarchy.Cache") l2.addParams(l2_params) - l2_cpulink = l2.setSubComponent("cpulink", "memHierarchy.MemLink") - l2_memlink = l2.setSubComponent("memlink", "Opal.OpalMemNIC") - l2_cpulink.addParams(link_params) - l2_memlink.addParams(nic_params) - l2_cpulink.addParams({ "node" : node}) - l2_memlink.addParams({ "node" : node}) - l2_memlink.addParams({ "group" : 1}) + l2_highlink = l2.setSubComponent("highlink", "memHierarchy.MemLink") + l2_lowlink = l2.setSubComponent("lowlink", "Opal.OpalMemNIC") + l2_highlink.addParams(link_params) + l2_lowlink.addParams(nic_params) + l2_highlink.addParams({ "node" : node}) + l2_lowlink.addParams({ "node" : node}) + l2_lowlink.addParams({ "group" : 1}) arielMMULink = sst.Link("node"+str(node)+"_cpu_mmu_link_" + str(next_core)) MMUCacheLink = sst.Link("node"+str(node)+"_mmu_cache_link_" + str(next_core)) @@ -249,20 +249,20 @@ def getNextPort(self): if next_core < cores//2: arielMMULink.connect((ariel, "cache_link_%d"%next_core, "300ps"), (mmu, "cpu_to_mmu%d"%next_core, "300ps")) ArielOpalLink.connect((memmgr, "opal_link_%d"%next_core, "300ps"), (opal, "coreLink%d"%(next_core + node*(cores//2)), "300ps")) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core, "300ps"), (l1_cpulink, "port", "300ps")) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core, "300ps"), (l1_highlink, "port", "300ps")) PTWOpalLink.connect( (pagefaulthandler, "opal_link_%d"%next_core, "300ps"), (opal, "mmuLink%d"%(next_core + node*(cores//2)), "300ps") ) else: - PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core-cores//2), "300ps"), (l1_cpulink, "port", "300ps")) + PTWMemLink.connect((mmu, "ptw_to_mem%d"%(next_core-cores//2), "300ps"), (l1_highlink, "port", "300ps")) l2_core_link = sst.Link("node"+str(node)+"_l2cache_" + str(next_core) + "_link") - l2_core_link.connect((l1_memlink, "port", "300ps"), (l2_cpulink, "port", "300ps")) + l2_core_link.connect((l1_lowlink, "port", "300ps"), (l2_highlink, "port", "300ps")) l2_ring_link = sst.Link("node"+str(node)+"_l2_ring_link_" + str(next_core)) - l2_ring_link.connect((l2_memlink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) + l2_ring_link.connect((l2_lowlink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) l3cache = sst.Component("node"+str(node)+"_l3cache", "memHierarchy.Cache") l3cache.addParams(l3_params) - l3_link = l3cache.setSubComponent("cpulink", "Opal.OpalMemNIC") + l3_link = l3cache.setSubComponent("highlink", "Opal.OpalMemNIC") l3cache.addParams({ "slice_id" : 0 }) l3_link.addParams(nic_params) l3_link.addParams({ @@ -301,7 +301,7 @@ def getNextPort(self): "backend.channel.rank.bank.transactionQ" : "memHierarchy.fifoTransactionQ", "backend.channel.rank.bank.pagePolicy.close" : 1, }) - mem_link = mem.setSubComponent("cpulink", "memHierarchy.MemLink") + mem_link = mem.setSubComponent("highlink", "memHierarchy.MemLink") mem_link.addParams({ "shared_memory": 1, "node" : 0 @@ -315,11 +315,11 @@ def getNextPort(self): #"debug_level" : 10, }) - dc_cpulink = dc.setSubComponent("cpulink", "Opal.OpalMemNIC") - dc_memlink = dc.setSubComponent("memlink", "memHierarchy.MemLink") - dc_memlink.addParams(link_params) - dc_cpulink.addParams(nic_params) - dc_cpulink.addParams({ + dc_highlink = dc.setSubComponent("highlink", "Opal.OpalMemNIC") + dc_lowlink = dc.setSubComponent("lowlink", "memHierarchy.MemLink") + dc_lowlink.addParams(link_params) + dc_highlink.addParams(nic_params) + dc_highlink.addParams({ "node" : node, "group" : 3, "addr_range_start" : 0, @@ -330,10 +330,10 @@ def getNextPort(self): }) memLink = sst.Link("node"+str(node)+"_mem_link") - memLink.connect((mem_link, "port", "300ps"), (dc_memlink, "port", "300ps")) + memLink.connect((mem_link, "port", "300ps"), (dc_lowlink, "port", "300ps")) netLink = sst.Link("node"+str(node)+"_dc_link") - netLink.connect((dc_cpulink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) + netLink.connect((dc_highlink, "port", "300ps"), (internal_network.rtr, "port%d"%(internal_network.getNextPort()), "300ps")) internal_network_map[str(node)] = internal_network @@ -359,7 +359,7 @@ def getNextPort(self): "clock" : clock, }) -ext_mem_link = ext_mem.setSubComponent("cpulink", "memHierarchy.MemLink") +ext_mem_link = ext_mem.setSubComponent("highlink", "memHierarchy.MemLink") ext_mem_link.addParams({ "node" : 9999, }) ## does not belong to any node ext_dc = sst.Component("ExtMemDc", "memHierarchy.DirectoryController") @@ -367,9 +367,9 @@ def getNextPort(self): "entry_cache_size": 256*1024*1024, #Entry cache size of mem/blocksize "clock": "1GHz", }) -ext_dc_cpulink = ext_dc.setSubComponent("cpulink", "Opal.OpalMemNIC") -ext_dc_memlink = ext_dc.setSubComponent("memlink", "memHierarchy.MemLink") -ext_dc_cpulink.addParams({ +ext_dc_highlink = ext_dc.setSubComponent("highlink", "Opal.OpalMemNIC") +ext_dc_lowlink = ext_dc.setSubComponent("lowlink", "memHierarchy.MemLink") +ext_dc_highlink.addParams({ "network_bw": "80GiB/s", "addr_range_start" : (local_memory_capacity*1024*1024), "addr_range_end" : (local_memory_capacity*1024*1024) + (shared_memory_capacity*1024*1024) -1, @@ -399,10 +399,10 @@ def getNextPort(self): link_nvm_bus_link.connect( (messier, "bus", "50ps"), (ext_memory, "nvm_link", "50ps") ) extmemLink = sst.Link("External_mem_dc_link") -extmemLink.connect( (ext_dc_memlink, "port", "500ps"), (ext_mem_link, "port", "500ps") ) +extmemLink.connect( (ext_dc_lowlink, "port", "500ps"), (ext_mem_link, "port", "500ps") ) ext_dcLink = sst.Link("External_mem_link") -ext_dcLink.connect( (ext_dc_cpulink, "port", "500ps"), (external_network.rtr, "port%d"%port, "500ps") ) +ext_dcLink.connect( (ext_dc_highlink, "port", "500ps"), (external_network.rtr, "port%d"%port, "500ps") ) diff --git a/src/sst/elements/osseous/tests/runstream.py b/src/sst/elements/osseous/tests/runstream.py index 2d61e3f9cf..dac90e48e0 100644 --- a/src/sst/elements/osseous/tests/runstream.py +++ b/src/sst/elements/osseous/tests/runstream.py @@ -74,16 +74,16 @@ } ) cpu_cache_link = sst.Link("cpu_cache_link") -cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cpucache, "high_network_0", "50ps") ) +cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cpucache, "highlink", "50ps") ) rtl_cache_link = sst.Link("rtl_cache_link") -rtl_cache_link.connect( (rtl, "RtlCacheLink", "50ps"), (l1rtlcache, "high_network_0", "50ps") ) +rtl_cache_link.connect( (rtl, "RtlCacheLink", "50ps"), (l1rtlcache, "highlink", "50ps") ) l1cpu_bus_link = sst.Link("l1cpu_bus_link") -l1cpu_bus_link.connect( (l1cpucache, "low_network_0", "50ps"), (membus, "high_network_0", "50ps") ) +l1cpu_bus_link.connect( (l1cpucache, "lowlink", "50ps"), (membus, "highlink0", "50ps") ) l1rtl_bus_link = sst.Link("l1rtl_bus_link") -l1rtl_bus_link.connect( (l1rtlcache, "low_network_0", "50ps"), (membus, "high_network_1", "50ps") ) +l1rtl_bus_link.connect( (l1rtlcache, "lowlink", "50ps"), (membus, "highlink1", "50ps") ) # Shared L2 # 1MB*cores, 16-way set associative, 64B line, 15 cycle access @@ -100,7 +100,7 @@ } ) l2_bus_link = sst.Link("l2_bus_link") -l2_bus_link.connect( (l2, "high_network_0", "50ps"), (membus, "low_network_0", "50ps") ) +l2_bus_link.connect( (l2, "highlink", "50ps"), (membus, "lowlink0", "50ps") ) memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams({ @@ -117,7 +117,7 @@ cpu_rtl_link.connect( (ariel, "rtl_link_0", "50ps"), (rtl, "ArielRtllink", "50ps") ) memory_link = sst.Link("mem_bus_link") -memory_link.connect( (l2, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") ) +memory_link.connect( (l2, "lowlink", "50ps"), (memctrl, "highlink", "50ps") ) # Set the Statistic Load Level; Statistics with Enable Levels (set in # elementInfoStatistic) lower or equal to the load can be enabled (default = 0) diff --git a/src/sst/elements/prospero/Makefile.am b/src/sst/elements/prospero/Makefile.am index 97397d0ae2..6418feeeaa 100644 --- a/src/sst/elements/prospero/Makefile.am +++ b/src/sst/elements/prospero/Makefile.am @@ -22,11 +22,8 @@ libprospero_la_SOURCES = \ EXTRA_DIST = \ tests/array/trace-binary.py \ - tests/array/trace-binary-withdramsim.py \ tests/array/trace-compressed.py \ - tests/array/trace-compressed-withdramsim.py \ tests/array/trace-text.py \ - tests/array/trace-text-withdramsim.py \ tests/array/trace-common.py \ tests/array/array.c \ tests/array/Makefile \ diff --git a/src/sst/elements/prospero/tests/array/NCtrace-withdramsim.py b/src/sst/elements/prospero/tests/array/NCtrace-withdramsim.py deleted file mode 100644 index ff55393cc1..0000000000 --- a/src/sst/elements/prospero/tests/array/NCtrace-withdramsim.py +++ /dev/null @@ -1,48 +0,0 @@ -# Automatically generated SST Python input -import sst -import os - -# Define SST core options -sst.setProgramOption("timebase", "1ps") -sst.setProgramOption("stop-at", "1000000ns") - -# Define the simulation components -comp_cpu = sst.Component("cpu", "prospero.prospero") -comp_cpu.addParams({ - "physlimit" : str(512 * 1024 * 1024), - "tracetype" : "file", - "outputlevel" : "0", - "cache_line" : "64", - "trace" : os.environ['SST_ROOT'] + '/sst/elements/prospero/tests/array/sstprospero-0', - "traceformat" : "text" -}) -comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache") -comp_l1cache.addParams({ - "access_latency_cycles" : "1", - "cache_frequency" : "2 Ghz", - "replacement_policy" : "lru", - "coherence_protocol" : "MESI", - "associativity" : "8", - "cache_line_size" : "64", - "L1" : "1", - "cache_size" : "64 KB" -}) -comp_memctrl = sst.Component("memory", "memHierarchy.MemController") -comp_memctrl.addParams({ - "clock" : "1GHz", -}) - -memory = comp_memctrl.setSubComponent("backend", "memHierarchy.dramsim") -memory.addParams({ - "access_time" : "1000 ns", - "system_ini" : "system.ini", - "device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini", - "mem_size" : "512MiB", -}) - -# Define the simulation links -link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) -# End of generated output. diff --git a/src/sst/elements/prospero/tests/array/NCtrace.py b/src/sst/elements/prospero/tests/array/NCtrace.py index 05339d1923..22dddac820 100644 --- a/src/sst/elements/prospero/tests/array/NCtrace.py +++ b/src/sst/elements/prospero/tests/array/NCtrace.py @@ -48,7 +48,7 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) # End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-binary-withdramsim.py b/src/sst/elements/prospero/tests/array/trace-binary-withdramsim.py deleted file mode 100644 index c1b5ae8cf3..0000000000 --- a/src/sst/elements/prospero/tests/array/trace-binary-withdramsim.py +++ /dev/null @@ -1,45 +0,0 @@ -# Automatically generated SST Python input -import sst -import os - -# Define SST core options -sst.setProgramOption("timebase", "1ps") -sst.setProgramOption("stop-at", "5s") - -# Define the simulation components -comp_cpu = sst.Component("cpu", "prospero.prosperoCPU") -comp_cpu.addParams({ - "verbose" : "0", - "reader" : "prospero.ProsperoBinaryTraceReader", - "readerParams.file" : "sstprospero-0-0-bin.trace" -}) -comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache") -comp_l1cache.addParams({ - "access_latency_cycles" : "1", - "cache_frequency" : "2 Ghz", - "replacement_policy" : "lru", - "coherence_protocol" : "MESI", - "associativity" : "8", - "cache_line_size" : "64", - "L1" : "1", - "cache_size" : "64 KB" -}) -comp_memctrl = sst.Component("memory", "memHierarchy.MemController") -comp_memctrl.addParams({ - "clock" : "1GHz", -}) - -memory = comp_memctrl.setSubComponent("backend", "memHierarchy.dramsim") -memory.addParams({ - "access_time" : "1000 ns", - "device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini", - "system_ini" : "system.ini", - "mem_size" : "512MiB", -}) - -# Define the simulation links -link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) -# End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-binary.py b/src/sst/elements/prospero/tests/array/trace-binary.py index af4814956c..7c1199c3be 100644 --- a/src/sst/elements/prospero/tests/array/trace-binary.py +++ b/src/sst/elements/prospero/tests/array/trace-binary.py @@ -37,7 +37,7 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) # End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-common.py b/src/sst/elements/prospero/tests/array/trace-common.py index 84da6d445a..7f219c2931 100644 --- a/src/sst/elements/prospero/tests/array/trace-common.py +++ b/src/sst/elements/prospero/tests/array/trace-common.py @@ -112,7 +112,7 @@ def main(): # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) # End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-compressed-withdramsim.py b/src/sst/elements/prospero/tests/array/trace-compressed-withdramsim.py deleted file mode 100644 index afb3526aae..0000000000 --- a/src/sst/elements/prospero/tests/array/trace-compressed-withdramsim.py +++ /dev/null @@ -1,44 +0,0 @@ -# Automatically generated SST Python input -import sst -import os - -# Define SST core options -sst.setProgramOption("timebase", "1ps") -sst.setProgramOption("stop-at", "5s") - -# Define the simulation components -comp_cpu = sst.Component("cpu", "prospero.prosperoCPU") -comp_cpu.addParams({ - "verbose" : "0", - "reader" : "prospero.ProsperoCompressedBinaryTraceReader", - "readerParams.file" : "sstprospero-0-0-gz.trace" -}) -comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache") -comp_l1cache.addParams({ - "access_latency_cycles" : "1", - "cache_frequency" : "2 Ghz", - "replacement_policy" : "lru", - "coherence_protocol" : "MESI", - "associativity" : "8", - "cache_line_size" : "64", - "L1" : "1", - "cache_size" : "64 KB" -}) -comp_memctrl = sst.Component("memory", "memHierarchy.MemController") -comp_memctrl.addParams({ - "clock" : "1GHz", -}) -memory = comp_memctrl.setSubComponent("backend", "memHierarchy.dramsim") -memory.addParams({ - "access_time" : "1000 ns", - "device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini", - "system_ini" : "system.ini", - "mem_size" : "512MiB", -}) - -# Define the simulation links -link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) -# End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-compressed.py b/src/sst/elements/prospero/tests/array/trace-compressed.py index c09199284b..e98fed2d4d 100644 --- a/src/sst/elements/prospero/tests/array/trace-compressed.py +++ b/src/sst/elements/prospero/tests/array/trace-compressed.py @@ -36,7 +36,7 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) # End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-text-withdramsim.py b/src/sst/elements/prospero/tests/array/trace-text-withdramsim.py deleted file mode 100644 index ac987a8478..0000000000 --- a/src/sst/elements/prospero/tests/array/trace-text-withdramsim.py +++ /dev/null @@ -1,45 +0,0 @@ -# Automatically generated SST Python input -import sst -import os - -# Define SST core options -sst.setProgramOption("timebase", "1ps") -sst.setProgramOption("stop-at", "5s") - -# Define the simulation components -comp_cpu = sst.Component("cpu", "prospero.prosperoCPU") -comp_cpu.addParams({ - "verbose" : "0", - "reader" : "prospero.ProsperoTextTraceReader", - "readerParams.file" : "sstprospero-0-0.trace" -}) -comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache") -comp_l1cache.addParams({ - "access_latency_cycles" : "1", - "cache_frequency" : "2 Ghz", - "replacement_policy" : "lru", - "coherence_protocol" : "MESI", - "associativity" : "8", - "cache_line_size" : "64", - "L1" : "1", - "cache_size" : "64 KB" -}) - -comp_memctrl = sst.Component("memory", "memHierarchy.MemController") -comp_memctrl.addParams({ - "clock" : "1GHz", -}) -memory = comp_memctrl.setSubComponent("backend", "memHierarchy.dramsim") -memory.addParams({ - "access_time" : "1000 ns", - "system_ini" : "system.ini", - "device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini", - "mem_size" : "512MiB", -}) - -# Define the simulation links -link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) -# End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-text.py b/src/sst/elements/prospero/tests/array/trace-text.py index 693fa34063..cab618f5d6 100644 --- a/src/sst/elements/prospero/tests/array/trace-text.py +++ b/src/sst/elements/prospero/tests/array/trace-text.py @@ -36,7 +36,7 @@ # Define the simulation links link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) +link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "highlink", "1000ps") ) link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) # End of generated output. diff --git a/src/sst/elements/prospero/tests/array/trace-withdramsim.py b/src/sst/elements/prospero/tests/array/trace-withdramsim.py deleted file mode 100644 index 8fd89dfdb5..0000000000 --- a/src/sst/elements/prospero/tests/array/trace-withdramsim.py +++ /dev/null @@ -1,48 +0,0 @@ -# Automatically generated SST Python input -import sst -import os - -# Define SST core options -sst.setProgramOption("timebase", "1ps") -sst.setProgramOption("stop-at", "1000000ns") - -# Define the simulation components -comp_cpu = sst.Component("cpu", "prospero.prospero") -comp_cpu.addParams({ - "physlimit" : str(512 * 1024 * 1024), - "tracetype" : "file", - "outputlevel" : "0", - "cache_line" : "64", - "trace" : os.getcwd() + '/sstprospero-0', - "traceformat" : "text" -}) -comp_l1cache = sst.Component("l1cache", "memHierarchy.Cache") -comp_l1cache.addParams({ - "access_latency_cycles" : "1", - "cache_frequency" : "2 Ghz", - "replacement_policy" : "lru", - "coherence_protocol" : "MESI", - "associativity" : "8", - "cache_line_size" : "64", - "L1" : "1", - "cache_size" : "64 KB" -}) -comp_memctrl = sst.Component("memory", "memHierarchy.MemController") -comp_memctrl.addParams({ - "clock" : "1GHz", -}) -memory = comp_memctrl.setSubComponent("backend", "memHierarchy.dramsim") -memory.addParams({ - "access_time" : "1000 ns", - "system_ini" : "system.ini", - "device_ini" : "DDR3_micron_32M_8B_x4_sg125.ini", - "mem_size" : "512MiB", -}) - - -# Define the simulation links -link_cpu_cache_link = sst.Link("link_cpu_cache_link") -link_cpu_cache_link.connect( (comp_cpu, "cache_link", "1000ps"), (comp_l1cache, "high_network_0", "1000ps") ) -link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) -# End of generated output. diff --git a/src/sst/elements/rdmaNic/tests/memory.py b/src/sst/elements/rdmaNic/tests/memory.py index 48edb840a3..59e3bdaa5e 100644 --- a/src/sst/elements/rdmaNic/tests/memory.py +++ b/src/sst/elements/rdmaNic/tests/memory.py @@ -48,8 +48,7 @@ def build( self, nodeId, numPorts, group ): "debug_level" : 11, "debug_addr" : debug_addr, }) - dirtoMemLink = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") - self.connect( "Dirctrl", numPorts, dirctrl, group, linkType="cpulink" ) + self.connect( "Dirctrl", numPorts, dirctrl, group, linkType="highlink" ) memctrl = sst.Component(self.prefix + ".memory", "memHierarchy.MemController") memctrl.addParams({ @@ -64,8 +63,6 @@ def build( self, nodeId, numPorts, group ): "debug_addr" : debug_addr, }) - memToDir = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") - memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") memory.addParams({ "mem_size" : "2GiB", @@ -75,9 +72,9 @@ def build( self, nodeId, numPorts, group ): }) link = sst.Link(self.prefix + ".link_dir_mem") - link.connect( (dirtoMemLink, "port", "1ns"), (memToDir, "port", "1ns") ) + link.connect( (dirctrl, "lowlink", "1ns"), (memctrl, "highlink", "1ns") ) - def connect( self, name, port, comp, group=None, source=None, dest=None, linkType="memlink" ): + def connect( self, name, port, comp, group=None, source=None, dest=None, linkType="lowlink" ): assert group assert port < self.numPorts diff --git a/src/sst/elements/rdmaNic/tests/rdmaNic.py b/src/sst/elements/rdmaNic/tests/rdmaNic.py index 0bf63cb450..7eb5b11769 100644 --- a/src/sst/elements/rdmaNic/tests/rdmaNic.py +++ b/src/sst/elements/rdmaNic/tests/rdmaNic.py @@ -95,16 +95,13 @@ def build( self, nodeId ): tlb = tlbWrapper.setSubComponent("tlb", "mmu.simpleTLB" ); tlb.addParams(tlbParams) - # Cache to CPU interface - dmaCacheToCpu = dmaCache.setSubComponent("cpulink", "memHierarchy.MemLink") - # NIC DMA -> TLB link = sst.Link(prefix+".link_cpu_dtlb") - link.connect( (dmaIf, "port", "1ns"), (tlbWrapper, "cpu_if", "1ns") ) + link.connect( (dmaIf, "lowlink", "1ns"), (tlbWrapper, "cpu_if", "1ns") ) # NIC DMA TLB -> cache link = sst.Link(prefix+".link_cpu_l1dcache") - link.connect( (tlbWrapper, "cache_if", "1ns"), (dmaCacheToCpu, "port", "1ns") ) + link.connect( (tlbWrapper, "cache_if", "1ns"), (dmaCache, "highlink", "1ns") ) # NIC internode interface netLink = nic.setSubComponent( "rtrLink", "merlin.linkcontrol" ) diff --git a/src/sst/elements/rdmaNic/tests/vanadisBlock.py b/src/sst/elements/rdmaNic/tests/vanadisBlock.py index c7184bffc7..0a145a0196 100644 --- a/src/sst/elements/rdmaNic/tests/vanadisBlock.py +++ b/src/sst/elements/rdmaNic/tests/vanadisBlock.py @@ -154,8 +154,8 @@ def build( self, nodeId, cpuId ): }) # L1 D-Cache - l1cache = sst.Component(prefix + ".l1dcache", "memHierarchy.Cache") - l1cache.addParams({ + l1dcache = sst.Component(prefix + ".l1dcache", "memHierarchy.Cache") + l1dcache.addParams({ "access_latency_cycles" : "2", "cache_frequency" : cpu_clock, "replacement_policy" : "lru", @@ -169,9 +169,6 @@ def build( self, nodeId, cpuId ): "debug_addr" : debug_addr, }) - l1dcache_2_cpu = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l1dcache_2_l2cache = l1cache.setSubComponent("memlink", "memHierarchy.MemLink") - # L1 I-Cache l1icache = sst.Component(prefix + ".l1icache", "memHierarchy.Cache") l1icache.addParams({ @@ -212,8 +209,6 @@ def build( self, nodeId, cpuId ): "debug_addr" : debug_addr, }) - l2cache_2_cpu = l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - # CPU D-TLB dtlbWrapper = sst.Component(prefix+".dtlb", "mmu.tlb_wrapper") dtlbWrapper.addParams(tlbWrapperParams) @@ -229,33 +224,30 @@ def build( self, nodeId, cpuId ): # CPU (data) -> D-TLB link = sst.Link(prefix+".link_cpu_dtlb") - link.connect( (dcache_if, "port", "1ns"), (dtlbWrapper, "cpu_if", "1ns") ) + link.connect( (dcache_if, "lowlink", "1ns"), (dtlbWrapper, "cpu_if", "1ns") ) # CPU (instruction) -> I-TLB link = sst.Link(prefix+".link_cpu_itlb") - link.connect( (icache_if, "port", "1ns"), (itlbWrapper, "cpu_if", "1ns") ) - - l1icache_2_cpu = l1icache.setSubComponent("cpulink", "memHierarchy.MemLink") - l1icache_2_l2cache = l1icache.setSubComponent("memlink", "memHierarchy.MemLink") + link.connect( (icache_if, "lowlink", "1ns"), (itlbWrapper, "cpu_if", "1ns") ) # D-TLB -> D-L1 link = sst.Link(prefix+".link_l1cache") - link.connect( (dtlbWrapper, "cache_if", "1ns"), (l1dcache_2_cpu, "port", "1ns") ) + link.connect( (dtlbWrapper, "cache_if", "1ns"), (l1dcache, "highlink", "1ns") ) # I-TLB -> I-L1 link = sst.Link(prefix+".link_l1icache") - link.connect( (itlbWrapper, "cache_if", "1ns"), (l1icache_2_cpu, "port", "1ns") ) + link.connect( (itlbWrapper, "cache_if", "1ns"), (l1icache, "highlink", "1ns") ) # L1 I-Cache to bus link = sst.Link(prefix + ".link_l1dcache_l2cache") - link.connect( (l1dcache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_0", "1ns") ) + link.connect( (l1dcache, "lowlink", "1ns"), (cache_bus, "highlink0", "1ns") ) # L1 D-Cache to bus link = sst.Link(prefix + ".link_l1icache_l2cache") - link.connect( (l1icache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_1", "1ns") ) + link.connect( (l1icache, "lowlink", "1ns"), (cache_bus, "highlink1", "1ns") ) # BUS to L2 cache link = sst.Link(prefix+".link_bus_l2cache") - link.connect( (cache_bus, "low_network_0", "1ns"), (l2cache_2_cpu, "port", "1ns") ) + link.connect( (cache_bus, "lowlink0", "1ns"), (l2cache, "highlink", "1ns") ) return cpu, l2cache, dtlb, itlb diff --git a/src/sst/elements/rdmaNic/tests/vanadisOS.py b/src/sst/elements/rdmaNic/tests/vanadisOS.py index 72a33f6e86..a7d30b96dc 100644 --- a/src/sst/elements/rdmaNic/tests/vanadisOS.py +++ b/src/sst/elements/rdmaNic/tests/vanadisOS.py @@ -99,10 +99,8 @@ def build( self, numNodes, nodeId, cpuId ): "debug_addr": debug_addr }) - l1cache_2_cpu = l1cache.setSubComponent("cpulink", "memHierarchy.MemLink") - link = sst.Link(self.prefix + ".link_os_l1cache") - link.connect( (mem_if, "port", "1ns"), (l1cache_2_cpu, "port", "1ns") ) + link.connect( (mem_if, "lowlink", "1ns"), (l1cache, "highlink", "1ns") ) return l1cache diff --git a/src/sst/elements/samba/tests/gupsgen_mmu.py b/src/sst/elements/samba/tests/gupsgen_mmu.py index 8a407e3f82..89bd9c5c63 100644 --- a/src/sst/elements/samba/tests/gupsgen_mmu.py +++ b/src/sst/elements/samba/tests/gupsgen_mmu.py @@ -111,7 +111,7 @@ arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id)) arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielMMULink.setNoCut() MMUCacheLink.setNoCut() ''' @@ -122,10 +122,10 @@ link_cpu_mmu_link.connect( (comp_cpu, "cache_link", "50ps"), (mmu, "cpu_to_mmu0", "50ps") ) link_cpu_mmu_link.setNoCut() -link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_mmu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps") ) diff --git a/src/sst/elements/samba/tests/gupsgen_mmu_4KB.py b/src/sst/elements/samba/tests/gupsgen_mmu_4KB.py index 433e25e442..697350f6a6 100644 --- a/src/sst/elements/samba/tests/gupsgen_mmu_4KB.py +++ b/src/sst/elements/samba/tests/gupsgen_mmu_4KB.py @@ -111,7 +111,7 @@ arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id)) arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielMMULink.setNoCut() MMUCacheLink.setNoCut() ''' @@ -122,10 +122,10 @@ link_cpu_mmu_link.connect( (comp_cpu, "cache_link", "50ps"), (mmu, "cpu_to_mmu0", "50ps") ) link_cpu_mmu_link.setNoCut() -link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_mmu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/samba/tests/gupsgen_mmu_opal.py b/src/sst/elements/samba/tests/gupsgen_mmu_opal.py index 0a3610ba24..16556cb591 100644 --- a/src/sst/elements/samba/tests/gupsgen_mmu_opal.py +++ b/src/sst/elements/samba/tests/gupsgen_mmu_opal.py @@ -120,7 +120,7 @@ arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id)) arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielMMULink.setNoCut() MMUCacheLink.setNoCut() ''' @@ -133,7 +133,7 @@ link_cpu_mmu_link.setNoCut() -link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_mmu_opal_link.connect( (mmu, "ptw_to_opal0", "50ps"), (opal, "requestLink0", "50ps") ) link_mmu_cache_link.setNoCut() @@ -142,4 +142,4 @@ link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/samba/tests/gupsgen_mmu_three_levels.py b/src/sst/elements/samba/tests/gupsgen_mmu_three_levels.py index 8983bcab3c..f4421a5b4f 100644 --- a/src/sst/elements/samba/tests/gupsgen_mmu_three_levels.py +++ b/src/sst/elements/samba/tests/gupsgen_mmu_three_levels.py @@ -120,7 +120,7 @@ arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id)) arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielMMULink.setNoCut() MMUCacheLink.setNoCut() ''' @@ -131,10 +131,10 @@ link_cpu_mmu_link.connect( (comp_cpu, "cache_link", "50ps"), (mmu, "cpu_to_mmu0", "50ps") ) link_cpu_mmu_link.setNoCut() -link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_mmu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu.out b/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu.out index cfa1c87c08..88c28ad2fc 100644 --- a/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu.out +++ b/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu.out @@ -1,19 +1,19 @@ -0:cpu:RequestGenCPU[RequestGenCPU:44]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:46]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:48]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:55]: CPU clock configured for 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.memInterface -0:cpu:RequestGenCPU[RequestGenCPU:73]: Loaded memory interface successfully. -0:cpu:RequestGenCPU[RequestGenCPU:101]: Generator loaded successfully. -0:cpu:RequestGenCPU[RequestGenCPU:157]: Miranda CPU Configuration: -0:cpu:RequestGenCPU[RequestGenCPU:158]: - Max requests per cycle: 2 -0:cpu:RequestGenCPU[RequestGenCPU:159]: - Max reorder lookups 16 -0:cpu:RequestGenCPU[RequestGenCPU:160]: - Clock: 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:161]: - Cache line size: 64 bytes -0:cpu:RequestGenCPU[RequestGenCPU:162]: - Max Load requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:163]: - Max Store requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Custom requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:165]: Configuration completed. +0:cpu:RequestGenCPU[RequestGenCPU:43]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:45]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:47]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:54]: CPU clock configured for 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.standardInterface +0:cpu:RequestGenCPU[RequestGenCPU:75]: Loaded memory interface successfully. +0:cpu:RequestGenCPU[RequestGenCPU:103]: Generator loaded successfully. +0:cpu:RequestGenCPU[RequestGenCPU:159]: Miranda CPU Configuration: +0:cpu:RequestGenCPU[RequestGenCPU:160]: - Max requests per cycle: 2 +0:cpu:RequestGenCPU[RequestGenCPU:161]: - Max reorder lookups 16 +0:cpu:RequestGenCPU[RequestGenCPU:162]: - Clock: 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:163]: - Cache line size: 64 bytes +0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Load requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:165]: - Max Store requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:166]: - Max Custom requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:167]: Configuration completed. memory, WARNING: Memories no longer inherit address regions from directories and no region parameters (addr_range_start, addr_range_end, interleave_size, interleave_step) were detected. All addresses will map to this memory: if this is intended, you may ignore this warning or set addr_range_start to 0 in your input deck to eliminate this warning. Initialized with 1 cores Before initialization @@ -26,34 +26,34 @@ After initialization cpu.split_write_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu.split_custom_reqs : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu.cycles_with_issue : Accumulator : Sum.u64 = 19993; SumSQ.u64 = 19993; Count.u64 = 19993; Min.u64 = 1; Max.u64 = 1; - cpu.cycles_no_issue : Accumulator : Sum.u64 = 62933; SumSQ.u64 = 62933; Count.u64 = 62933; Min.u64 = 1; Max.u64 = 1; + cpu.cycles_no_issue : Accumulator : Sum.u64 = 62921; SumSQ.u64 = 62921; Count.u64 = 62921; Min.u64 = 1; Max.u64 = 1; cpu.total_bytes_read : Accumulator : Sum.u64 = 80000; SumSQ.u64 = 640000; Count.u64 = 10000; Min.u64 = 8; Max.u64 = 8; cpu.total_bytes_write : Accumulator : Sum.u64 = 80000; SumSQ.u64 = 640000; Count.u64 = 10000; Min.u64 = 8; Max.u64 = 8; cpu.total_bytes_custom : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu.req_latency : Accumulator : Sum.u64 = 696021; SumSQ.u64 = 46401935; Count.u64 = 20000; Min.u64 = 2; Max.u64 = 260; - cpu.time : Accumulator : Sum.u64 = 41463; SumSQ.u64 = 1719180369; Count.u64 = 1; Min.u64 = 41463; Max.u64 = 41463; + cpu.req_latency : Accumulator : Sum.u64 = 695452; SumSQ.u64 = 46355138; Count.u64 = 20000; Min.u64 = 2; Max.u64 = 260; + cpu.time : Accumulator : Sum.u64 = 41457; SumSQ.u64 = 1718682849; Count.u64 = 1; Min.u64 = 41457; Max.u64 = 41457; cpu.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu.cycles_max_issue : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; cpu.cycles_max_reorder : Accumulator : Sum.u64 = 9986; SumSQ.u64 = 9986; Count.u64 = 9986; Min.u64 = 1; Max.u64 = 1; - cpu.cycles : Accumulator : Sum.u64 = 82927; SumSQ.u64 = 82927; Count.u64 = 82927; Min.u64 = 1; Max.u64 = 1; + cpu.cycles : Accumulator : Sum.u64 = 82915; SumSQ.u64 = 82915; Count.u64 = 82915; Min.u64 = 1; Max.u64 = 1; l1cache.prefetch_opportunities : Accumulator : Sum.u64 = 5000; SumSQ.u64 = 5000; Count.u64 = 5000; Min.u64 = 1; Max.u64 = 1; - l1cache.prefetches_issued : Accumulator : Sum.u64 = 4107; SumSQ.u64 = 4107; Count.u64 = 4107; Min.u64 = 1; Max.u64 = 1; - l1cache.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 81; SumSQ.u64 = 81; Count.u64 = 81; Min.u64 = 1; Max.u64 = 1; - l1cache.prefetches_canceled_by_history : Accumulator : Sum.u64 = 893; SumSQ.u64 = 893; Count.u64 = 893; Min.u64 = 1; Max.u64 = 1; - l1cache.Prefetch_requests : Accumulator : Sum.u64 = 4107; SumSQ.u64 = 4107; Count.u64 = 4107; Min.u64 = 1; Max.u64 = 1; + l1cache.prefetches_issued : Accumulator : Sum.u64 = 4088; SumSQ.u64 = 4088; Count.u64 = 4088; Min.u64 = 1; Max.u64 = 1; + l1cache.prefetches_canceled_by_page_boundary : Accumulator : Sum.u64 = 82; SumSQ.u64 = 82; Count.u64 = 82; Min.u64 = 1; Max.u64 = 1; + l1cache.prefetches_canceled_by_history : Accumulator : Sum.u64 = 912; SumSQ.u64 = 912; Count.u64 = 912; Min.u64 = 1; Max.u64 = 1; + l1cache.Prefetch_requests : Accumulator : Sum.u64 = 4088; SumSQ.u64 = 4088; Count.u64 = 4088; Min.u64 = 1; Max.u64 = 1; l1cache.Prefetch_drops : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 14100; SumSQ.u64 = 14100; Count.u64 = 14100; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_I : Accumulator : Sum.u64 = 14082; SumSQ.u64 = 14082; Count.u64 = 14082; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_GetS_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetS_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_I : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_GetX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetSX_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetSX_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetSX_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_GetSResp_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 14097; SumSQ.u64 = 14097; Count.u64 = 14097; Min.u64 = 1; Max.u64 = 1; - l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IS : Accumulator : Sum.u64 = 14080; SumSQ.u64 = 14080; Count.u64 = 14080; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetXResp_IM : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_GetXResp_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_Inv_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_Inv_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -100,21 +100,24 @@ After initialization l1cache.stateEvent_FlushLineResp_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_FlushLineResp_IB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_FlushLineResp_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.eventSent_GetS : Accumulator : Sum.u64 = 14100; SumSQ.u64 = 14100; Count.u64 = 14100; Min.u64 = 1; Max.u64 = 1; - l1cache.eventSent_GetX : Accumulator : Sum.u64 = 170; SumSQ.u64 = 170; Count.u64 = 170; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetS : Accumulator : Sum.u64 = 14082; SumSQ.u64 = 14082; Count.u64 = 14082; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_GetX : Accumulator : Sum.u64 = 162; SumSQ.u64 = 162; Count.u64 = 162; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetSX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Write : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.eventSent_PutM : Accumulator : Sum.u64 = 9908; SumSQ.u64 = 9908; Count.u64 = 9908; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutM : Accumulator : Sum.u64 = 9909; SumSQ.u64 = 9909; Count.u64 = 9909; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,17 +125,17 @@ After initialization l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 423; SumSQ.u64 = 423; Count.u64 = 423; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 406; SumSQ.u64 = 406; Count.u64 = 406; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_M : Accumulator : Sum.u64 = 9908; SumSQ.u64 = 9908; Count.u64 = 9908; Min.u64 = 1; Max.u64 = 1; - l1cache.evict_IS : Accumulator : Sum.u64 = 252; SumSQ.u64 = 252; Count.u64 = 252; Min.u64 = 1; Max.u64 = 1; - l1cache.evict_IM : Accumulator : Sum.u64 = 44; SumSQ.u64 = 44; Count.u64 = 44; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_M : Accumulator : Sum.u64 = 9909; SumSQ.u64 = 9909; Count.u64 = 9909; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 241; SumSQ.u64 = 241; Count.u64 = 241; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IM : Accumulator : Sum.u64 = 39; SumSQ.u64 = 39; Count.u64 = 39; Min.u64 = 1; Max.u64 = 1; l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 219; SumSQ.u64 = 22903; Count.u64 = 7; Min.u64 = 1; Max.u64 = 107; - l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 1552316; SumSQ.u64 = 171174158; Count.u64 = 14097; Min.u64 = 105; Max.u64 = 208; - l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 29490; SumSQ.u64 = 88470; Count.u64 = 9830; Min.u64 = 3; Max.u64 = 3; - l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 21578; SumSQ.u64 = 2812654; Count.u64 = 170; Min.u64 = 108; Max.u64 = 222; + l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 218; SumSQ.u64 = 22902; Count.u64 = 6; Min.u64 = 1; Max.u64 = 107; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 1550357; SumSQ.u64 = 170928503; Count.u64 = 14080; Min.u64 = 105; Max.u64 = 204; + l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 29514; SumSQ.u64 = 88542; Count.u64 = 9838; Min.u64 = 3; Max.u64 = 3; + l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 20467; SumSQ.u64 = 2651919; Count.u64 = 162; Min.u64 = 108; Max.u64 = 194; l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_GetSX_hit : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_GetSX_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -141,39 +144,40 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 5; SumSQ.u64 = 5; Count.u64 = 5; Min.u64 = 1; Max.u64 = 1; - l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9830; SumSQ.u64 = 9830; Count.u64 = 9830; Min.u64 = 1; Max.u64 = 1; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 4; SumSQ.u64 = 4; Count.u64 = 4; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9838; SumSQ.u64 = 9838; Count.u64 = 9838; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 13945; SumSQ.u64 = 13945; Count.u64 = 13945; Min.u64 = 1; Max.u64 = 1; - l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 73; SumSQ.u64 = 73; Count.u64 = 73; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 13930; SumSQ.u64 = 13930; Count.u64 = 13930; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 72; SumSQ.u64 = 72; Count.u64 = 72; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 155; SumSQ.u64 = 155; Count.u64 = 155; Min.u64 = 1; Max.u64 = 1; - l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 97; SumSQ.u64 = 97; Count.u64 = 97; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 152; SumSQ.u64 = 152; Count.u64 = 152; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 90; SumSQ.u64 = 90; Count.u64 = 90; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.CacheHits : Accumulator : Sum.u64 = 9837; SumSQ.u64 = 9837; Count.u64 = 9837; Min.u64 = 1; Max.u64 = 1; - l1cache.CacheMisses : Accumulator : Sum.u64 = 14270; SumSQ.u64 = 14270; Count.u64 = 14270; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheHits : Accumulator : Sum.u64 = 9844; SumSQ.u64 = 9844; Count.u64 = 9844; Min.u64 = 1; Max.u64 = 1; + l1cache.CacheMisses : Accumulator : Sum.u64 = 14244; SumSQ.u64 = 14244; Count.u64 = 14244; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_AckPut_I : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_PutS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.eventSent_PutE : Accumulator : Sum.u64 = 4234; SumSQ.u64 = 4234; Count.u64 = 4234; Min.u64 = 1; Max.u64 = 1; - l1cache.prefetch_evict : Accumulator : Sum.u64 = 4064; SumSQ.u64 = 4064; Count.u64 = 4064; Min.u64 = 1; Max.u64 = 1; + l1cache.eventSent_PutE : Accumulator : Sum.u64 = 4207; SumSQ.u64 = 4207; Count.u64 = 4207; Min.u64 = 1; Max.u64 = 1; + l1cache.prefetch_evict : Accumulator : Sum.u64 = 4045; SumSQ.u64 = 4045; Count.u64 = 4045; Min.u64 = 1; Max.u64 = 1; l1cache.prefetch_inv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.prefetch_useful : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.prefetch_coherence_miss : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.prefetch_redundant : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; - l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 9830; SumSQ.u64 = 9830; Count.u64 = 9830; Min.u64 = 1; Max.u64 = 1; + l1cache.prefetch_redundant : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetS_E : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache.stateEvent_GetX_E : Accumulator : Sum.u64 = 9838; SumSQ.u64 = 9838; Count.u64 = 9838; Min.u64 = 1; Max.u64 = 1; l1cache.stateEvent_GetSX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_FlushLine_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_FlushLineInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_FetchInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_ForceInv_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_E : Accumulator : Sum.u64 = 4234; SumSQ.u64 = 4234; Count.u64 = 4234; Min.u64 = 1; Max.u64 = 1; - l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 34267; SumSQ.u64 = 34267; Count.u64 = 34267; Min.u64 = 1; Max.u64 = 1; - l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 593; SumSQ.u64 = 593; Count.u64 = 593; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_E : Accumulator : Sum.u64 = 4207; SumSQ.u64 = 4207; Count.u64 = 4207; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 34242; SumSQ.u64 = 34242; Count.u64 = 34242; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 560; SumSQ.u64 = 560; Count.u64 = 560; Min.u64 = 1; Max.u64 = 1; l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -183,31 +187,35 @@ After initialization l1cache.CustomResp_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.CustomAck_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NULLCMD_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetS_recv : Accumulator : Sum.u64 = 14107; SumSQ.u64 = 14107; Count.u64 = 14107; Min.u64 = 1; Max.u64 = 1; + l1cache.GetS_recv : Accumulator : Sum.u64 = 14088; SumSQ.u64 = 14088; Count.u64 = 14088; Min.u64 = 1; Max.u64 = 1; l1cache.GetX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetXResp_recv : Accumulator : Sum.u64 = 14267; SumSQ.u64 = 14267; Count.u64 = 14267; Min.u64 = 1; Max.u64 = 1; + l1cache.GetXResp_recv : Accumulator : Sum.u64 = 14242; SumSQ.u64 = 14242; Count.u64 = 14242; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1539676; SumSQ.u64 = 29516856; Count.u64 = 82927; Min.u64 = 0; Max.u64 = 29; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1536624; SumSQ.u64 = 29395376; Count.u64 = 82915; Min.u64 = 0; Max.u64 = 28; l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmu0.tlb_hits.Core0_PTWC : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmu0.tlb_misses.Core0_PTWC : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; - mmu0.total_waiting.0 : Accumulator : Sum.u64 = 237821; SumSQ.u64 = 16030175; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 414; - mmu0.tlb_hits.Core0_L2 : Accumulator : Sum.u64 = 8652; SumSQ.u64 = 8652; Count.u64 = 8652; Min.u64 = 1; Max.u64 = 1; + mmu0.total_waiting.0 : Accumulator : Sum.u64 = 237803; SumSQ.u64 = 16030709; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 414; + mmu0.tlb_hits.Core0_L2 : Accumulator : Sum.u64 = 8650; SumSQ.u64 = 8650; Count.u64 = 8650; Min.u64 = 1; Max.u64 = 1; mmu0.tlb_misses.Core0_L2 : Accumulator : Sum.u64 = 257; SumSQ.u64 = 257; Count.u64 = 257; Min.u64 = 1; Max.u64 = 1; mmu0.tlb_shootdown.Core0_L2 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - mmu0.tlb_hits.Core0_L1 : Accumulator : Sum.u64 = 11091; SumSQ.u64 = 11091; Count.u64 = 11091; Min.u64 = 1; Max.u64 = 1; - mmu0.tlb_misses.Core0_L1 : Accumulator : Sum.u64 = 8909; SumSQ.u64 = 8909; Count.u64 = 8909; Min.u64 = 1; Max.u64 = 1; + mmu0.tlb_hits.Core0_L1 : Accumulator : Sum.u64 = 11093; SumSQ.u64 = 11093; Count.u64 = 11093; Min.u64 = 1; Max.u64 = 1; + mmu0.tlb_misses.Core0_L1 : Accumulator : Sum.u64 = 8907; SumSQ.u64 = 8907; Count.u64 = 8907; Min.u64 = 1; Max.u64 = 1; mmu0.tlb_shootdown.Core0_L1 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; -Simulation is complete, simulated time: 41.4635 us +Simulation is complete, simulated time: 41.4575 us diff --git a/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_4KB.out b/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_4KB.out index 7b093e919f..637133fbeb 100644 --- a/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_4KB.out +++ b/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_4KB.out @@ -1,19 +1,19 @@ -0:cpu:RequestGenCPU[RequestGenCPU:44]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:46]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:48]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:55]: CPU clock configured for 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.memInterface -0:cpu:RequestGenCPU[RequestGenCPU:73]: Loaded memory interface successfully. -0:cpu:RequestGenCPU[RequestGenCPU:101]: Generator loaded successfully. -0:cpu:RequestGenCPU[RequestGenCPU:157]: Miranda CPU Configuration: -0:cpu:RequestGenCPU[RequestGenCPU:158]: - Max requests per cycle: 2 -0:cpu:RequestGenCPU[RequestGenCPU:159]: - Max reorder lookups 16 -0:cpu:RequestGenCPU[RequestGenCPU:160]: - Clock: 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:161]: - Cache line size: 64 bytes -0:cpu:RequestGenCPU[RequestGenCPU:162]: - Max Load requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:163]: - Max Store requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Custom requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:165]: Configuration completed. +0:cpu:RequestGenCPU[RequestGenCPU:43]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:45]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:47]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:54]: CPU clock configured for 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.standardInterface +0:cpu:RequestGenCPU[RequestGenCPU:75]: Loaded memory interface successfully. +0:cpu:RequestGenCPU[RequestGenCPU:103]: Generator loaded successfully. +0:cpu:RequestGenCPU[RequestGenCPU:159]: Miranda CPU Configuration: +0:cpu:RequestGenCPU[RequestGenCPU:160]: - Max requests per cycle: 2 +0:cpu:RequestGenCPU[RequestGenCPU:161]: - Max reorder lookups 16 +0:cpu:RequestGenCPU[RequestGenCPU:162]: - Clock: 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:163]: - Cache line size: 64 bytes +0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Load requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:165]: - Max Store requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:166]: - Max Custom requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:167]: Configuration completed. memory, WARNING: Memories no longer inherit address regions from directories and no region parameters (addr_range_start, addr_range_end, interleave_size, interleave_step) were detected. All addresses will map to this memory: if this is intended, you may ignore this warning or set addr_range_start to 0 in your input deck to eliminate this warning. Initialized with 1 cores Before initialization @@ -30,7 +30,7 @@ After initialization cpu.total_bytes_read : Accumulator : Sum.u64 = 80000; SumSQ.u64 = 640000; Count.u64 = 10000; Min.u64 = 8; Max.u64 = 8; cpu.total_bytes_write : Accumulator : Sum.u64 = 80000; SumSQ.u64 = 640000; Count.u64 = 10000; Min.u64 = 8; Max.u64 = 8; cpu.total_bytes_custom : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - cpu.req_latency : Accumulator : Sum.u64 = 2964474; SumSQ.u64 = 510256296; Count.u64 = 20000; Min.u64 = 2; Max.u64 = 261; + cpu.req_latency : Accumulator : Sum.u64 = 2964475; SumSQ.u64 = 510256457; Count.u64 = 20000; Min.u64 = 2; Max.u64 = 261; cpu.time : Accumulator : Sum.u64 = 129963; SumSQ.u64 = 16890381369; Count.u64 = 1; Min.u64 = 129963; Max.u64 = 129963; cpu.cycles_hit_fence : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; cpu.cycles_max_issue : Accumulator : Sum.u64 = 7; SumSQ.u64 = 7; Count.u64 = 7; Min.u64 = 1; Max.u64 = 1; @@ -108,13 +108,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,15 +125,15 @@ After initialization l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 131; SumSQ.u64 = 131; Count.u64 = 131; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 129; SumSQ.u64 = 129; Count.u64 = 129; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 9909; SumSQ.u64 = 9909; Count.u64 = 9909; Min.u64 = 1; Max.u64 = 1; - l1cache.evict_IS : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_IS : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_SM : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_SB : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_GetS_hit : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; - l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 1620526; SumSQ.u64 = 176433938; Count.u64 = 14889; Min.u64 = 105; Max.u64 = 116; + l1cache.latency_GetS_miss : Accumulator : Sum.u64 = 1620524; SumSQ.u64 = 176433506; Count.u64 = 14889; Min.u64 = 105; Max.u64 = 116; l1cache.latency_GetX_hit : Accumulator : Sum.u64 = 29814; SumSQ.u64 = 89442; Count.u64 = 9938; Min.u64 = 3; Max.u64 = 3; l1cache.latency_GetX_miss : Accumulator : Sum.u64 = 6749; SumSQ.u64 = 735297; Count.u64 = 62; Min.u64 = 107; Max.u64 = 132; l1cache.latency_GetX_upgrade : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -141,16 +144,17 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9938; SumSQ.u64 = 9938; Count.u64 = 9938; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSXHit_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 14889; SumSQ.u64 = 14889; Count.u64 = 14889; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Arrival : Accumulator : Sum.u64 = 14891; SumSQ.u64 = 14891; Count.u64 = 14891; Min.u64 = 1; Max.u64 = 1; l1cache.GetXMiss_Arrival : Accumulator : Sum.u64 = 61; SumSQ.u64 = 61; Count.u64 = 61; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXMiss_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; + l1cache.GetSMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXMiss_Blocked : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXMiss_Blocked : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.CacheHits : Accumulator : Sum.u64 = 9940; SumSQ.u64 = 9940; Count.u64 = 9940; Min.u64 = 1; Max.u64 = 1; @@ -173,7 +177,7 @@ After initialization l1cache.stateEvent_FetchInvX_E : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_E : Accumulator : Sum.u64 = 4916; SumSQ.u64 = 4916; Count.u64 = 4916; Min.u64 = 1; Max.u64 = 1; l1cache.TotalEventsReceived : Accumulator : Sum.u64 = 34951; SumSQ.u64 = 34951; Count.u64 = 34951; Min.u64 = 1; Max.u64 = 1; - l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 6; SumSQ.u64 = 6; Count.u64 = 6; Min.u64 = 1; Max.u64 = 1; + l1cache.TotalEventsReplayed : Accumulator : Sum.u64 = 2; SumSQ.u64 = 2; Count.u64 = 2; Min.u64 = 1; Max.u64 = 1; l1cache.GetS_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Write_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSX_uncache_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -189,21 +193,25 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 14951; SumSQ.u64 = 14951; Count.u64 = 14951; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1592304; SumSQ.u64 = 9859256; Count.u64 = 259927; Min.u64 = 0; Max.u64 = 11; + l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1592302; SumSQ.u64 = 9859230; Count.u64 = 259927; Min.u64 = 0; Max.u64 = 11; l1cache.Bank_conflicts : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmu0.tlb_hits.Core0_PTWC : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; mmu0.tlb_misses.Core0_PTWC : Accumulator : Sum.u64 = 9897; SumSQ.u64 = 9897; Count.u64 = 9897; Min.u64 = 1; Max.u64 = 1; - mmu0.total_waiting.0 : Accumulator : Sum.u64 = 4801042; SumSQ.u64 = 1242502976; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 414; + mmu0.total_waiting.0 : Accumulator : Sum.u64 = 4801046; SumSQ.u64 = 1242504836; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 414; mmu0.tlb_hits.Core0_L2 : Accumulator : Sum.u64 = 447; SumSQ.u64 = 447; Count.u64 = 447; Min.u64 = 1; Max.u64 = 1; mmu0.tlb_misses.Core0_L2 : Accumulator : Sum.u64 = 9897; SumSQ.u64 = 9897; Count.u64 = 9897; Min.u64 = 1; Max.u64 = 1; mmu0.tlb_shootdown.Core0_L2 : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_three_levels.out b/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_three_levels.out index 50c0e8a8ea..d11d0e825f 100644 --- a/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_three_levels.out +++ b/src/sst/elements/samba/tests/refFiles/test_Samba_gupsgen_mmu_three_levels.out @@ -1,19 +1,19 @@ -0:cpu:RequestGenCPU[RequestGenCPU:44]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:46]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:48]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:55]: CPU clock configured for 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.memInterface -0:cpu:RequestGenCPU[RequestGenCPU:73]: Loaded memory interface successfully. -0:cpu:RequestGenCPU[RequestGenCPU:101]: Generator loaded successfully. -0:cpu:RequestGenCPU[RequestGenCPU:157]: Miranda CPU Configuration: -0:cpu:RequestGenCPU[RequestGenCPU:158]: - Max requests per cycle: 2 -0:cpu:RequestGenCPU[RequestGenCPU:159]: - Max reorder lookups 16 -0:cpu:RequestGenCPU[RequestGenCPU:160]: - Clock: 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:161]: - Cache line size: 64 bytes -0:cpu:RequestGenCPU[RequestGenCPU:162]: - Max Load requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:163]: - Max Store requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Custom requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:165]: Configuration completed. +0:cpu:RequestGenCPU[RequestGenCPU:43]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:45]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:47]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:54]: CPU clock configured for 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.standardInterface +0:cpu:RequestGenCPU[RequestGenCPU:75]: Loaded memory interface successfully. +0:cpu:RequestGenCPU[RequestGenCPU:103]: Generator loaded successfully. +0:cpu:RequestGenCPU[RequestGenCPU:159]: Miranda CPU Configuration: +0:cpu:RequestGenCPU[RequestGenCPU:160]: - Max requests per cycle: 2 +0:cpu:RequestGenCPU[RequestGenCPU:161]: - Max reorder lookups 16 +0:cpu:RequestGenCPU[RequestGenCPU:162]: - Clock: 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:163]: - Cache line size: 64 bytes +0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Load requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:165]: - Max Store requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:166]: - Max Custom requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:167]: Configuration completed. memory, WARNING: Memories no longer inherit address regions from directories and no region parameters (addr_range_start, addr_range_end, interleave_size, interleave_step) were detected. All addresses will map to this memory: if this is intended, you may ignore this warning or set addr_range_start to 0 in your input deck to eliminate this warning. Initialized with 1 cores Before initialization @@ -108,13 +108,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -141,6 +144,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 1; SumSQ.u64 = 1; Count.u64 = 1; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 9925; SumSQ.u64 = 9925; Count.u64 = 9925; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -189,14 +193,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 14973; SumSQ.u64 = 14973; Count.u64 = 14973; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 1594620; SumSQ.u64 = 9674920; Count.u64 = 266503; Min.u64 = 0; Max.u64 = 11; diff --git a/src/sst/elements/samba/tests/refFiles/test_Samba_stencil3dbench_mmu.out b/src/sst/elements/samba/tests/refFiles/test_Samba_stencil3dbench_mmu.out index 58819a8830..83defddc61 100644 --- a/src/sst/elements/samba/tests/refFiles/test_Samba_stencil3dbench_mmu.out +++ b/src/sst/elements/samba/tests/refFiles/test_Samba_stencil3dbench_mmu.out @@ -1,19 +1,19 @@ -0:cpu:RequestGenCPU[RequestGenCPU:44]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:46]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:48]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. -0:cpu:RequestGenCPU[RequestGenCPU:55]: CPU clock configured for 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.memInterface -0:cpu:RequestGenCPU[RequestGenCPU:73]: Loaded memory interface successfully. -0:cpu:RequestGenCPU[RequestGenCPU:101]: Generator loaded successfully. -0:cpu:RequestGenCPU[RequestGenCPU:157]: Miranda CPU Configuration: -0:cpu:RequestGenCPU[RequestGenCPU:158]: - Max requests per cycle: 2 -0:cpu:RequestGenCPU[RequestGenCPU:159]: - Max reorder lookups 16 -0:cpu:RequestGenCPU[RequestGenCPU:160]: - Clock: 2GHz -0:cpu:RequestGenCPU[RequestGenCPU:161]: - Cache line size: 64 bytes -0:cpu:RequestGenCPU[RequestGenCPU:162]: - Max Load requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:163]: - Max Store requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Custom requests pending: 16 -0:cpu:RequestGenCPU[RequestGenCPU:165]: Configuration completed. +0:cpu:RequestGenCPU[RequestGenCPU:43]: Configured CPU to allow 16 maximum Load requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:45]: Configured CPU to allow 16 maximum Store requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:47]: Configured CPU to allow 16 maximum Custom requests to be memory to be outstanding. +0:cpu:RequestGenCPU[RequestGenCPU:54]: CPU clock configured for 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:60]: Memory interface to be loaded is: memHierarchy.standardInterface +0:cpu:RequestGenCPU[RequestGenCPU:75]: Loaded memory interface successfully. +0:cpu:RequestGenCPU[RequestGenCPU:103]: Generator loaded successfully. +0:cpu:RequestGenCPU[RequestGenCPU:159]: Miranda CPU Configuration: +0:cpu:RequestGenCPU[RequestGenCPU:160]: - Max requests per cycle: 2 +0:cpu:RequestGenCPU[RequestGenCPU:161]: - Max reorder lookups 16 +0:cpu:RequestGenCPU[RequestGenCPU:162]: - Clock: 2GHz +0:cpu:RequestGenCPU[RequestGenCPU:163]: - Cache line size: 64 bytes +0:cpu:RequestGenCPU[RequestGenCPU:164]: - Max Load requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:165]: - Max Store requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:166]: - Max Custom requests pending: 16 +0:cpu:RequestGenCPU[RequestGenCPU:167]: Configuration completed. memory, WARNING: Memories no longer inherit address regions from directories and no region parameters (addr_range_start, addr_range_end, interleave_size, interleave_step) were detected. All addresses will map to this memory: if this is intended, you may ignore this warning or set addr_range_start to 0 in your input deck to eliminate this warning. Initialized with 1 cores Before initialization @@ -108,13 +108,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 108864; SumSQ.u64 = 108864; Count.u64 = 108864; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -122,7 +125,7 @@ After initialization l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 399; SumSQ.u64 = 399; Count.u64 = 399; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -141,6 +144,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 112248; SumSQ.u64 = 112248; Count.u64 = 112248; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 3405; SumSQ.u64 = 3405; Count.u64 = 3405; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -189,14 +193,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 4032; SumSQ.u64 = 4032; Count.u64 = 4032; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 1304; SumSQ.u64 = 1304; Count.u64 = 1304; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 314278; SumSQ.u64 = 836336; Count.u64 = 608368; Min.u64 = 0; Max.u64 = 20; diff --git a/src/sst/elements/samba/tests/refFiles/test_Samba_streambench_mmu.out b/src/sst/elements/samba/tests/refFiles/test_Samba_streambench_mmu.out index 143fad7c3e..3dbe6c5e52 100644 --- a/src/sst/elements/samba/tests/refFiles/test_Samba_streambench_mmu.out +++ b/src/sst/elements/samba/tests/refFiles/test_Samba_streambench_mmu.out @@ -92,13 +92,16 @@ After initialization l1cache.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_GetSResp : Accumulator : Sum.u64 = 20000; SumSQ.u64 = 20000; Count.u64 = 20000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_WriteResp : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -106,7 +109,7 @@ After initialization l1cache.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.evict_M : Accumulator : Sum.u64 = 2313; SumSQ.u64 = 2313; Count.u64 = 2313; Min.u64 = 1; Max.u64 = 1; l1cache.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -125,6 +128,7 @@ After initialization l1cache.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSHit_Arrival : Accumulator : Sum.u64 = 969; SumSQ.u64 = 969; Count.u64 = 969; Min.u64 = 1; Max.u64 = 1; l1cache.GetXHit_Arrival : Accumulator : Sum.u64 = 342; SumSQ.u64 = 342; Count.u64 = 342; Min.u64 = 1; Max.u64 = 1; l1cache.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -173,14 +177,18 @@ After initialization l1cache.Write_recv : Accumulator : Sum.u64 = 10000; SumSQ.u64 = 10000; Count.u64 = 10000; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.GetXResp_recv : Accumulator : Sum.u64 = 7503; SumSQ.u64 = 7503; Count.u64 = 7503; Min.u64 = 1; Max.u64 = 1; l1cache.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache.MSHR_occupancy : Accumulator : Sum.u64 = 6611682; SumSQ.u64 = 145366974; Count.u64 = 317459; Min.u64 = 0; Max.u64 = 33; diff --git a/src/sst/elements/samba/tests/simpletlb_test.py b/src/sst/elements/samba/tests/simpletlb_test.py index c525a20dc1..85b92f94cc 100644 --- a/src/sst/elements/samba/tests/simpletlb_test.py +++ b/src/sst/elements/samba/tests/simpletlb_test.py @@ -79,7 +79,7 @@ #link_cpu_mmu_link.connect( (comp_cpu, "cache_link", "50ps"), (mmu, "cpu_to_mmu0", "50ps") ) # #link_mmu_cache_link = sst.Link("link_mmu_cache_link") -#link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +#link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) def makeLink(name, portA, portB): 'ports should be tuple like `(component, "port_name", "50ps")`' @@ -91,12 +91,12 @@ def makeLink(name, portA, portB): (comp_cpu, "cache_link", "50ps"), (comp_tlb, "high_network", "50ps")) makeLink("link_tlb_l1cache", - (comp_tlb, "low_network", "50ps"), (comp_l1cache, "high_network_0", "50ps")) + (comp_tlb, "low_network", "50ps"), (comp_l1cache, "highlink", "50ps")) ##===== Alternately, self-loop the TLB and connect cpu to cache #makeLink("link_cpu_l1cache", -# (comp_cpu, "cache_link", "50ps"), (comp_l1cache, "high_network_0", "50ps")) +# (comp_cpu, "cache_link", "50ps"), (comp_l1cache, "highlink", "50ps")) # #makeLink("linkself_tlb", # (comp_tlb, "link_high", "50ps"), (comp_tlb, "link_low", "50ps")) @@ -104,5 +104,5 @@ def makeLink(name, portA, portB): # === CPU to mem makeLink("link_l1cache_membus", - (comp_l1cache, "low_network_0", "50ps"), (comp_memctrl, "direct_link", "50ps")) + (comp_l1cache, "lowlink", "50ps"), (comp_memctrl, "highlink", "50ps")) diff --git a/src/sst/elements/samba/tests/stencil3dbench_mmu.py b/src/sst/elements/samba/tests/stencil3dbench_mmu.py index 050999f10c..d6f06e27c8 100644 --- a/src/sst/elements/samba/tests/stencil3dbench_mmu.py +++ b/src/sst/elements/samba/tests/stencil3dbench_mmu.py @@ -86,7 +86,7 @@ arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id)) arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielMMULink.setNoCut() MMUCacheLink.setNoCut() ''' @@ -95,11 +95,11 @@ link_cpu_mmu_link.connect( (comp_cpu, "cache_link", "50ps"), (mmu, "cpu_to_mmu0", "50ps") ) link_cpu_mmu_link.setNoCut() -link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_mmu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/samba/tests/streambench_mmu.py b/src/sst/elements/samba/tests/streambench_mmu.py index 015e90b60d..b853f57172 100644 --- a/src/sst/elements/samba/tests/streambench_mmu.py +++ b/src/sst/elements/samba/tests/streambench_mmu.py @@ -85,7 +85,7 @@ arielMMULink = sst.Link("cpu_mmu_link_" + str(next_core_id)) MMUCacheLink = sst.Link("mmu_cache_link_" + str(next_core_id)) arielMMULink.connect((ariel, "cache_link_%d"%next_core_id, ring_latency), (mmu, "cpu_to_mmu%d"%next_core_id, ring_latency)) - MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "high_network_0", ring_latency)) + MMUCacheLink.connect((mmu, "mmu_to_cache%d"%next_core_id, ring_latency), (l1, "highlink", ring_latency)) arielMMULink.setNoCut() MMUCacheLink.setNoCut() ''' @@ -94,11 +94,11 @@ link_cpu_mmu_link.connect( (comp_cpu, "cache_link", "50ps"), (mmu, "cpu_to_mmu0", "50ps") ) link_cpu_mmu_link.setNoCut() -link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "high_network_0", "50ps") ) +link_mmu_cache_link.connect( (mmu, "mmu_to_cache0", "50ps"), (comp_l1cache, "highlink", "50ps") ) link_mmu_cache_link.setNoCut() link_mem_bus_link = sst.Link("link_mem_bus_link") -link_mem_bus_link.connect( (comp_l1cache, "low_network_0", "50ps"), (comp_memory, "direct_link", "50ps") ) +link_mem_bus_link.connect( (comp_l1cache, "lowlink", "50ps"), (comp_memory, "highlink", "50ps") ) diff --git a/src/sst/elements/shogun/tests/basic_miranda.py b/src/sst/elements/shogun/tests/basic_miranda.py index f08cc9aa00..82af98db7f 100644 --- a/src/sst/elements/shogun/tests/basic_miranda.py +++ b/src/sst/elements/shogun/tests/basic_miranda.py @@ -49,10 +49,9 @@ "verbose" : 0 }) pref0 = comp_l1cache0.setSubComponent("prefetcher", "cassini.StridePrefetcher") -l1c0_cpulink = comp_l1cache0.setSubComponent("cpulink", "memHierarchy.MemLink") -l1c0_memlink = comp_l1cache0.setSubComponent("memlink", "memHierarchy.MemNIC") -l1c0_memlink.addParams({ "group" : 2 }) -l1c0_linkctrl = l1c0_memlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") +l1c0_lowlink = comp_l1cache0.setSubComponent("lowlink", "memHierarchy.MemNIC") +l1c0_lowlink.addParams({ "group" : 2 }) +l1c0_linkctrl = l1c0_lowlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") comp_l1cache1 = sst.Component("l1cache1", "memHierarchy.Cache") comp_l1cache1.addParams({ @@ -67,10 +66,9 @@ "cache_size" : "8KB", }) pref1 = comp_l1cache1.setSubComponent("prefetcher", "cassini.StridePrefetcher") -l1c1_cpulink = comp_l1cache1.setSubComponent("cpulink", "memHierarchy.MemLink") -l1c1_memlink = comp_l1cache1.setSubComponent("memlink", "memHierarchy.MemNIC") -l1c1_memlink.addParams({ "group" : 2 }) -l1c1_linkctrl = l1c1_memlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") +l1c1_lowlink = comp_l1cache1.setSubComponent("lowlink", "memHierarchy.MemNIC") +l1c1_lowlink.addParams({ "group" : 2 }) +l1c1_linkctrl = l1c1_lowlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") # Enable statistics outputs comp_l1cache0.enableAllStatistics({"type":"sst.AccumulatorStatistic"}) @@ -122,14 +120,13 @@ "interleave_step" : "128B", }) -dc0_cpulink = comp_dirctrl0.setSubComponent("cpulink", "memHierarchy.MemNIC") -dc0_memlink = comp_dirctrl0.setSubComponent("memlink", "memHierarchy.MemLink") -dc0_cpulink.addParams({ +dc0_highlink = comp_dirctrl0.setSubComponent("highlink", "memHierarchy.MemNIC") +dc0_highlink.addParams({ "group" : 3, "debug" : 0, "debug_level" : 10, }) -dc0_linkctrl = dc0_cpulink.setSubComponent("linkcontrol", "shogun.ShogunNIC") +dc0_linkctrl = dc0_highlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") comp_dirctrl1 = sst.Component("dirctrl1", "memHierarchy.DirectoryController") comp_dirctrl1.addParams({ @@ -141,14 +138,13 @@ "interleave_step" : "128B", }) -dc1_cpulink = comp_dirctrl1.setSubComponent("cpulink", "memHierarchy.MemNIC") -dc1_memlink = comp_dirctrl1.setSubComponent("memlink", "memHierarchy.MemLink") -dc1_cpulink.addParams({ +dc1_highlink = comp_dirctrl1.setSubComponent("highlink", "memHierarchy.MemNIC") +dc1_highlink.addParams({ "group" : 3, "debug" : 0, "debug_level" : 10, }) -dc1_linkctrl = dc1_cpulink.setSubComponent("linkcontrol", "shogun.ShogunNIC") +dc1_linkctrl = dc1_highlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") shogun_xbar = sst.Component("shogunxbar", "shogun.ShogunXBar") shogun_xbar.addParams({ @@ -161,11 +157,11 @@ # Define the simulation links link_cpu_cache_link0 = sst.Link("link_cpu_cache_link0") -link_cpu_cache_link0.connect( (comp_cpu0, "cache_link", "100ps"), (l1c0_cpulink, "port", "100ps") ) +link_cpu_cache_link0.connect( (comp_cpu0, "cache_link", "100ps"), (comp_l1cache0, "highlink", "100ps") ) link_cpu_cache_link0.setNoCut() link_cpu_cache_link1 = sst.Link("link_cpu_cache_link1") -link_cpu_cache_link1.connect( (comp_cpu1, "cache_link", "100ps"), (l1c1_cpulink, "port", "100ps") ) +link_cpu_cache_link1.connect( (comp_cpu1, "cache_link", "100ps"), (comp_l1cache1, "highlink", "100ps") ) link_cpu_cache_link1.setNoCut() xbar_cpu0_link = sst.Link("xbar_cpu0_link") @@ -175,13 +171,13 @@ xbar_cpu1_link.connect( (shogun_xbar, "port1", "100ps"), (l1c1_linkctrl, "port", "100ps") ) dir0_mem0_link = sst.Link("dir0_mem0_link") -dir0_mem0_link.connect( (dc0_memlink, "port", "500ps"), (comp_memctrl0, "direct_link", "50ps") ) +dir0_mem0_link.connect( (comp_dirctrl0, "lowlink", "500ps"), (comp_memctrl0, "highlink", "50ps") ) dir0_net_link = sst.Link("dir0_net_link") dir0_net_link.connect( (shogun_xbar, "port2", "100ps"), (dc0_linkctrl, "port", "200ps") ) dir1_mem1_link = sst.Link("dir1_mem1_link") -dir1_mem1_link.connect( (dc1_memlink, "port", "500ps"), (comp_memctrl1, "direct_link", "50ps") ) +dir1_mem1_link.connect( (comp_dirctrl1, "lowlink", "500ps"), (comp_memctrl1, "highlink", "50ps") ) dir1_net_link = sst.Link("dir1_net_link") dir1_net_link.connect( (shogun_xbar, "port3", "100ps"), (dc1_linkctrl, "port", "200ps") ) diff --git a/src/sst/elements/shogun/tests/hierarchy_test.py b/src/sst/elements/shogun/tests/hierarchy_test.py index 1c63e86a91..a96ad7eaab 100644 --- a/src/sst/elements/shogun/tests/hierarchy_test.py +++ b/src/sst/elements/shogun/tests/hierarchy_test.py @@ -88,13 +88,12 @@ "cache_size" : "32KB", }) - l1_cpulink = l1_cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l1_memlink = l1_cache.setSubComponent("memlink", "memHierarchy.MemNIC") - l1_memlink.addParams({ "group" : 1 }) - l1_linkctrl = l1_memlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") + l1_lowlink = l1_cache.setSubComponent("lowlink", "memHierarchy.MemNIC") + l1_lowlink.addParams({ "group" : 1 }) + l1_linkctrl = l1_lowlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") corel1link = sst.Link("cpu_l1_link_" + str(cpu_id)) - corel1link.connect((comp_cpu, "cache_link", "100ps"), (l1_cpulink, "port", "100ps")) + corel1link.connect((comp_cpu, "cache_link", "100ps"), (l1_cache, "highlink", "100ps")) corel1link.setNoCut() l1xbarlink = sst.Link("l1_xbar_link_" + str(cpu_id)) @@ -143,7 +142,6 @@ "interleave_step" : str(total_mems * 256) + "B", }) - mem_cpulink = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") if backend == "simple": # Create DDR (Simple) @@ -277,7 +275,7 @@ linkDimmCtrl.connect( (cramsimCtrl, "memLink", "1ns"), (cramsimDimm, "ctrlLink", "1ns") ) bus_mem_link = sst.Link("bus_mem_link_" + str(next_mem)) - bus_mem_link.connect((mem_l2_bus, "low_network_%d"%sub_group_id, "100ps"), (mem_cpulink, "port", "100ps")) + bus_mem_link.connect((mem_l2_bus, "lowlink%d"%sub_group_id, "100ps"), (memctrl, "highlink", "100ps")) bus_mem_link.setNoCut() next_mem = next_mem + 1 @@ -307,12 +305,11 @@ "interleave_step" : str(num_l2 * 256) + "B", }) - l2_cpulink = l2_cache.setSubComponent("cpulink", "memHierarchy.MemNIC") - l2_cpulink.addParams({ + l2_highlink = l2_cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l2_highlink.addParams({ "group" : 2, }) - l2_linkctrl = l2_cpulink.setSubComponent("linkcontrol", "shogun.ShogunNIC") - l2_memlink = l2_cache.setSubComponent("memlink", "memHierarchy.MemLink") + l2_linkctrl = l2_highlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") l2xbarlink = sst.Link("l2_xbar_link_" + str(next_cache)) l2xbarlink.connect((l2_linkctrl, "port", "100ps"), (router, "port" + str(next_port), "100ps")) @@ -321,7 +318,7 @@ next_port = next_port + 1 l2_bus_link = sst.Link("l2g_mem_link_" + str(next_cache)) - l2_bus_link.connect((l2_memlink, "port", "100ps"), (mem_l2_bus, "high_network_" + str(next_mem_id), "100ps")) + l2_bus_link.connect((l2_cache, "lowlink", "100ps"), (mem_l2_bus, "highlink" + str(next_mem_id), "100ps")) l2_bus_link.setNoCut() if (next_cache + 1) % sub_mems == 0: diff --git a/src/sst/elements/shogun/tests/hierarchy_test_multi.py b/src/sst/elements/shogun/tests/hierarchy_test_multi.py index 5958568086..2632c523a9 100644 --- a/src/sst/elements/shogun/tests/hierarchy_test_multi.py +++ b/src/sst/elements/shogun/tests/hierarchy_test_multi.py @@ -88,13 +88,12 @@ "cache_size" : "32KB", }) - l1_cpulink = l1_cache.setSubComponent("cpulink", "memHierarchy.MemLink") - l1_memlink = l1_cache.setSubComponent("memlink", "memHierarchy.MemNIC") - l1_memlink.addParams({"group" : 1 }) - l1_linkctrl = l1_memlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") + l1_lowlink = l1_cache.setSubComponent("lowlink", "memHierarchy.MemNIC") + l1_lowlink.addParams({"group" : 1 }) + l1_linkctrl = l1_lowlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") corel1link = sst.Link("cpu_l1_link_" + str(cpu_id)) - corel1link.connect((comp_cpu, "cache_link", "100ps"), (l1_cpulink, "port", "100ps")) + corel1link.connect((comp_cpu, "cache_link", "100ps"), (l1_cache, "highlink", "100ps")) corel1link.setNoCut() l1xbarlink = sst.Link("l1_xbar_link_" + str(cpu_id)) @@ -143,8 +142,6 @@ "interleave_step" : str(total_mems * 256) + "B", }) - mem_cpulink = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") - if backend == "simple": # Create DDR (Simple) mem = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") @@ -277,7 +274,7 @@ linkDimmCtrl.connect( (cramsimCtrl, "memLink", "1ns"), (cramsimDimm, "ctrlLink", "1ns") ) bus_mem_link = sst.Link("bus_mem_link_" + str(next_mem)) - bus_mem_link.connect((mem_l2_bus, "low_network_%d"%sub_group_id, "100ps"), (mem_cpulink, "port", "100ps")) + bus_mem_link.connect((mem_l2_bus, "lowlink%d"%sub_group_id, "100ps"), (memctrl, "highlink", "100ps")) bus_mem_link.setNoCut() next_mem = next_mem + 1 @@ -306,10 +303,9 @@ "replacement_policy" : "lru", "verbose" : "2", }) - l2_cpulink = l2_cache.setSubComponent("cpulink", "memHierarchy.MemNIC") - l2_memlink = l2_cache.setSubComponent("memlink", "memHierarchy.MemLink") - l2_linkctrl = l2_cpulink.setSubComponent("linkcontrol", "shogun.ShogunNIC") - l2_cpulink.addParams({ "group" : "2" }) + l2_highlink = l2_cache.setSubComponent("highlink", "memHierarchy.MemNIC") + l2_linkctrl = l2_highlink.setSubComponent("linkcontrol", "shogun.ShogunNIC") + l2_highlink.addParams({ "group" : "2" }) l2xbarlink = sst.Link("l2_xbar_link_" + str(next_cache)) l2xbarlink.connect((l2_linkctrl, "port", "100ps"), (router, "port" + str(next_port), "100ps")) @@ -318,7 +314,7 @@ next_port = next_port + 1 l2_bus_link = sst.Link("l2g_mem_link_" + str(next_cache)) - l2_bus_link.connect((l2_memlink, "port", "100ps"), (mem_l2_bus, "high_network_" + str(next_mem_id), "100ps")) + l2_bus_link.connect((l2_cache, "lowlink", "100ps"), (mem_l2_bus, "highlink" + str(next_mem_id), "100ps")) l2_bus_link.setNoCut() if (next_cache + 1) % sub_mems == 0: diff --git a/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out b/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out index 0a14f7177e..70787c8e9e 100644 --- a/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out +++ b/src/sst/elements/shogun/tests/refFiles/test_shogun_basic_miranda.out @@ -104,13 +104,16 @@ l1cache0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_GetSResp : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_WriteResp : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; l1cache0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -137,6 +140,7 @@ l1cache0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSHit_Arrival : Accumulator : Sum.u64 = 305; SumSQ.u64 = 305; Count.u64 = 305; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXHit_Arrival : Accumulator : Sum.u64 = 94927; SumSQ.u64 = 94927; Count.u64 = 94927; Min.u64 = 1; Max.u64 = 1; l1cache0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -185,14 +189,18 @@ l1cache0.Write_recv : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.GetSResp_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache0.GetXResp_recv : Accumulator : Sum.u64 = 149980; SumSQ.u64 = 149980; Count.u64 = 149980; Min.u64 = 1; Max.u64 = 1; l1cache0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache0.AckPut_recv : Accumulator : Sum.u64 = 149855; SumSQ.u64 = 149855; Count.u64 = 149855; Min.u64 = 1; Max.u64 = 1; l1cache0.MSHR_occupancy : Accumulator : Sum.u64 = 19014584; SumSQ.u64 = 486112436; Count.u64 = 894486; Min.u64 = 0; Max.u64 = 39; @@ -269,13 +277,16 @@ l1cache1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_FetchXResp : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_GetSResp : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_WriteResp : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; l1cache1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -302,6 +313,7 @@ l1cache1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSHit_Arrival : Accumulator : Sum.u64 = 295; SumSQ.u64 = 295; Count.u64 = 295; Min.u64 = 1; Max.u64 = 1; l1cache1.GetXHit_Arrival : Accumulator : Sum.u64 = 96081; SumSQ.u64 = 96081; Count.u64 = 96081; Min.u64 = 1; Max.u64 = 1; l1cache1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -350,14 +362,18 @@ l1cache1.Write_recv : Accumulator : Sum.u64 = 100000; SumSQ.u64 = 100000; Count.u64 = 100000; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.GetXResp_recv : Accumulator : Sum.u64 = 148960; SumSQ.u64 = 148960; Count.u64 = 148960; Min.u64 = 1; Max.u64 = 1; l1cache1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.FetchInvX_recv : Accumulator : Sum.u64 = 3; SumSQ.u64 = 3; Count.u64 = 3; Min.u64 = 1; Max.u64 = 1; + l1cache1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache1.AckPut_recv : Accumulator : Sum.u64 = 148832; SumSQ.u64 = 148832; Count.u64 = 148832; Min.u64 = 1; Max.u64 = 1; l1cache1.MSHR_occupancy : Accumulator : Sum.u64 = 21923537; SumSQ.u64 = 544082959; Count.u64 = 894486; Min.u64 = 0; Max.u64 = 39; diff --git a/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out b/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out index 383ba80e39..a97a9602f6 100644 --- a/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out +++ b/src/sst/elements/shogun/tests/refFiles/test_shogun_hierarchy_test.out @@ -103,13 +103,16 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_GetSResp : Accumulator : Sum.u64 = 200000; SumSQ.u64 = 200000; Count.u64 = 200000; Min.u64 = 1; Max.u64 = 1; l1cache_0.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -117,7 +120,7 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.eventSent_CustomResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.eventSent_CustomAck : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.EventStalledForLockedCacheline : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; - l1cache_0.evict_I : Accumulator : Sum.u64 = 511; SumSQ.u64 = 511; Count.u64 = 511; Min.u64 = 1; Max.u64 = 1; + l1cache_0.evict_I : Accumulator : Sum.u64 = 512; SumSQ.u64 = 512; Count.u64 = 512; Min.u64 = 1; Max.u64 = 1; l1cache_0.evict_S : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_M : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.evict_IS : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -136,6 +139,7 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -182,14 +186,18 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.GetXResp_recv : Accumulator : Sum.u64 = 200000; SumSQ.u64 = 200000; Count.u64 = 200000; Min.u64 = 1; Max.u64 = 1; l1cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_0.AckPut_recv : Accumulator : Sum.u64 = 199488; SumSQ.u64 = 199488; Count.u64 = 199488; Min.u64 = 1; Max.u64 = 1; l1cache_0.MSHR_occupancy : Accumulator : Sum.u64 = 33344536; SumSQ.u64 = 518726562; Count.u64 = 3884829; Min.u64 = 0; Max.u64 = 16; @@ -278,13 +286,16 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_GetSResp : Accumulator : Sum.u64 = 400000; SumSQ.u64 = 400000; Count.u64 = 400000; Min.u64 = 1; Max.u64 = 1; l1cache_1.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -311,6 +322,7 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -357,14 +369,18 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.GetXResp_recv : Accumulator : Sum.u64 = 200001; SumSQ.u64 = 200001; Count.u64 = 200001; Min.u64 = 1; Max.u64 = 1; l1cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_1.AckPut_recv : Accumulator : Sum.u64 = 199489; SumSQ.u64 = 199489; Count.u64 = 199489; Min.u64 = 1; Max.u64 = 1; l1cache_1.MSHR_occupancy : Accumulator : Sum.u64 = 63046098; SumSQ.u64 = 1028206806; Count.u64 = 3884829; Min.u64 = 0; Max.u64 = 17; @@ -453,13 +469,16 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.eventSent_NACK : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_GetSResp : Accumulator : Sum.u64 = 400000; SumSQ.u64 = 400000; Count.u64 = 400000; Min.u64 = 1; Max.u64 = 1; l1cache_2.eventSent_GetXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_WriteResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_FlushLineResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Put : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_Get : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.eventSent_AckMove : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -486,6 +505,7 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.latency_FlushLine_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.latency_FlushLineInv_fail : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.latency_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSXHit_Arrival : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -532,14 +552,18 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l1cache_2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.GetXResp_recv : Accumulator : Sum.u64 = 200001; SumSQ.u64 = 200001; Count.u64 = 200001; Min.u64 = 1; Max.u64 = 1; l1cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Inv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.ForceInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.Fetch_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FetchInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l1cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l1cache_2.AckPut_recv : Accumulator : Sum.u64 = 199489; SumSQ.u64 = 199489; Count.u64 = 199489; Min.u64 = 1; Max.u64 = 1; l1cache_2.MSHR_occupancy : Accumulator : Sum.u64 = 63044580; SumSQ.u64 = 1028031812; Count.u64 = 3884829; Min.u64 = 0; Max.u64 = 17; @@ -663,6 +687,11 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -761,10 +790,12 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.GetXResp_recv : Accumulator : Sum.u64 = 150000; SumSQ.u64 = 150000; Count.u64 = 150000; Min.u64 = 1; Max.u64 = 1; l2cache_0.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.PutE_recv : Accumulator : Sum.u64 = 149616; SumSQ.u64 = 149616; Count.u64 = 149616; Min.u64 = 1; Max.u64 = 1; @@ -776,6 +807,9 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_0.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_0.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_0.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -872,6 +906,11 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -970,10 +1009,12 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.GetXResp_recv : Accumulator : Sum.u64 = 150001; SumSQ.u64 = 150001; Count.u64 = 150001; Min.u64 = 1; Max.u64 = 1; l2cache_1.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.PutE_recv : Accumulator : Sum.u64 = 149617; SumSQ.u64 = 149617; Count.u64 = 149617; Min.u64 = 1; Max.u64 = 1; @@ -985,6 +1026,9 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_1.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_1.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_1.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1109,6 +1153,11 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1207,10 +1256,12 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.GetXResp_recv : Accumulator : Sum.u64 = 150001; SumSQ.u64 = 150001; Count.u64 = 150001; Min.u64 = 1; Max.u64 = 1; l2cache_2.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.PutE_recv : Accumulator : Sum.u64 = 149617; SumSQ.u64 = 149617; Count.u64 = 149617; Min.u64 = 1; Max.u64 = 1; @@ -1222,6 +1273,9 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_2.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_2.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_2.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1318,6 +1372,11 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.eventSent_PutX : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLine : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FlushLineInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAll : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_FlushAllResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_ForwardFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_UnblockFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.eventSent_AckFlush : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_FetchXResp : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.eventSent_AckInv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; @@ -1416,10 +1475,12 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.Write_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLine_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAll_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetSResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.GetXResp_recv : Accumulator : Sum.u64 = 150000; SumSQ.u64 = 150000; Count.u64 = 150000; Min.u64 = 1; Max.u64 = 1; l2cache_3.WriteResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FlushLineResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.FlushAllResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutS_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutM_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.PutE_recv : Accumulator : Sum.u64 = 149616; SumSQ.u64 = 149616; Count.u64 = 149616; Min.u64 = 1; Max.u64 = 1; @@ -1431,6 +1492,9 @@ l2cache_3: No MSHR lookup latency provided (mshr_latency_cycles)...intrapolated l2cache_3.FetchInvX_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FetchResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.FetchXResp_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.ForwardFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.AckFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; + l2cache_3.UnblockFlush_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.NACK_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckInv_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; l2cache_3.AckPut_recv : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; diff --git a/src/sst/elements/vanadis/tests/basic_vanadis.py b/src/sst/elements/vanadis/tests/basic_vanadis.py index 7a3615992e..9476ed5fee 100644 --- a/src/sst/elements/vanadis/tests/basic_vanadis.py +++ b/src/sst/elements/vanadis/tests/basic_vanadis.py @@ -373,29 +373,16 @@ def build( self, prefix, nodeId, cpuId ): cpu_l1dcache = sst.Component(prefix + ".l1dcache", "memHierarchy.Cache") cpu_l1dcache.addParams( l1dcacheParams ) - # L1 I-cache to cpu interface - l1dcache_2_cpu = cpu_l1dcache.setSubComponent("cpulink", "memHierarchy.MemLink") - # L1 I-cache to L2 interface - l1dcache_2_l2cache = cpu_l1dcache.setSubComponent("memlink", "memHierarchy.MemLink") - # L2 I-cache cpu_l1icache = sst.Component( prefix + ".l1icache", "memHierarchy.Cache") cpu_l1icache.addParams( l1icacheParams ) - # L1 I-iache to cpu interface - l1icache_2_cpu = cpu_l1icache.setSubComponent("cpulink", "memHierarchy.MemLink") - # L1 I-cache to L2 interface - l1icache_2_l2cache = cpu_l1icache.setSubComponent("memlink", "memHierarchy.MemLink") - # L2 cache cpu_l2cache = sst.Component(prefix+".l2cache", "memHierarchy.Cache") cpu_l2cache.addParams( l2cacheParams ) - # L2 cache cpu interface - l2cache_2_l1caches = cpu_l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - # L2 cache mem interface - l2cache_2_mem = cpu_l2cache.setSubComponent("memlink", "memHierarchy.MemNIC") + l2cache_2_mem = cpu_l2cache.setSubComponent("lowlink", "memHierarchy.MemNIC") l2cache_2_mem.addParams( l2memLinkParams ) # L1 to L2 buss @@ -419,37 +406,37 @@ def build( self, prefix, nodeId, cpuId ): # CPU (data) -> TLB -> Cache link_cpu_dtlb_link = sst.Link(prefix+".link_cpu_dtlb_link") - link_cpu_dtlb_link.connect( (cpuDcacheIf, "port", "1ns"), (dtlbWrapper, "cpu_if", "1ns") ) + link_cpu_dtlb_link.connect( (cpuDcacheIf, "lowlink", "1ns"), (dtlbWrapper, "cpu_if", "1ns") ) link_cpu_dtlb_link.setNoCut() # data TLB -> data L1 link_cpu_l1dcache_link = sst.Link(prefix+".link_cpu_l1dcache_link") - link_cpu_l1dcache_link.connect( (dtlbWrapper, "cache_if", "1ns"), (l1dcache_2_cpu, "port", "1ns") ) + link_cpu_l1dcache_link.connect( (dtlbWrapper, "cache_if", "1ns"), (cpu_l1dcache, "highlink", "1ns") ) link_cpu_l1dcache_link.setNoCut() # CPU (instruction) -> TLB -> Cache link_cpu_itlb_link = sst.Link(prefix+".link_cpu_itlb_link") - link_cpu_itlb_link.connect( (cpuIcacheIf, "port", "1ns"), (itlbWrapper, "cpu_if", "1ns") ) + link_cpu_itlb_link.connect( (cpuIcacheIf, "lowlink", "1ns"), (itlbWrapper, "cpu_if", "1ns") ) link_cpu_itlb_link.setNoCut() # instruction TLB -> instruction L1 link_cpu_l1icache_link = sst.Link(prefix+".link_cpu_l1icache_link") - link_cpu_l1icache_link.connect( (itlbWrapper, "cache_if", "1ns"), (l1icache_2_cpu, "port", "1ns") ) + link_cpu_l1icache_link.connect( (itlbWrapper, "cache_if", "1ns"), (cpu_l1icache, "highlink", "1ns") ) link_cpu_l1icache_link.setNoCut(); # data L1 -> bus link_l1dcache_l2cache_link = sst.Link(prefix+".link_l1dcache_l2cache_link") - link_l1dcache_l2cache_link.connect( (l1dcache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_0", "1ns") ) + link_l1dcache_l2cache_link.connect( (cpu_l1dcache, "lowlink", "1ns"), (cache_bus, "highlink0", "1ns") ) link_l1dcache_l2cache_link.setNoCut() # instruction L1 -> bus link_l1icache_l2cache_link = sst.Link(prefix+".link_l1icache_l2cache_link") - link_l1icache_l2cache_link.connect( (l1icache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_1", "1ns") ) + link_l1icache_l2cache_link.connect( (cpu_l1icache, "lowlink", "1ns"), (cache_bus, "highlink1", "1ns") ) link_l1icache_l2cache_link.setNoCut() # BUS to L2 cache link_bus_l2cache_link = sst.Link(prefix+".link_bus_l2cache_link") - link_bus_l2cache_link.connect( (cache_bus, "low_network_0", "1ns"), (l2cache_2_l1caches, "port", "1ns") ) + link_bus_l2cache_link.connect( (cache_bus, "lowlink0", "1ns"), (cpu_l2cache, "highlink", "1ns") ) link_bus_l2cache_link.setNoCut() return (cpu, "os_link", "5ns"), (l2cache_2_mem, "port", "1ns") , (dtlb, "mmu", "1ns"), (itlb, "mmu", "1ns") @@ -490,8 +477,7 @@ def addParamsPrefix(prefix,params): # node OS l1 data cache os_cache = sst.Component("node_os.cache", "memHierarchy.Cache") os_cache.addParams(osl1cacheParams) -os_cache_2_cpu = os_cache.setSubComponent("cpulink", "memHierarchy.MemLink") -os_cache_2_mem = os_cache.setSubComponent("memlink", "memHierarchy.MemNIC") +os_cache_2_mem = os_cache.setSubComponent("lowlink", "memHierarchy.MemNIC") os_cache_2_mem.addParams( l2memLinkParams ) # node memory router @@ -503,19 +489,14 @@ def addParamsPrefix(prefix,params): dirctrl = sst.Component("dirctrl", "memHierarchy.DirectoryController") dirctrl.addParams(dirCtrlParams) -# node directory controller port to memory -dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") # node directory controller port to cpu -dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNIC") +dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNIC") dirNIC.addParams(dirNicParams) # node memory controller memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams( memCtrlParams ) -# node memory controller port to directory controller -memToDir = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") - # node memory controller backend memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") memory.addParams(memParams) @@ -529,7 +510,7 @@ def addParamsPrefix(prefix,params): # OS (data) -> TLB -> Cache #link_os_ostlb_link = sst.Link("link_os_ostlb_link") -#link_os_ostlb_link.connect( (node_os_mem_if, "port", "1ns"), (ostlbWrapper, "cpu_if", "1ns") ) +#link_os_ostlb_link.connect( (node_os_mem_if, "lowlink", "1ns"), (ostlbWrapper, "cpu_if", "1ns") ) # Directory controller to memory router link_dir_2_rtr = sst.Link("link_dir_2_rtr") @@ -538,7 +519,7 @@ def addParamsPrefix(prefix,params): # Directory controller to memory controller link_dir_2_mem = sst.Link("link_dir_2_mem") -link_dir_2_mem.connect( (dirtoM, "port", "1ns"), (memToDir, "port", "1ns") ) +link_dir_2_mem.connect( (dirctrl, "lowlink", "1ns"), (memctrl, "highlink", "1ns") ) link_dir_2_mem.setNoCut() # MMU -> ostlb @@ -548,8 +529,8 @@ def addParamsPrefix(prefix,params): # ostlb -> os l1 cache link_os_cache_link = sst.Link("link_os_cache_link") -#link_os_cache_link.connect( (ostlbWrapper, "cache_if", "1ns"), (os_cache_2_cpu, "port", "1ns") ) -link_os_cache_link.connect( (node_os_mem_if, "port", "1ns"), (os_cache_2_cpu, "port", "1ns") ) +#link_os_cache_link.connect( (ostlbWrapper, "cache_if", "1ns"), (os_cache, "highlink", "1ns") ) +link_os_cache_link.connect( (node_os_mem_if, "lowlink", "1ns"), (os_cache, "highlink", "1ns") ) link_os_cache_link.setNoCut() os_cache_2_rtr = sst.Link("os_cache_2_rtr") diff --git a/src/sst/elements/vanadis/tests/boom_vanadis-kingsley.py b/src/sst/elements/vanadis/tests/boom_vanadis-kingsley.py index 13a9cb9641..8470f8bffa 100644 --- a/src/sst/elements/vanadis/tests/boom_vanadis-kingsley.py +++ b/src/sst/elements/vanadis/tests/boom_vanadis-kingsley.py @@ -431,31 +431,18 @@ def build( self, prefix, nodeId, cpuId ): cpu_l1dcache = sst.Component(prefix + ".l1dcache", "memHierarchy.Cache") cpu_l1dcache.addParams( l1dcacheParams ) - # L1 I-cache to cpu interface - l1dcache_2_cpu = cpu_l1dcache.setSubComponent("cpulink", "memHierarchy.MemLink") - # L1 I-cache to L2 interface - l1dcache_2_l2cache = cpu_l1dcache.setSubComponent("memlink", "memHierarchy.MemLink") - # L2 I-cache cpu_l1icache = sst.Component( prefix + ".l1icache", "memHierarchy.Cache") cpu_l1icache.addParams( l1icacheParams ) - # L1 I-iache to cpu interface - l1icache_2_cpu = cpu_l1icache.setSubComponent("cpulink", "memHierarchy.MemLink") - # L1 I-cache to L2 interface - l1icache_2_l2cache = cpu_l1icache.setSubComponent("memlink", "memHierarchy.MemLink") - # L2 cache cpu_l2cache = sst.Component(prefix + ".l2cache", "memHierarchy.Cache") cpu_l2cache.addParams( l2cacheParams ) l2pre = cpu_l2cache.setSubComponent("prefetcher", "cassini.StridePrefetcher") l2pre.addParams(l2_prefetch_params) - # L2 cache cpu interface - l2cache_2_l1caches = cpu_l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") - # L2 cache mem interface - l2cache_2_mem = cpu_l2cache.setSubComponent("memlink", "memHierarchy.MemNICFour") + l2cache_2_mem = cpu_l2cache.setSubComponent("lowlink", "memHierarchy.MemNICFour") l2cache_2_mem.addParams( l2memLinkParams ) l2data = l2cache_2_mem.setSubComponent("data", "kingsley.linkcontrol") l2req = l2cache_2_mem.setSubComponent("req", "kingsley.linkcontrol") @@ -487,37 +474,37 @@ def build( self, prefix, nodeId, cpuId ): # CPU (data) -> TLB -> Cache link_cpu_dtlb_link = sst.Link(prefix+".link_cpu_dtlb_link") - link_cpu_dtlb_link.connect( (cpuDcacheIf, "port", "1ns"), (dtlbWrapper, "cpu_if", "1ns") ) + link_cpu_dtlb_link.connect( (cpuDcacheIf, "lowlink", "1ns"), (dtlbWrapper, "cpu_if", "1ns") ) link_cpu_dtlb_link.setNoCut() # data TLB -> data L1 link_cpu_l1dcache_link = sst.Link(prefix+".link_cpu_l1dcache_link") - link_cpu_l1dcache_link.connect( (dtlbWrapper, "cache_if", "1ns"), (l1dcache_2_cpu, "port", "1ns") ) + link_cpu_l1dcache_link.connect( (dtlbWrapper, "cache_if", "1ns"), (cpu_l1dcache, "highlink", "1ns") ) link_cpu_l1dcache_link.setNoCut() # CPU (instruction) -> TLB -> Cache link_cpu_itlb_link = sst.Link(prefix+".link_cpu_itlb_link") - link_cpu_itlb_link.connect( (cpuIcacheIf, "port", "1ns"), (itlbWrapper, "cpu_if", "1ns") ) + link_cpu_itlb_link.connect( (cpuIcacheIf, "lowlink", "1ns"), (itlbWrapper, "cpu_if", "1ns") ) link_cpu_itlb_link.setNoCut() # instruction TLB -> instruction L1 link_cpu_l1icache_link = sst.Link(prefix+".link_cpu_l1icache_link") - link_cpu_l1icache_link.connect( (itlbWrapper, "cache_if", "1ns"), (l1icache_2_cpu, "port", "1ns") ) + link_cpu_l1icache_link.connect( (itlbWrapper, "cache_if", "1ns"), (cpu_l1icache, "highlink", "1ns") ) link_cpu_l1icache_link.setNoCut(); # data L1 -> bus link_l1dcache_l2cache_link = sst.Link(prefix+".link_l1dcache_l2cache_link") - link_l1dcache_l2cache_link.connect( (l1dcache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_0", "1ns") ) + link_l1dcache_l2cache_link.connect( (cpu_l1dcache, "lowlink", "1ns"), (cache_bus, "highlink0", "1ns") ) link_l1dcache_l2cache_link.setNoCut() # instruction L1 -> bus link_l1icache_l2cache_link = sst.Link(prefix+".link_l1icache_l2cache_link") - link_l1icache_l2cache_link.connect( (l1icache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_1", "1ns") ) + link_l1icache_l2cache_link.connect( (cpu_l1icache, "lowlink", "1ns"), (cache_bus, "highlink1", "1ns") ) link_l1icache_l2cache_link.setNoCut() # BUS to L2 cache link_bus_l2cache_link = sst.Link(prefix+".link_bus_l2cache_link") - link_bus_l2cache_link.connect( (cache_bus, "low_network_0", "1ns"), (l2cache_2_l1caches, "port", "1ns") ) + link_bus_l2cache_link.connect( (cache_bus, "lowlink0", "1ns"), (cpu_l2cache, "highlink", "1ns") ) link_bus_l2cache_link.setNoCut() return (cpu, "os_link", "5ns"), (dtlb, "mmu", "1ns"), (itlb, "mmu", "1ns"), \ @@ -560,8 +547,7 @@ def addParamsPrefix(prefix,params): # node OS l1 data cache os_cache = sst.Component("node_os.cache", "memHierarchy.Cache") os_cache.addParams(osl1cacheParams) -os_cache_2_cpu = os_cache.setSubComponent("cpulink", "memHierarchy.MemLink") -os_cache_2_mem = os_cache.setSubComponent("memlink", "memHierarchy.MemNICFour") +os_cache_2_mem = os_cache.setSubComponent("lowlink", "memHierarchy.MemNICFour") os_cache_2_mem.addParams( l2memLinkParams ) os_data = os_cache_2_mem.setSubComponent("data", "kingsley.linkcontrol") os_req = os_cache_2_mem.setSubComponent("req", "kingsley.linkcontrol") @@ -596,7 +582,7 @@ def build(self, nodeID, memID): "addr_range_end" : 1024*1024*1024 - ((numMemories - memID) * 64) + 63, }) - memNIC = memctrl.setSubComponent("cpulink", "memHierarchy.MemNICFour") + memNIC = memctrl.setSubComponent("highlink", "memHierarchy.MemNICFour") memNIC.addParams({ "group" : 3, "debug_level" : mh_debug_level, @@ -643,7 +629,7 @@ def build(self, nodeID, memID): }) # node directory controller port to cpu - dirNIC = dirctrl.setSubComponent("cpulink", "memHierarchy.MemNICFour") + dirNIC = dirctrl.setSubComponent("highlink", "memHierarchy.MemNICFour") dirNIC.addParams({ "group" : 2, "debug" : mh_debug, @@ -669,8 +655,8 @@ def build(self, nodeID, memID): # ostlb -> os l1 cache link_os_cache_link = sst.Link("link_os_cache_link") -#link_os_cache_link.connect( (ostlbWrapper, "cache_if", "1ns"), (os_cache_2_cpu, "port", "1ns") ) -link_os_cache_link.connect( (node_os_mem_if, "port", "1ns"), (os_cache_2_cpu, "port", "1ns") ) +#link_os_cache_link.connect( (ostlbWrapper, "cache_if", "1ns"), (os_cache, "highlink", "1ns") ) +link_os_cache_link.connect( (node_os_mem_if, "lowlink", "1ns"), (os_cache, "highlink", "1ns") ) link_os_cache_link.setNoCut() def is_on_top_row(index): diff --git a/src/sst/elements/vanadis/tests/no_rtr_vanadis.py b/src/sst/elements/vanadis/tests/no_rtr_vanadis.py index afdce423ce..7032632ae9 100644 --- a/src/sst/elements/vanadis/tests/no_rtr_vanadis.py +++ b/src/sst/elements/vanadis/tests/no_rtr_vanadis.py @@ -219,8 +219,6 @@ "debug_level" : 10, "debug_addr" : dbg_addr, }) -l1dcache_2_cpu = cpu0_l1dcache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1dcache_2_l2cache = cpu0_l1dcache.setSubComponent("memlink", "memHierarchy.MemLink") cpu0_l1icache = sst.Component("cpu0.l1icache", "memHierarchy.Cache") cpu0_l1icache.addParams({ @@ -238,8 +236,6 @@ "debug_level" : 10, "debug_addr" : dbg_addr, }) -l1icache_2_cpu = cpu0_l1icache.setSubComponent("cpulink", "memHierarchy.MemLink") -l1icache_2_l2cache = cpu0_l1icache.setSubComponent("memlink", "memHierarchy.MemLink") cpu0_l2cache = sst.Component("l2cache", "memHierarchy.Cache") cpu0_l2cache.addParams({ @@ -254,8 +250,6 @@ "debug_level" : 10, "debug_addr" : dbg_addr, }) -l2cache_2_l1caches = cpu0_l2cache.setSubComponent("cpulink", "memHierarchy.MemLink") -l2cache_2_mem = cpu0_l2cache.setSubComponent("memlink", "memHierarchy.MemLink") cache_bus = sst.Component("bus", "memHierarchy.Bus") cache_bus.addParams({ @@ -275,7 +269,6 @@ "debug_addr" : dbg_addr, }) dirtoM = dirctrl.setSubComponent("memlink", "memHierarchy.MemLink") -dirtoCPU = dirctrl.setSubComponent("cpulink", "memHierarchy.MemLink") memctrl = sst.Component("memory", "memHierarchy.MemController") memctrl.addParams({ @@ -289,7 +282,6 @@ "debug_level" : 10, "debug_addr" : dbg_addr, }) -memToDir = memctrl.setSubComponent("cpulink", "memHierarchy.MemLink") memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem") memory.addParams({ @@ -304,32 +296,32 @@ branch_pred.enableAllStatistics() link_cpu0_l1dcache_link = sst.Link("link_cpu0_l1dcache_link") -link_cpu0_l1dcache_link.connect( (dcache_if, "port", "1ns"), (l1dcache_2_cpu, "port", "1ns") ) +link_cpu0_l1dcache_link.connect( (dcache_if, "lowlink", "1ns"), (cpu0_l1dcache, "highlink", "1ns") ) link_cpu0_l1icache_link = sst.Link("link_cpu0_l1icache_link") -link_cpu0_l1icache_link.connect( (icache_if, "port", "1ns"), (l1icache_2_cpu, "port", "1ns") ) +link_cpu0_l1icache_link.connect( (icache_if, "lowlink", "1ns"), (cpu0_l1icache, "highlink", "1ns") ) link_os_l1dcache_link = sst.Link("link_os_l1dcache_link") -link_os_l1dcache_link.connect( (node_os_mem_if, "port", "1ns"), (os_l1dcache, "high_network_0", "1ns") ) +link_os_l1dcache_link.connect( (node_os_mem_if, "lowlink", "1ns"), (os_l1dcache, "highlink", "1ns") ) link_l1dcache_l2cache_link = sst.Link("link_l1dcache_l2cache_link") -link_l1dcache_l2cache_link.connect( (l1dcache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_0", "1ns") ) +link_l1dcache_l2cache_link.connect( (cpu0_l1dcache, "lowlink", "1ns"), (cache_bus, "highlink0", "1ns") ) link_l1icache_l2cache_link = sst.Link("link_l1icache_l2cache_link") -link_l1icache_l2cache_link.connect( (l1icache_2_l2cache, "port", "1ns"), (cache_bus, "high_network_1", "1ns") ) +link_l1icache_l2cache_link.connect( (cpu0_l1icache, "lowlink", "1ns"), (cache_bus, "highlink1", "1ns") ) link_os_l1dcache_l2cache_link = sst.Link("link_os_l1dcache_l2cache_link") -link_os_l1dcache_l2cache_link.connect( (os_l1dcache, "low_network_0", "1ns"), (cache_bus, "high_network_2", "1ns") ) +link_os_l1dcache_l2cache_link.connect( (os_l1dcache, "lowlink", "1ns"), (cache_bus, "highlink2", "1ns") ) link_bus_l2cache_link = sst.Link("link_bus_l2cache_link") -link_bus_l2cache_link.connect( (cache_bus, "low_network_0", "1ns"), (l2cache_2_l1caches, "port", "1ns") ) +link_bus_l2cache_link.connect( (cache_bus, "lowlink0", "1ns"), (cpu0_l2cache, "highlink", "1ns") ) link_l2cache_2_dir = sst.Link("link_l2cache_2_dir") -link_l2cache_2_dir.connect( (dirtoCPU, "port", "1ns"), (l2cache_2_mem, "port", "1ns") ) +link_l2cache_2_dir.connect( (dirctrl, "highlink", "1ns"), (cpu0_l2cache, "lowlink", "1ns") ) link_dir_2_mem = sst.Link("link_dir_2_mem") -link_dir_2_mem.connect( (dirtoM, "port", "1ns"), (memToDir, "port", "1ns") ) +link_dir_2_mem.connect( (dirctrl, "lowlink", "1ns"), (memctrl, "highlink", "1ns") ) link_core0_os_link = sst.Link("link_core0_os_link") link_core0_os_link.connect( (v_cpu_0, "os_link", "5ns"), (node_os, "core0", "5ns") ) diff --git a/src/sst/elements/vaultsim/logicLayer.cc b/src/sst/elements/vaultsim/logicLayer.cc index fa676f854d..71257145c2 100644 --- a/src/sst/elements/vaultsim/logicLayer.cc +++ b/src/sst/elements/vaultsim/logicLayer.cc @@ -131,7 +131,7 @@ void logicLayer::init(unsigned int phase) { SST::MemHierarchy::Addr addr = me->getAddr(); for (int i = 0; i < numNewEv; ++i) { // make new event - MemEvent *newEv = new MemEvent(this, addr, + MemEvent *newEv = new MemEvent(getName(), addr, me->getBaseAddr(), me->getCmd()); // set size and payload diff --git a/src/sst/elements/vaultsim/tests/pimExper.py b/src/sst/elements/vaultsim/tests/pimExper.py index 95137ff0ab..325b992217 100644 --- a/src/sst/elements/vaultsim/tests/pimExper.py +++ b/src/sst/elements/vaultsim/tests/pimExper.py @@ -134,13 +134,13 @@ def doQuad(quad, cores, rtr, rtrPort, netAddr): portName = "cache_link_" + str(coreCtr.nextPort()) arielL1Link.connect((ariel, portName, busLat), - (l1id, "high_network_0", busLat)) + (l1id, "highlink", busLat)) else: coreL1Link = sst.Link("core_cache_link_%d"%core) coreL1Link.connect((coreObj, "mem_link", busLat), - (l1id, "high_network_0", busLat)) + (l1id, "highlink", busLat)) membusLink = sst.Link("cache_bus_link_%d"%core) - membusLink.connect((l1id, "low_network_0", busLat), (bus, "high_network_%d"%x, busLat)) + membusLink.connect((l1id, "lowlink", busLat), (bus, "highlink%d"%x, busLat)) #make the L2 for the quad cluster l2 = sst.Component("l2cache_nid%d"%netAddr, "memHierarchy.Cache") @@ -154,15 +154,20 @@ def doQuad(quad, cores, rtr, rtrPort, netAddr): "access_latency_cycles": 23, "mshr_num_entries" : 4096, #64, # TODO: Cesar will update "L1": 0, - "network_bw": coreNetBW, "debug_level" : 6, "debug": memDebug }) l2.addParams(l2PrefetchParams) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams({ + "network_bw" : coreNetBW, + "group" : 1, + }) + link = sst.Link("l2cache_%d_link"%quad) - link.connect((l2, "high_network_0", busLat), (bus, "low_network_0", busLat)) + link.connect((l2, "highlink", busLat), (bus, "lowlink0", busLat)) link = sst.Link("l2cache_%d_netlink"%quad) - link.connect((l2, "directory", netLat), (rtr, "port%d"%(rtrPort), netLat)) + link.connect((l2_nic, "port", netLat), (rtr, "port%d"%(rtrPort), netLat)) sst.popNamePrefix() @@ -217,11 +222,17 @@ def doFakeDC(rtr, nextPort, netAddr, dcNum): "clock": memclock, "debug": memDebug, }) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams({ + "network_bw" : memNetBW, + "group" : 2, + }) + #wire up memLink = sst.Link("fake_mem%d_link"%dcNum) - memLink.connect((memctrl, "direct_link", busLat), (dc, "memory", busLat)) + memLink.connect((memctrl, "highlink", busLat), (dc, "lowlink", busLat)) netLink = sst.Link("fake_dc%d_netlink"%dcNum) - netLink.connect((dc, "network", netLat), (rtr, "port%d"%(nextPort), netLat)) + netLink.connect((dc_nic, "port", netLat), (rtr, "port%d"%(nextPort), netLat)) def doDC(rtr, nextPort, netAddr, dcNum): start_pos = (dcNum * interleave_size); @@ -259,11 +270,16 @@ def doDC(rtr, nextPort, netAddr, dcNum): "clock": memclock, "debug": memDebug, }) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams({ + "network_bw" : memNetBW, + "group" : 2, + }) #wire up memLink = sst.Link("mem%d_link"%dcNum) - memLink.connect((memctrl, "direct_link", busLat), (dc, "memory", busLat)) + memLink.connect((memctrl, "highlink", busLat), (dc, "lowlink", busLat)) netLink = sst.Link("dc%d_netlink"%dcNum) - netLink.connect((dc, "network", netLat), (rtr, "port%d"%(nextPort), netLat)) + netLink.connect((dc_nic, "port", netLat), (rtr, "port%d"%(nextPort), netLat)) def doCPU(): sst.pushNamePrefix("cpu") diff --git a/src/sst/elements/vaultsim/tests/sdl3.py b/src/sst/elements/vaultsim/tests/sdl3.py index e108d485bc..96512dc008 100644 --- a/src/sst/elements/vaultsim/tests/sdl3.py +++ b/src/sst/elements/vaultsim/tests/sdl3.py @@ -174,13 +174,13 @@ def doQuad(quad, cores, rtr, rtrPort, netAddr): portName = "cache_link_" + str(coreCtr.nextPort()) arielL1Link.connect((ariel, portName, busLat), - (l1id, "high_network_0", busLat)) + (l1id, "highlink", busLat)) else: coreL1Link = sst.Link("core_cache_link_%d"%core) coreL1Link.connect((coreObj, "mem_link", busLat), - (l1id, "high_network_0", busLat)) + (l1id, "highlink", busLat)) membusLink = sst.Link("cache_bus_link_%d"%core) - membusLink.connect((l1id, "low_network_0", busLat), (bus, "high_network_%d"%x, busLat)) + membusLink.connect((l1id, "lowlink", busLat), (bus, "highlink%d"%x, busLat)) #make the L2 for the quad cluster l2 = sst.Component("l2cache_nid%d"%netAddr, "memHierarchy.Cache") @@ -198,10 +198,15 @@ def doQuad(quad, cores, rtr, rtrPort, netAddr): "debug": memDebug }) l2.addParams(l2PrefetchParams) + l2_nic = l2.setSubComponent("lowlink", "memHierarchy.MemNIC") + l2_nic.addParams({ + "network_bw" : coreNetBW, + "group" : 1, + }) link = sst.Link("l2cache_%d_link"%quad) - link.connect((l2, "high_network_0", busLat), (bus, "low_network_0", busLat)) + link.connect((l2, "highlink", busLat), (bus, "lowlink0", busLat)) link = sst.Link("l2cache_%d_netlink"%quad) - link.connect((l2, "directory", netLat), (rtr, "port%d"%(rtrPort), netLat)) + link.connect((l2_nic, "port", netLat), (rtr, "port%d"%(rtrPort), netLat)) sst.popNamePrefix() @@ -254,7 +259,6 @@ def doFakeDC(rtr, nextPort, netAddr, dcNum): print("DC nid%d\n %x to %x\n iSize %x iStep %x" % (netAddr, 0, 0, 0, 0)) dc.addParams({ "coherence_protocol": coherence_protocol, - "network_bw": memNetBW, "addr_range_start": 0, "addr_range_end": 0, "interleave_size": 0//1024, # in KB @@ -263,11 +267,16 @@ def doFakeDC(rtr, nextPort, netAddr, dcNum): "clock": memclock, "debug": memDebug, }) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams({ + "network_bw": memNetBW, + "group" : 2, + }) #wire up memLink = sst.Link("fake_mem%d_link"%dcNum) - memLink.connect((memctrl, "direct_link", busLat), (dc, "memctrl", busLat)) + memLink.connect((memctrl, "highlink", busLat), (dc, "lowlink", busLat)) netLink = sst.Link("fake_dc%d_netlink"%dcNum) - netLink.connect((dc, "network", netLat), (rtr, "port%d"%(nextPort), netLat)) + netLink.connect((dc_nic, "port", netLat), (rtr, "port%d"%(nextPort), netLat)) def doDC(rtr, nextPort, netAddr, dcNum): start_pos = (dcNum * interleave_size); @@ -304,11 +313,16 @@ def doDC(rtr, nextPort, netAddr, dcNum): "clock": memclock, "debug": memDebug, }) + dc_nic = dc.setSubComponent("highlink", "memHierarchy.MemNIC") + dc_nic.addParams({ + "network_bw": memNetBW, + "group" : 2, + }) #wire up memLink = sst.Link("mem%d_link"%dcNum) - memLink.connect((memctrl, "direct_link", busLat), (dc, "memory", busLat)) + memLink.connect((memctrl, "highlink", busLat), (dc, "lowlink", busLat)) netLink = sst.Link("dc%d_netlink"%dcNum) - netLink.connect((dc, "network", netLat), (rtr, "port%d"%(nextPort), netLat)) + netLink.connect((dc_nic, "port", netLat), (rtr, "port%d"%(nextPort), netLat)) def doCPU(): sst.pushNamePrefix("cpu")