diff --git a/src/sst/elements/osseous/AXI_port.h b/src/sst/elements/osseous/AXI_port.h
deleted file mode 100644
index c25802304e..0000000000
--- a/src/sst/elements/osseous/AXI_port.h
+++ /dev/null
@@ -1,995 +0,0 @@
-// Copyright (c) 2019-2022 Antmicro (https://www.antmicro.com/). All rights reserved. 
-// Licensed under the Apache License, Version 2.0, you may not use this file except in 
-// compliance with the Apache License. You may obtain a copy of the Apache License at 
-// http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or 
-// agreed to in writing, software distributed under the Apache License is distributed 
-// on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 
-// implied. See the Apache License for the specific language governing permissions and 
-// limitations under the Apache License.
-
-#ifndef AXITOP_H_
-#define AXITOP_H_
-
-//not originally included in the headerfile 
-enum DEBUG_FLAGS{d_control, d_data, d_addr, d_reg};  
-DEBUG_FLAGS debug_flag;
-//void print_registers(DEBUG_FLAGS);
-
-
-#include <array>
-#include <cstdint>
-#include <cstdlib>
-#include "uint.h"
-#include "sint.h"
-#define UNLIKELY(condition) __builtin_expect(static_cast<bool>(condition), 0)
-
-typedef struct AXI4LiteCSR {
-  UInt<3> state;
-  UInt<1> awready;
-  UInt<1> wready;
-  UInt<1> bvalid;
-  UInt<1> arready;
-  UInt<1> rvalid;
-  UInt<32> addr;
-
-  AXI4LiteCSR() {
-    state.rand_init();
-    awready.rand_init();
-    wready.rand_init();
-    bvalid.rand_init();
-    arready.rand_init();
-    rvalid.rand_init();
-    addr.rand_init();
-  }
-} AXI4LiteCSR;
-
-typedef struct AXIStreamSlave {
-  UInt<2> state;
-  UInt<1> done;
-  UInt<1> enable;
-  UInt<32> length;
-
-  AXIStreamSlave() {
-    state.rand_init();
-    done.rand_init();
-    enable.rand_init();
-    length.rand_init();
-  }
-} AXIStreamSlave;
-
-typedef struct AXI4Writer {
-  UInt<2> dataState;
-  UInt<2> addrState;
-  UInt<1> done;
-  UInt<1> enable;
-  UInt<32> length;
-  UInt<32> awlen;
-  UInt<32> awaddr;
-  UInt<1> awvalid;
-  UInt<1> bready;
-
-  AXI4Writer() {
-    dataState.rand_init();
-    addrState.rand_init();
-    done.rand_init();
-    enable.rand_init();
-    length.rand_init();
-    awlen.rand_init();
-    awaddr.rand_init();
-    awvalid.rand_init();
-    bready.rand_init();
-  }
-} AXI4Writer;
-
-typedef struct CSR {
-
-  CSR() {
-  }
-} CSR;
-
-typedef struct AddressGenerator {
-  UInt<2> state;
-  UInt<32> lineCount;
-  UInt<32> lineGap;
-  UInt<32> address_o;
-  UInt<32> address_i;
-  UInt<32> length_o;
-  UInt<32> length_i;
-  UInt<1> valid;
-  UInt<1> busy;
-
-  AddressGenerator() {
-    state.rand_init();
-    lineCount.rand_init();
-    lineGap.rand_init();
-    address_o.rand_init();
-    address_i.rand_init();
-    length_o.rand_init();
-    length_i.rand_init();
-    valid.rand_init();
-    busy.rand_init();
-  }
-} AddressGenerator;
-
-typedef struct TransferSplitter {
-
-  TransferSplitter() {
-  }
-} TransferSplitter;
-
-typedef struct TransferSplitter_1 {
-  UInt<32> _T_42;
-  UInt<32> _T_45;
-  UInt<32> _T_48;
-  UInt<32> _T_51;
-  UInt<1> _T_60;
-  UInt<1> _T_63;
-  UInt<2> _T_65;
-
-  TransferSplitter_1() {
-    _T_42.rand_init();
-    _T_45.rand_init();
-    _T_48.rand_init();
-    _T_51.rand_init();
-    _T_60.rand_init();
-    _T_63.rand_init();
-    _T_65.rand_init();
-  }
-} TransferSplitter_1;
-
-typedef struct ClearCSR {
-  UInt<32> reg;
-
-  ClearCSR() {
-    reg.rand_init();
-  }
-} ClearCSR;
-
-typedef struct StatusCSR {
-  UInt<32> reg;
-
-  StatusCSR() {
-    reg.rand_init();
-  }
-} StatusCSR;
-
-typedef struct SimpleCSR {
-  UInt<32> reg;
-
-  SimpleCSR() {
-    reg.rand_init();
-  }
-} SimpleCSR;
-
-typedef struct SetCSR {
-  UInt<32> reg;
-
-  SetCSR() {
-    reg.rand_init();
-  }
-} SetCSR;
-
-typedef struct InterruptController {
-  UInt<1> readBusy;
-  UInt<1> readBusyOld;
-  UInt<1> writeBusy;
-  UInt<1> writeBusyOld;
-  UInt<1> writeBusyIrq;
-  UInt<1> readBusyIrq;
-  SimpleCSR SimpleCSR$$inst;
-  SetCSR SetCSR$$inst;
-
-  InterruptController() {
-    readBusy.rand_init();
-    readBusyOld.rand_init();
-    writeBusy.rand_init();
-    writeBusyOld.rand_init();
-    writeBusyIrq.rand_init();
-    readBusyIrq.rand_init();
-  }
-} InterruptController;
-
-typedef struct WorkerCSRWrapper {
-  UInt<2> status;
-  UInt<1> readerSync;
-  UInt<1> readerSyncOld;
-  UInt<1> writerSync;
-  UInt<1> writerSyncOld;
-  UInt<1> readerStart;
-  UInt<1> writerStart;
-  AddressGenerator addressGeneratorRead;
-  TransferSplitter transferSplitterRead;
-  AddressGenerator addressGeneratorWrite;
-  TransferSplitter_1 transferSplitterWrite;
-  ClearCSR ClearCSR$$inst;
-  StatusCSR StatusCSR$$inst;
-  InterruptController InterruptController$$inst;
-  SimpleCSR SimpleCSR$$inst;
-  SimpleCSR SimpleCSR_1;
-  SimpleCSR SimpleCSR_2;
-  SimpleCSR SimpleCSR_3;
-  SimpleCSR SimpleCSR_4;
-  SimpleCSR SimpleCSR_5;
-  SimpleCSR SimpleCSR_6;
-  SimpleCSR SimpleCSR_7;
-  SimpleCSR SimpleCSR_8;
-  SimpleCSR SimpleCSR_9;
-  SimpleCSR SimpleCSR_10;
-  SimpleCSR SimpleCSR_11;
-
-  WorkerCSRWrapper() {
-    status.rand_init();
-    readerSync.rand_init();
-    readerSyncOld.rand_init();
-    writerSync.rand_init();
-    writerSyncOld.rand_init();
-    readerStart.rand_init();
-    writerStart.rand_init();
-  }
-} WorkerCSRWrapper;
-
-typedef struct Queue {
-  UInt<9> value;
-  UInt<9> value_1;
-  UInt<1> maybe_full;
-  UInt<32> ram[512];
-
-  Queue() {
-    value.rand_init();
-    value_1.rand_init();
-    maybe_full.rand_init();
-    for (size_t a=0; a < 512; a++) ram[a].rand_init();
-  }
-} Queue;
-
-typedef struct AXITop {
-  UInt<1> clock;
-  UInt<1> reset;
-  UInt<32> io_control_aw_awaddr;
-  UInt<3> io_control_aw_awprot;
-  UInt<1> io_control_aw_awvalid;
-  UInt<1> io_control_aw_awready;
-  UInt<32> io_control_w_wdata;
-  UInt<4> io_control_w_wstrb;
-  UInt<1> io_control_w_wvalid;
-  UInt<1> io_control_w_wready;
-  UInt<2> io_control_b_bresp;
-  UInt<1> io_control_b_bvalid;
-  UInt<1> io_control_b_bready;
-  UInt<32> io_control_ar_araddr;
-  UInt<3> io_control_ar_arprot;
-  UInt<1> io_control_ar_arvalid;
-  UInt<1> io_control_ar_arready;
-  UInt<32> io_control_r_rdata;
-  UInt<2> io_control_r_rresp;
-  UInt<1> io_control_r_rvalid;
-  UInt<1> io_control_r_rready;
-  UInt<32> io_read_tdata;
-  //================================= i would have to use these pins ============
-  UInt<1> io_read_tvalid;
-  UInt<1> io_read_tready;
-  UInt<1> io_read_tuser;
-  UInt<1> io_read_tlast;
-  //================================= i would have to use these pins ============
-  UInt<4>  io_write_aw_awid;
-  UInt<32> io_write_aw_awaddr;
-  UInt<8>  io_write_aw_awlen;
-  UInt<3>  io_write_aw_awsize;
-  UInt<2>  io_write_aw_awburst;
-  UInt<1>  io_write_aw_awlock;
-  UInt<4>  io_write_aw_awcache;
-  UInt<3>  io_write_aw_awprot;
-  UInt<4>  io_write_aw_awqos;
-  UInt<1>  io_write_aw_awvalid;
-  UInt<1>  io_write_aw_awready;
-  UInt<32> io_write_w_wdata;
-  UInt<4>  io_write_w_wstrb;
-  UInt<1>  io_write_w_wlast;
-  UInt<1>  io_write_w_wvalid;
-  UInt<1>  io_write_w_wready;
-  UInt<4>  io_write_b_bid;
-  UInt<2>  io_write_b_bresp;
-  UInt<1>  io_write_b_bvalid;
-  UInt<1>  io_write_b_bready;
-  UInt<4>  io_write_ar_arid;
-  UInt<32> io_write_ar_araddr;
-  UInt<8>  io_write_ar_arlen;
-  UInt<3>  io_write_ar_arsize;
-  UInt<2>  io_write_ar_arburst;
-  UInt<1>  io_write_ar_arlock;
-  UInt<4>  io_write_ar_arcache;
-  UInt<3>  io_write_ar_arprot;
-  UInt<4>  io_write_ar_arqos;
-  UInt<1>  io_write_ar_arvalid;
-  UInt<1>  io_write_ar_arready;
-  UInt<4>  io_write_r_rid;
-  UInt<32> io_write_r_rdata;
-  UInt<2> io_write_r_rresp;
-  UInt<1> io_write_r_rlast;
-  UInt<1> io_write_r_rvalid;
-  UInt<1> io_write_r_rready;
-  UInt<1> io_irq_readerDone;
-  UInt<1> io_irq_writerDone;
-  UInt<1> io_sync_readerSync;
-  UInt<1> io_sync_writerSync;
-  AXI4LiteCSR csrFrontend;
-  AXIStreamSlave readerFrontend;
-  AXI4Writer writerFrontend;
-  CSR csr;
-  WorkerCSRWrapper ctl;
-  Queue queue;
-
-  AXITop() {
-    reset.rand_init();
-    io_control_aw_awaddr.rand_init();
-    io_control_aw_awprot.rand_init();
-    io_control_aw_awvalid.rand_init();
-    io_control_aw_awready.rand_init();
-    io_control_w_wdata.rand_init();
-    io_control_w_wstrb.rand_init();
-    io_control_w_wvalid.rand_init();
-    io_control_w_wready.rand_init();
-    io_control_b_bresp.rand_init();
-    io_control_b_bvalid.rand_init();
-    io_control_b_bready.rand_init();
-    io_control_ar_araddr.rand_init();
-    io_control_ar_arprot.rand_init();
-    io_control_ar_arvalid.rand_init();
-    io_control_ar_arready.rand_init();
-    io_control_r_rdata.rand_init();
-    io_control_r_rresp.rand_init();
-    io_control_r_rvalid.rand_init();
-    io_control_r_rready.rand_init();
-    io_read_tdata.rand_init();
-    io_read_tvalid.rand_init();
-    io_read_tready.rand_init();
-    io_read_tuser.rand_init();
-    io_read_tlast.rand_init();
-    io_write_aw_awid.rand_init();
-    io_write_aw_awaddr.rand_init();
-    io_write_aw_awlen.rand_init();
-    io_write_aw_awsize.rand_init();
-    io_write_aw_awburst.rand_init();
-    io_write_aw_awlock.rand_init();
-    io_write_aw_awcache.rand_init();
-    io_write_aw_awprot.rand_init();
-    io_write_aw_awqos.rand_init();
-    io_write_aw_awvalid.rand_init();
-    io_write_aw_awready.rand_init();
-    io_write_w_wdata.rand_init();
-    io_write_w_wstrb.rand_init();
-    io_write_w_wlast.rand_init();
-    io_write_w_wvalid.rand_init();
-    io_write_w_wready.rand_init();
-    io_write_b_bid.rand_init();
-    io_write_b_bresp.rand_init();
-    io_write_b_bvalid.rand_init();
-    io_write_b_bready.rand_init();
-    io_write_ar_arid.rand_init();
-    io_write_ar_araddr.rand_init();
-    io_write_ar_arlen.rand_init();
-    io_write_ar_arsize.rand_init();
-    io_write_ar_arburst.rand_init();
-    io_write_ar_arlock.rand_init();
-    io_write_ar_arcache.rand_init();
-    io_write_ar_arprot.rand_init();
-    io_write_ar_arqos.rand_init();
-    io_write_ar_arvalid.rand_init();
-    io_write_ar_arready.rand_init();
-    io_write_r_rid.rand_init();
-    io_write_r_rdata.rand_init();
-    io_write_r_rresp.rand_init();
-    io_write_r_rlast.rand_init();
-    io_write_r_rvalid.rand_init();
-    io_write_r_rready.rand_init();
-    io_irq_readerDone.rand_init();
-    io_irq_writerDone.rand_init();
-    io_sync_readerSync.rand_init();
-    io_sync_writerSync.rand_init();
-  }
-
-  void eval(bool update_registers, bool verbose, bool done_reset) {
-
-    //std::cout<<reset<<std::endl;
-    //std::cout<<"io_control_aw_awready "<<io_control_aw_awready <<std::endl;
-    //std::cout<<"io_control_w_wready   "<<io_control_w_wready   <<std::endl;
-    //std::cout<<"io_control_b_bresp    "<<io_control_b_bresp    <<std::endl;
-    //std::cout<<"io_control_b_bvalid   "<<io_control_b_bvalid   <<std::endl;
-    //std::cout<<"io_control_ar_arready "<<io_control_ar_arready <<std::endl;    
-    
-    io_control_aw_awready = csrFrontend.awready;
-    io_control_w_wready   = csrFrontend.wready;
-    io_control_b_bresp    = UInt<2>(0x0);
-    io_control_b_bvalid   = csrFrontend.bvalid;
-    io_control_ar_arready = csrFrontend.arready;
-    fprintf(stderr, "\nAXI_Port Eval Called");
-
-    UInt<4> csrFrontend$io_bus_addr = csrFrontend.addr.bits<3,0>();
-    UInt<1> csr$_T_343 = csrFrontend$io_bus_addr == UInt<4>(0xf);
-    UInt<1> csrFrontend$io_bus_read = io_control_r_rready & csrFrontend.rvalid;
-    UInt<1> csr$_T_344 = csr$_T_343 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_332 = csrFrontend$io_bus_addr == UInt<4>(0xe);
-    UInt<1> csr$_T_333 = csr$_T_332 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_321 = csrFrontend$io_bus_addr == UInt<4>(0xd);
-    UInt<1> csr$_T_322 = csr$_T_321 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_310 = csrFrontend$io_bus_addr == UInt<4>(0xc);
-    UInt<1> csr$_T_311 = csr$_T_310 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_299 = csrFrontend$io_bus_addr == UInt<4>(0xb);
-    UInt<1> csr$_T_300 = csr$_T_299 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_288 = csrFrontend$io_bus_addr == UInt<4>(0xa);
-    UInt<1> csr$_T_289 = csr$_T_288 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_277 = csrFrontend$io_bus_addr == UInt<4>(0x9);
-    UInt<1> csr$_T_278 = csr$_T_277 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_266 = csrFrontend$io_bus_addr == UInt<4>(0x8);
-    UInt<1> csr$_T_267 = csr$_T_266 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_255 = csrFrontend$io_bus_addr == UInt<4>(0x7);
-    UInt<1> csr$_T_256 = csr$_T_255 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_244 = csrFrontend$io_bus_addr == UInt<4>(0x6);
-    UInt<1> csr$_T_245 = csr$_T_244 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_233 = csrFrontend$io_bus_addr == UInt<4>(0x5);
-    UInt<1> csr$_T_234 = csr$_T_233 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_222 = csrFrontend$io_bus_addr == UInt<4>(0x4);
-    UInt<1> csr$_T_223 = csr$_T_222 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_211 = csrFrontend$io_bus_addr == UInt<4>(0x3);
-    UInt<1> csr$_T_212 = csr$_T_211 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_200 = csrFrontend$io_bus_addr == UInt<4>(0x2);
-    UInt<1> csr$_T_201 = csr$_T_200 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_189 = csrFrontend$io_bus_addr == UInt<4>(0x1);
-    UInt<1> csr$_T_190 = csr$_T_189 & csrFrontend$io_bus_read;
-    UInt<1> csr$_T_178 = csrFrontend$io_bus_addr == UInt<4>(0x0);
-    UInt<1> csr$_T_179 = csr$_T_178 & csrFrontend$io_bus_read;
-    UInt<32> csr$_GEN_0 = csr$_T_179 ? ctl.ClearCSR$$inst.reg : UInt<32>(0x0);
-    UInt<32> csr$_GEN_4 = csr$_T_190 ? ctl.StatusCSR$$inst.reg : csr$_GEN_0;
-    UInt<32> csr$_GEN_8 = csr$_T_201 ? ctl.InterruptController$$inst.SimpleCSR$$inst.reg : csr$_GEN_4;
-    UInt<32> csr$_GEN_12 = csr$_T_212 ? ctl.InterruptController$$inst.SetCSR$$inst.reg : csr$_GEN_8;
-    UInt<32> csr$_GEN_16 = csr$_T_223 ? ctl.SimpleCSR$$inst.reg : csr$_GEN_12;
-    UInt<32> csr$_GEN_20 = csr$_T_234 ? ctl.SimpleCSR_1.reg : csr$_GEN_16;
-    UInt<32> csr$_GEN_24 = csr$_T_245 ? ctl.SimpleCSR_2.reg : csr$_GEN_20;
-    UInt<32> csr$_GEN_28 = csr$_T_256 ? ctl.SimpleCSR_3.reg : csr$_GEN_24;
-    UInt<32> csr$_GEN_32 = csr$_T_267 ? ctl.SimpleCSR_4.reg : csr$_GEN_28;
-    UInt<32> csr$_GEN_36 = csr$_T_278 ? ctl.SimpleCSR_5.reg : csr$_GEN_32;
-    UInt<32> csr$_GEN_40 = csr$_T_289 ? ctl.SimpleCSR_6.reg : csr$_GEN_36;
-    UInt<32> csr$_GEN_44 = csr$_T_300 ? ctl.SimpleCSR_7.reg : csr$_GEN_40;
-    UInt<32> csr$_GEN_48 = csr$_T_311 ? ctl.SimpleCSR_8.reg : csr$_GEN_44;
-    UInt<32> csr$_GEN_52 = csr$_T_322 ? ctl.SimpleCSR_9.reg : csr$_GEN_48;
-    UInt<32> csr$_GEN_56 = csr$_T_333 ? ctl.SimpleCSR_10.reg : csr$_GEN_52;
-    UInt<32> csr$io_bus_dataIn = csr$_T_344 ? ctl.SimpleCSR_11.reg : csr$_GEN_56;
-    io_control_r_rdata = csr$io_bus_dataIn;    
-    io_control_r_rresp = UInt<2>(0x0);
-    io_control_r_rvalid = csrFrontend.rvalid;
-    UInt<1> queue$_T_41 = queue.value == queue.value_1;
-    UInt<1> queue$_T_44 = queue$_T_41 & queue.maybe_full;
-    UInt<1> queue$io_enq_ready = ~queue$_T_44;
-    UInt<1> readerFrontend$io_bus_tready = queue$io_enq_ready & readerFrontend.enable;
-    io_read_tready = readerFrontend$io_bus_tready;
-
-
-    io_write_aw_awid = UInt<4>(0x0);    
-    
-    io_write_aw_awaddr = writerFrontend.awaddr;
-    std::cout<<"io_write_aw_awaddr "<<io_write_aw_awaddr <<std::endl;
-    UInt<8> writerFrontend$io_bus_aw_awlen = writerFrontend.awlen.bits<7,0>();
-  
-  
-  //================================problem is here==================================
-  
-    io_write_aw_awlen   = writerFrontend$io_bus_aw_awlen;
-    io_write_aw_awsize  = UInt<3>(0x2);
-    io_write_aw_awburst = UInt<2>(0x1);
-    io_write_aw_awlock  = UInt<1>(0x0);
-    io_write_aw_awcache = UInt<4>(0x2);
-    io_write_aw_awprot  = UInt<3>(0x0);
-    io_write_aw_awqos   = UInt<4>(0x0);
-    
-  //================================problem is here==================================  
-    io_write_aw_awvalid = writerFrontend.awvalid;
-    UInt<32> queue$ram$_T_63 = queue.ram[queue.value_1.as_single_word()];
-    io_write_w_wdata = queue$ram$_T_63;
-    std::cout<<"io_write_w_wdata: "<<io_write_w_wdata;
-    io_write_w_wstrb = UInt<4>(0xf);
-    UInt<1> writerFrontend$io_bus_w_wlast = writerFrontend.length == UInt<32>(0x1);
-    io_write_w_wlast = writerFrontend$io_bus_w_wlast;
-    UInt<1> queue$_T_43 = ~queue.maybe_full;
-    UInt<1> queue$empty = queue$_T_41 & queue$_T_43;
-    UInt<1> queue$io_deq_valid = ~queue$empty;
-    UInt<1> writerFrontend$io_bus_w_wvalid = queue$io_deq_valid & writerFrontend.enable;
-    io_write_w_wvalid = writerFrontend$io_bus_w_wvalid;
-    io_write_b_bready = writerFrontend.bready;
-    io_write_ar_arid = UInt<4>(0x0);
-    io_write_ar_araddr = UInt<32>(0x0);
-    io_write_ar_arlen = UInt<8>(0x0);
-    io_write_ar_arsize = UInt<3>(0x0);
-    io_write_ar_arburst = UInt<2>(0x0);
-    io_write_ar_arlock = UInt<1>(0x0);
-    io_write_ar_arcache = UInt<4>(0x0);
-    io_write_ar_arprot = UInt<3>(0x0);
-    io_write_ar_arqos = UInt<4>(0x0);
-    io_write_ar_arvalid = UInt<1>(0x0);
-    io_write_r_rready = UInt<1>(0x0);
-    UInt<32> ctl$InterruptController$$inst$isr = ctl.InterruptController$$inst.SetCSR$$inst.reg;
-    UInt<1> ctl$InterruptController$$inst$io_irq_readerDone = ctl$InterruptController$$inst$isr.bits<1,1>();
-    io_irq_readerDone = ctl$InterruptController$$inst$io_irq_readerDone;
-    UInt<1> ctl$InterruptController$$inst$io_irq_writerDone = ctl$InterruptController$$inst$isr.bits<0,0>();
-    io_irq_writerDone = ctl$InterruptController$$inst$io_irq_writerDone;
-    UInt<1> csrFrontend$_T_110 = io_control_r_rready & csrFrontend.rvalid;
-    UInt<1> csrFrontend$_T_111 = io_control_w_wvalid & csrFrontend.wready;
-    UInt<1> csrFrontend$_T_112 = UInt<3>(0x0) == csrFrontend.state;
-    UInt<4> csrFrontend$_T_113 = io_control_aw_awaddr.bits<5,2>();
-    UInt<4> csrFrontend$_T_115 = io_control_ar_araddr.bits<5,2>();
-    UInt<3> csrFrontend$_GEN_0 = io_control_ar_arvalid ? UInt<3>(0x1) : csrFrontend.state;
-    UInt<32> csrFrontend$_GEN_1 = io_control_ar_arvalid ? (csrFrontend$_T_115.pad<32>()) : csrFrontend.addr;
-    UInt<1> csrFrontend$_GEN_2 = io_control_ar_arvalid | csrFrontend.arready;
-    UInt<3> csrFrontend$_GEN_3 = io_control_aw_awvalid ? UInt<3>(0x3) : csrFrontend$_GEN_0;
-    UInt<32> csrFrontend$_GEN_4 = io_control_aw_awvalid ? (csrFrontend$_T_113.pad<32>()) : csrFrontend$_GEN_1;
-    UInt<1> csrFrontend$_GEN_5 = io_control_aw_awvalid | csrFrontend.awready;
-    UInt<1> csrFrontend$_GEN_6 = io_control_aw_awvalid ? csrFrontend.arready : csrFrontend$_GEN_2;
-    UInt<1> csrFrontend$_T_117 = UInt<3>(0x1) == csrFrontend.state;
-    UInt<1> csrFrontend$_T_118 = io_control_ar_arvalid & csrFrontend.arready;
-    UInt<3> csrFrontend$_GEN_7 = csrFrontend$_T_118 ? UInt<3>(0x2) : csrFrontend.state;
-    UInt<1> csrFrontend$_GEN_8 = csrFrontend$_T_118 ? UInt<1>(0x0) : csrFrontend.arready;
-    UInt<1> csrFrontend$_GEN_9 = csrFrontend$_T_118 | csrFrontend.rvalid;
-    UInt<1> csrFrontend$_T_121 = UInt<3>(0x2) == csrFrontend.state;
-    UInt<3> csrFrontend$_GEN_10 = csrFrontend$_T_110 ? UInt<3>(0x0) : csrFrontend.state;
-    UInt<1> csrFrontend$_GEN_11 = csrFrontend$_T_110 ? UInt<1>(0x0) : csrFrontend.rvalid;
-    UInt<1> csrFrontend$_T_124 = UInt<3>(0x3) == csrFrontend.state;
-    UInt<1> csrFrontend$_T_125 = io_control_aw_awvalid & csrFrontend.awready;
-    UInt<3> csrFrontend$_GEN_12 = csrFrontend$_T_125 ? UInt<3>(0x4) : csrFrontend.state;
-    UInt<1> csrFrontend$_GEN_13 = csrFrontend$_T_125 ? UInt<1>(0x0) : csrFrontend.awready;
-    UInt<1> csrFrontend$_GEN_14 = csrFrontend$_T_125 | csrFrontend.wready;
-    UInt<1> csrFrontend$_T_128 = UInt<3>(0x4) == csrFrontend.state;
-    UInt<3> csrFrontend$_GEN_15 = csrFrontend$_T_111 ? UInt<3>(0x5) : csrFrontend.state;
-    UInt<1> csrFrontend$_GEN_16 = csrFrontend$_T_111 ? UInt<1>(0x0) : csrFrontend.wready;
-    UInt<1> csrFrontend$_GEN_17 = csrFrontend$_T_111 | csrFrontend.bvalid;
-    UInt<1> csrFrontend$_T_132 = UInt<3>(0x5) == csrFrontend.state;
-    UInt<1> csrFrontend$_T_133 = io_control_b_bready & csrFrontend.bvalid;
-    UInt<3> csrFrontend$_GEN_18 = csrFrontend$_T_133 ? UInt<3>(0x0) : csrFrontend.state;
-    UInt<1> csrFrontend$_GEN_19 = csrFrontend$_T_133 ? UInt<1>(0x0) : csrFrontend.bvalid;
-    UInt<3> csrFrontend$_GEN_20 = csrFrontend$_T_132 ? csrFrontend$_GEN_18 : csrFrontend.state;
-    UInt<1> csrFrontend$_GEN_21 = csrFrontend$_T_132 ? csrFrontend$_GEN_19 : csrFrontend.bvalid;
-    UInt<3> csrFrontend$_GEN_22 = csrFrontend$_T_128 ? csrFrontend$_GEN_15 : csrFrontend$_GEN_20;
-    UInt<1> csrFrontend$_GEN_23 = csrFrontend$_T_128 ? csrFrontend$_GEN_16 : csrFrontend.wready;
-    UInt<1> csrFrontend$_GEN_24 = csrFrontend$_T_128 ? csrFrontend$_GEN_17 : csrFrontend$_GEN_21;
-    UInt<3> csrFrontend$_GEN_25 = csrFrontend$_T_124 ? csrFrontend$_GEN_12 : csrFrontend$_GEN_22;
-    UInt<1> csrFrontend$_GEN_26 = csrFrontend$_T_124 ? csrFrontend$_GEN_13 : csrFrontend.awready;
-    UInt<1> csrFrontend$_GEN_27 = csrFrontend$_T_124 ? csrFrontend$_GEN_14 : csrFrontend$_GEN_23;
-    UInt<1> csrFrontend$_GEN_28 = csrFrontend$_T_124 ? csrFrontend.bvalid : csrFrontend$_GEN_24;
-    UInt<3> csrFrontend$_GEN_29 = csrFrontend$_T_121 ? csrFrontend$_GEN_10 : csrFrontend$_GEN_25;
-    UInt<1> csrFrontend$_GEN_30 = csrFrontend$_T_121 ? csrFrontend$_GEN_11 : csrFrontend.rvalid;
-    UInt<1> csrFrontend$_GEN_31 = csrFrontend$_T_121 ? csrFrontend.awready : csrFrontend$_GEN_26;
-    UInt<1> csrFrontend$_GEN_32 = csrFrontend$_T_121 ? csrFrontend.wready : csrFrontend$_GEN_27;
-    UInt<1> csrFrontend$_GEN_33 = csrFrontend$_T_121 ? csrFrontend.bvalid : csrFrontend$_GEN_28;
-    UInt<3> csrFrontend$_GEN_34 = csrFrontend$_T_117 ? csrFrontend$_GEN_7 : csrFrontend$_GEN_29;
-    UInt<1> csrFrontend$_GEN_35 = csrFrontend$_T_117 ? csrFrontend$_GEN_8 : csrFrontend.arready;
-    UInt<1> csrFrontend$_GEN_36 = csrFrontend$_T_117 ? csrFrontend$_GEN_9 : csrFrontend$_GEN_30;
-    UInt<1> csrFrontend$_GEN_37 = csrFrontend$_T_117 ? csrFrontend.awready : csrFrontend$_GEN_31;
-    UInt<1> csrFrontend$_GEN_38 = csrFrontend$_T_117 ? csrFrontend.wready : csrFrontend$_GEN_32;
-    UInt<1> csrFrontend$_GEN_39 = csrFrontend$_T_117 ? csrFrontend.bvalid : csrFrontend$_GEN_33;
-    UInt<3> csrFrontend$_GEN_40 = csrFrontend$_T_112 ? csrFrontend$_GEN_3 : csrFrontend$_GEN_34;
-    UInt<32> csrFrontend$_GEN_41 = csrFrontend$_T_112 ? csrFrontend$_GEN_4 : csrFrontend.addr;
-    UInt<1> csrFrontend$_GEN_42 = csrFrontend$_T_112 ? csrFrontend$_GEN_5 : csrFrontend$_GEN_37;
-    UInt<1> csrFrontend$_GEN_43 = csrFrontend$_T_112 ? csrFrontend$_GEN_6 : csrFrontend$_GEN_35;
-    UInt<1> csrFrontend$_GEN_44 = csrFrontend$_T_112 ? csrFrontend.rvalid : csrFrontend$_GEN_36;
-    UInt<1> csrFrontend$_GEN_45 = csrFrontend$_T_112 ? csrFrontend.wready : csrFrontend$_GEN_38;
-    UInt<1> csrFrontend$_GEN_46 = csrFrontend$_T_112 ? csrFrontend.bvalid : csrFrontend$_GEN_39;
-    UInt<1> csrFrontend$io_bus_write = io_control_w_wvalid & csrFrontend.wready;
-    if (update_registers) csrFrontend.state = reset ? UInt<3>(0x0) : csrFrontend$_GEN_40;
-    if (update_registers) csrFrontend.awready = reset ? UInt<1>(0x0) : csrFrontend$_GEN_42;
-    if (update_registers) csrFrontend.wready = reset ? UInt<1>(0x0) : csrFrontend$_GEN_45;
-    if (update_registers) csrFrontend.bvalid = reset ? UInt<1>(0x0) : csrFrontend$_GEN_46;
-    if (update_registers) csrFrontend.arready = reset ? UInt<1>(0x0) : csrFrontend$_GEN_43;
-    if (update_registers) csrFrontend.rvalid = reset ? UInt<1>(0x0) : csrFrontend$_GEN_44;
-    if (update_registers) csrFrontend.addr = reset ? UInt<32>(0x0) : csrFrontend$_GEN_41;
-    UInt<1> readerFrontend$ready = queue$io_enq_ready & readerFrontend.enable;
-    UInt<1> readerFrontend$valid = io_read_tvalid & readerFrontend.enable;
-    UInt<1> readerFrontend$_T_66 = UInt<2>(0x0) == readerFrontend.state;
-    UInt<2> readerFrontend$_GEN_0 = ctl.addressGeneratorRead.valid ? UInt<2>(0x1) : readerFrontend.state;
-    UInt<32> readerFrontend$_GEN_1 = ctl.addressGeneratorRead.valid ? ctl.addressGeneratorRead.length_o : readerFrontend.length;
-    UInt<1> readerFrontend$_T_70 = UInt<2>(0x1) == readerFrontend.state;
-    UInt<1> readerFrontend$_T_71 = readerFrontend$ready & readerFrontend$valid;
-    UInt<33> readerFrontend$_T_73 = readerFrontend.length - UInt<32>(0x1);
-    UInt<32> readerFrontend$_T_75 = readerFrontend$_T_73.tail<1>();
-    UInt<1> readerFrontend$_T_77 = readerFrontend.length == UInt<32>(0x1);
-    UInt<2> readerFrontend$_GEN_3 = readerFrontend$_T_77 ? UInt<2>(0x2) : readerFrontend.state;
-    UInt<1> readerFrontend$_GEN_4 = readerFrontend$_T_77 ? UInt<1>(0x0) : readerFrontend.enable;
-    UInt<32> readerFrontend$_GEN_5 = readerFrontend$_T_71 ? readerFrontend$_T_75 : readerFrontend.length;
-    UInt<2> readerFrontend$_GEN_6 = readerFrontend$_T_71 ? readerFrontend$_GEN_3 : readerFrontend.state;
-    UInt<1> readerFrontend$_GEN_7 = readerFrontend$_T_71 ? readerFrontend$_GEN_4 : readerFrontend.enable;
-    UInt<1> readerFrontend$_T_79 = UInt<2>(0x2) == readerFrontend.state;
-    UInt<2> readerFrontend$_GEN_8 = readerFrontend$_T_79 ? UInt<2>(0x0) : readerFrontend.state;
-    UInt<1> readerFrontend$_GEN_9 = readerFrontend$_T_79 | readerFrontend.done;
-    UInt<32> readerFrontend$_GEN_10 = readerFrontend$_T_70 ? readerFrontend$_GEN_5 : readerFrontend.length;
-    UInt<2> readerFrontend$_GEN_11 = readerFrontend$_T_70 ? readerFrontend$_GEN_6 : readerFrontend$_GEN_8;
-    UInt<1> readerFrontend$_GEN_12 = readerFrontend$_T_70 ? readerFrontend$_GEN_7 : readerFrontend.enable;
-    UInt<1> readerFrontend$_GEN_13 = readerFrontend$_T_70 ? readerFrontend.done : readerFrontend$_GEN_9;
-    UInt<1> readerFrontend$_GEN_14 = readerFrontend$_T_66 ? UInt<1>(0x0) : readerFrontend$_GEN_13;
-    UInt<1> readerFrontend$_GEN_15 = readerFrontend$_T_66 ? ctl.addressGeneratorRead.valid : readerFrontend$_GEN_12;
-    UInt<2> readerFrontend$_GEN_16 = readerFrontend$_T_66 ? readerFrontend$_GEN_0 : readerFrontend$_GEN_11;
-    UInt<32> readerFrontend$_GEN_17 = readerFrontend$_T_66 ? readerFrontend$_GEN_1 : readerFrontend$_GEN_10;
-    UInt<1> readerFrontend$io_dataOut_valid = io_read_tvalid & readerFrontend.enable;
-    if (update_registers) readerFrontend.state = reset ? UInt<2>(0x0) : readerFrontend$_GEN_16;
-    UInt<1> ctl$addressGeneratorRead$_T_69 = ctl.addressGeneratorRead.lineCount > UInt<32>(0x0);
-    UInt<2> ctl$addressGeneratorRead$_GEN_7 = ctl$addressGeneratorRead$_T_69 ? UInt<2>(0x1) : UInt<2>(0x0);
-    UInt<2> ctl$addressGeneratorRead$_GEN_8 = readerFrontend.done ? ctl$addressGeneratorRead$_GEN_7 : ctl.addressGeneratorRead.state;
-    if (update_registers) readerFrontend.done = reset ? UInt<1>(0x0) : readerFrontend$_GEN_14;
-    if (update_registers) readerFrontend.enable = reset ? UInt<1>(0x0) : readerFrontend$_GEN_15;
-    if (update_registers) readerFrontend.length = reset ? UInt<32>(0x0) : readerFrontend$_GEN_17;
-    UInt<1> writerFrontend$ready = io_write_w_wready & writerFrontend.enable;
-    UInt<1> writerFrontend$valid = queue$io_deq_valid & writerFrontend.enable;
-    UInt<1> writerFrontend$_T_243 = UInt<2>(0x0) == writerFrontend.dataState;
-    UInt<32> writerFrontend$_GEN_0 = ctl.transferSplitterWrite._T_63 ? ctl.transferSplitterWrite._T_51 : writerFrontend.length;
-    UInt<2> writerFrontend$_GEN_1 = ctl.transferSplitterWrite._T_63 ? UInt<2>(0x1) : writerFrontend.dataState;
-    UInt<1> writerFrontend$_GEN_2 = ctl.transferSplitterWrite._T_63 | writerFrontend.enable;
-    UInt<1> writerFrontend$_T_246 = UInt<2>(0x1) == writerFrontend.dataState;
-    UInt<1> writerFrontend$_T_247 = writerFrontend$ready & writerFrontend$valid;
-    UInt<1> writerFrontend$_T_249 = writerFrontend.length > UInt<32>(0x1);
-    UInt<33> writerFrontend$_T_251 = writerFrontend.length - UInt<32>(0x1);
-    UInt<32> writerFrontend$_T_253 = writerFrontend$_T_251.tail<1>();
-    UInt<32> writerFrontend$_GEN_3 = writerFrontend$_T_249 ? writerFrontend$_T_253 : writerFrontend.length;
-    UInt<2> writerFrontend$_GEN_4 = writerFrontend$_T_249 ? writerFrontend.dataState : UInt<2>(0x2);
-    UInt<1> writerFrontend$_GEN_5 = writerFrontend$_T_249 & writerFrontend.enable;
-    UInt<1> writerFrontend$_GEN_6 = writerFrontend$_T_249 ? writerFrontend.bready : UInt<1>(0x1);
-    UInt<32> writerFrontend$_GEN_7 = writerFrontend$_T_247 ? writerFrontend$_GEN_3 : writerFrontend.length;
-    UInt<2> writerFrontend$_GEN_8 = writerFrontend$_T_247 ? writerFrontend$_GEN_4 : writerFrontend.dataState;
-    UInt<1> writerFrontend$_GEN_9 = writerFrontend$_T_247 ? writerFrontend$_GEN_5 : writerFrontend.enable;
-    UInt<1> writerFrontend$_GEN_10 = writerFrontend$_T_247 ? writerFrontend$_GEN_6 : writerFrontend.bready;
-    UInt<1> writerFrontend$_T_256 = UInt<2>(0x2) == writerFrontend.dataState;
-    UInt<1> writerFrontend$_T_257 = writerFrontend.bready & io_write_b_bvalid;
-    UInt<1> writerFrontend$_GEN_11 = writerFrontend$_T_257 ? UInt<1>(0x0) : writerFrontend.bready;
-    UInt<2> writerFrontend$_GEN_12 = writerFrontend$_T_257 ? UInt<2>(0x3) : writerFrontend.dataState;
-    UInt<1> writerFrontend$_T_259 = UInt<2>(0x3) == writerFrontend.dataState;
-    UInt<1> writerFrontend$_GEN_13 = writerFrontend$_T_259 | writerFrontend.done;
-    UInt<2> writerFrontend$_GEN_14 = writerFrontend$_T_259 ? UInt<2>(0x0) : writerFrontend.dataState;
-    UInt<1> writerFrontend$_GEN_15 = writerFrontend$_T_256 ? writerFrontend$_GEN_11 : writerFrontend.bready;
-    UInt<2> writerFrontend$_GEN_16 = writerFrontend$_T_256 ? writerFrontend$_GEN_12 : writerFrontend$_GEN_14;
-    UInt<1> writerFrontend$_GEN_17 = writerFrontend$_T_256 ? writerFrontend.done : writerFrontend$_GEN_13;
-    UInt<32> writerFrontend$_GEN_18 = writerFrontend$_T_246 ? writerFrontend$_GEN_7 : writerFrontend.length;
-    UInt<2> writerFrontend$_GEN_19 = writerFrontend$_T_246 ? writerFrontend$_GEN_8 : writerFrontend$_GEN_16;
-    UInt<1> writerFrontend$_GEN_20 = writerFrontend$_T_246 ? writerFrontend$_GEN_9 : writerFrontend.enable;
-    UInt<1> writerFrontend$_GEN_21 = writerFrontend$_T_246 ? writerFrontend$_GEN_10 : writerFrontend$_GEN_15;
-    UInt<1> writerFrontend$_GEN_22 = writerFrontend$_T_246 ? writerFrontend.done : writerFrontend$_GEN_17;
-    UInt<1> writerFrontend$_GEN_23 = writerFrontend$_T_243 ? UInt<1>(0x0) : writerFrontend$_GEN_22;
-    UInt<32> writerFrontend$_GEN_24 = writerFrontend$_T_243 ? writerFrontend$_GEN_0 : writerFrontend$_GEN_18;
-    UInt<2> writerFrontend$_GEN_25 = writerFrontend$_T_243 ? writerFrontend$_GEN_1 : writerFrontend$_GEN_19;
-    UInt<1> writerFrontend$_GEN_26 = writerFrontend$_T_243 ? writerFrontend$_GEN_2 : writerFrontend$_GEN_20;
-    UInt<1> writerFrontend$_GEN_27 = writerFrontend$_T_243 ? writerFrontend.bready : writerFrontend$_GEN_21;
-    UInt<1> writerFrontend$_T_261 = UInt<2>(0x0) == writerFrontend.addrState;
-    UInt<33> writerFrontend$_T_263 = ctl.transferSplitterWrite._T_51 - UInt<32>(0x1);
-    UInt<32> writerFrontend$_T_265 = writerFrontend$_T_263.tail<1>();
-    UInt<32> writerFrontend$_GEN_28 = ctl.transferSplitterWrite._T_63 ? ctl.transferSplitterWrite._T_48 : writerFrontend.awaddr;
-    UInt<32> writerFrontend$_GEN_29 = ctl.transferSplitterWrite._T_63 ? writerFrontend$_T_265 : writerFrontend.awlen;
-    UInt<1> writerFrontend$_GEN_30 = ctl.transferSplitterWrite._T_63 | writerFrontend.awvalid;
-    UInt<2> writerFrontend$_GEN_31 = ctl.transferSplitterWrite._T_63 ? UInt<2>(0x1) : writerFrontend.addrState;
-    UInt<1> writerFrontend$_T_267 = UInt<2>(0x1) == writerFrontend.addrState;
-    UInt<1> writerFrontend$_T_268 = writerFrontend.awvalid & io_write_aw_awready;
-    UInt<2> writerFrontend$_GEN_32 = writerFrontend$_T_268 ? UInt<2>(0x2) : writerFrontend.addrState;
-    UInt<1> writerFrontend$_GEN_33 = writerFrontend$_T_268 ? UInt<1>(0x0) : writerFrontend.awvalid;
-    UInt<1> writerFrontend$_T_270 = UInt<2>(0x2) == writerFrontend.addrState;
-    UInt<2> writerFrontend$_GEN_34 = writerFrontend.done ? UInt<2>(0x0) : writerFrontend.addrState;
-    UInt<2> writerFrontend$_GEN_35 = writerFrontend$_T_270 ? writerFrontend$_GEN_34 : writerFrontend.addrState;
-    UInt<2> writerFrontend$_GEN_36 = writerFrontend$_T_267 ? writerFrontend$_GEN_32 : writerFrontend$_GEN_35;
-    UInt<1> writerFrontend$_GEN_37 = writerFrontend$_T_267 ? writerFrontend$_GEN_33 : writerFrontend.awvalid;
-    UInt<32> writerFrontend$_GEN_38 = writerFrontend$_T_261 ? writerFrontend$_GEN_28 : writerFrontend.awaddr;
-
-    std::cout<<"writerFrontend$_GEN_38     "<<writerFrontend$_GEN_37<<std::endl;
-
-    UInt<32> writerFrontend$_GEN_39 = writerFrontend$_T_261 ? writerFrontend$_GEN_29 : writerFrontend.awlen;
-    UInt<1> writerFrontend$_GEN_40 = writerFrontend$_T_261 ? writerFrontend$_GEN_30 : writerFrontend$_GEN_37;
-    UInt<2> writerFrontend$_GEN_41 = writerFrontend$_T_261 ? writerFrontend$_GEN_31 : writerFrontend$_GEN_36;
-    UInt<1> writerFrontend$io_dataIn_ready = io_write_w_wready & writerFrontend.enable;
-    if (update_registers) writerFrontend.dataState = reset ? UInt<2>(0x0) : writerFrontend$_GEN_25;
-    if (update_registers) writerFrontend.addrState = reset ? UInt<2>(0x0) : writerFrontend$_GEN_41;
-    UInt<1> ctl$transferSplitterWrite$_T_91 = ctl.transferSplitterWrite._T_45 > UInt<32>(0x0);
-    UInt<2> ctl$transferSplitterWrite$_GEN_7 = ctl$transferSplitterWrite$_T_91 ? UInt<2>(0x1) : UInt<2>(0x0);
-    UInt<2> ctl$transferSplitterWrite$_GEN_9 = writerFrontend.done ? ctl$transferSplitterWrite$_GEN_7 : ctl.transferSplitterWrite._T_65;
-    UInt<1> ctl$transferSplitterWrite$_GEN_8 = ctl$transferSplitterWrite$_T_91 ? ctl.transferSplitterWrite._T_60 : UInt<1>(0x1);
-    UInt<1> ctl$transferSplitterWrite$_GEN_10 = writerFrontend.done ? ctl$transferSplitterWrite$_GEN_8 : ctl.transferSplitterWrite._T_60;
-    if (update_registers) writerFrontend.done = reset ? UInt<1>(0x0) : writerFrontend$_GEN_23;
-    if (update_registers) writerFrontend.enable = reset ? UInt<1>(0x0) : writerFrontend$_GEN_26;
-    if (update_registers) writerFrontend.length = reset ? UInt<32>(0x0) : writerFrontend$_GEN_24;
-    if (update_registers) writerFrontend.awlen = reset ? UInt<32>(0x0) : writerFrontend$_GEN_39;
-    if (update_registers) writerFrontend.awaddr = reset ? UInt<32>(0x0) : writerFrontend$_GEN_38;
-    if (update_registers) writerFrontend.awvalid = reset ? UInt<1>(0x0) : writerFrontend$_GEN_40;
-    if (update_registers) writerFrontend.bready = reset ? UInt<1>(0x0) : writerFrontend$_GEN_27;
-    UInt<1> csr$_T_184 = csr$_T_178 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_206 = csr$_T_200 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_217 = csr$_T_211 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_228 = csr$_T_222 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_239 = csr$_T_233 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_250 = csr$_T_244 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_261 = csr$_T_255 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_272 = csr$_T_266 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_283 = csr$_T_277 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_294 = csr$_T_288 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_305 = csr$_T_299 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_316 = csr$_T_310 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_327 = csr$_T_321 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_338 = csr$_T_332 & csrFrontend$io_bus_write;
-    UInt<1> csr$_T_349 = csr$_T_343 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_0_dataOut = csr$_T_184 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_0_dataWrite = csr$_T_178 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_2_dataOut = csr$_T_206 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_2_dataWrite = csr$_T_200 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_3_dataOut = csr$_T_217 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_3_dataWrite = csr$_T_211 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_4_dataOut = csr$_T_228 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_4_dataWrite = csr$_T_222 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_5_dataOut = csr$_T_239 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_5_dataWrite = csr$_T_233 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_6_dataOut = csr$_T_250 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_6_dataWrite = csr$_T_244 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_7_dataOut = csr$_T_261 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_7_dataWrite = csr$_T_255 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_8_dataOut = csr$_T_272 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_8_dataWrite = csr$_T_266 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_9_dataOut = csr$_T_283 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_9_dataWrite = csr$_T_277 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_10_dataOut = csr$_T_294 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_10_dataWrite = csr$_T_288 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_11_dataOut = csr$_T_305 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_11_dataWrite = csr$_T_299 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_12_dataOut = csr$_T_316 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_12_dataWrite = csr$_T_310 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_13_dataOut = csr$_T_327 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_13_dataWrite = csr$_T_321 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_14_dataOut = csr$_T_338 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_14_dataWrite = csr$_T_332 & csrFrontend$io_bus_write;
-    UInt<32> csr$io_csr_15_dataOut = csr$_T_349 ? io_control_w_wdata : UInt<32>(0x0);
-    UInt<1> csr$io_csr_15_dataWrite = csr$_T_343 & csrFrontend$io_bus_write;
-    UInt<2> ctl$_T_203 = ctl.readerStart.cat(ctl.writerStart);
-    UInt<32> ctl$control = ctl.ClearCSR$$inst.reg;
-    UInt<1> ctl$_T_204 = ctl$control.bits<5,5>();
-    UInt<1> ctl$_T_205 = ctl$control.bits<4,4>();
-    UInt<2> ctl$_T_206 = ctl$_T_204.cat(ctl$_T_205);
-    UInt<2> ctl$_T_207 = ~ctl$_T_206;
-    UInt<2> ctl$clear = ctl$_T_203 & ctl$_T_207;
-    UInt<1> ctl$_T_210 = ~ctl.readerSyncOld;
-    UInt<1> ctl$_T_211 = ctl$_T_210 & ctl.readerSync;
-    UInt<1> ctl$_T_212 = ctl$control.bits<3,3>();
-    UInt<1> ctl$_T_213 = ctl$_T_211 | ctl$_T_212;
-    UInt<1> ctl$_T_214 = ctl$control.bits<1,1>();
-    UInt<1> ctl$_T_215 = ctl$_T_213 & ctl$_T_214;
-    UInt<1> ctl$_T_217 = ~ctl.writerSyncOld;
-    UInt<1> ctl$_T_218 = ctl$_T_217 & ctl.writerSync;
-    UInt<1> ctl$_T_219 = ctl$control.bits<2,2>();
-    UInt<1> ctl$_T_220 = ctl$_T_218 | ctl$_T_219;
-    UInt<1> ctl$_T_221 = ctl$control.bits<0,0>();
-    UInt<1> ctl$_T_222 = ctl$_T_220 & ctl$_T_221;
-    UInt<32> ctl$ClearCSR$$inst$io_clear = ctl$clear.pad<32>();
-    UInt<32> ctl$StatusCSR$$inst$io_value = ctl.status.pad<32>();
-    if (update_registers) ctl.status = ctl.addressGeneratorRead.busy.cat(ctl.addressGeneratorWrite.busy);
-    if (update_registers) ctl.readerSyncOld = ctl.readerSync;
-    if (update_registers) ctl.readerSync = io_sync_readerSync;
-    if (update_registers) ctl.writerSyncOld = ctl.writerSync;
-    if (update_registers) ctl.writerSync = io_sync_writerSync;
-    UInt<2> ctl$addressGeneratorRead$_GEN_1 = ctl.readerStart ? UInt<2>(0x1) : ctl.addressGeneratorRead.state;
-    UInt<32> ctl$addressGeneratorRead$_GEN_2 = ctl.readerStart ? ctl.SimpleCSR$$inst.reg : ctl.addressGeneratorRead.address_i;
-    UInt<32> ctl$addressGeneratorRead$_GEN_3 = ctl.readerStart ? ctl.SimpleCSR_1.reg : ctl.addressGeneratorRead.length_i;
-    UInt<32> ctl$addressGeneratorRead$_GEN_4 = ctl.readerStart ? ctl.SimpleCSR_2.reg : ctl.addressGeneratorRead.lineCount;
-    UInt<32> ctl$addressGeneratorRead$_GEN_5 = ctl.readerStart ? ctl.SimpleCSR_3.reg : ctl.addressGeneratorRead.lineGap;
-    if (update_registers) ctl.readerStart = reset ? UInt<1>(0x0) : ctl$_T_215;
-    UInt<2> ctl$addressGeneratorWrite$_GEN_1 = ctl.writerStart ? UInt<2>(0x1) : ctl.addressGeneratorWrite.state;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_2 = ctl.writerStart ? ctl.SimpleCSR_4.reg : ctl.addressGeneratorWrite.address_i;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_3 = ctl.writerStart ? ctl.SimpleCSR_5.reg : ctl.addressGeneratorWrite.length_i;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_4 = ctl.writerStart ? ctl.SimpleCSR_6.reg : ctl.addressGeneratorWrite.lineCount;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_5 = ctl.writerStart ? ctl.SimpleCSR_7.reg : ctl.addressGeneratorWrite.lineGap;
-    if (update_registers) ctl.writerStart = reset ? UInt<1>(0x0) : ctl$_T_222;
-    UInt<1> ctl$addressGeneratorRead$_T_46 = ctl.addressGeneratorRead.state == UInt<2>(0x0);
-    UInt<1> ctl$addressGeneratorRead$_GEN_0 = ctl$addressGeneratorRead$_T_46 ? UInt<1>(0x0) : UInt<1>(0x1);
-    UInt<1> ctl$addressGeneratorRead$_T_49 = UInt<2>(0x0) == ctl.addressGeneratorRead.state;
-    UInt<1> ctl$addressGeneratorRead$_T_51 = UInt<2>(0x1) == ctl.addressGeneratorRead.state;
-    UInt<35> ctl$addressGeneratorRead$_T_54 = (ctl.addressGeneratorRead.length_i * UInt<32>(0x4)).tail<29>();
-    UInt<35> ctl$addressGeneratorRead$_GEN_28 = ctl.addressGeneratorRead.address_i.pad<35>();
-    UInt<36> ctl$addressGeneratorRead$_T_55 = ctl$addressGeneratorRead$_GEN_28 + ctl$addressGeneratorRead$_T_54;
-    UInt<35> ctl$addressGeneratorRead$_T_56 = ctl$addressGeneratorRead$_T_55.tail<1>();
-    UInt<35> ctl$addressGeneratorRead$_T_58 = (ctl.addressGeneratorRead.lineGap * UInt<32>(0x4)).tail<29>();
-    UInt<36> ctl$addressGeneratorRead$_T_59 = ctl$addressGeneratorRead$_T_56 + ctl$addressGeneratorRead$_T_58;
-    UInt<35> ctl$addressGeneratorRead$_T_60 = ctl$addressGeneratorRead$_T_59.tail<1>();
-    UInt<33> ctl$addressGeneratorRead$_T_62 = ctl.addressGeneratorRead.lineCount - UInt<32>(0x1);
-    UInt<32> ctl$addressGeneratorRead$_T_64 = ctl$addressGeneratorRead$_T_62.tail<1>();
-    UInt<1> ctl$addressGeneratorRead$_T_65 = UInt<2>(0x2) == ctl.addressGeneratorRead.state;
-    UInt<1> ctl$addressGeneratorRead$_GEN_9 = ctl$addressGeneratorRead$_T_65 ? UInt<1>(0x0) : ctl.addressGeneratorRead.valid;
-    UInt<2> ctl$addressGeneratorRead$_GEN_11 = ctl$addressGeneratorRead$_T_65 ? ctl$addressGeneratorRead$_GEN_8 : ctl.addressGeneratorRead.state;
-    UInt<1> ctl$addressGeneratorRead$_GEN_12 = ctl$addressGeneratorRead$_T_51 | ctl$addressGeneratorRead$_GEN_9;
-    UInt<32> ctl$addressGeneratorRead$_GEN_13 = ctl$addressGeneratorRead$_T_51 ? ctl.addressGeneratorRead.address_i : ctl.addressGeneratorRead.address_o;
-    UInt<32> ctl$addressGeneratorRead$_GEN_14 = ctl$addressGeneratorRead$_T_51 ? ctl.addressGeneratorRead.length_i : ctl.addressGeneratorRead.length_o;
-    UInt<35> ctl$addressGeneratorRead$_GEN_15 = ctl$addressGeneratorRead$_T_51 ? ctl$addressGeneratorRead$_T_60 : (ctl.addressGeneratorRead.address_i.pad<35>());
-    UInt<32> ctl$addressGeneratorRead$_GEN_16 = ctl$addressGeneratorRead$_T_51 ? ctl$addressGeneratorRead$_T_64 : ctl.addressGeneratorRead.lineCount;
-    UInt<2> ctl$addressGeneratorRead$_GEN_17 = ctl$addressGeneratorRead$_T_51 ? UInt<2>(0x2) : ctl$addressGeneratorRead$_GEN_11;
-    UInt<2> ctl$addressGeneratorRead$_GEN_19 = ctl$addressGeneratorRead$_T_49 ? ctl$addressGeneratorRead$_GEN_1 : ctl$addressGeneratorRead$_GEN_17;
-    UInt<35> ctl$addressGeneratorRead$_GEN_20 = ctl$addressGeneratorRead$_T_49 ? (ctl$addressGeneratorRead$_GEN_2.pad<35>()) : ctl$addressGeneratorRead$_GEN_15;
-    UInt<32> ctl$addressGeneratorRead$_GEN_21 = ctl$addressGeneratorRead$_T_49 ? ctl$addressGeneratorRead$_GEN_3 : ctl.addressGeneratorRead.length_i;
-    UInt<32> ctl$addressGeneratorRead$_GEN_22 = ctl$addressGeneratorRead$_T_49 ? ctl$addressGeneratorRead$_GEN_4 : ctl$addressGeneratorRead$_GEN_16;
-    UInt<32> ctl$addressGeneratorRead$_GEN_23 = ctl$addressGeneratorRead$_T_49 ? ctl$addressGeneratorRead$_GEN_5 : ctl.addressGeneratorRead.lineGap;
-    UInt<1> ctl$addressGeneratorRead$_GEN_25 = ctl$addressGeneratorRead$_T_49 ? ctl.addressGeneratorRead.valid : ctl$addressGeneratorRead$_GEN_12;
-    UInt<32> ctl$addressGeneratorRead$_GEN_26 = ctl$addressGeneratorRead$_T_49 ? ctl.addressGeneratorRead.address_o : ctl$addressGeneratorRead$_GEN_13;
-    UInt<32> ctl$addressGeneratorRead$_GEN_27 = ctl$addressGeneratorRead$_T_49 ? ctl.addressGeneratorRead.length_o : ctl$addressGeneratorRead$_GEN_14;
-    if (update_registers) ctl.addressGeneratorRead.state = reset ? UInt<2>(0x0) : ctl$addressGeneratorRead$_GEN_19;
-    if (update_registers) ctl.addressGeneratorRead.lineCount = reset ? UInt<32>(0x0) : ctl$addressGeneratorRead$_GEN_22;
-    if (update_registers) ctl.addressGeneratorRead.lineGap = reset ? UInt<32>(0x0) : ctl$addressGeneratorRead$_GEN_23;
-    if (update_registers) ctl.addressGeneratorRead.address_o = reset ? UInt<32>(0x0) : ctl$addressGeneratorRead$_GEN_26;
-    if (update_registers) ctl.addressGeneratorRead.address_i = reset ? UInt<32>(0x0) : (ctl$addressGeneratorRead$_GEN_20.bits<31,0>());
-    if (update_registers) ctl.addressGeneratorRead.length_o = reset ? UInt<32>(0x0) : ctl$addressGeneratorRead$_GEN_27;
-    if (update_registers) ctl.addressGeneratorRead.length_i = reset ? UInt<32>(0x0) : ctl$addressGeneratorRead$_GEN_21;
-    if (update_registers) ctl.addressGeneratorRead.valid = reset ? UInt<1>(0x0) : ctl$addressGeneratorRead$_GEN_25;
-    UInt<1> ctl$InterruptController$$inst$_T_64 = ~ctl.InterruptController$$inst.readBusy;
-    UInt<1> ctl$InterruptController$$inst$_T_65 = ctl.InterruptController$$inst.readBusyOld & ctl$InterruptController$$inst$_T_64;
-    if (update_registers) ctl.InterruptController$$inst.readBusyOld = ctl.InterruptController$$inst.readBusy;
-    if (update_registers) ctl.InterruptController$$inst.readBusy = ctl.addressGeneratorRead.busy;
-    if (update_registers) ctl.addressGeneratorRead.busy = reset ? UInt<1>(0x0) : ctl$addressGeneratorRead$_GEN_0;
-    UInt<1> ctl$addressGeneratorWrite$_T_46 = ctl.addressGeneratorWrite.state == UInt<2>(0x0);
-    UInt<1> ctl$addressGeneratorWrite$_GEN_0 = ctl$addressGeneratorWrite$_T_46 ? UInt<1>(0x0) : UInt<1>(0x1);
-    UInt<1> ctl$addressGeneratorWrite$_T_49 = UInt<2>(0x0) == ctl.addressGeneratorWrite.state;
-    UInt<1> ctl$addressGeneratorWrite$_T_51 = UInt<2>(0x1) == ctl.addressGeneratorWrite.state;
-    UInt<35> ctl$addressGeneratorWrite$_T_54 = (ctl.addressGeneratorWrite.length_i * UInt<32>(0x4)).tail<29>();
-    UInt<35> ctl$addressGeneratorWrite$_GEN_28 = ctl.addressGeneratorWrite.address_i.pad<35>();
-    UInt<36> ctl$addressGeneratorWrite$_T_55 = ctl$addressGeneratorWrite$_GEN_28 + ctl$addressGeneratorWrite$_T_54;
-    UInt<35> ctl$addressGeneratorWrite$_T_56 = ctl$addressGeneratorWrite$_T_55.tail<1>();
-    UInt<35> ctl$addressGeneratorWrite$_T_58 = (ctl.addressGeneratorWrite.lineGap * UInt<32>(0x4)).tail<29>();
-    UInt<36> ctl$addressGeneratorWrite$_T_59 = ctl$addressGeneratorWrite$_T_56 + ctl$addressGeneratorWrite$_T_58;
-    UInt<35> ctl$addressGeneratorWrite$_T_60 = ctl$addressGeneratorWrite$_T_59.tail<1>();
-    UInt<33> ctl$addressGeneratorWrite$_T_62 = ctl.addressGeneratorWrite.lineCount - UInt<32>(0x1);
-    UInt<32> ctl$addressGeneratorWrite$_T_64 = ctl$addressGeneratorWrite$_T_62.tail<1>();
-    UInt<1> ctl$addressGeneratorWrite$_T_65 = UInt<2>(0x2) == ctl.addressGeneratorWrite.state;
-    UInt<1> ctl$addressGeneratorWrite$_T_69 = ctl.addressGeneratorWrite.lineCount > UInt<32>(0x0);
-    UInt<2> ctl$addressGeneratorWrite$_GEN_7 = ctl$addressGeneratorWrite$_T_69 ? UInt<2>(0x1) : UInt<2>(0x0);
-    UInt<2> ctl$addressGeneratorWrite$_GEN_8 = ctl.transferSplitterWrite._T_60 ? ctl$addressGeneratorWrite$_GEN_7 : ctl.addressGeneratorWrite.state;
-    UInt<1> ctl$addressGeneratorWrite$_GEN_9 = ctl$addressGeneratorWrite$_T_65 ? UInt<1>(0x0) : ctl.addressGeneratorWrite.valid;
-    UInt<2> ctl$addressGeneratorWrite$_GEN_11 = ctl$addressGeneratorWrite$_T_65 ? ctl$addressGeneratorWrite$_GEN_8 : ctl.addressGeneratorWrite.state;
-    UInt<1> ctl$addressGeneratorWrite$_GEN_12 = ctl$addressGeneratorWrite$_T_51 | ctl$addressGeneratorWrite$_GEN_9;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_13 = ctl$addressGeneratorWrite$_T_51 ? ctl.addressGeneratorWrite.address_i : ctl.addressGeneratorWrite.address_o;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_14 = ctl$addressGeneratorWrite$_T_51 ? ctl.addressGeneratorWrite.length_i : ctl.addressGeneratorWrite.length_o;
-    UInt<35> ctl$addressGeneratorWrite$_GEN_15 = ctl$addressGeneratorWrite$_T_51 ? ctl$addressGeneratorWrite$_T_60 : (ctl.addressGeneratorWrite.address_i.pad<35>());
-    UInt<32> ctl$addressGeneratorWrite$_GEN_16 = ctl$addressGeneratorWrite$_T_51 ? ctl$addressGeneratorWrite$_T_64 : ctl.addressGeneratorWrite.lineCount;
-    UInt<2> ctl$addressGeneratorWrite$_GEN_17 = ctl$addressGeneratorWrite$_T_51 ? UInt<2>(0x2) : ctl$addressGeneratorWrite$_GEN_11;
-    UInt<2> ctl$addressGeneratorWrite$_GEN_19 = ctl$addressGeneratorWrite$_T_49 ? ctl$addressGeneratorWrite$_GEN_1 : ctl$addressGeneratorWrite$_GEN_17;
-    UInt<35> ctl$addressGeneratorWrite$_GEN_20 = ctl$addressGeneratorWrite$_T_49 ? (ctl$addressGeneratorWrite$_GEN_2.pad<35>()) : ctl$addressGeneratorWrite$_GEN_15;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_21 = ctl$addressGeneratorWrite$_T_49 ? ctl$addressGeneratorWrite$_GEN_3 : ctl.addressGeneratorWrite.length_i;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_22 = ctl$addressGeneratorWrite$_T_49 ? ctl$addressGeneratorWrite$_GEN_4 : ctl$addressGeneratorWrite$_GEN_16;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_23 = ctl$addressGeneratorWrite$_T_49 ? ctl$addressGeneratorWrite$_GEN_5 : ctl.addressGeneratorWrite.lineGap;
-    UInt<1> ctl$addressGeneratorWrite$_GEN_25 = ctl$addressGeneratorWrite$_T_49 ? ctl.addressGeneratorWrite.valid : ctl$addressGeneratorWrite$_GEN_12;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_26 = ctl$addressGeneratorWrite$_T_49 ? ctl.addressGeneratorWrite.address_o : ctl$addressGeneratorWrite$_GEN_13;
-    UInt<32> ctl$addressGeneratorWrite$_GEN_27 = ctl$addressGeneratorWrite$_T_49 ? ctl.addressGeneratorWrite.length_o : ctl$addressGeneratorWrite$_GEN_14;
-    if (update_registers) ctl.addressGeneratorWrite.state = reset ? UInt<2>(0x0) : ctl$addressGeneratorWrite$_GEN_19;
-    if (update_registers) ctl.addressGeneratorWrite.lineCount = reset ? UInt<32>(0x0) : ctl$addressGeneratorWrite$_GEN_22;
-    if (update_registers) ctl.addressGeneratorWrite.lineGap = reset ? UInt<32>(0x0) : ctl$addressGeneratorWrite$_GEN_23;
-    UInt<32> ctl$transferSplitterWrite$_GEN_0 = ctl.addressGeneratorWrite.valid ? ctl.addressGeneratorWrite.address_o : ctl.transferSplitterWrite._T_42;
-    if (update_registers) ctl.addressGeneratorWrite.address_o = reset ? UInt<32>(0x0) : ctl$addressGeneratorWrite$_GEN_26;
-    if (update_registers) ctl.addressGeneratorWrite.address_i = reset ? UInt<32>(0x0) : (ctl$addressGeneratorWrite$_GEN_20.bits<31,0>());
-    UInt<32> ctl$transferSplitterWrite$_GEN_1 = ctl.addressGeneratorWrite.valid ? ctl.addressGeneratorWrite.length_o : ctl.transferSplitterWrite._T_45;
-    if (update_registers) ctl.addressGeneratorWrite.length_o = reset ? UInt<32>(0x0) : ctl$addressGeneratorWrite$_GEN_27;
-    if (update_registers) ctl.addressGeneratorWrite.length_i = reset ? UInt<32>(0x0) : ctl$addressGeneratorWrite$_GEN_21;
-    UInt<2> ctl$transferSplitterWrite$_GEN_3 = ctl.addressGeneratorWrite.valid ? UInt<2>(0x1) : ctl.transferSplitterWrite._T_65;
-    if (update_registers) ctl.addressGeneratorWrite.valid = reset ? UInt<1>(0x0) : ctl$addressGeneratorWrite$_GEN_25;
-    UInt<1> ctl$InterruptController$$inst$_T_59 = ~ctl.InterruptController$$inst.writeBusy;
-    UInt<1> ctl$InterruptController$$inst$_T_60 = ctl.InterruptController$$inst.writeBusyOld & ctl$InterruptController$$inst$_T_59;
-    if (update_registers) ctl.InterruptController$$inst.writeBusyOld = ctl.InterruptController$$inst.writeBusy;
-    if (update_registers) ctl.InterruptController$$inst.writeBusy = ctl.addressGeneratorWrite.busy;
-    if (update_registers) ctl.addressGeneratorWrite.busy = reset ? UInt<1>(0x0) : ctl$addressGeneratorWrite$_GEN_0;
-    UInt<1> ctl$transferSplitterWrite$_T_66 = UInt<2>(0x0) == ctl.transferSplitterWrite._T_65;
-    UInt<1> ctl$transferSplitterWrite$_T_68 = UInt<2>(0x1) == ctl.transferSplitterWrite._T_65;
-    UInt<1> ctl$transferSplitterWrite$_T_71 = ctl.transferSplitterWrite._T_45 > UInt<32>(0x100);
-    UInt<33> ctl$transferSplitterWrite$_T_74 = ctl.transferSplitterWrite._T_45 - UInt<32>(0x100);
-    UInt<32> ctl$transferSplitterWrite$_T_76 = ctl$transferSplitterWrite$_T_74.tail<1>();
-    UInt<12> ctl$transferSplitterWrite$_T_79 = (UInt<9>(0x100) * UInt<9>(0x4)).tail<6>();
-    UInt<32> ctl$transferSplitterWrite$_GEN_33 = ctl$transferSplitterWrite$_T_79.pad<32>();
-    UInt<33> ctl$transferSplitterWrite$_T_80 = ctl.transferSplitterWrite._T_42 + ctl$transferSplitterWrite$_GEN_33;
-    UInt<32> ctl$transferSplitterWrite$_T_81 = ctl$transferSplitterWrite$_T_80.tail<1>();
-    UInt<35> ctl$transferSplitterWrite$_T_84 = (ctl.transferSplitterWrite._T_45 * UInt<32>(0x4)).tail<29>();
-    UInt<35> ctl$transferSplitterWrite$_GEN_34 = ctl.transferSplitterWrite._T_42.pad<35>();
-    UInt<36> ctl$transferSplitterWrite$_T_85 = ctl$transferSplitterWrite$_GEN_34 + ctl$transferSplitterWrite$_T_84;
-    UInt<35> ctl$transferSplitterWrite$_T_86 = ctl$transferSplitterWrite$_T_85.tail<1>();
-    UInt<32> ctl$transferSplitterWrite$_GEN_4 = ctl$transferSplitterWrite$_T_71 ? UInt<32>(0x100) : ctl.transferSplitterWrite._T_45;
-    UInt<32> ctl$transferSplitterWrite$_GEN_5 = ctl$transferSplitterWrite$_T_71 ? ctl$transferSplitterWrite$_T_76 : UInt<32>(0x0);
-    UInt<35> ctl$transferSplitterWrite$_GEN_6 = ctl$transferSplitterWrite$_T_71 ? (ctl$transferSplitterWrite$_T_81.pad<35>()) : ctl$transferSplitterWrite$_T_86;
-    UInt<1> ctl$transferSplitterWrite$_T_87 = UInt<2>(0x2) == ctl.transferSplitterWrite._T_65;
-    UInt<1> ctl$transferSplitterWrite$_GEN_11 = ctl$transferSplitterWrite$_T_87 ? UInt<1>(0x0) : ctl.transferSplitterWrite._T_63;
-    UInt<2> ctl$transferSplitterWrite$_GEN_13 = ctl$transferSplitterWrite$_T_87 ? ctl$transferSplitterWrite$_GEN_9 : ctl.transferSplitterWrite._T_65;
-    UInt<1> ctl$transferSplitterWrite$_GEN_14 = ctl$transferSplitterWrite$_T_87 ? ctl$transferSplitterWrite$_GEN_10 : ctl.transferSplitterWrite._T_60;
-    UInt<32> ctl$transferSplitterWrite$_GEN_15 = ctl$transferSplitterWrite$_T_68 ? ctl.transferSplitterWrite._T_42 : ctl.transferSplitterWrite._T_48;
-    UInt<1> ctl$transferSplitterWrite$_GEN_17 = ctl$transferSplitterWrite$_T_68 | ctl$transferSplitterWrite$_GEN_11;
-    UInt<2> ctl$transferSplitterWrite$_GEN_18 = ctl$transferSplitterWrite$_T_68 ? UInt<2>(0x2) : ctl$transferSplitterWrite$_GEN_13;
-    UInt<32> ctl$transferSplitterWrite$_GEN_19 = ctl$transferSplitterWrite$_T_68 ? ctl$transferSplitterWrite$_GEN_4 : ctl.transferSplitterWrite._T_51;
-    UInt<32> ctl$transferSplitterWrite$_GEN_20 = ctl$transferSplitterWrite$_T_68 ? ctl$transferSplitterWrite$_GEN_5 : ctl.transferSplitterWrite._T_45;
-    UInt<35> ctl$transferSplitterWrite$_GEN_21 = ctl$transferSplitterWrite$_T_68 ? ctl$transferSplitterWrite$_GEN_6 : (ctl.transferSplitterWrite._T_42.pad<35>());
-    UInt<1> ctl$transferSplitterWrite$_GEN_23 = ctl$transferSplitterWrite$_T_68 ? ctl.transferSplitterWrite._T_60 : ctl$transferSplitterWrite$_GEN_14;
-    UInt<1> ctl$transferSplitterWrite$_GEN_24 = ctl$transferSplitterWrite$_T_66 ? UInt<1>(0x0) : ctl$transferSplitterWrite$_GEN_23;
-    UInt<35> ctl$transferSplitterWrite$_GEN_25 = ctl$transferSplitterWrite$_T_66 ? (ctl$transferSplitterWrite$_GEN_0.pad<35>()) : ctl$transferSplitterWrite$_GEN_21;
-    UInt<32> ctl$transferSplitterWrite$_GEN_26 = ctl$transferSplitterWrite$_T_66 ? ctl$transferSplitterWrite$_GEN_1 : ctl$transferSplitterWrite$_GEN_20;
-    UInt<2> ctl$transferSplitterWrite$_GEN_28 = ctl$transferSplitterWrite$_T_66 ? ctl$transferSplitterWrite$_GEN_3 : ctl$transferSplitterWrite$_GEN_18;
-    UInt<32> ctl$transferSplitterWrite$_GEN_29 = ctl$transferSplitterWrite$_T_66 ? ctl.transferSplitterWrite._T_48 : ctl$transferSplitterWrite$_GEN_15;
-    UInt<1> ctl$transferSplitterWrite$_GEN_31 = ctl$transferSplitterWrite$_T_66 ? ctl.transferSplitterWrite._T_63 : ctl$transferSplitterWrite$_GEN_17;
-    UInt<32> ctl$transferSplitterWrite$_GEN_32 = ctl$transferSplitterWrite$_T_66 ? ctl.transferSplitterWrite._T_51 : ctl$transferSplitterWrite$_GEN_19;
-    if (update_registers) ctl.transferSplitterWrite._T_42 = reset ? UInt<32>(0x0) : (ctl$transferSplitterWrite$_GEN_25.bits<31,0>());
-    if (update_registers) ctl.transferSplitterWrite._T_45 = reset ? UInt<32>(0x0) : ctl$transferSplitterWrite$_GEN_26;
-    if (update_registers) ctl.transferSplitterWrite._T_48 = reset ? UInt<32>(0x0) : ctl$transferSplitterWrite$_GEN_29;
-    if (update_registers) ctl.transferSplitterWrite._T_51 = reset ? UInt<32>(0x0) : ctl$transferSplitterWrite$_GEN_32;
-    if (update_registers) ctl.transferSplitterWrite._T_60 = reset ? UInt<1>(0x0) : ctl$transferSplitterWrite$_GEN_24;
-    if (update_registers) ctl.transferSplitterWrite._T_63 = reset ? UInt<1>(0x0) : ctl$transferSplitterWrite$_GEN_31;
-    if (update_registers) ctl.transferSplitterWrite._T_65 = reset ? UInt<2>(0x0) : ctl$transferSplitterWrite$_GEN_28;
-    UInt<32> ctl$ClearCSR$$inst$_T_29 = ~ctl$ClearCSR$$inst$io_clear;
-    UInt<32> ctl$ClearCSR$$inst$_T_30 = ctl.ClearCSR$$inst.reg & ctl$ClearCSR$$inst$_T_29;
-    UInt<32> ctl$ClearCSR$$inst$_GEN_0 = csr$io_csr_0_dataWrite ? csr$io_csr_0_dataOut : ctl$ClearCSR$$inst$_T_30;
-    if (update_registers) ctl.ClearCSR$$inst.reg = reset ? UInt<32>(0x0) : ctl$ClearCSR$$inst$_GEN_0;
-    if (update_registers) ctl.StatusCSR$$inst.reg = ctl$StatusCSR$$inst$io_value;
-    UInt<32> ctl$InterruptController$$inst$mask = ctl.InterruptController$$inst.SimpleCSR$$inst.reg;
-    UInt<1> ctl$InterruptController$$inst$_T_61 = ctl$InterruptController$$inst$mask.bits<0,0>();
-    UInt<1> ctl$InterruptController$$inst$_T_62 = ctl$InterruptController$$inst$_T_60 & ctl$InterruptController$$inst$_T_61;
-    UInt<1> ctl$InterruptController$$inst$_T_66 = ctl$InterruptController$$inst$mask.bits<1,1>();
-    UInt<1> ctl$InterruptController$$inst$_T_67 = ctl$InterruptController$$inst$_T_65 & ctl$InterruptController$$inst$_T_66;
-    UInt<2> ctl$InterruptController$$inst$irq = ctl.InterruptController$$inst.readBusyIrq.cat(ctl.InterruptController$$inst.writeBusyIrq);
-    UInt<32> ctl$InterruptController$$inst$SetCSR$$inst$io_set = ctl$InterruptController$$inst$irq.pad<32>();
-    if (update_registers) ctl.InterruptController$$inst.writeBusyIrq = reset ? UInt<1>(0x0) : ctl$InterruptController$$inst$_T_62;
-    if (update_registers) ctl.InterruptController$$inst.readBusyIrq = reset ? UInt<1>(0x0) : ctl$InterruptController$$inst$_T_67;
-    UInt<32> ctl$InterruptController$$inst$SimpleCSR$$inst$_GEN_0 = csr$io_csr_2_dataWrite ? csr$io_csr_2_dataOut : ctl.InterruptController$$inst.SimpleCSR$$inst.reg;
-    if (update_registers) ctl.InterruptController$$inst.SimpleCSR$$inst.reg = reset ? UInt<32>(0x0) : ctl$InterruptController$$inst$SimpleCSR$$inst$_GEN_0;
-    UInt<32> ctl$InterruptController$$inst$SetCSR$$inst$_T_29 = ~csr$io_csr_3_dataOut;
-    UInt<32> ctl$InterruptController$$inst$SetCSR$$inst$_T_30 = ctl.InterruptController$$inst.SetCSR$$inst.reg & ctl$InterruptController$$inst$SetCSR$$inst$_T_29;
-    UInt<32> ctl$InterruptController$$inst$SetCSR$$inst$_T_31 = ctl$InterruptController$$inst$SetCSR$$inst$_T_30 | ctl$InterruptController$$inst$SetCSR$$inst$io_set;
-    UInt<32> ctl$InterruptController$$inst$SetCSR$$inst$_T_32 = ctl.InterruptController$$inst.SetCSR$$inst.reg | ctl$InterruptController$$inst$SetCSR$$inst$io_set;
-    UInt<32> ctl$InterruptController$$inst$SetCSR$$inst$_GEN_0 = csr$io_csr_3_dataWrite ? ctl$InterruptController$$inst$SetCSR$$inst$_T_31 : ctl$InterruptController$$inst$SetCSR$$inst$_T_32;
-    if (update_registers) ctl.InterruptController$$inst.SetCSR$$inst.reg = reset ? UInt<32>(0x0) : ctl$InterruptController$$inst$SetCSR$$inst$_GEN_0;
-    UInt<32> ctl$SimpleCSR$$inst$_GEN_0 = csr$io_csr_4_dataWrite ? csr$io_csr_4_dataOut : ctl.SimpleCSR$$inst.reg;
-    if (update_registers) ctl.SimpleCSR$$inst.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR$$inst$_GEN_0;
-    UInt<32> ctl$SimpleCSR_1$_GEN_0 = csr$io_csr_5_dataWrite ? csr$io_csr_5_dataOut : ctl.SimpleCSR_1.reg;
-    if (update_registers) ctl.SimpleCSR_1.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_1$_GEN_0;
-    UInt<32> ctl$SimpleCSR_2$_GEN_0 = csr$io_csr_6_dataWrite ? csr$io_csr_6_dataOut : ctl.SimpleCSR_2.reg;
-    if (update_registers) ctl.SimpleCSR_2.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_2$_GEN_0;
-    UInt<32> ctl$SimpleCSR_3$_GEN_0 = csr$io_csr_7_dataWrite ? csr$io_csr_7_dataOut : ctl.SimpleCSR_3.reg;
-    if (update_registers) ctl.SimpleCSR_3.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_3$_GEN_0;
-    UInt<32> ctl$SimpleCSR_4$_GEN_0 = csr$io_csr_8_dataWrite ? csr$io_csr_8_dataOut : ctl.SimpleCSR_4.reg;
-    if (update_registers) ctl.SimpleCSR_4.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_4$_GEN_0;
-    UInt<32> ctl$SimpleCSR_5$_GEN_0 = csr$io_csr_9_dataWrite ? csr$io_csr_9_dataOut : ctl.SimpleCSR_5.reg;
-    if (update_registers) ctl.SimpleCSR_5.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_5$_GEN_0;
-    UInt<32> ctl$SimpleCSR_6$_GEN_0 = csr$io_csr_10_dataWrite ? csr$io_csr_10_dataOut : ctl.SimpleCSR_6.reg;
-    if (update_registers) ctl.SimpleCSR_6.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_6$_GEN_0;
-    UInt<32> ctl$SimpleCSR_7$_GEN_0 = csr$io_csr_11_dataWrite ? csr$io_csr_11_dataOut : ctl.SimpleCSR_7.reg;
-    if (update_registers) ctl.SimpleCSR_7.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_7$_GEN_0;
-    UInt<32> ctl$SimpleCSR_8$_GEN_0 = csr$io_csr_12_dataWrite ? csr$io_csr_12_dataOut : ctl.SimpleCSR_8.reg;
-    if (update_registers) ctl.SimpleCSR_8.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_8$_GEN_0;
-    UInt<32> ctl$SimpleCSR_9$_GEN_0 = csr$io_csr_13_dataWrite ? csr$io_csr_13_dataOut : ctl.SimpleCSR_9.reg;
-    if (update_registers) ctl.SimpleCSR_9.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_9$_GEN_0;
-    UInt<32> ctl$SimpleCSR_10$_GEN_0 = csr$io_csr_14_dataWrite ? csr$io_csr_14_dataOut : ctl.SimpleCSR_10.reg;
-    if (update_registers) ctl.SimpleCSR_10.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_10$_GEN_0;
-    UInt<32> ctl$SimpleCSR_11$_GEN_0 = csr$io_csr_15_dataWrite ? csr$io_csr_15_dataOut : ctl.SimpleCSR_11.reg;
-    if (update_registers) ctl.SimpleCSR_11.reg = reset ? UInt<32>(0x0) : ctl$SimpleCSR_11$_GEN_0;
-    UInt<1> queue$do_enq = queue$io_enq_ready & readerFrontend$io_dataOut_valid;
-    UInt<1> queue$do_deq = writerFrontend$io_dataIn_ready & queue$io_deq_valid;
-    UInt<10> queue$_T_52 = queue.value + UInt<9>(0x1);
-    UInt<9> queue$_T_53 = queue$_T_52.tail<1>();
-    UInt<9> queue$_GEN_5 = queue$do_enq ? queue$_T_53 : queue.value;
-    UInt<10> queue$_T_56 = queue.value_1 + UInt<9>(0x1);
-    UInt<9> queue$_T_57 = queue$_T_56.tail<1>();
-    UInt<9> queue$_GEN_6 = queue$do_deq ? queue$_T_57 : queue.value_1;
-    UInt<1> queue$_T_58 = queue$do_enq != queue$do_deq;
-    UInt<1> queue$_GEN_7 = queue$_T_58 ? queue$do_enq : queue.maybe_full;
-    std::cout<<"queue$io_enq_ready is: "<<queue$io_enq_ready; 
-    std::cout<<"readerFrontend$io_dataOut_valid is: "<<readerFrontend$io_dataOut_valid; 
-    if (update_registers && (queue$io_enq_ready & readerFrontend$io_dataOut_valid) && UInt<1>(0x1)) { 
-        queue.ram[queue.value.as_single_word()] = io_read_tdata;
-        std::cout<<"Queue value is: "<<queue.ram[queue.value.as_single_word()]; 
-    }
-    if (update_registers) queue.value = reset ? UInt<9>(0x0) : queue$_GEN_5;
-    if (update_registers) queue.value_1 = reset ? UInt<9>(0x0) : queue$_GEN_6;
-    if (update_registers) queue.maybe_full = reset ? UInt<1>(0x0) : queue$_GEN_7;
-  
-    print_registers();
-  } 
-  
-//define debug functions here
-
-void print_registers(){
-    std::cout<<"   io_control_aw_awaddr   "<<io_control_aw_awaddr<<std::endl;     
-    std::cout<<"   io_control_w_wdata     "<<io_control_w_wdata  <<std::endl;   
-    std::cout<<"   io_control_ar_araddr   "<<io_control_ar_araddr<<std::endl;   
-    std::cout<<"   io_control_r_rdata     "<<io_control_r_rdata  <<std::endl<<std::endl;
-    std::cout<<"   io_write_aw_awid       "<<io_write_aw_awid    <<std::endl;    
-    std::cout<<"   io_read_tdata          "<<io_read_tdata       <<std::endl;   
-    std::cout<<"   io_read_tvalid          "<<io_read_tvalid       <<std::endl;   
-    std::cout<<"   io_write_aw_awaddr     "<<io_write_aw_awaddr  <<std::endl;
-    std::cout<<"   io_write_w_wdata       "<<io_write_w_wdata    <<std::endl;
-    std::cout<<"   io_write_ar_araddr     "<<io_write_ar_araddr  <<std::endl;
-    std::cout<<"   io_write_r_rdata       "<<io_write_r_rdata    <<std::endl;
-  }
-} AXITop;
-
-#endif  // AXITOP_H_
diff --git a/src/sst/elements/osseous/Makefile.am b/src/sst/elements/osseous/Makefile.am
deleted file mode 100644
index 6f4dc66b73..0000000000
--- a/src/sst/elements/osseous/Makefile.am
+++ /dev/null
@@ -1,48 +0,0 @@
-# -*- Makefile -*-
-#
-#
-INCLUDE = -I$(top_srcdir)/src/sst/elements/osseous/eras_datatypes/ -I$(top_srcdir)/src/sst/elements/ariel/
-FLAGS = -fpermissive -std=c++11 
-
-
-AM_CPPFLAGS += \
-	$(MPI_CPPFLAGS) \
-	$(INCLUDE) \
-	$(FLAGS)
-
-compdir = $(pkglibdir)
-comp_LTLIBRARIES = librtlcomponent.la
-librtlcomponent_la_SOURCES = \
-	rtlcomponent.h \
-	rtlcomponent.cc \
-	rtlevent.h \
-	rtlevent.cc \
-	rtlmemmgr.h \
-	rtlmemmgr_cache.h \
-	rtlmemmgr_simple.h \
-	rtlmemmgr_simple.cc \
-	rtl_header.h \
-	rtlreadev.h \
-	AXI_port.h \
-	rtlwriteev.h 
-
-EXTRA_DIST = \
-			 eras_datatypes/sint.h \
-			 eras_datatypes/uint.h \
-			 tests/Makefile \
-			 tests/tb_header.h \
-			 tests/tb_header.c \
-			 tests/testbench.c \
-			 tests/runstream.py
-
-
-librtlcomponent_la_LDFLAGS = -module -avoid-version
-
-install-exec-hook:
-	$(SST_REGISTER_TOOL) rtlcomponent  rtlcomponent_LIBDIR=$(abs_srcdir)
-	$(SST_REGISTER_TOOL) SST_ELEMENT_SOURCE  rtlcomponent=$(abs_srcdir)
-
-
-##########################################################################
-##########################################################################
-##########################################################################
diff --git a/src/sst/elements/osseous/README.md b/src/sst/elements/osseous/README.md
deleted file mode 100644
index d113c67280..0000000000
--- a/src/sst/elements/osseous/README.md
+++ /dev/null
@@ -1,71 +0,0 @@
-#### Osseous
-
-Osseous is a generic RTL Component template, a major portion of ERAS framework, which is updated based on the user requirement to generate dynamically loadable component with SST. The automation flow of the ERAS framework set up by the parser takes in the generic RTL template and C-model header as input and emits final dynamically loadable SST component library integrable with SST.
-
-The repository contain _osseous_ and an example of dynamically loadable component formed out of osseous. 
-Currently, the example is a simple vector shift register(_vecshiftreg_).
-
-```
-osseous
-osseous/tests/
-```
-To build and register _osseous_ & _vecshiftreg_ and run the shift register example, below are the steps.
-```
-clone the repository containing osseous
-
-Update other Env variables as part of standard sst-elements build process(SST_ELEMENTS_HOME, SST_CORE_HOME)
-cd path/to/sst-elements/
-./autogen.sh
-./configure --prefix=$SST_ELEMENTS_HOME --with-sst-core=$SST_CORE_HOME --with-pin=$PINHOME
-make all
-make install
-export PATH=$SST_CORE_HOME/bin:$SST_ELEMENTS_HOME/bin:$PATH
-
-cd src/sst/elements/osseous/tests
-make all (compiles RTL testbench into executable that is fed to Ariel)
-sst runstream.py
-```
-Note that Ariel and its links with vecshiftreg has to be specified in python configuration file for appropriate functionality. The statistics collected will be visible at the end of simulation. The cycle count of RTL testbench has to be increased by significant figure to observe notable changes in simulation time due to RTL simulation.
-
-**Modifying C-testbench: **
-```
-osseous/tests/testbench.c
-```
-Provided testbench (_testbench.c_) contains both non-RTL computations (weighted matrix addition) and RTL testvectors. 
-It has following APIs:
-
-**User APIs:**
-```
-start_RTL_sim(shmem) - To begin RTL simulation and pass the virtual addresses of RTL inputs(shmem) to send it to DUT. Ariel sends an event to DUT (RTL Component) to initiate simulation
-update_RTL_sig(shmem) - To update the RTL input signals while simulation progresses.
-```
-**Supporting APIs (Definition in tb_header.c):**
-```
-RTL_shmem_info(): mem malloc space to store RTL inputs into memH (intercepted by PIN)
-Update_RTL_params(): Updates RTL params to defaults
-
-perform_update(upd_inp, upd_ctrl, upd_eval_args, upd_reg, verbose, done_rst, sim_done, sim_cycles): RTL parameters specified as arguments
-bool upd_inp: Update RTL inputs?
-bool upd_ctrl: Update control data?
-bool upd_eval_args: Update eval() API arguments? eval() is primary API of C-model header
-
-storetomem(): Updates the RTL parameters in memH (stores are intercepted by PIN)
-```
-**_eval(upd_reg, verbose, done_rst)_ API Arguments (Part of C-model header):**
-```
-bool upd_reg: Update C-model registers?
-bool verbose: Print debug information?
-bool done_rst: NA (Not used)
-bool sim_done: simulation done? ("true" marks end of simulation after specified cycles)
-uint64_t sim_cyles: specifies number of SST cycles RTL C-model should simulate with provided inputs (shmem)
-```
-Eval API arguments are passed along with rest of the RTL inputs to be stored into memH.
-
-**Statistics collected:**
-```
- vecshiftregister. : Accumulator : Sum.u64 = 9; SumSQ.u64 = 9; Count.u64 = 9; Min.u64 = 1; Max.u64 = 1; (read_requests)
- vecshiftregister. : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; (write_requests)
- vecshiftregister. : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; (write_request_sizes)
- vecshiftregister. : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; (split_read_requests)
- vecshiftregister. : Accumulator : Sum.u64 = 0; SumSQ.u64 = 0; Count.u64 = 0; Min.u64 = 0; Max.u64 = 0; (split_write_requests)
- ```
diff --git a/src/sst/elements/osseous/eras_datatypes/sint.h b/src/sst/elements/osseous/eras_datatypes/sint.h
deleted file mode 100644
index 8ba089a09f..0000000000
--- a/src/sst/elements/osseous/eras_datatypes/sint.h
+++ /dev/null
@@ -1,394 +0,0 @@
-// Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) Copyright
-// (c) 2019, The Regents of the University of California, through Lawrence
-// Berkeley National Laboratory (subject to receipt of any required approvals from
-// the U.S. Dept. of Energy). All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// (1) Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// (2) Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-// 
-// (3) Neither the name of the University of California, Lawrence Berkeley
-// National Laboratory, U.S. Dept. of Energy nor the names of its contributors
-// may be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-// 
-// You are under no obligation whatsoever to provide any bug fixes, patches,
-// or upgrades to the features, functionality or performance of the source
-// code ("Enhancements") to anyone; however, if you choose to make your
-// Enhancements available either publicly, or directly to Lawrence Berkeley
-// National Laboratory, without imposing a separate written license agreement
-// for such Enhancements, then you hereby grant the following license: a
-// non-exclusive, royalty-free perpetual license to install, use, modify,
-// prepare derivative works, incorporate into other computer software,
-// distribute, and sublicense such enhancements or derivative works thereof,
-// in binary and source code form.
-
-#ifndef SINT_H_
-#define SINT_H_
-
-#include <cinttypes>
-
-#include "uint.h"
-
-
-template<int w_>
-class SInt {
-  private: // copied from uint.h
-  constexpr static int cmin(int wa, int wb) { return wa < wb ? wa : wb; }
-  constexpr static int cmax(int wa, int wb) { return wa > wb ? wa : wb; }
-
-public:
-  SInt() : ui(0) {}
-
-  SInt(int64_t i) : ui(i) {
-    if (w_ > kWordSize)
-      sign_extend(kWordSize - 1);
-    else
-      sign_extend();
-  }
-
-  SInt(std::string initial) : ui(initial) {
-    sign_extend();
-  }
-
-  // TODO: make array's template parameters somehow inherit from ui
-  SInt(std::array<uint64_t, (w_+63)/64> raw_input_reversed) : ui(raw_input_reversed) {
-    sign_extend();
-  }
-
-  template<int other_w>
-  explicit SInt(const SInt<other_w> &other) {
-    static_assert(other_w <= w_, "Can't copy construct from wider SInt");
-    ui = UInt<w_>(other.ui);
-    sign_extend(other_w - 1);
-  }
-
-  SInt(const UInt<w_> &other) : ui(other) {}
-
-  void rand_init() {
-    ui.core_rand_init();
-    sign_extend();
-  }
-
-  template<int out_w>
-  SInt<cmax(w_,out_w)> pad() const {
-    return SInt<cmax(w_,out_w)>(*this);
-  }
-
-  template<int other_w>
-  SInt<w_ + other_w> cat(const SInt<other_w> &other) const {
-    UInt<other_w> other_ui = other.ui;
-    other_ui.mask_top_unused();
-    SInt<w_ + other_w> result(ui.cat(other_ui));
-    result.sign_extend();
-    return result;
-  }
-
-  SInt<w_ + 1> operator+(const SInt<w_> &other) const {
-    SInt<w_+1> result(ui.template core_add_sub<w_+1, false>(other.ui));
-    if (w_ % kWordSize == 0) {
-      if (negative() == other.negative()) {
-        result.ui.words_[ui.word_index(w_)] = negative() ? -1 : 0;
-      } else {
-        bool is_neg = static_cast<int64_t>(result.ui.words_[ui.word_index(w_-1)]) < 0;
-        result.ui.words_[ui.word_index(w_)] = is_neg ? -1 : 0;
-      }
-    }
-    return result;
-  }
-
-  SInt<w_> addw(const SInt<w_> &other) const {
-    return ui.template core_add_sub<w_, false>(other.ui);
-  }
-
-  SInt<w_> subw(const SInt<w_> &other) const {
-    SInt<w_> result(ui.template core_add_sub<w_, true>(other.ui));
-    result.sign_extend();
-    return result;
-  }
-
-  SInt<w_ + 1> operator-() const {
-    return SInt<w_>(0) - *this;
-  }
-
-  SInt<w_ + 1> operator-(const SInt<w_> &other) const {
-    SInt<w_ + 1> result(ui.template core_add_sub<w_+1, true>(other.ui));
-    if (w_ % kWordSize == 0) {
-      if (negative() != other.negative()) {
-        result.ui.words_[ui.word_index(w_)] = negative() ? -1 : 0;
-      } else {
-        bool is_neg = static_cast<int64_t>(result.ui.words_[ui.word_index(w_-1)]) < 0;
-        result.ui.words_[ui.word_index(w_)] = is_neg ? -1 : 0;
-      }
-    }
-    return result;
-  }
-
-  SInt<w_ + w_> operator*(const SInt<w_> &other) const {
-    SInt<4*w_> product(pad<w_ + w_>().ui * other.pad<w_ + w_>().ui);
-    SInt<w_ + w_> result = (product.template tail<w_ + w_>()).asSInt();
-    result.sign_extend();
-    return result;
-  }
-
-  template<int other_w>
-  SInt<w_+1> operator/(const SInt<other_w> &other) const {
-    static_assert(w_ <= kWordSize, "Div not supported beyond 64b");
-    static_assert(other_w <= kWordSize, "Div not supported beyond 64b");
-    return SInt<w_+1>(as_single_word() / other.as_single_word());
-  }
-
-  template<int other_w>
-  SInt<cmin(w_, other_w)> operator%(const SInt<other_w> &other) const {
-    static_assert(w_ <= kWordSize, "Mod not supported beyond 64b");
-    static_assert(other_w <= kWordSize, "Mod not supported beyond 64b");
-    return SInt<cmin(w_, other_w)>(as_single_word() % other.as_single_word());
-  }
-
-  UInt<w_> operator~() const {
-    return ~ui;
-  }
-
-  UInt<w_> operator&(const SInt<w_> &other) const {
-    UInt<w_> result = ui & other.ui;
-    result.mask_top_unused();
-    return result;
-  }
-
-  UInt<w_> operator|(const SInt<w_> &other) const {
-    UInt<w_> result = ui | other.ui;
-    result.mask_top_unused();
-    return result;
-  }
-
-  UInt<w_> operator^(const SInt<w_> &other) const {
-    UInt<w_> result = ui ^ other.ui;
-    result.mask_top_unused();
-    return result;
-  }
-
-  UInt<1> andr() const {
-    UInt<w_> upper_bits_clear = ui;
-    upper_bits_clear.mask_top_unused();
-    return upper_bits_clear.andr();
-  }
-
-  UInt<1> orr() const {
-    UInt<w_> upper_bits_clear = ui;
-    upper_bits_clear.mask_top_unused();
-    return upper_bits_clear.orr();
-  }
-
-  UInt<1> xorr() const {
-    UInt<w_> upper_bits_clear = ui;
-    upper_bits_clear.mask_top_unused();
-    return upper_bits_clear.xorr();
-  }
-
-  template<int hi, int lo>
-  UInt<hi - lo + 1> bits() const {
-    return ui.template bits<hi,lo>();
-  }
-
-  template<int n>
-  UInt<n> head() const {
-    static_assert(n <= w_, "Head n must be <= width");
-    return bits<w_-1, w_-n>();
-  }
-
-  template<int n>
-  UInt<w_ - n> tail() const {
-    static_assert(n < w_, "Tail n must be < width");
-    return bits<w_-n-1, 0>();
-  }
-
-  template<int shamt>
-  SInt<w_ + shamt> shl() const {
-    return cat(SInt<shamt>(0));
-  }
-
-  template<int shamt>
-  SInt<w_> shlw() const {
-    SInt<w_> result(ui.template shlw<shamt>());
-    result.sign_extend();
-    return result;
-  }
-
-  template<int shamt>
-  SInt<w_ - shamt> shr() const {
-    SInt<w_ - shamt> result(ui.template core_bits<w_-1, shamt>());
-    result.sign_extend(w_ - shamt - 1);
-    return result;
-  }
-
-  template<int other_w>
-  SInt<w_> operator>>(const UInt<other_w> &other) const {
-    uint64_t dshamt = other.as_single_word();
-    SInt<w_> result(ui >> other);
-    result.sign_extend(w_ - dshamt - 1);
-    return result;
-  }
-
-  template<int other_w>
-  SInt<w_ + (1<<other_w) - 1> operator<<(const UInt<other_w> &other) const {
-    uint64_t dshamt = other.as_single_word();
-    SInt<w_ + (1<<other_w) - 1> result(ui << other);
-    result.sign_extend(w_ + dshamt - 1);
-    return result;
-  }
-
-  template<int other_w>
-  SInt<w_> dshlw(const UInt<other_w> &other) const {
-    SInt<w_> result(ui.dshlw(other));
-    result.sign_extend();
-    return result;
-  }
-
-  UInt<1> operator<=(const SInt<w_> &other) const {
-    // if (ui.NW == 1)
-    //   return as_single_word() <= other.as_single_word();
-    if (negative()) {
-      if (other.negative())
-        return ui >= other.ui;
-      else
-        return UInt<1>(1);
-    } else {
-      if (other.negative())
-        return UInt<1>(0);
-      else
-        return ui <= other.ui;
-    }
-  }
-
-  UInt<1> operator>=(const SInt<w_> &other) const {
-    // if (ui.NW == 1)
-    //   return as_single_word() >= other.as_single_word();
-    if (negative()) {
-      if (other.negative())
-        return ui <= other.ui;
-      else
-        return UInt<1>(0);
-    } else {
-      if (other.negative())
-        return UInt<1>(1);
-      else
-        return ui >= other.ui;
-    }
-  }
-
-  UInt<1> operator<(const SInt<w_> &other) const {
-    return ~(*this >= other);
-  }
-
-  UInt<1> operator>(const SInt<w_> &other) const {
-    return ~(*this <= other);
-  }
-
-  UInt<1> operator==(const SInt<w_> &other) const {
-    return ui == other.ui;
-  }
-
-  UInt<1> operator!=(const SInt<w_> &other) const {
-    return ~(*this == other);
-  }
-
-  UInt<w_> asUInt() const {
-    UInt<w_> result(ui);
-    result.mask_top_unused();
-    return result;
-  }
-
-  SInt<w_> asSInt() const {
-    return SInt<w_>(*this);
-  }
-
-  SInt<w_> cvt() const {
-    return SInt<w_>(*this);
-  }
-
-  // Direct access for ops that only need small signals
-  int64_t as_single_word() const {
-    static_assert(w_ <= kWordSize, "SInt too big for single int64_t");
-    return ui.words_[0];
-  }
-
-
-protected:
-  template<int other_w>
-  friend class sint_wrapper_t;
-
-  void raw_copy_in(uint64_t *src) {
-    ui.raw_copy_in(src);
-  }
-
-  void raw_copy_out(uint64_t *dst) {
-    ui.raw_copy_out(dst);
-  }
-
-
-private:
-  UInt<w_> ui;
-
-  const static int kWordSize = UInt<w_>::kWordSize;
-
-  bool negative() const {
-    return static_cast<int64_t>(ui.words_[ui.word_index(w_ - 1)]) < 0;
-    // return (ui.words_[ui.word_index(w_ - 1)] >> ((w_-1) % kWordSize)) & 1;
-  }
-
-  void sign_extend(int sign_index = (w_-1)) {
-    int sign_offset = sign_index % kWordSize;
-    int sign_word = ui.word_index(sign_index);
-    bool is_neg = (ui.words_[sign_word] >> sign_offset) & 1;
-    ui.words_[sign_word] = (static_cast<int64_t>(ui.words_[sign_word]) <<
-                             (kWordSize - sign_offset - 1)) >>
-                             (kWordSize - sign_offset - 1);
-    for (int i = sign_word+1; i < ui.NW; i++) {
-      ui.words_[i] = is_neg ? -1 : 0;
-    }
-  }
-
-  void print_to_stream(std::ostream& os) const {
-    ui.print_to_stream(os);
-  }
-
-  template<int other_w, typename other_word_t, int other_n>
-  friend class UInt;
-
-  template<int w>
-  friend class SInt;
-
-  template<int w>
-  friend std::ostream& operator<<(std::ostream& os, const SInt<w>& ui);
-};
-
-template<int w>
-std::ostream& operator<<(std::ostream& os, const SInt<w>& si) {
-  // static_assert(w <= SInt<w>::kWordSize, "SInt too big to print");
-  // os << si.as_single_word() << "<S" << w << ">";
-  // return os;
-  si.print_to_stream(os);
-  os << "<S" << w << ">";
-  return os;
-}
-
-#endif  // SINT_H_
diff --git a/src/sst/elements/osseous/eras_datatypes/uint.h b/src/sst/elements/osseous/eras_datatypes/uint.h
deleted file mode 100644
index 158bc3cb9a..0000000000
--- a/src/sst/elements/osseous/eras_datatypes/uint.h
+++ /dev/null
@@ -1,549 +0,0 @@
-// Essential Signal Simulation Enabled by Netlist Transforms (ESSENT) Copyright
-// (c) 2019, The Regents of the University of California, through Lawrence
-// Berkeley National Laboratory (subject to receipt of any required approvals from
-// the U.S. Dept. of Energy). All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// (1) Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// (2) Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-// 
-// (3) Neither the name of the University of California, Lawrence Berkeley
-// National Laboratory, U.S. Dept. of Energy nor the names of its contributors
-// may be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-// 
-// You are under no obligation whatsoever to provide any bug fixes, patches,
-// or upgrades to the features, functionality or performance of the source
-// code ("Enhancements") to anyone; however, if you choose to make your
-// Enhancements available either publicly, or directly to Lawrence Berkeley
-// National Laboratory, without imposing a separate written license agreement
-// for such Enhancements, then you hereby grant the following license: a
-// non-exclusive, royalty-free perpetual license to install, use, modify,
-// prepare derivative works, incorporate into other computer software,
-// distribute, and sublicense such enhancements or derivative works thereof,
-// in binary and source code form.
-
-#ifndef UINT_H_
-#define UINT_H_
-
-#include <algorithm>
-#include <array>
-#include <cinttypes>
-#include <iomanip>
-#include <iostream>
-#include <random>
-#include <type_traits>
-
-
-// Internal RNG
-namespace {
-  std::mt19937_64 rng64(14);
-  uint64_t rng_leftover;
-  uint64_t rng_bits_left = 0;
-}
-
-// Forward dec
-template<int w_>
-class SInt;
-
-template<int w_,
-         typename word_t = typename std::conditional<(w_ <= 8),
-                                                     uint8_t, uint64_t>::type,
-         int n_ = (w_ <= 8) ? 1 : (w_ + 64 - 1) / 64>
-class UInt {
-private:
-  constexpr static int cmin(int wa, int wb) { return wa < wb ? wa : wb; }
-  constexpr static int cmax(int wa, int wb) { return wa > wb ? wa : wb; }
-
-public:
-  UInt() {
-    for (int i=0; i < n_; i++)
-      words_[i] = 0;
-  }
-
-  UInt(uint64_t initial) : UInt() {
-    words_[0] = initial;
-    mask_top_unused();
-  }
-
-  UInt(std::string initial) {
-    if (initial.substr(0,2) != "0x") {
-      std::cout << "ERROR: UInt string literal must start with 0x!" << std::endl;
-      std::exit(-17);
-    }
-    initial.erase(0,2);
-    // FUTURE: check that literal isn't too big
-    int input_bits = 4*initial.length();
-    int last_start = initial.length();
-    for (int word=0; word < n_; word++) {
-      if (word * kWordSize >= input_bits)
-        words_[word] = 0;
-      else {
-        int word_start = std::max(static_cast<int>(initial.length())
-                                  - 16*(word+1), 0);
-        int word_len = std::min(16, last_start - word_start);
-        last_start = word_start;
-        const std::string substr = initial.substr(word_start, word_len);
-        words_[word] = static_cast<uint64_t>(std::stoul(substr, nullptr, 16));
-      }
-    }
-  }
-
-  // NOTE: reads words right to left so literal appears to be concatted
-  UInt(std::array<word_t, n_> raw_input_reversed) {
-    for (int i = 0; i < n_; i++)
-      words_[i] = raw_input_reversed[n_ - i - 1];
-    mask_top_unused();
-  }
-
-  template<int other_w>
-  explicit UInt(const UInt<other_w> &other) {
-    static_assert(other_w <= w_, "Can't copy construct from wider UInt");
-    for (int word=0; word < n_; word++) {
-      if (word < UInt<other_w>::NW)
-        words_[word] = other.words_[word];
-      else
-        words_[word] = 0;
-    }
-  }
-
-  void rand_init() {
-    core_rand_init();
-    mask_top_unused();
-  }
-
-  template<int out_w>
-  UInt<cmax(w_,out_w)> pad() const {
-    return UInt<cmax(w_,out_w)>(*this);
-  }
-
-  template<int other_w>
-  UInt<w_ + other_w> cat(const UInt<other_w> &other) const {
-    UInt<w_ + other_w> to_return(other);
-    const int offset = other_w % kWordSize;
-    for (int i = 0; i < n_; i++) {
-      to_return.words_[word_index(other_w) + i] |= static_cast<uint64_t>(words_[i]) <<
-                                                     cap(offset);
-      if ((offset != 0) && (i + 1 < to_return.NW - word_index(other_w)))
-        to_return.words_[word_index(other_w) + i + 1] |= static_cast<uint64_t>(words_[i]) >>
-                                                           cap(kWordSize - offset);
-    }
-    return to_return;
-  }
-
-  UInt<w_ + 1> operator+(const UInt<w_> &other) const {
-    UInt<w_ + 1> result = core_add_sub<w_+1, false>(other);
-    if ((kWordSize * n_ == w_) && (result.words_[n_-1] < words_[n_-1]))
-      result.words_[word_index(w_ + 1)] = 1;
-    return result;
-  }
-
-  UInt<w_> addw(const UInt<w_> &other) const {
-    UInt<w_> result = core_add_sub<w_, false>(other);
-    result.mask_top_unused();
-    return result;
-  }
-
-  UInt<w_> subw(const UInt<w_> &other) const {
-    UInt<w_> result(core_add_sub<w_, true>(other.ui));
-    result.mask_top_unused();
-    return result;
-  }
-
-  SInt<w_ + 1> operator-() const {
-    return SInt<w_+1>(0).subw(SInt<w_+1>(pad<w_+1>()));
-  }
-
-  UInt<w_ + 1> operator-(const UInt<w_> &other) const {
-    UInt<w_ + 1> result = core_add_sub<w_+1, true>(other);
-    if (kWordSize * n_ == w_) {
-      if (result.words_[n_-1] < other.words_[n_-1])
-        result.words_[word_index(w_ + 1)] = 1;
-    } else {
-      result.mask_top_unused();
-    }
-    return result;
-  }
-
-  UInt<w_ + w_> operator*(const UInt<w_> &other) const {
-    UInt<w_ + w_> result(0);
-    uint64_t carry = 0;
-    for (int i=0; i < n_; i++) {
-      carry = 0;
-      for (int j=0; j < n_; j++) {
-        uint64_t prod_ll = lower(words_[i]) * lower(other.words_[j]);
-        uint64_t prod_lu = lower(words_[i]) * upper(other.words_[j]);
-        uint64_t prod_ul = upper(words_[i]) * lower(other.words_[j]);
-        uint64_t prod_uu = upper(words_[i]) * upper(other.words_[j]);
-        uint64_t lower_sum = lower(result.words_[i+j]) + lower(carry) +
-                             lower(prod_ll);
-        uint64_t upper_sum = upper(result.words_[i+j]) + upper(carry) +
-                             upper(prod_ll) + upper(lower_sum) +
-                             lower(prod_lu) + lower(prod_ul);
-        result.words_[i+j] = (upper_sum << 32) | lower(lower_sum);
-        carry = upper(upper_sum) + upper(prod_lu) + upper(prod_ul) + prod_uu;
-      }
-      if ((i+n_) < result.NW)
-        result.words_[i + n_] += carry;
-    }
-    return result;
-  }
-
-  // this / other
-  template<int other_w>
-  UInt<w_> operator/(const UInt<other_w> &other) const {
-    static_assert(w_ <= kWordSize, "Div not supported beyond 64b");
-    static_assert(other_w <= kWordSize, "Div not supported beyond 64b");
-    return UInt<w_>(as_single_word() / other.as_single_word());
-  }
-
-  // this % other
-  template<int other_w>
-  UInt<cmin(w_, other_w)> operator%(const UInt<other_w> &other) const {
-    static_assert(w_ <= kWordSize, "Mod not supported beyond 64b");
-    static_assert(other_w <= kWordSize, "Mod not supported beyond 64b");
-    return UInt<cmin(w_, other_w)>(as_single_word() % other.as_single_word());
-  }
-
-  UInt<w_> operator~() const {
-    UInt<w_> result;
-    for (int i = 0; i < n_; i++) {
-      result.words_[i] = ~words_[i];
-    }
-    result.mask_top_unused();
-    return result;
-  }
-
-  UInt<w_> operator&(const UInt<w_> &other) const {
-    UInt<w_> result;
-    for (int i = 0; i < n_; i++) {
-      result.words_[i] = words_[i] & other.words_[i];
-    }
-    return result;
-  }
-
-  UInt<w_> operator|(const UInt<w_> &other) const {
-    UInt<w_> result;
-    for (int i = 0; i < n_; i++) {
-      result.words_[i] = words_[i] | other.words_[i];
-    }
-    return result;
-  }
-
-  UInt<w_> operator^(const UInt<w_> &other) const {
-    UInt<w_> result;
-    for (int i = 0; i < n_; i++) {
-      result.words_[i] = words_[i] ^ other.words_[i];
-    }
-    return result;
-  }
-
-  UInt<1> andr() const {
-    return *this == ~UInt<w_>(0);
-  }
-
-  UInt<1> orr() const {
-    return *this != UInt<w_>(0);
-  }
-
-  UInt<1> xorr() const {
-    word_t result = 0;
-    for (int i = 0; i < n_; i++) {
-      word_t word_parity_scratch = words_[i] ^ (words_[i] >> 1);
-      word_parity_scratch ^= (word_parity_scratch >> 2);
-      word_parity_scratch ^= (word_parity_scratch >> 4);
-      if (WW > 8) {
-        word_parity_scratch ^= (word_parity_scratch >> 8);
-        word_parity_scratch ^= (word_parity_scratch >> 16);
-        word_parity_scratch ^= (word_parity_scratch >> 32);
-      }
-      result ^= word_parity_scratch;
-    }
-    return UInt<1>(result & 1);
-  }
-
-  template<int hi, int lo>
-  UInt<hi - lo + 1> bits() const {
-    UInt<hi - lo + 1> result = core_bits<hi,lo>();
-    result.mask_top_unused();
-    return result;
-  }
-
-  template<int n>
-  UInt<n> head() const {
-    static_assert(n <= w_, "Head n must be <= width");
-    return bits<w_-1, w_-n>();
-  }
-
-  template<int n>
-  UInt<w_ - n> tail() const {
-    static_assert(n < w_, "Tail n must be < width");
-    return bits<w_-n-1, 0>();
-  }
-
-  template<int shamt>
-  UInt<w_ + shamt> shl() const {
-    return cat(UInt<shamt>(0));
-  }
-
-  template<int shamt>
-  UInt<w_> shlw() const {
-    return shl<shamt>().template tail<shamt>();
-  }
-
-  template<int shamt>
-  UInt<w_ - shamt> shr() const {
-    return bits<w_-1, shamt>();
-  }
-
-  template<int other_w>
-  UInt<w_> operator>>(const UInt<other_w> &other) const {
-    UInt<w_> result(0);
-    uint64_t dshamt = other.as_single_word();
-    uint64_t word_down = word_index(dshamt);
-    uint64_t bits_down = dshamt % kWordSize;
-    for (uint64_t i=word_down; i < n_; i++) {
-      result.words_[i - word_down] = words_[i] >> bits_down;
-      if ((bits_down != 0) && (i < n_-1))
-        result.words_[i - word_down] |= words_[i + 1] << cap(kWordSize - bits_down);
-    }
-    return result;
-  }
-
-  template<int other_w>
-  UInt<w_ + (1<<other_w) - 1> operator<<(const UInt<other_w> &other) const {
-    UInt<w_ + (1<<other_w) - 1> result(0);
-    uint64_t dshamt = other.as_single_word();
-    uint64_t word_up = word_index(dshamt);
-    uint64_t bits_up = dshamt % kWordSize;
-    for (uint64_t i=0; i < n_; i++) {
-      result.words_[i + word_up] |= words_[i] << bits_up;
-      if ((bits_up != 0) && (dshamt + w_ > kWordSize) && (i + word_up + 1 < result.NW))
-        result.words_[i + word_up + 1] = words_[i] >> cap(kWordSize - bits_up);
-    }
-    return result;
-  }
-
-  template<int other_w>
-  UInt<w_> dshlw(const UInt<other_w> &other) const {
-    // return operator<<(other).template bits<w_-1,0>();
-    UInt<w_> result(0);
-    uint64_t dshamt = other.as_single_word();
-    uint64_t word_up = word_index(dshamt);
-    uint64_t bits_up = dshamt % kWordSize;
-    for (uint64_t i=0; i + word_up < n_; i++) {
-      result.words_[i + word_up] |= words_[i] << bits_up;
-      if ((bits_up != 0) && (w_ > kWordSize) && (i + word_up + 1 < n_))
-        result.words_[i + word_up + 1] = words_[i] >> cap(kWordSize - bits_up);
-    }
-    result.mask_top_unused();
-    return result;
-  }
-
-  UInt<1> operator<=(const UInt<w_> &other) const {
-    for (int i=n_-1; i >= 0; i--) {
-      if (words_[i] < other.words_[i]) return UInt<1>(1);
-      if (words_[i] > other.words_[i]) return UInt<1>(0);
-    }
-    return UInt<1>(1);
-  }
-
-  UInt<1> operator>=(const UInt<w_> &other) const {
-    for (int i=n_-1; i >= 0; i--) {
-      if (words_[i] > other.words_[i]) return UInt<1>(1);
-      if (words_[i] < other.words_[i]) return UInt<1>(0);
-    }
-    return UInt<1>(1);
-  }
-
-  UInt<1> operator<(const UInt<w_> &other) const {
-    return ~(*this >= other);
-  }
-
-  UInt<1> operator>(const UInt<w_> &other) const {
-    return ~(*this <= other);
-  }
-
-  UInt<1> operator==(const UInt<w_> &other) const {
-    for (int i = 0; i < n_; i++) {
-      if (words_[i] != other.words_[i])
-        return UInt<1>(0);
-    }
-    return UInt<1>(1);
-  }
-
-  UInt<1> operator!=(const UInt<w_> &other) const {
-    return ~(*this == other);
-  }
-
-  operator bool() const {
-    static_assert(w_ == 1, "conversion to bool only allowed for width 1");
-    return static_cast<bool>(words_[0]);
-  }
-
-  UInt<w_> asUInt() const {
-    return UInt<w_>(*this);
-  }
-
-  SInt<w_> asSInt() const {
-    SInt<w_> result(*this);
-    result.sign_extend();
-    return result;
-  }
-
-  SInt<w_ + 1> cvt() const {
-    return pad<w_+1>().asSInt();
-  }
-
-  // Direct access for ops that only need small signals
-  uint64_t as_single_word() const {
-    static_assert(w_ <= kWordSize, "UInt too big for single uint64_t");
-    return words_[0];
-  }
-
-protected:
-  template<int other_w>
-  friend class uint_wrapper_t;
-
-  void raw_copy_in(uint64_t *src) {
-    for (int word=0; word < n_; word++)
-      words_[word] = *src++;
-  }
-
-  void raw_copy_out(uint64_t *dst) {
-    for (int word=0; word < n_; word++)
-      *dst++ = words_[word];
-  }
-
-private:
-  // Internal state
-  std::array<word_t, n_> words_;
-
-  // Access array word type
-  typedef word_t WT;
-  // Access array length
-  const static int NW = n_;
-  // Access array word type bit width
-  const static int WW = std::is_same<word_t,uint64_t>::value ? 64 : 8;
-
-  const static int bits_in_top_word_ = w_ % WW == 0 ? WW : w_ % WW;
-
-  // Friend Access
-  template<int other_w, typename other_word_t, int other_n>
-  friend class UInt;
-
-  template<int other_w>
-  friend class SInt;
-
-  template<int w>
-  friend std::ostream& operator<<(std::ostream& os, const UInt<w>& ui);
-
-  // Bit Addressing
-  const static int kWordSize = 64;
-
-  int static word_index(int bit_index) { return bit_index / kWordSize; }
-
-  uint64_t static upper(uint64_t i) { return i >> 32; }
-  uint64_t static lower(uint64_t i) { return i & 0x00000000ffffffff; }
-
-  // Hack to prevent compiler warnings for shift amount being too large
-  int static cap(int s) { return s % kWordSize; }
-
-  // Clean up high bits
-  void mask_top_unused() {
-    if (bits_in_top_word_ != WW) {
-      words_[n_-1] = words_[n_-1] & ((1l << cap(bits_in_top_word_)) - 1l);
-    }
-  }
-
-  // Reused math operators
-  template<int out_w, bool subtract>
-  UInt<out_w> core_add_sub(const UInt<w_> &other) const {
-    UInt<out_w> result;
-    uint64_t carry = subtract;
-    for (int i = 0; i < n_; i++) {
-      uint64_t operand = subtract ? ~other.words_[i] : other.words_[i];
-      result.words_[i] = words_[i] + operand + carry;
-      carry = result.words_[i] < operand ? 1 : 0;
-    }
-    return result;
-  }
-
-  __attribute__((noinline))
-  void core_rand_init() {
-    // trusting mask_top_unused() will be called afterwards
-    if (w_ < 64) {
-      if (w_ > rng_bits_left) {
-        rng_leftover = rng64();
-        rng_bits_left = 64;
-      }
-      words_[0] = rng_leftover;
-      rng_leftover = rng_leftover >> cap(w_);
-      rng_bits_left -= w_;
-    } else {
-      for (int word=0; word < n_; word++) {
-        words_[word] = rng64();
-      }
-    }
-  }
-
-  template<int hi, int lo>
-  UInt<hi - lo + 1> core_bits() const {
-    static_assert(hi < w_, "Bit extract hi bigger than width");
-    static_assert(hi >= lo, "Bit extract lo > hi");
-    static_assert(lo >= 0, "Bit extract lo is negative");
-    UInt<hi - lo + 1> result;
-    int word_down = word_index(lo);
-    int bits_down = lo % kWordSize;
-    for (int i=0; i < result.NW; i++) {
-      result.words_[i] = words_[i + word_down] >> bits_down;
-      if ((bits_down != 0) && (i + word_down + 1 < n_))
-        result.words_[i] |= words_[i + word_down + 1] << cap(kWordSize - bits_down);
-    }
-    return result;
-  }
-
-
-  void print_to_stream(std::ostream& os) const {
-    os << "0x" << std::hex << std::setfill('0');
-    int top_nibble_width = (bits_in_top_word_ + 3) / 4;
-    os << std::setw(top_nibble_width);
-    uint64_t top_word_mask = bits_in_top_word_ == kWordSize ? -1 :
-                               (1l << cap(bits_in_top_word_)) - 1;
-    os << (static_cast<uint64_t>(words_[n_-1]) & top_word_mask);
-    for (int word=n_ - 2; word >= 0; word--) {
-     os << std::hex << std::setfill('0') << std::setw(16) << words_[word];
-    }
-    os << std::dec;
-  }
-};
-
-
-
-template<int w>
-std::ostream& operator<<(std::ostream& os, const UInt<w>& ui) {
-  ui.print_to_stream(os);
-  os << "<U" << w << ">";
-  return os;
-}
-
-#endif  // UINT_H_
diff --git a/src/sst/elements/osseous/input_port.spec b/src/sst/elements/osseous/input_port.spec
deleted file mode 100644
index 6dbd8c403e..0000000000
--- a/src/sst/elements/osseous/input_port.spec
+++ /dev/null
@@ -1,31 +0,0 @@
-#Full signal names along with complete alias path for external object reference (E.g. ldut.cbus.fixer.TLMonitor$$inst.plusarg_reader$$inst.out)
-Input_sig:
-io_ins_0
-io_ins_1
-io_ins_2
-io_ins_3
-io_load
-io_shift
-
-#Interface Ports floating out in RTL C-Model
-AXIPort 
-#AXI Protocol to use. Will support AXIStream, AXI4, AXI4Lite
-AXIProtocol:AXIStream
-#Config - Master or Slave
-config:Slave
-#Mode - Streaming or Burst mode is supported. Current design supports only streaming mode
-Mode:Streaming 
-#Interface Signals
-AXI_sig:
-io_nasti_aw_ready
-io_nasti_ar_ready
-io_nasti_w_ready
-io_nasti_b_valid
-io_nasti_b_bits_id
-io_nasti_b_bits_resp
-io_nasti_r_valid 
-io_nasti_r_bits_id 
-io_nasti_r_bits_resp
-io_nasti_r_bits_last
-io_nasti_r_bits_data
-
diff --git a/src/sst/elements/osseous/rtl_header.h b/src/sst/elements/osseous/rtl_header.h
deleted file mode 100644
index 723fabbcd4..0000000000
--- a/src/sst/elements/osseous/rtl_header.h
+++ /dev/null
@@ -1,79 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#ifndef VECSHIFTREGISTER_H_
-#define VECSHIFTREGISTER_H_
-
-#include <iostream>
-#include <sstream> 
-#include <inttypes.h>
-#include <array>
-#include <cstdint>
-#include <cstdlib>
-#include <uint.h>
-#include <string.h>
-#include <sint.h>
-namespace SST {
-//#define UNLIKELY(condition) __builtin_expect(static_cast<bool>(condition), 0)
-typedef struct Rtlheader {
-  UInt<4> delays_0;
-  UInt<4> delays_1;
-  UInt<4> delays_2;
-  UInt<4> delays_3;
-  UInt<1> clock;
-  UInt<1> reset;
-  UInt<4> io_ins_0;
-  UInt<4> io_ins_1;
-  UInt<4> io_ins_2;
-  UInt<4> io_ins_3;
-  UInt<1> io_load;
-  UInt<1> io_shift;
-  UInt<4> io_out;
-
-
-  Rtlheader() {
-    delays_0.rand_init();
-    delays_1.rand_init();
-    delays_2.rand_init();
-    delays_3.rand_init();
-    reset.rand_init();
-    io_ins_0.rand_init();
-    io_ins_1.rand_init();
-    io_ins_2.rand_init();
-    io_ins_3.rand_init();
-    io_load.rand_init();
-    io_shift.rand_init();
-    io_out.rand_init();
-  }
-
-  void eval(bool update_registers, bool verbose, bool done_reset) {
-    std::stringstream str;
-    UInt<4> _GEN_0 = io_shift ? io_ins_0 : delays_0;
-    UInt<4> _GEN_1 = io_shift ? delays_0 : delays_1;
-    UInt<4> _GEN_2 = io_shift ? delays_1 : delays_2;
-    UInt<4> _GEN_3 = io_shift ? delays_2 : delays_3;
-    io_out = delays_3;
-    if(update_registers) {
-        str << io_out;
-        printf("\nio_out: %s", str.str().c_str());
-    }
-    if (update_registers) delays_0 = io_load ? io_ins_0 : _GEN_0;
-    if (update_registers) delays_1 = io_load ? io_ins_1 : _GEN_1;
-    if (update_registers) delays_2 = io_load ? io_ins_2 : _GEN_2;
-    if (update_registers) delays_3 = io_load ? io_ins_3 : _GEN_3;
-  }
-} Rtlheader;
-} //namespace SST
-#endif  // VECSHIFTREGISTER_H_
diff --git a/src/sst/elements/osseous/rtlcomponent.cc b/src/sst/elements/osseous/rtlcomponent.cc
deleted file mode 100644
index 378b18f143..0000000000
--- a/src/sst/elements/osseous/rtlcomponent.cc
+++ /dev/null
@@ -1,527 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#include <sst_config.h>
-#include <sst/core/event.h>
-#include "rtlcomponent.h"
-#include "rtlevent.h"
-#include "rtl_header.h"
-#include "rtlmemmgr.h"
-
-using namespace SST;
-using namespace std;
-using namespace SST::RtlComponent;
-using namespace SST::Interfaces;
-
-Rtlmodel::Rtlmodel(SST::ComponentId_t id, SST::Params& params) :
-	SST::Component(id)/*, verbosity(static_cast<uint32_t>(out->getVerboseLevel()))*/ {
-
-    bool found;
-    dut = new Rtlheader;
-    axiport = new AXITop;
-    RtlAckEv = new ArielComponent::ArielRtlEvent();
-	output.init("Rtlmodel-" + getName() + "-> ", 1, 0, SST::Output::STDOUT);
-
-	RTLClk  = params.find<std::string>("ExecFreq", "1GHz" , found);
-    if (!found) {
-        getSimulationOutput().fatal(CALL_INFO, -1,"couldn't find work per cycle\n");
-    }
-
-	maxCycles = params.find<Cycle_t>("maxCycles", 0, found);
-    if (!found) {
-        getSimulationOutput().fatal(CALL_INFO, -1,"couldn't find work per cycle\n");
-    }
-
-	/*if(RTLClk == NULL || RTLClk == "0") 
-		output.fatal(CALL_INFO, -1, "Error: printFrequency must be greater than zero.\n");*/
-
- 	output.verbose(CALL_INFO, 1, 0, "Config: maxCycles=%" PRIu64 ", RTL Clock Freq=%s\n",
-		static_cast<uint64_t>(maxCycles), RTLClk.c_str());
-
-	// Just register a plain clock for this simple example
-    output.verbose(CALL_INFO, 1, 0, "Registering RTL clock at %s\n", RTLClk.c_str());
-   
-   //set our clock 
-   clock_handler = new Clock::Handler<Rtlmodel>(this, &Rtlmodel::clockTick); 
-   timeConverter = registerClock(RTLClk, clock_handler);
-   unregisterClock(timeConverter, clock_handler);
-   writePayloads = params.find<int>("writepayloadtrace") == 0 ? false : true;
-
-    //Configure and register Event Handler for ArielRtllink
-   ArielRtlLink = configureLink("ArielRtllink", new Event::Handler<Rtlmodel>(this, &Rtlmodel::handleArielEvent)); 
-
-    // Find all the components loaded into the "memory" slot
-    // Make sure all cores have a loaded subcomponent in their slot
-    cacheLink = loadUserSubComponent<Interfaces::StandardMem>("memory", ComponentInfo::SHARE_NONE, timeConverter, new StandardMem::Handler<Rtlmodel>(this, &Rtlmodel::handleMemEvent));
-    if(!cacheLink) {
-       std::string interfaceName = params.find<std::string>("memoryinterface", "memHierarchy.standardInterface");
-       output.verbose(CALL_INFO, 1, 0, "Memory interface to be loaded is: %s\n", interfaceName.c_str());
-       
-       Params interfaceParams = params.get_scoped_params("memoryinterfaceparams");
-       interfaceParams.insert("port", "RtlCacheLink");
-       cacheLink = loadAnonymousSubComponent<Interfaces::StandardMem>(interfaceName, "memory", 0, ComponentInfo::SHARE_PORTS | ComponentInfo::INSERT_STATS,
-               interfaceParams, timeConverter, new StandardMem::Handler<Rtlmodel>(this, &Rtlmodel::handleMemEvent));
-       
-       if (!cacheLink)
-           output.fatal(CALL_INFO, -1, "%s, Error loading memory interface\n", getName().c_str());
-   }
-
-    std::string memorymanager = params.find<std::string>("memmgr", "rtl.MemoryManagerSimple");
-    if (NULL != (memmgr = loadUserSubComponent<RtlMemoryManager>("memmgr"))) {
-        output.verbose(CALL_INFO, 1, 0, "Loaded memory manager: %s\n", memmgr->getName().c_str());
-    } else {
-        // Warn about memory levels and the selected memory manager if needed
-        if (memorymanager == "rtl.MemoryManagerSimple" /*&& memLevels > 1*/) {
-            output.verbose(CALL_INFO, 1, 0, "Warning - the default 'rtl.MemoryManagerSimple' does not support multiple memory levels. Configuring anyways but memorylevels will be 1.\n");
-            params.insert("memmgr.memorylevels", "1", true);
-        }
-
-        output.verbose(CALL_INFO, 1, 0, "Loading memory manager: %s\n", memorymanager.c_str());
-        Params mmParams = params.get_scoped_params("memmgr");
-        memmgr = loadAnonymousSubComponent<RtlMemoryManager>(memorymanager, "memmgr", 0, ComponentInfo::SHARE_NONE | ComponentInfo::INSERT_STATS, mmParams);
-        if (NULL == memmgr) output.fatal(CALL_INFO, -1, "Failed to load memory manager: %s\n", memorymanager.c_str());
-    }
-
-    output.verbose(CALL_INFO, 1, 0, "RTL Memory manager construction is completed.\n");
-
-   pendingTransactions = new std::unordered_map<StandardMem::Request::id_t, StandardMem::Request*>();
-   pending_transaction_count = 0;
-   unregisterClock(timeConverter, clock_handler);
-   isStalled = true;
-
-    statReadRequests  = registerStatistic<uint64_t>( "read_requests");
-    statWriteRequests = registerStatistic<uint64_t>( "write_requests");
-    statReadRequestSizes = registerStatistic<uint64_t>( "read_request_sizes");
-    statWriteRequestSizes = registerStatistic<uint64_t>( "write_request_sizes");
-    statSplitReadRequests = registerStatistic<uint64_t>( "split_read_requests");
-    statSplitWriteRequests = registerStatistic<uint64_t>( "split_write_requests");
-    statFlushRequests = registerStatistic<uint64_t>( "flush_requests");
-    statFenceRequests = registerStatistic<uint64_t>( "fence_requests");
-
-
-   // Tell SST to wait until we authorize it to exit
-   registerAsPrimaryComponent();
-   primaryComponentDoNotEndSim();
-
-   sst_assert(ArielRtlLink, CALL_INFO, -1, "ArielRtlLink is null");
-}
-
-Rtlmodel::~Rtlmodel() {
-    delete dut;
-    delete axiport;
-}
-
-void Rtlmodel::setup() {
-    dut->reset = UInt<1>(1);
-    axiport->reset = UInt<1>(1);
-	output.verbose(CALL_INFO, 1, 0, "Component is being setup.\n");
-    for(int i = 0; i < 512; i++)
-        axiport->queue.ram[i] = 0;
-    axiport->eval(true,true,true);
-    axiport->reset = UInt<1>(0);
-}
-
-void Rtlmodel::init(unsigned int phase) {
-	output.verbose(CALL_INFO, 1, 0, "Component Init Phase Called %d\n", phase);
-    cacheLink->init(phase);
-}
-
-//Nothing to add in finish as of now. Need to see what could be added.
-void Rtlmodel::finish() {
-	output.verbose(CALL_INFO, 1, 0, "Component is being finished.\n");
-    free(getBaseDataAddress());
-}
-
-//clockTick will actually execute the RTL design at every cycle based on the input and control signals updated by CPU CPU or Event Handler.
-bool Rtlmodel::clockTick( SST::Cycle_t currentCycle ) {
-
-    /*if(!isStalled) {
-        if(tickCount == 4) {
-            output.verbose(CALL_INFO, 1, 0, "AXI signals changed"); 
-            axi_tvalid_$next = 1;
-            axi_tdata_$next = 34;
-            output.verbose(CALL_INFO, 1, 0, "\n Sending data at tickCount 4");
-        }
-    }
-
-    if((axi_tvalid_$old ^ axi_tvalid_$next) || (axi_tdata_$old ^ axi_tdata_$next))  {
-        uint8_t ready = 1;
-        output.verbose(CALL_INFO, 1, 0, "handleAXISignals called"); 
-        if(axiport->queue.maybe_full) 
-            ready = 0;
-        handleAXISignals(ready); 
-        axiport->eval(true, true, true);
-
-        //Initial value of AXI control signals
-        fifo_enq_$old = axiport->queue.value_1.as_single_word();
-        fifo_enq_$next = axiport->queue.value.as_single_word();
-        uint64_t prev_data = axiport->queue.ram[fifo_enq_$old].as_single_word();
-
-        while(!(prev_data ^ axiport->queue.ram[fifo_enq_$next].as_single_word())) {
-            prev_data = axiport->queue.ram[fifo_enq_$next].as_single_word();
-            axiport->eval(true, true, true);
-            fifo_enq_$next = axiport->queue.value.as_single_word();
-            if(fifo_enq_$old ^ fifo_enq_$next) {
-                stringstream queue_value, queue_ram;
-                queue_value << axiport->queue.value;
-                queue_ram << axiport->queue.ram[fifo_enq_$next];
-                output.verbose(CALL_INFO, 1, 0, "\nQueue_value is: %s %" PRIu64, queue_value.str().c_str(), fifo_enq_$next); 
-                output.verbose(CALL_INFO, 1, 0, "\nData enqueued in the queue: %s", queue_ram.str().c_str());
-            }
-            fifo_enq_$old = fifo_enq_$next;
-        }
-    }
-
-    axi_tdata_$old = axi_tdata_$next;
-    axi_tvalid_$old = axi_tvalid_$next;
-    axi_tready_$old = axi_tready_$next;
-
-    uint64_t read_addr = (axiport->queue.ram[fifo_enq_$next].as_single_word());// << 32) | (axiport->queue.ram[fifo_enq_$next+1].as_single_word());
-    uint64_t size = (axiport->queue.ram[fifo_enq_$next+2].as_single_word());// << 32) | (axiport->queue.ram[fifo_enq_$next+3].as_single_word());*/
-
-    //output.verbose(CALL_INFO, 1, 0, "\nSim Done is: %d", ev.sim_done);
-
-    if(!isStalled) {
-        dut->eval(ev.update_registers, ev.verbose, ev.done_reset);
-        tickCount++;
-    }
-	if( tickCount >= sim_cycle) {
-        if(ev.sim_done) {
-            output.verbose(CALL_INFO, 1, 0, "OKToEndSim, TickCount %" PRIu64, tickCount);
-            RtlAckEv->setEndSim(true);
-            ArielRtlLink->send(RtlAckEv);
-            primaryComponentOKToEndSim();  //Tell the SST that it can finish the simulation.
-            return true;
-        }
-    }
-    
-    return false;
-}
-
-
-/*Event Handle will be called by Ariel CPU once it(Ariel CPU) puts the input and control signals in the shared memory. Now, we need to modify Ariel CPU code for that.
-Event handler will update the input and control signal based on the workload/C program to be executed.
-Don't know what should be the argument of Event handle as of now. As, I think we don't need any argument. It's just a requst/call by Ariel CPU to update input and control signals.*/
-void Rtlmodel::handleArielEvent(SST::Event *event) {
-    /*
-    * Event will pick information from shared memory. (What will be the use of Event queue.)
-    * Need to insert code for it. 
-    * Probably void pointers will be used to get the data from the shared memory which will get casted based on the width set by the user at runtime.
-    * void pointers will be defined by Ariel CPU and passed as parameters through SST::Event to the C++ model. 
-    * As of now, shared memory is like a scratch-pad or heap which is passive without any intelligent performance improving stuff like TLB, Cache hierarchy, accessing mechanisms(VIPT/PIPT) etc.  
-    */
-
-    unregisterClock(timeConverter, clock_handler);
-    ArielComponent::ArielRtlEvent* ariel_ev = dynamic_cast<ArielComponent::ArielRtlEvent*>(event);
-    RtlAckEv->setEventRecvAck(true);
-    ArielRtlLink->send(RtlAckEv);
-
-    output.verbose(CALL_INFO, 1, 0, "\nVecshiftReg RTL Event handle called \n");
-
- 
-    memmgr->AssignRtlMemoryManagerSimple(*ariel_ev->RtlData.pageTable, ariel_ev->RtlData.freePages, ariel_ev->RtlData.pageSize);
-    memmgr->AssignRtlMemoryManagerCache(*ariel_ev->RtlData.translationCache, ariel_ev->RtlData.translationCacheEntries, ariel_ev->RtlData.translationEnabled);
-
-    //Update all the virtual address pointers in RTLEvent class
-    updated_rtl_params = ariel_ev->get_updated_rtl_params();
-    inp_ptr = ariel_ev->get_rtl_inp_ptr(); 
-    inp_size = ariel_ev->RtlData.rtl_inp_size;
-    cacheLineSize = ariel_ev->RtlData.cacheLineSize;
-
-    //Creating Read Event from memHierarchy for the above virtual address pointers
-    RtlReadEvent* rtlrev_params = new RtlReadEvent((uint64_t)ariel_ev->get_updated_rtl_params(),(uint32_t)ariel_ev->get_updated_rtl_params_size()); 
-    RtlReadEvent* rtlrev_inp_ptr = new RtlReadEvent((uint64_t)ariel_ev->get_rtl_inp_ptr(),(uint32_t)ariel_ev->get_rtl_inp_size()); 
-    RtlReadEvent* rtlrev_ctrl_ptr = new RtlReadEvent((uint64_t)ariel_ev->get_rtl_ctrl_ptr(),(uint32_t)ariel_ev->get_rtl_ctrl_size()); 
-    output.verbose(CALL_INFO, 1, 0, "\nVirtual address in handleArielEvent is: %" PRIu64, (uint64_t)ariel_ev->get_updated_rtl_params());
-
-    if(!mem_allocated) {
-        size_t size = ariel_ev->get_updated_rtl_params_size() + ariel_ev->get_rtl_inp_size() + ariel_ev->get_rtl_ctrl_size();
-        uint8_t* data = (uint8_t*)malloc(size);
-        VA_VA_map.insert({(uint64_t)ariel_ev->get_updated_rtl_params(), (uint64_t)data});
-        uint64_t index = ariel_ev->get_updated_rtl_params_size()/sizeof(uint8_t);
-        VA_VA_map.insert({(uint64_t)ariel_ev->get_rtl_inp_ptr(), (uint64_t)(data+index)});
-        index += ariel_ev->get_rtl_inp_size()/sizeof(uint8_t);
-        VA_VA_map.insert({(uint64_t)ariel_ev->get_rtl_ctrl_ptr(), (uint64_t)(data+index)});
-        setBaseDataAddress(data);
-        setDataAddress(getBaseDataAddress());
-        mem_allocated = true;
-    }
-
-
-
-    //Initiating the read request from memHierarchy
-    generateReadRequest(rtlrev_params);
-    generateReadRequest(rtlrev_inp_ptr);
-    generateReadRequest(rtlrev_ctrl_ptr);
-    isStalled = true;
-    sendArielEvent();
-}
-
-void Rtlmodel::sendArielEvent() {
-     
-    RtlAckEv = new ArielComponent::ArielRtlEvent();
-    RtlAckEv->RtlData.rtl_inp_ptr = inp_ptr;
-    RtlAckEv->RtlData.rtl_inp_size = inp_size;
-    ArielRtlLink->send(RtlAckEv);
-    return;
-}
-
-
-void Rtlmodel::handleAXISignals(uint8_t tready) {
-    axiport->readerFrontend.done = 0;
-    axiport->readerFrontend.enable = 1;
-    axiport->readerFrontend.length = 64;
-    axiport->io_read_tdata = axi_tdata_$next; 
-    axiport->io_read_tvalid = axi_tvalid_$next; 
-    axiport->io_read_tready = tready; 
-    //axiport->cmd_queue.push('r');
-}
-
-void Rtlmodel::handleMemEvent(StandardMem::Request* event) {
-    StandardMem::ReadResp* read = (StandardMem::ReadResp*)event;
-    output.verbose(CALL_INFO, 4, 0, " handling a memory event in RtlModel.\n");
-    StandardMem::Request::id_t mev_id = read->getID();
-
-    auto find_entry = pendingTransactions->find(mev_id);
-    if(find_entry != pendingTransactions->end()) {
-        output.verbose(CALL_INFO, 4, 0, "Correctly identified event in pending transactions, removing from list, before there are: %" PRIu32 " transactions pending.\n", (uint32_t) pendingTransactions->size());
-       
-        int i;
-        auto DataAddress = VA_VA_map.find(read->vAddr);
-        if(DataAddress != VA_VA_map.end())
-            setDataAddress((uint8_t*)DataAddress->second);
-        else
-            output.fatal(CALL_INFO, -1, "Error: DataAddress corresponding to VA: %" PRIu64, read->vAddr);
-
-        //Actual reading of data from memEvent and storing it to getDataAddress
-        output.verbose(CALL_INFO, 1, 0, "\nAddress is: %" PRIu64, (uint64_t)getDataAddress());
-        for(i = 0; i < read->data.size(); i++)
-            getDataAddress()[i] = read->data[i]; 
-
-        if(read->vAddr == (uint64_t)updated_rtl_params) {
-            bool* ptr = (bool*)getBaseDataAddress();
-            output.verbose(CALL_INFO, 1, 0, "Updated Rtl Params is: %d\n",*ptr);
-        }
-
-        pendingTransactions->erase(find_entry);
-        pending_transaction_count--;
-
-        if(isStalled && pending_transaction_count == 0) {
-            ev.UpdateRtlSignals((void*)getBaseDataAddress(), dut, sim_cycle);
-            tickCount = 0;
-            reregisterClock(timeConverter, clock_handler);
-            setDataAddress(getBaseDataAddress());
-            isStalled = false;
-        }
-    } 
-    
-    else 
-        output.fatal(CALL_INFO, -4, "Memory event response to VecShiftReg was not found in pending list.\n");
-        
-    delete event;
-}
-
-void Rtlmodel::commitReadEvent(const uint64_t address,
-            const uint64_t virtAddress, const uint32_t length) {
-    if(length > 0) {
-        StandardMem::Read *req = new StandardMem::Read(address, length, 0, virtAddress);
-        
-        pending_transaction_count++;
-        pendingTransactions->insert(std::pair<StandardMem::Request::id_t, StandardMem::Request*>(req->getID(), req));
-        //memmgr_transactions->insert(std::pair<StandardMem::Request::id_t, int>(req->getID(), flag));
-
-        // Actually send the event to the cache
-        cacheLink->send(req);
-    }
-}
-
-void Rtlmodel::commitWriteEvent(const uint64_t address,
-        const uint64_t virtAddress, const uint32_t length, const uint8_t* payload) {
-
-    if(length > 0) {
-
-        std::vector<uint8_t> data;
-
-        if( writePayloads ) {
-                data.insert(data.end(), &payload[0], &payload[length]);
-                char* buffer = new char[64];
-                std::string payloadString = "";
-                for(int i = 0; i < length; ++i) {
-                    snprintf(buffer, 64, "0x%X ", payload[i]);
-                    payloadString.append(buffer);
-                }
-
-                delete[] buffer;
-
-                output.verbose(CALL_INFO, 16, 0, "Write-Payload: Len=%" PRIu32 ", Data={ %s } %p\n",
-                        length, payloadString.c_str(), (void*)virtAddress);
-        } else {
-            data.resize(length, 0);
-        }
-        
-        StandardMem::Write *req = new StandardMem::Write(address, length, data, false, 0, virtAddress);
-        pending_transaction_count++;
-        pendingTransactions->insert( std::pair<StandardMem::Request::id_t, StandardMem::Request*>(req->getID(), req) );
-
-        // Actually send the event to the cache
-        cacheLink->send(req);
-    }
-}
-
-void Rtlmodel::generateReadRequest(RtlReadEvent* rEv) {
-
-    const uint64_t readAddress = rEv->getAddress();
-    const uint64_t readLength  = std::min((uint64_t) rEv->getLength(), cacheLineSize); // Trim to cacheline size (occurs rarely for instructions such as xsave and fxsave)
-
-    // NOTE: Physical and virtual addresses may not be aligned the same w.r.t. line size if map-on-malloc is being used (arielinterceptcalls != 0), so use physical offsets to determine line splits
-    // There is a chance that the non-alignment causes an undetected bug if an access spans multiple malloc regions that are contiguous in VA space but non-contiguous in PA space.
-    // However, a single access spanning multiple malloc'd regions shouldn't happen...
-    // Addresses mapped via first touch are always line/page aligned
-    /*if(rEv->physaddr == 0) { 
-        physaddr = memmgr->translateAddress(readAddress);
-    }
-    else 
-        physaddr = memmgr->translateAddress(readAddress);
-
-    const uint64_t physAddr = physaddr;*/
-    const uint64_t physAddr = memmgr->translateAddress(readAddress);
-    const uint64_t addr_offset  = physAddr % ((uint64_t) cacheLineSize);
-
-    if((addr_offset + readLength) <= cacheLineSize) {
-        output.verbose(CALL_INFO, 4, 0, " generating a non-split read request: Addr=%" PRIu64 " Length=%" PRIu64 "\n",
-                            readAddress, readLength);
-
-        // We do not need to perform a split operation
-
-        output.verbose(CALL_INFO, 4, 0, " issuing read, VAddr=%" PRIu64 ", Size=%" PRIu64 ", PhysAddr=%" PRIu64 "\n",
-                            readAddress, readLength, physAddr);
-
-        commitReadEvent(physAddr, readAddress, (uint32_t) readLength);
-    } else {
-        output.verbose(CALL_INFO, 4, 0, " generating a split read request: Addr=%" PRIu64 " Length=%" PRIu64 "\n",
-                            readAddress, readLength);
-
-        // We need to perform a split operation
-        const uint64_t leftAddr = readAddress;
-        const uint64_t leftSize = cacheLineSize - addr_offset;
-
-        const uint64_t rightAddr = (readAddress + ((uint64_t) cacheLineSize)) - addr_offset;
-        const uint64_t rightSize = readLength - leftSize;
-
-        const uint64_t physLeftAddr = physAddr;
-        const uint64_t physRightAddr = memmgr->translateAddress(rightAddr);
-
-        output.verbose(CALL_INFO, 4, 0, " issuing split-address read, LeftVAddr=%" PRIu64 ", RightVAddr=%" PRIu64 ", LeftSize=%" PRIu64 ", RightSize=%" PRIu64 ", LeftPhysAddr=%" PRIu64 ", RightPhysAddr=%" PRIu64 "\n",
-                            leftAddr, rightAddr, leftSize, rightSize, physLeftAddr, physRightAddr);
-
-        if(((physLeftAddr + leftSize) % cacheLineSize) != 0) {
-            output.fatal(CALL_INFO, -4, "Error leftAddr=%" PRIu64 " + size=%" PRIu64 " is not a multiple of cache line size: %" PRIu64 "\n",
-                    leftAddr, leftSize, cacheLineSize);
-        }
-
-        commitReadEvent(physLeftAddr, leftAddr, (uint32_t) leftSize);
-        commitReadEvent(physRightAddr, rightAddr, (uint32_t) rightSize);
-
-        statSplitReadRequests->addData(1);
-    }
-
-    statReadRequests->addData(1);
-    statReadRequestSizes->addData(readLength);
-    delete rEv;
-}
-
-void Rtlmodel::generateWriteRequest(RtlWriteEvent* wEv) {
-
-    const uint64_t writeAddress = wEv->getAddress();
-    const uint64_t writeLength  = std::min((uint64_t) wEv->getLength(), cacheLineSize); // Trim to cacheline size (occurs rarely for instructions such as xsave and fxsave)
-
-    // See note in handleReadRequest() on alignment issues
-    const uint64_t physAddr = memmgr->translateAddress(writeAddress);
-    const uint64_t addr_offset  = physAddr % ((uint64_t) cacheLineSize);
-
-    // We do not need to perform a split operation
-    if((addr_offset + writeLength) <= cacheLineSize) {
-        
-        output.verbose(CALL_INFO, 4, 0, " generating a non-split write request: Addr=%" PRIu64 " Length=%" PRIu64 "\n",
-                            writeAddress, writeLength);
-
-
-        output.verbose(CALL_INFO, 4, 0, " issuing write, VAddr=%" PRIu64 ", Size=%" PRIu64 ", PhysAddr=%" PRIu64 "\n",
-                            writeAddress, writeLength, physAddr);
-
-        if(writePayloads) {
-            uint8_t* payloadPtr = wEv->getPayload();
-            commitWriteEvent(physAddr, writeAddress, (uint32_t) writeLength, payloadPtr);
-        } else {
-            commitWriteEvent(physAddr, writeAddress, (uint32_t) writeLength, NULL);
-        }
-    } else {
-        output.verbose(CALL_INFO, 4, 0, " generating a split write request: Addr=%" PRIu64 " Length=%" PRIu64 "\n",
-                            writeAddress, writeLength);
-
-        // We need to perform a split operation
-        const uint64_t leftAddr = writeAddress;
-        const uint64_t leftSize = cacheLineSize - addr_offset;
-
-        const uint64_t rightAddr = (writeAddress + ((uint64_t) cacheLineSize)) - addr_offset;
-        const uint64_t rightSize = writeLength - leftSize;
-
-        const uint64_t physLeftAddr = physAddr;
-        const uint64_t physRightAddr = memmgr->translateAddress(rightAddr);
-
-        output.verbose(CALL_INFO, 4, 0, " issuing split-address write, LeftVAddr=%" PRIu64 ", RightVAddr=%" PRIu64 ", LeftSize=%" PRIu64 ", RightSize=%" PRIu64 ", LeftPhysAddr=%" PRIu64 ", RightPhysAddr=%" PRIu64 "\n",
-                            leftAddr, rightAddr, leftSize, rightSize, physLeftAddr, physRightAddr);
-
-        if(((physLeftAddr + leftSize) % cacheLineSize) != 0) {
-            output.fatal(CALL_INFO, -4, "Error leftAddr=%" PRIu64 " + size=%" PRIu64 " is not a multiple of cache line size: %" PRIu64 "\n",
-                            leftAddr, leftSize, cacheLineSize);
-        }
-
-        if(writePayloads) {
-            uint8_t* payloadPtr = wEv->getPayload();
-            commitWriteEvent(physLeftAddr, leftAddr, (uint32_t) leftSize, payloadPtr);
-            commitWriteEvent(physRightAddr, rightAddr, (uint32_t) rightSize, &payloadPtr[leftSize]);
-        } else {
-            commitWriteEvent(physLeftAddr, leftAddr, (uint32_t) leftSize, NULL);
-            commitWriteEvent(physRightAddr, rightAddr, (uint32_t) rightSize, NULL);
-        }
-        statSplitWriteRequests->addData(1);
-    }
-
-    statWriteRequests->addData(1);
-    statWriteRequestSizes->addData(writeLength);
-    delete wEv;
-}
-
-uint8_t* Rtlmodel::getDataAddress() {
-    return dataAddress;
-}
-
-uint64_t* Rtlmodel::getAXIDataAddress() {
-    return AXIdataAddress;
-}
-
-
-void Rtlmodel::setDataAddress(uint8_t* virtAddress){
-    dataAddress = virtAddress;
-}
-
-uint8_t* Rtlmodel::getBaseDataAddress(){
-    return baseDataAddress;
-}
-
-void Rtlmodel::setBaseDataAddress(uint8_t* virtAddress){
-    baseDataAddress = virtAddress;
-}
diff --git a/src/sst/elements/osseous/rtlcomponent.h b/src/sst/elements/osseous/rtlcomponent.h
deleted file mode 100644
index e82547d468..0000000000
--- a/src/sst/elements/osseous/rtlcomponent.h
+++ /dev/null
@@ -1,166 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#ifndef _SIMPLE_VECTORSHIFTREG_H
-#define _SIMPLE_VECTORSHIFTREG_H
-
-#include <sst/core/component.h>
-#include <sst/core/interfaces/stdMem.h>
-#include <sst/core/timeConverter.h>
-#include <queue>
-
-//Header file will be changed to the RTL C-model under test
-#include "rtl_header.h"
-#include <sst/core/link.h>
-#include <sst/core/clock.h>
-#include <sst/core/eli/elementinfo.h>
-#include "rtlevent.h"
-#include "arielrtlev.h"
-#include "rtlreadev.h"
-#include "rtlwriteev.h"
-#include "rtlmemmgr.h"
-
-#undef UNLIKELY
-#include "AXI_port.h"
-
-namespace SST {
-    namespace RtlComponent {
-
-class Rtlmodel : public SST::Component {
-
-public:
-	Rtlmodel( SST::ComponentId_t id, SST::Params& params );
-    ~Rtlmodel();
-
-	void setup();
-	void init(unsigned);
-	void finish();
-
-	bool clockTick( SST::Cycle_t currentCycle );
-
-	SST_ELI_REGISTER_COMPONENT(
-		Rtlmodel,
-		"rtlcomponent",
-		"Rtlmodel",
-		SST_ELI_ELEMENT_VERSION( 1, 0, 0 ),
-		"Demonstration of an External Element for SST",
-		COMPONENT_CATEGORY_PROCESSOR
-	)
-    //Stats needs to be added. Now, stats will be added based on the outputs as mentioned by the user based on the RTL login provided. 
-    SST_ELI_DOCUMENT_STATISTICS(
-        { "read_requests",        "Statistic counts number of read requests", "requests", 1},   // Name, Desc, Enable Level
-        { "write_requests",       "Statistic counts number of write requests", "requests", 1},
-        { "read_request_sizes",   "Statistic for size of read requests", "bytes", 1},   // Name, Desc, Enable Level
-        { "write_request_sizes",  "Statistic for size of write requests", "bytes", 1},
-        { "split_read_requests",  "Statistic counts number of split read requests (requests which come from multiple lines)", "requests", 1},
-        { "split_write_requests", "Statistic counts number of split write requests (requests which are split over multiple lines)", "requests", 1},
-	    { "flush_requests",       "Statistic counts instructions which perform flushes", "requests", 1},
-        { "fence_requests",       "Statistic counts instructions which perform fences", "requests", 1}
-    )
-    //Parameters will mostly be just frequency/clock in the design. User will mention specifically if there could be other parameters for the RTL design which needs to be configured before runtime.  Don't mix RTL input/control signals with SST parameters. SST parameters of RTL design will make the RTL design/C++ model synchronous with rest of the SST full system.   
-	SST_ELI_DOCUMENT_PARAMS(
-		{ "ExecFreq", "Clock frequency of RTL design in GHz", "1GHz" },
-		{ "maxCycles", "Number of Clock ticks the simulation must atleast execute before halting", "1000" },
-        {"memoryinterface", "Interface to memory", "memHierarchy.standardInterface"}
-	)
-
-    //Default will be single port for communicating with Ariel CPU. Need to see the requirement/use-case of multi-port design and how to incorporate it in our parser tool.  
-    SST_ELI_DOCUMENT_PORTS(
-        {"ArielRtllink", "Link to the Rtlmodel", { "Rtlmodel.RTLEvent", "" } },
-        {"RtlCacheLink", "Link to Cache", {"memHierarchy.memInterface" , ""} }
-    )
-    
-    SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS(
-            {"memmgr", "Memory manager to translate virtual addresses to physical, handle malloc/free, etc.", "SST::RtlComponent::RtlMemoryManager"},
-            {"memory", "Interface to the memoryHierarchy (e.g., caches)", "SST::Interfaces::StandardMem" }
-    )
-
-    void generateReadRequest(RtlReadEvent* rEv);
-    void generateWriteRequest(RtlWriteEvent* wEv);
-    void setDataAddress(uint8_t*);
-    uint8_t* getDataAddress();
-    void setBaseDataAddress(uint8_t*);
-    uint8_t* getBaseDataAddress();
-
-private:
-	SST::Output output;
-    
-    //RTL Clock frequency of execution and maximum Cycles/clockTicks for which RTL simulation will run.
-    std::string RTLClk;
-	SST::Cycle_t maxCycles;
-
-    //SST Links
-    SST::Link* ArielRtlLink;
-    Interfaces::StandardMem* cacheLink;
-
-    void handleArielEvent(SST::Event *ev);
-    void handleMemEvent(Interfaces::StandardMem::Request* event);
-    void handleAXISignals(uint8_t);
-    void commitReadEvent(const uint64_t address, const uint64_t virtAddr, const uint32_t length);
-    void commitWriteEvent(const uint64_t address, const uint64_t virtAddr, const uint32_t length, const uint8_t* payload);
-    void sendArielEvent();
-    uint64_t* getAXIDataAddress();
-    
-    TimeConverter* timeConverter;
-    Clock::HandlerBase* clock_handler;
-    bool writePayloads;
-    bool update_registers, verbose, done_reset, sim_done;
-    bool update_inp, update_ctrl, update_eval_args;
-    RTLEvent ev;
-    Rtlheader *dut;
-    AXITop *axiport;
-    ArielComponent::ArielRtlEvent* RtlAckEv;
-    uint64_t inp_VA, ctrl_VA, updated_rtl_params_VA, inp_PA, ctrl_PA, updated_rtl_params_PA;
-    size_t inp_size, ctrl_size, updated_rtl_params_size;
-    std::queue<char> cmd_queue;
-    void* inp_ptr = nullptr;
-    void* updated_rtl_params = nullptr;
-    RtlMemoryManager* memmgr;
-    bool mem_allocated = false;
-    uint64_t sim_cycle;
-
-    //AXI Handler signals
-    uint64_t axi_tdata_$old = 0, axi_tdata_$next = 0;
-    uint8_t axi_tvalid_$old = 0, axi_tvalid_$next = 0;
-    uint8_t axi_tready_$old = 0, axi_tready_$next = 0;
-    uint64_t axi_fifo_enq_$old = 0, axi_fifo_enq_$next = 0;
-    uint64_t fifo_enq_$old = 0, fifo_enq_$next = 0;
-    uint64_t fifo_deq_$old = 0, fifo_deq_$next = 0;
-
-    std::unordered_map<Interfaces::StandardMem::Request::id_t, Interfaces::StandardMem::Request*>* pendingTransactions;
-    std::unordered_map<uint64_t, uint64_t> VA_VA_map;
-    uint32_t pending_transaction_count;
-
-    bool isStalled;
-    uint64_t cacheLineSize;
-    uint8_t *dataAddress, *baseDataAddress;
-    uint64_t *AXIdataAddress; 
-    
-    Statistic<uint64_t>* statReadRequests;
-    Statistic<uint64_t>* statWriteRequests;
-    Statistic<uint64_t>* statFlushRequests;
-    Statistic<uint64_t>* statFenceRequests;
-    Statistic<uint64_t>* statReadRequestSizes;
-    Statistic<uint64_t>* statWriteRequestSizes;
-    Statistic<uint64_t>* statSplitReadRequests;
-    Statistic<uint64_t>* statSplitWriteRequests;
-
-    uint64_t tickCount;
-    uint64_t dynCycles; 
-};
-
- } //namespace RtlComponent 
-} //namespace SST
-#endif //_SIMPLE_VECTORSHIFTREG_H
diff --git a/src/sst/elements/osseous/rtlevent.cc b/src/sst/elements/osseous/rtlevent.cc
deleted file mode 100644
index 193caba02c..0000000000
--- a/src/sst/elements/osseous/rtlevent.cc
+++ /dev/null
@@ -1,92 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#include <sst_config.h>
-
-#include "uint.h"
-#include "sint.h"
-#include "rtl_header.h"
-#include "rtlevent.h"
-
-using namespace SST;
-using namespace SST::RtlComponent;
-
-void RTLEvent::UpdateRtlSignals(void *update_data, Rtlheader* cmodel, uint64_t& cycles) {
-    bool* update_rtl_params = (bool*)update_data; 
-    update_inp = update_rtl_params[0];
-    update_ctrl = update_rtl_params[1];
-    update_eval_args = update_rtl_params[2];
-    update_registers = update_rtl_params[3];
-    verbose = update_rtl_params[4];
-    done_reset = update_rtl_params[5];
-    sim_done = update_rtl_params[6];
-    uint64_t* cycles_ptr = (uint64_t*)(&update_rtl_params[7]);
-    sim_cycles = *cycles_ptr;
-    cycles = sim_cycles;
-    cycles_ptr++;
-
-    output.verbose(CALL_INFO, 1, 0, "sim_cycles: %" PRIu64 "\n", sim_cycles);
-    output.verbose(CALL_INFO, 1, 0, "update_inp: %d\n", update_inp);
-    output.verbose(CALL_INFO, 1, 0, "update_ctrl: %d\n", update_ctrl);
-    if(update_inp) {
-        inp_ptr =  (void*)cycles_ptr; 
-        input_sigs(cmodel);
-    }
-
-    if(update_ctrl) {
-        UInt<4>* rtl_inp_ptr = (UInt<4>*)inp_ptr;
-        ctrl_ptr = (void*)(&rtl_inp_ptr[5]);
-        control_sigs(cmodel);
-    }
-}
-
-void RTLEvent::input_sigs(Rtlheader* cmodel) {
-
-    cmodel->reset = UInt<1>(1);
-    //Cast all the variables to 4 byte UInt types for uniform storage for now. Later, we either will remove UInt and SInt and use native types. Even then we would need to cast the every variables based on type, width and order while storing in shmem and accordingly access it at runtime from shmem.   
-    UInt<4>* rtl_inp_ptr = (UInt<4>*)inp_ptr;
-    cmodel->io_ins_0 = rtl_inp_ptr[0];
-    cmodel->io_ins_1 = rtl_inp_ptr[1];
-    cmodel->io_ins_2 = rtl_inp_ptr[2];
-    cmodel->io_ins_3 = rtl_inp_ptr[3];
-    cmodel->reset = UInt<1>(0);
-    stringstream io_ins_0, io_ins_1, io_ins_2, io_ins_3;
-    io_ins_0 << cmodel->io_ins_0;
-    io_ins_1 << cmodel->io_ins_1;
-    io_ins_2 << cmodel->io_ins_2;
-    io_ins_3 << cmodel->io_ins_3;
-    output.verbose(CALL_INFO, 1, 0, "input_sigs: %s", io_ins_0.str().c_str());
-    output.verbose(CALL_INFO, 1, 0, "input_sigs: %s", io_ins_1.str().c_str());
-    output.verbose(CALL_INFO, 1, 0, "input_sigs: %s", io_ins_2.str().c_str());
-    output.verbose(CALL_INFO, 1, 0, "input_sigs: %s", io_ins_3.str().c_str());
-    return;
-}
-
-void RTLEvent::control_sigs(Rtlheader* cmodel) {
-
-    output.verbose(CALL_INFO, 1, 0, "\nctrl_sigs called"); 
-    cmodel->reset = UInt<1>(1);
-    UInt<1>* rtl_ctrl_ptr = (UInt<1>*)ctrl_ptr;
-    cmodel->io_shift = rtl_ctrl_ptr[0];
-    cmodel->io_load = rtl_ctrl_ptr[1];
-    cmodel->reset = UInt<1>(0);
-    stringstream io_shift, io_load;
-    io_shift << cmodel->io_shift;
-    io_load << cmodel->io_load;
-    output.verbose(CALL_INFO, 1, 0, "ctrl_sigs: %s", io_shift.str().c_str());
-    output.verbose(CALL_INFO, 1, 0, "ctrl_sigs: %s", io_load.str().c_str());
-    return;
-}
-
diff --git a/src/sst/elements/osseous/rtlevent.h b/src/sst/elements/osseous/rtlevent.h
deleted file mode 100644
index a74d2d1d9c..0000000000
--- a/src/sst/elements/osseous/rtlevent.h
+++ /dev/null
@@ -1,66 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#ifndef _RTLEVENT_H
-#define _RTLEVENT_H
-
-#include "uint.h"
-#include "rtl_header.h"
-#include <string>
-#include <sst/core/event.h>
-using namespace SST;
-using namespace std;
-
-namespace SST {
-    namespace RtlComponent { 
-
-class RTLEvent : public SST::Event {
-public:
-
-    bool update_inp, update_ctrl, update_registers, verbose, done_reset,
-         update_eval_args, sim_done;
-    uint64_t sim_cycles;
-    RTLEvent() : SST::Event() {
-        //output.init("RtlEvent-" + getName() + "-> ", 1, 0, SST::Output::STDOUT); 
-        output.init("Rtlmodel->", 1, 0, SST::Output::STDOUT);
-    }
-
-    void input_sigs(Rtlheader*);
-    void control_sigs(Rtlheader*);
-    void UpdateRtlSignals(void*, Rtlheader*, uint64_t&);
-    void *inp_ptr, *ctrl_ptr;
-
-    void serialize_order(SST::Core::Serialization::serializer &ser)  override {
-        SST::Event::serialize_order(ser);
-        ser & update_inp;
-        ser & update_ctrl;
-        ser & update_registers;
-        ser & verbose;
-        ser & done_reset;
-        ser & update_eval_args;
-        ser & sim_done;
-    }
-
-    ImplementSerializable(SST::RtlComponent::RTLEvent);
-private:
-    SST::Output output;
-
-
-};
-
-} //namespace RtlComponent
-} //namespace SST
-
-#endif /* _RTLEVENT_H */
diff --git a/src/sst/elements/osseous/rtlmemmgr.h b/src/sst/elements/osseous/rtlmemmgr.h
deleted file mode 100644
index 4c6782371c..0000000000
--- a/src/sst/elements/osseous/rtlmemmgr.h
+++ /dev/null
@@ -1,92 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-
-#ifndef _H_RTL_MEM_MANAGER
-#define _H_RTL_MEM_MANAGER
-
-#include <sst/core/subcomponent.h>
-#include <sst/core/output.h>
-
-#include <stdint.h>
-#include <vector>
-#include <unordered_map>
-#include <deque>
-
-namespace SST {
-
-namespace RtlComponent {
-
-class RtlMemoryManager : public SubComponent {
-
-    public:
-        SST_ELI_REGISTER_SUBCOMPONENT_API(SST::RtlComponent::RtlMemoryManager)
-
-        RtlMemoryManager(ComponentId_t id, Params& params) : SubComponent(id) {
-            int verbosity = params.find<int>("verbose", 0);
-            output = new SST::Output("RtlMemoryManager[@f:@l:@p] ",
-                verbosity, 0, SST::Output::STDOUT);
-        }
-
-
-        ~RtlMemoryManager() {};
-
-        /** Set default memory pool for allocation */
-        virtual void setDefaultPool(uint32_t pool) {
-        }
-
-        virtual uint32_t getDefaultPool() {
-            return 0;
-        }
-
-        virtual void AssignRtlMemoryManagerSimple(std::unordered_map<uint64_t, uint64_t>, std::deque<uint64_t>*, uint64_t) { }
-
-        virtual void AssignRtlMemoryManagerCache(std::unordered_map<uint64_t, uint64_t>, uint32_t, bool) { }
-
-        /** Return the physical address for the request virtual address */
-        virtual uint64_t translateAddress(uint64_t virtAddr) = 0;
-
-        /** Request to allocate a malloc, not supported by all memory managers */
-        virtual bool allocateMalloc(const uint64_t size, const uint32_t level, const uint64_t virtualAddress, const uint64_t instructionPointer, const uint32_t thread) {
-            output->verbose(CALL_INFO, 0, 0, "The instantiated RtlMemoryManager does not support malloc handling.\n");
-            //fprintf(stderr, "\nAllocateMalloc is not supported\n");
-            return false;
-        }
-
-        /** Request to free a malloc, not supported by all memory managers */
-        virtual void freeMalloc(const uint64_t vAddr) {
-            output->verbose(CALL_INFO, 4, 0, "The instantiated RtlMemoryManager does not support malloc handling.\n");
-        }
-
-        virtual bool allocateMMAP(const uint64_t size, const uint32_t level, const uint64_t virtualAddress, const uint64_t instructionPointer, const uint32_t file, const uint32_t thread) {
-            output->verbose(CALL_INFO, 4, 0, "The instantiated RtlMemoryManager does nto support MMAP handling.\n");
-            return false;
-        }
-
-        virtual void freeMMAP(const uint32_t file) {
-            output->verbose(CALL_INFO, 4, 0, "The instantiated RtlMemoryManager does not support MMAP handling.\n");
-        }
-
-        /** Print statistics: TODO move statistics to Statistics API */
-        virtual void printStats() {};
-
-    protected:
-        Output* output;
-};
-
-}
-}
-
-#endif
diff --git a/src/sst/elements/osseous/rtlmemmgr_cache.h b/src/sst/elements/osseous/rtlmemmgr_cache.h
deleted file mode 100644
index 620634aa6b..0000000000
--- a/src/sst/elements/osseous/rtlmemmgr_cache.h
+++ /dev/null
@@ -1,107 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-
-#ifndef _H_RTL_MEM_MANAGER_CACHE
-#define _H_RTL_MEM_MANAGER_CACHE
-
-#include <sst/core/output.h>
-#include <sst/core/rng/marsaglia.h>
-
-#include <stdint.h>
-//#include <deque>
-#include <vector>
-#include <inttypes.h>
-//#include <unordered_map>
-
-#include "rtlmemmgr.h"
-
-namespace SST {
-
-namespace RtlComponent {
-
-/* Base class for memory managers that cache translation addresses */
-class RtlMemoryManagerCache : public RtlMemoryManager{
-
-    public:
-
-        /* ELI defines for RtlMemoryManagerCache subcomponents */
-    #define RTL_ELI_MEMMGR_CACHE_STATS { "tlb_hits", "Hits in the simple Rtl TLB", "hits", 2 },\
-        { "tlb_evicts",           "Number of evictions in the simple Rtl TLB", "evictions", 2 },\
-        { "tlb_translate_queries","Number of TLB translations performed", "translations", 2 },\
-        { "tlb_shootdown",        "Number of TLB clears because of page-frees", "shootdowns", 2 },\
-        { "tlb_page_allocs",      "Number of pages allocated by the memory manager", "pages", 2 }
-
-        /* Constructor
-            *  Supports multiple memory pools with independent page sizes/counts
-            *  Constructs free page sets for each memory pool
-            *  Initializes a translation cache
-            */
-        RtlMemoryManagerCache(ComponentId_t id, Params& params) : RtlMemoryManager(id, params) {
-            translationEnabled = params.find<bool>("vtop_translate", true);
-
-            /* Common statistics */
-            statTranslationCacheHits    = registerStatistic<uint64_t>("tlb_hits");
-            statTranslationCacheEvict   = registerStatistic<uint64_t>("tlb_evicts");
-            statTranslationQueries      = registerStatistic<uint64_t>("tlb_translate_queries");
-            statTranslationShootdown    = registerStatistic<uint64_t>("tlb_shootdown");
-            statPageAllocationCount     = registerStatistic<uint64_t>("tlb_page_allocs");
-
-            /* Statistics used by all memory managers; managers may also have their own */
-        } // End constructor
-
-        ~RtlMemoryManagerCache() {};
-
-        void AssignRtlMemoryManagerCache(std::unordered_map<uint64_t, uint64_t> Cache, uint32_t CacheEntries, bool Enabled) {
-            
-            // Set up translation cache
-            translationCache = Cache;
-            translationCacheEntries = CacheEntries;
-            translationEnabled = Enabled;
-            /*fprintf(stderr, "\ntranslationCache size in RtlMemorymanager is: %" PRIu64, translationCache.size());
-            fprintf(stderr, "\ntranslationCacheEntries in RtlMemorymanager is: %" PRIu32, translationCacheEntries);
-            fprintf(stderr, "\ntranslationEnabled in RtlMemorymanager is: %d", translationEnabled);*/
-
-            return;
-        }
-
-    protected:
-        Statistic<uint64_t>* statTranslationCacheHits;
-        Statistic<uint64_t>* statTranslationCacheEvict;
-        Statistic<uint64_t>* statTranslationQueries;
-        Statistic<uint64_t>* statTranslationShootdown;
-        Statistic<uint64_t>* statPageAllocationCount;
-
-        std::unordered_map<uint64_t, uint64_t> translationCache;
-        uint32_t translationCacheEntries;
-        bool translationEnabled;
-
-        void cacheTranslation(uint64_t virtualA, uint64_t physicalA) {
-            // Remove the oldest entry if we do not have enough slots TODO is begin() really the oldest...?
-            if(translationCache.size() == translationCacheEntries) {
-            statTranslationCacheEvict->addData(1);
-            translationCache.erase(translationCache.begin());
-            }
-
-            // Insert the translated entry into the cache
-            translationCache.insert(std::pair<uint64_t, uint64_t>(virtualA, physicalA));
-        }
-
-};
-
-}
-}
-
-#endif
diff --git a/src/sst/elements/osseous/rtlmemmgr_simple.cc b/src/sst/elements/osseous/rtlmemmgr_simple.cc
deleted file mode 100644
index e3c3b9ce2c..0000000000
--- a/src/sst/elements/osseous/rtlmemmgr_simple.cc
+++ /dev/null
@@ -1,167 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#include <sst_config.h>
-#include <inttypes.h>
-#include <stdio.h>
-
-#include "rtlmemmgr_simple.h"
-
-using namespace SST::RtlComponent;
-
-RtlMemoryManagerSimple::RtlMemoryManagerSimple(ComponentId_t id, Params& params) :
-            RtlMemoryManagerCache(id, params) { }
-
-RtlMemoryManagerSimple::~RtlMemoryManagerSimple() { /*free((void*)(&freePages));*/ }
-
-void RtlMemoryManagerSimple::AssignRtlMemoryManagerSimple(std::unordered_map<uint64_t, uint64_t> pagetable, std::deque<uint64_t>* freepages, uint64_t pagesize) {
-    pageTable = pagetable; 
-    freePages = freepages;
-    pageSize = pagesize;
-    return; 
-}
-
-void RtlMemoryManagerSimple::allocate(const uint64_t size, const uint32_t level, const uint64_t virtualAddress) {
-        // Simple manager ignores 'level' parameter
-
-    output->verbose(CALL_INFO, 4, 0, "Requesting a memory allocation of %" PRIu64 " bytes, Virtual mapping=%" PRIu64 "\n",
-        size, virtualAddress);
-    statPageAllocationCount->addData(1);
-
-    uint64_t roundedSize = size;
-    uint64_t remainder = size % pageSize;
-
-    // We will do all of our allocated based on whole pages, inefficient maybe but much
-    // simpler to implement and debug
-    if (remainder > 0) {
-        roundedSize += (pageSize - remainder);
-    }
-
-    output->verbose(CALL_INFO, 4, 0, "Requesting rounded to %" PRIu64 " bytes\n", roundedSize);
-
-    uint64_t nextVirtPage = virtualAddress;
-    for(uint64_t bytesLeft = 0; bytesLeft < roundedSize; bytesLeft += pageSize) {
-        if(freePages->empty()) {
-                output->fatal(CALL_INFO, -1, "Requested a memory allocation of size: %" PRIu64 " which failed due to not having enough free pages\n",
-                    size);
-        }
-
-        output->verbose(CALL_INFO, 1, 0, "\nAllocation, Popping freepages");
-        const uint64_t nextPhysPage = freePages->front();
-        freePages->pop_front();
-
-        pageTable.insert( std::pair<uint64_t, uint64_t>(nextVirtPage, nextPhysPage) );
-
-        output->verbose(CALL_INFO, 4, 0, "Allocating memory page, physical page=%" PRIu64 ", virtual page=%" PRIu64 "\n",
-                nextPhysPage, nextVirtPage);
-
-        nextVirtPage += pageSize;
-    }
-
-    output->verbose(CALL_INFO, 4, 0, "Request leaves: %" PRIu32 " free pages\n",
-        (uint32_t) freePages->size());
-
-}
-
-uint64_t RtlMemoryManagerSimple::translateAddress(uint64_t virtAddr) {
-    // If translation is disabled, then just return address
-    if( ! translationEnabled ) {
-        return virtAddr;
-    }
-
-    if( output->getVerboseLevel() > 15 ) {
-	printTable();
-    }
-
-    // Keep track of how many translations we are performing
-    statTranslationQueries->addData(1);
-
-    output->verbose(CALL_INFO, 4, 0, "Page Table: translate virtual address %" PRIu64 "\n", virtAddr);
-
-    // Check the translation cache otherwise carry on
-    auto checkCache = translationCache.find(virtAddr);
-    if(checkCache != translationCache.end()) {
-        statTranslationCacheHits->addData(1);
-        output->verbose(CALL_INFO, 1, 0, "\nCacheTranslation successful");
-        return checkCache->second;
-    }
-
-    std::unordered_map<uint64_t, uint64_t>::iterator page_itr;
-    const uint64_t page_offset = virtAddr % pageSize;
-    const uint64_t page_start = virtAddr - page_offset;
-
-    page_itr = pageTable.find(page_start);
-
-    if(page_itr != pageTable.end()) {
-        // Located
-        uint64_t physAddr = page_itr->second + page_offset;
-
-        output->verbose(CALL_INFO, 4, 0, "Page table hit: virtual address=%" PRIu64 " hit, virtual page start=%" PRIu64 ", virtual end=%" PRIu64 ", translates to phys page start=%" PRIu64 " translates to: phys address: %" PRIu64 " (offset added to phys start=%" PRIu64 ")\n",
-                virtAddr, page_itr->first, page_itr->first + pageSize, page_itr->second, physAddr, page_offset);
-
-        output->verbose(CALL_INFO, 1, 0, "\nPage table hit successful");
-        cacheTranslation(virtAddr, physAddr);
-        return physAddr;
-
-    } else {
-        output->verbose(CALL_INFO, 4, 0, "Page table miss for virtual address: %" PRIu64 "\n", virtAddr);
-
-        // We did not find the address in memory, that means we should allocate it one from our default pool
-        uint64_t offset = virtAddr % pageSize;
-
-        output->verbose(CALL_INFO, 4, 0, "Page offset calculation (generating a new page allocation request) for address %" PRIu64 ", offset=%" PRIu64 ", requesting virtual map to address: %" PRIu64 "\n",
-                virtAddr, offset, (virtAddr - offset));
-
-        output->verbose(CALL_INFO, 1, 0, "\nPage table miss. Allocation");
-        // Perform an allocation so we can then re-find the address
-        allocate(8, 0, virtAddr - offset);
-
-        // Now attempt to refind it
-        const uint64_t newPhysAddr = translateAddress(virtAddr);
-
-        output->verbose(CALL_INFO, 4, 0, "Page allocation routine mapped to address: %" PRIu64 "\n", newPhysAddr );
-
-        return newPhysAddr;
-    }
-}
-
-void RtlMemoryManagerSimple::printStats() {
-    output->output("\n");
-    output->output("Rtl Memory Management Statistics:\n");
-    output->output("---------------------------------------------------------------------\n");
-    output->output("Page Table Sizes:\n");
-
-    output->output("- Map entries         %" PRIu32 "\n",
-        (uint32_t) pageTable.size());
-
-    output->output("Page Table Coverages:\n");
-
-    output->output("- Bytes               %" PRIu64 "\n",
-        ((uint64_t) pageTable.size()) * ((uint64_t) pageSize));
-}
-
-void RtlMemoryManagerSimple::printTable() {
-
-    	output->output("---------------------------------------------------------------------\n");
-	output->verbose(CALL_INFO, 16, 0, "Page Table Map:\n");
-
-	for( auto table_itr : pageTable ) {
-		output->verbose(CALL_INFO, 16, 0, "-> VA: %15" PRIu64 " -> PA: %15" PRIu64 "\n",
-			table_itr.first, table_itr.second);
-	}
-
-    	output->output("---------------------------------------------------------------------\n");
-
-}
diff --git a/src/sst/elements/osseous/rtlmemmgr_simple.h b/src/sst/elements/osseous/rtlmemmgr_simple.h
deleted file mode 100644
index 27725c01de..0000000000
--- a/src/sst/elements/osseous/rtlmemmgr_simple.h
+++ /dev/null
@@ -1,68 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-
-#ifndef _H_RTL_MEM_MANAGER_SIMPLE
-#define _H_RTL_MEM_MANAGER_SIMPLE
-
-#include <sst/core/output.h>
-
-#include <stdint.h>
-#include <deque>
-#include <vector>
-#include <unordered_map>
-
-#include "rtlmemmgr_cache.h"
-
-namespace SST {
-namespace RtlComponent {
-
-class RtlMemoryManagerSimple : public RtlMemoryManagerCache {
-
-    public:
-        /* SST ELI */
-        SST_ELI_REGISTER_SUBCOMPONENT(
-            RtlMemoryManagerSimple,
-            "rtl",
-            "MemoryManagerSimple",
-            SST_ELI_ELEMENT_VERSION(1,0,0),
-            "Simple allocate-on-first touch memory manager",
-            SST::RtlComponent::RtlMemoryManager
-        )
-
-        SST_ELI_DOCUMENT_STATISTICS( RTL_ELI_MEMMGR_CACHE_STATS )
-
-        /* RtlMemoryManagerSimple */
-        RtlMemoryManagerSimple(ComponentId_t id, Params& params);
-        ~RtlMemoryManagerSimple();
-
-        uint64_t translateAddress(uint64_t virtAddr);
-        void printStats();
-        void AssignRtlMemoryManagerSimple(std::unordered_map<uint64_t, uint64_t>, std::deque<uint64_t>*, uint64_t);
-
-    private:
-        void allocate(const uint64_t size, const uint32_t level, const uint64_t virtualAddress);
-	void printTable();
-
-        uint64_t pageSize;
-        std::deque<uint64_t>* freePages;
-
-        std::unordered_map<uint64_t, uint64_t> pageTable;
-};
-
-}
-}
-
-#endif
diff --git a/src/sst/elements/osseous/rtlreadev.h b/src/sst/elements/osseous/rtlreadev.h
deleted file mode 100644
index 9f068678af..0000000000
--- a/src/sst/elements/osseous/rtlreadev.h
+++ /dev/null
@@ -1,52 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-
-#include <inttypes.h>
-
-#ifndef _H_SST_OSSEOUS_READ_EVENT
-#define _H_SST_OSSEOUS_READ_EVENT
-
-namespace SST {
-namespace RtlComponent {
-
-class RtlReadEvent {
-
-    public:
-        RtlReadEvent(uint64_t rAddr, uint32_t length) :
-                readAddress(rAddr), readLength(length) {
-        }
-
-        ~RtlReadEvent() {
-        }
-
-        uint64_t getAddress() const {
-                return readAddress;
-        }
-
-        uint32_t getLength() const {
-                return readLength;
-        }
-
-    private:
-        const uint64_t readAddress;
-        const uint32_t readLength;
-
-};
-
-}
-}
-
-#endif
diff --git a/src/sst/elements/osseous/rtlwriteev.h b/src/sst/elements/osseous/rtlwriteev.h
deleted file mode 100644
index bd6b7142da..0000000000
--- a/src/sst/elements/osseous/rtlwriteev.h
+++ /dev/null
@@ -1,64 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-
-#ifndef _H_SST_OSSEOUS_WRITE_EVENT
-#define _H_SST_OSSEOUS_WRITE_EVENT
-
-#include <inttypes.h>
-
-namespace SST {
-namespace RtlComponent {
-
-class RtlWriteEvent {
-
-    public:
-        RtlWriteEvent(uint64_t wAddr, uint32_t length, const uint8_t* payloadData) :
-                writeAddress(wAddr), writeLength(length) {
-
-                payload = new uint8_t[length];
-
-                for( int i = 0; i < length; ++i ) {
-                	payload[i] = payloadData[i];
-                }
-        }
-
-        ~RtlWriteEvent() {
-        	delete[] payload;
-        }
-
-        uint64_t getAddress() const {
-                return writeAddress;
-        }
-
-        uint32_t getLength() const {
-                return writeLength;
-        }
-
-        uint8_t* getPayload() const {
-        		return payload;
-        }
-
-    private:
-        const uint64_t writeAddress;
-        const uint32_t writeLength;
-              uint8_t* payload;
-
-};
-
-}
-}
-
-#endif
diff --git a/src/sst/elements/osseous/tests/Makefile b/src/sst/elements/osseous/tests/Makefile
deleted file mode 100644
index 1c2816fa5a..0000000000
--- a/src/sst/elements/osseous/tests/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-CXX=g++
-APIDIR=./
-INCLUDE=./../eras_datatypes/
-
-testbench: testbench.o
-	$(CXX) -O3 -o testbench testbench.o -I$(INCLUDE) -L$(APIDIR) -Wl,-rpath=$(APIDIR) -ltb_header 
-
-testbench.o: testbench.c
-	$(CXX) -O3 -I$(APIDIR) -I$(INCLUDE) -o testbench.o -c testbench.c
-
-tb_header.o: tb_header.c tb_header.h
-	$(CXX) -c -O3 -o tb_header.o -I./ -I$(INCLUDE) -fPIC tb_header.c
-
-libtb_header.so: tb_header.o
-	$(CXX) -shared -O3 -fPIC -o libtb_header.so tb_header.o
-
-libtb_header.a: tb_header.o
-	ar rcs $@ $^
-
-all: libtb_header.so libtb_header.a testbench 
-
-clean:
-	rm testbench testbench.o libtb_header.so tb_header.o libtb_header.a
-
diff --git a/src/sst/elements/osseous/tests/runstream.py b/src/sst/elements/osseous/tests/runstream.py
deleted file mode 100644
index 2d61e3f9cf..0000000000
--- a/src/sst/elements/osseous/tests/runstream.py
+++ /dev/null
@@ -1,153 +0,0 @@
-import sst
-import os
-
-clock = "1GHz"
-sst.setProgramOption("timebase", "0.5ps")
-
-sst_root = os.getenv( "SST_ROOT" )
-#sst.setProgramOption("timebase", "1ps")
-sst_workdir = os.getcwd();
-app = sst_workdir + "/testbench"
-
-if not os.path.exists(app):
-    app = os.getenv( "OMP_EXE" )
-    print("OS PATH DOESN'T EXIST")
-ariel = sst.Component("A0", "ariel.ariel")
-ariel.addParams({
-        "verbose" : "1",
-        "maxcorequeue" : "256",
-        "maxissuepercycle" : "2",
-        "pipetimeout" : "0",
-        "executable" : app,
-        "arielmode" : "1",
-        "clock" : "1GHz",
-        "arielinterceptcalls" : "1",
-        "launchparamcount" : 1,
-        "writepayloadtrace" : 1,
-        "launchparam0" : "-ifeellucky",
-        })
-
-memmgr = ariel.setSubComponent("memmgr", "ariel.MemoryManagerSimple")
-
-corecount = 1;
-
-rtl = sst.Component("rtlaximodel", "rtlcomponent.Rtlmodel")
-rtl.addParams({
-        "ExecFreq" : "1GHz",
-        "maxCycles" : "100"
-	})
-
-rtlmemmgr = rtl.setSubComponent("memmgr", "rtlaximodel.MemoryManagerSimple")
-
-l1cpucache = sst.Component("l1cpucache", "memHierarchy.Cache")
-l1cpucache.addParams({
-        "cache_frequency" : "1GHz",
-        "cache_size" : "64 KB",
-        "cache_type" : "inclusive",
-        "coherence_protocol" : "MSI",
-        "replacement_policy" : "lru",
-        "associativity" : "8",
-        "access_latency_cycles" : "1",
-        "cache_line_size" : "64",
-        "L1" : "1",
-        "debug" : "0",
-})
-
-l1rtlcache = sst.Component("l1rtlcache", "memHierarchy.Cache")
-l1rtlcache.addParams({
-        "cache_frequency" : "1GHz",
-        "cache_size" : "64 KB",
-        "coherence_protocol" : "MSI",
-        "replacement_policy" : "lru",
-        "associativity" : "8",
-        "access_latency_cycles" : "1",
-        "cache_line_size" : "64",
-        "L1" : "1",
-        "debug" : "0",
-})
-
-# Bus between private L1s and L2
-membus = sst.Component("membus", "memHierarchy.Bus")
-membus.addParams( { "bus_frequency" : clock,
-                    "debug" : 2,
-                    "debug_level" : 10
-} )
-
-cpu_cache_link = sst.Link("cpu_cache_link")
-cpu_cache_link.connect( (ariel, "cache_link_0", "50ps"), (l1cpucache, "high_network_0", "50ps") )
-
-rtl_cache_link = sst.Link("rtl_cache_link")
-rtl_cache_link.connect( (rtl, "RtlCacheLink", "50ps"), (l1rtlcache, "high_network_0", "50ps") )
-
-l1cpu_bus_link = sst.Link("l1cpu_bus_link")
-l1cpu_bus_link.connect( (l1cpucache, "low_network_0", "50ps"), (membus, "high_network_0", "50ps") )
-
-l1rtl_bus_link = sst.Link("l1rtl_bus_link")
-l1rtl_bus_link.connect( (l1rtlcache, "low_network_0", "50ps"), (membus, "high_network_1", "50ps") )
-
-# Shared L2
-# 1MB*cores, 16-way set associative, 64B line, 15 cycle access
-# MSI coherence with NMRU (not-most-recently-used) replacement
-l2 = sst.Component("l2cache", "memHierarchy.Cache")
-l2.addParams( {
-    "cache_frequency" : clock,
-    "access_latency_cycles" : 15,
-    "cache_size" : str(corecount) + "MB",   # 1MB/core
-    "associativity" : 16,
-    "cache_line_size" : 64,
-    "replacement_policy" : "nmru",
-    "coherence_protocol" : "MSI"
-} )
-
-l2_bus_link = sst.Link("l2_bus_link")
-l2_bus_link.connect( (l2, "high_network_0", "50ps"), (membus, "low_network_0", "50ps") )
-
-memctrl = sst.Component("memory", "memHierarchy.MemController")
-memctrl.addParams({
-        "clock" : "1GHz",
-})
-
-memory = memctrl.setSubComponent("backend", "memHierarchy.simpleMem")
-memory.addParams({
-        "access_time" : "10ns",
-        "mem_size" : "2048MiB",
-})
-
-cpu_rtl_link = sst.Link("cpu_rtl_link")
-cpu_rtl_link.connect( (ariel, "rtl_link_0", "50ps"), (rtl, "ArielRtllink", "50ps") )
-
-memory_link = sst.Link("mem_bus_link")
-memory_link.connect( (l2, "low_network_0", "50ps"), (memctrl, "direct_link", "50ps") )
-
-# Set the Statistic Load Level; Statistics with Enable Levels (set in
-# elementInfoStatistic) lower or equal to the load can be enabled (default = 0)
-sst.setStatisticLoadLevel(16)
-
-# Set the desired Statistic Output (sst.statOutputConsole is default)
-sst.setStatisticOutput("sst.statOutputConsole")
-#sst.setStatisticOutput("sst.statOutputTXT", {"filepath" : "./TestOutput.txt"
-#                                            })
-#sst.setStatisticOutput("sst.statOutputCSV", {"filepath" : "./TestOutput.csv",
-#                                                         "separator" : ", "
-#                                            })
-
-# Enable Individual Statistics for the Component with output at end of sim
-# Statistic defaults to Accumulator
-ariel.enableStatistics([
-      "cycles",
-      "active_cycles",
-      "instruction_count",
-      "read_requests",
-      "write_requests"
-])
-
-l1cpucache.enableStatistics([
-      #"CacheHits",
-      "latency_GetS_hit",
-      "latency_GetX_hit",
-      "latency_GetS_miss",
-      "latency_GetX_miss",
-      "GetSHit_Arrival",
-      "GetSHit_Blocked",
-      "CacheMisses"
-])
diff --git a/src/sst/elements/osseous/tests/tb_header.c b/src/sst/elements/osseous/tests/tb_header.c
deleted file mode 100644
index 1cd0479868..0000000000
--- a/src/sst/elements/osseous/tests/tb_header.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <execinfo.h>
-
-#include "tb_header.h"
-
-#define PAGE_SIZE 4096
-
-void ariel_enable() {
-    printf("\nStatic defination of Ariel_enable is being called\n");
-}
-
-void ariel_fence() {
-    printf("\nStatic defination of Ariel_fence is being called\n");
-}
-
-void mlm_set_pool(int level) {
-
-}
-
-void* mlm_malloc(size_t size, int level) {
-	if(size == 0) {
-		printf("ZERO BYTE MALLOC\n");
-		void* bt_entries[64];
-		int entries = backtrace(bt_entries, 64);
-		backtrace_symbols_fd(bt_entries, entries, 1);
-		exit(-1);
-	}
-
-#ifdef mlm_DEBUG
-	printf("Performing a mlm Malloc for size %llu\n", size);
-#endif
-
-	return malloc(size);
-}
-
-void  mlm_free(void* ptr) {
-	free(ptr);
-}
-
-mlm_Tag mlm_memcpy(void* dest, void* src, size_t length) {
-//	printf("Performing a mlm memcpy...\n");
-	size_t i;
-
-	char* dest_c = (char*) dest;
-	char* src_c  = (char*) src;
-
-	for(i = 0; i < length; i++) {
-		dest_c[i] = src_c[i];
-	}
-
-	return 0;
-}
-
-void mlm_waitComplete(mlm_Tag in) {
-	return;
-}
-    
-void start_RTL_sim(RTL_shmem_info* shmem) {     
-    printf("\nStatic defination of start_RTL_sim is being called\n"); 
-    return;
-}
-
-void update_RTL_sig(RTL_shmem_info* shmem) {     
-    printf("\nStatic defination of update_RTL_signals in being called\n");
-    return; 
-}
diff --git a/src/sst/elements/osseous/tests/tb_header.h b/src/sst/elements/osseous/tests/tb_header.h
deleted file mode 100644
index edec978bfb..0000000000
--- a/src/sst/elements/osseous/tests/tb_header.h
+++ /dev/null
@@ -1,170 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#ifndef _MLM_H
-#define _MLM_H
-
-#include <vector>
-#include <utility>
-#include <string>
-#include <stdlib.h>
-#include <iostream>
-#include <unistd.h>
-#include <inttypes.h>
-
-#if defined(c_plusplus) || defined(__cplusplus)
-extern "C" {
-#endif
-
-typedef int mlm_Tag;
-
-
-void* mlm_malloc(size_t size, int level);
-void  mlm_free(void* ptr);
-mlm_Tag mlm_memcpy(void* dest, void* src, size_t length);
-void mlm_waitComplete(mlm_Tag in);
-void mlm_set_pool(int pool);
-void ariel_enable();
-void ariel_fence();
-
-class RTL_shmem_info {
-
-  //  public:
-        /*RTL input information and control information corresponds to type(std::string) and size (in bytes) to which the void pointer will be casted to. Order of each stored input and control values should be maintained in accordance with the stored information in the TYPEINFO(std::array). Increment of void pointer once casted will align with the stored inp/ctrl data type. Any wrong cast can corrupt all the input and control signal information. */
-    private:      
-        void* rtl_inp_ptr;
-        void* rtl_ctrl_ptr;
-        void* updated_rtl_params;
-        size_t rtl_inp_size, rtl_ctrl_size, params_size;
-
-    public:
-
-        RTL_shmem_info(size_t inp_size, size_t ctrl_size) {
-            rtl_inp_size = inp_size;
-            rtl_ctrl_size = ctrl_size;
-            rtl_inp_ptr = mlm_malloc(inp_size, 0); 
-            rtl_ctrl_ptr = mlm_malloc(ctrl_size, 0); 
-            params_size = (7 * sizeof(bool) + sizeof(uint64_t));
-            updated_rtl_params = mlm_malloc(params_size, 0);
-            std::cout << "\nNew memory allocated at: ";
-        }
-        ~RTL_shmem_info() {
-            fprintf(stderr, "\nDeleting Shared Memory..\n");
-            free(rtl_inp_ptr);
-            free(rtl_ctrl_ptr);
-            free(updated_rtl_params);
-        }
-        size_t get_inp_size() { return rtl_inp_size; }
-        size_t get_ctrl_size() { return rtl_ctrl_size; }
-        size_t get_params_size() { return params_size; }
-        void* get_inp_ptr() { return rtl_inp_ptr; }
-        void* get_ctrl_ptr() { return rtl_ctrl_ptr; }
-        void* get_updated_rtl_params() { return updated_rtl_params; }
-};
-
-class Update_RTL_Params {
-    
-    private:
-        bool update_inp, update_ctrl, update_eval_args, update_reg, verbose, done_reset, sim_done;
-        uint64_t sim_cycles;
-    
-    public:
-        Update_RTL_Params(bool inp = true, bool ctrl = true, bool eval_args = true, bool reg = false, bool verb = true, bool done_rst = false, bool done = false, uint64_t cycles = 5) {
-            update_inp = inp;
-            update_ctrl = ctrl;
-            update_eval_args = eval_args;
-            update_reg = reg;
-            verbose = verb;
-            done_reset = done_rst;
-            sim_done = done;
-            sim_cycles = cycles;
-            std::cout << "\nUpdating RTL Params to default\n";
-        }
-
-        void perform_update(bool inp, bool ctrl, bool eval_args, bool reg, bool verb, bool done_rst, bool done, uint64_t cycles) {
-            update_inp = inp;
-            update_ctrl = ctrl;
-            update_eval_args = eval_args;
-            update_reg = reg;
-            verbose = verb;
-            done_reset = done_rst;
-            sim_done = done;
-            sim_cycles = cycles;
-
-            std::cout <<"\nPerforming update on RTL params\n";
-
-            return;
-        }
-
-        void storetomem(RTL_shmem_info* shmem) {
-            std::cout << "\nStore to mem called\n";
-            bool* Ptr = (bool*)shmem->get_updated_rtl_params();
-            *Ptr = update_inp;
-            Ptr++;
-            *Ptr = update_ctrl;
-            Ptr++;
-            *Ptr = update_eval_args;
-            Ptr++;
-            *Ptr = update_reg;
-            Ptr++;
-            *Ptr = verbose;
-            Ptr++;
-            *Ptr = done_reset;
-            Ptr++;
-            *Ptr = sim_done;
-            Ptr++;
-            uint64_t* Cycles_ptr  = (uint64_t*)Ptr;
-            *Cycles_ptr = sim_cycles; 
-            std::cout << "\nStore to mem finished \n"; 
-            return;
-        }
-
-        void check(RTL_shmem_info* shmem) {
-
-            bool* Ptr = (bool*)shmem->get_updated_rtl_params();
-            std::cout << "\n";
-            std::cout << *Ptr << " ";
-            Ptr++;
-            std::cout << *Ptr << " ";
-            Ptr++;
-            std::cout << *Ptr <<" ";
-            Ptr++;
-            std::cout << *Ptr <<" ";
-            Ptr++;
-            std::cout << *Ptr <<" ";
-            Ptr++;
-            std::cout << *Ptr <<" ";
-            Ptr++;
-            std::cout << *Ptr <<" ";
-            Ptr++;
-            uint64_t* Cycles_ptr = (uint64_t*)Ptr;
-            std::cout<< *Cycles_ptr <<" ";
-            std::cout << "\n";
-            return;
-        }
-};
-
-
-//Empty dummy function as PIN tool's dynamic instrumentation will replace it with its Ariel Equivalent API in PIN frontend - fesimple.cc (sst-elements/src/sst/elements/ariel/frontend/pin3/)
-void start_RTL_sim(RTL_shmem_info* shmem);
-
-//Empty function as PIN tool's dynamic instrumentation will replace it with Ariel Equivalent API in PIN frontend - fesimple.cc (sst-elements/src/sst/elements/ariel/frontend/pin3/)
-void update_RTL_sig(RTL_shmem_info* shmem); 
-
-#if defined(c_plusplus) || defined(__cplusplus)
-}
-#endif
-
-#endif //MLM_H
diff --git a/src/sst/elements/osseous/tests/testbench.c b/src/sst/elements/osseous/tests/testbench.c
deleted file mode 100644
index 6f5e45bd51..0000000000
--- a/src/sst/elements/osseous/tests/testbench.c
+++ /dev/null
@@ -1,143 +0,0 @@
-// Copyright 2009-2023 NTESS. Under the terms
-// of Contract DE-NA0003525 with NTESS, the U.S.
-// Government retains certain rights in this software.
-//
-// Copyright (c) 2009-2023, NTESS
-// All rights reserved.
-//
-// Portions are copyright of other developers:
-// See the file CONTRIBUTORS.TXT in the top level directory
-// of the distribution for more information.
-//
-// This file is part of the SST software package. For license
-// information, see the LICENSE file in the top level directory of the
-// distribution.
-
-#include "tb_header.h"
-#include <memory.h>
-#include <sint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <uint.h>
-#include <utility>
-#include <vector>
-#include <inttypes.h>
-int main(int argc, char *argv[]) {
-
-  const int LENGTH = 32768;
-
-  ariel_enable();
-
-  printf("Allocating arrays of size %d elements.\n", LENGTH);
-  double *a = (double *)mlm_malloc(sizeof(double) * LENGTH, 0);
-  double *b = (double *)mlm_malloc(sizeof(double) * LENGTH, 0);
-  double *fast_c = (double *)mlm_malloc(sizeof(double) * LENGTH, 0);
-
-  UInt<4> io_ins_0, io_ins_1, io_ins_2, io_ins_3, io_out;
-  UInt<1> io_load, io_shift;
-  UInt<4> *inp_ptr;
-  UInt<1> *ctrl_ptr;
-
-  mlm_set_pool(1);
-
-  printf("Allocation for fast_c is %llu\n", (unsigned long long int)fast_c);
-  double *c = (double *)malloc(sizeof(double) * LENGTH);
-  printf("Done allocating arrays.\n");
-
-  int i;
-  for (i = 0; i < LENGTH; ++i) {
-    a[i] = i;
-    b[i] = LENGTH - i;
-    c[i] = 0;
-  }
-
-  // Issue a memory copy
-  mlm_memcpy(fast_c, c, sizeof(double) * LENGTH);
-
-  printf("Perfoming the fast_c compute loop...\n");
-#pragma omp parallel for
-  for (i = 0; i < LENGTH; ++i) {
-    // printf("issuing a write to: %llu (fast_c)\n", ((unsigned long long int)
-    // &fast_c[i]));
-    fast_c[i] = 2.0 * a[i] + 1.5 * b[i];
-  }
-
-  // Now copy results back
-  mlm_Tag copy_tag = mlm_memcpy(c, fast_c, sizeof(double) * LENGTH);
-  mlm_waitComplete(copy_tag);
-
-  io_shift = UInt<1>(1);
-  io_ins_0 = UInt<4>(2);
-  io_ins_1 = UInt<4>(5);
-  io_ins_2 = UInt<4>(6);
-  io_ins_3 = UInt<4>(7);
-  io_load = UInt<1>(0);
-
-  size_t inp_size = sizeof(UInt<4>) * 5;
-  size_t ctrl_size = sizeof(UInt<1>) * 2;
-  RTL_shmem_info *shmem = new RTL_shmem_info(inp_size, ctrl_size);
-
-  inp_ptr = (UInt<4>*)shmem->get_inp_ptr();
-  ctrl_ptr = (UInt<1>*)shmem->get_ctrl_ptr();
-
-  ctrl_ptr[0] = io_shift;
-  ctrl_ptr[1] = io_load;
-  inp_ptr[0] = io_ins_0;
-  inp_ptr[1] = io_ins_1;
-  inp_ptr[2] = io_ins_2;
-  inp_ptr[3] = io_ins_3;
-
-  Update_RTL_Params *params = new Update_RTL_Params();
-  params->storetomem(shmem);
-  params->check(shmem);
-  ctrl_ptr[0] = io_shift;
-  ctrl_ptr[1] = io_load;
-  inp_ptr[0] = io_ins_0;
-  inp_ptr[1] = io_ins_1;
-  inp_ptr[2] = io_ins_2;
-  inp_ptr[3] = io_ins_3;
-  params->storetomem(shmem);
-
-  start_RTL_sim(shmem);
-  bool *check = (bool *)shmem->get_inp_ptr();
-  printf("\nSimulation started\n");
-
-  io_load = UInt<1>(1);
-  ctrl_ptr[1] = io_load;
-
-  params->perform_update(false, true, true, true, true, false, false, 1);
-  params->storetomem(shmem);
-  ctrl_ptr[1] = io_load;
-  params->storetomem(shmem);
-  update_RTL_sig(shmem);
-
-  io_load = UInt<1>(0);
-  ctrl_ptr[1] = io_load;
-
-  params->perform_update(false, true, true, true, true, true, true, 10);
-  params->storetomem(shmem);
-  ctrl_ptr[1] = io_load;
-  params->storetomem(shmem);
-  update_RTL_sig(shmem);
-
-
-  double sum = 0;
-  for (i = 0; i < LENGTH; ++i) {
-    sum += c[i];
-  }
-
-  printf("Sum of arrays is: %f\n", sum);
-  printf("Freeing arrays...\n");
-
-  mlm_free(a);
-  mlm_free(b);
-  mlm_free(fast_c);
-  free(c);
-
-  delete shmem;
-  delete params;
-
-  printf("Done.\n");
-
-  return 0;
-}
diff --git a/src/sst/elements/osseous/wrapper_code.spec b/src/sst/elements/osseous/wrapper_code.spec
deleted file mode 100644
index 2a78da3ebb..0000000000
--- a/src/sst/elements/osseous/wrapper_code.spec
+++ /dev/null
@@ -1,102 +0,0 @@
-    SST_ELI_DOCUMENT_STATISTICS(
-        { "read_requests",        "Statistic counts number of read requests", "requests", 1},   // Name, Desc, Enable Level
-        { "write_requests",       "Statistic counts number of write requests", "requests", 1},
-        { "read_request_sizes",   "Statistic for size of read requests", "bytes", 1},   // Name, Desc, Enable Level
-        { "write_request_sizes",  "Statistic for size of write requests", "bytes", 1},
-        { "split_read_requests",  "Statistic counts number of split read requests (requests which come from multiple lines)", "requests", 1},
-        { "split_write_requests", "Statistic counts number of split write requests (requests which are split over multiple lines)", "requests", 1},
-	    { "flush_requests",       "Statistic counts instructions which perform flushes", "requests", 1},
-        { "fence_requests",       "Statistic counts instructions which perform fences", "requests", 1}
-    )
-    //Parameters will mostly be just frequency/clock in the design. User will mention specifically if there could be other parameters for the RTL design which needs to be configured before runtime.  Don't mix RTL input/control signals with SST parameters. SST parameters of RTL design will make the RTL design/C++ model synchronous with rest of the SST full system.   
-	SST_ELI_DOCUMENT_PARAMS(
-		{ "ExecFreq", "Clock frequency of RTL design in GHz", "1GHz" },
-		{ "maxCycles", "Number of Clock ticks the simulation must atleast execute before halting", "1000" },
-        {"memoryinterface", "Interface to memory", "memHierarchy.memInterface"}
-	)
-
-    //Default will be single port for communicating with Ariel CPU. Need to see the requirement/use-case of multi-port design and how to incorporate it in our parser tool.  
-    SST_ELI_DOCUMENT_PORTS(
-        {"CPURtllink", "Link to the Rtlmodel", { "Rtlmodel.RTLEvent", "" } },
-        {"RtlCacheLink", "Link to Cache", {"memHierarchy.memInterface" , ""} }
-    )
-    
-    SST_ELI_DOCUMENT_SUBCOMPONENT_SLOTS(
-            {"memmgr", "Memory manager to translate virtual addresses to physical, handle malloc/free, etc.", "SST::RtlComponent::RtlMemoryManager"},
-            {"memory", "Interface to the memoryHierarchy (e.g., caches)", "SST::Interfaces::SimpleMem" }
-    )
-
-//Placeholder for Boiler Plate code
-
-void init() {
-    //Any initialization code or binary/hex file to be loaded to memHierarchy
-}
-
-void setup() {
-    dut->reset = UInt<1>(1);
-    axiport->reset = UInt<1>(1);
-	output.verbose(CALL_INFO, 1, 0, "Component is being setup.\n");
-}
-
-void finish() {
-	output.verbose(CALL_INFO, 1, 0, "Component is being finished.\n");
-    free(getBaseDataAddress());
-}
-
-void ClockTick() {
-    //Code or piece of logic to be executed other than eval() call at every SST Clock 
-}
-
-void handleRTLEvent() {
-    //Piece of logic other than updating input signals at stimulus based on input_port spec file
-}
-
-
-//Example statstics to be recorded for various events in DUT/SST Element
-Statistic<uint64_t>* statReadRequests ClockTick;
-Statistic<uint64_t>* statWriteRequests RTLSSTmemEvent; 
-Statistic<uint64_t>* statFlushRequests RTLSSTmemEvent;
-Statistic<uint64_t>* statFenceRequests AXISSTEvent;
-Statistic<uint64_t>* statReadRequestSizes SSTAXIEvent;
-Statistic<uint64_t>* statWriteRequestSizes RTLSSTmemEvent;
-Statistic<uint64_t>* statSplitReadRequests RTLSSTmemEvent;
-Statistic<uint64_t>* statSplitWriteRequests SSTRTLmemEvent;
-
-//Update Inputs based on exteral stimulus such as an event
-
-void RTLEvent::UpdateRtlSignals(void *update_data, Rtlheader* cmodel, uint64_t& cycles) {
-    bool* update_rtl_params = (bool*)update_data; 
-    update_inp = update_rtl_params[0];
-    update_ctrl = update_rtl_params[1];
-    update_eval_args = update_rtl_params[2];
-    update_registers = update_rtl_params[3];
-    verbose = update_rtl_params[4];
-    done_reset = update_rtl_params[5];
-    sim_done = update_rtl_params[6];
-    uint64_t* cycles_ptr = (uint64_t*)(&update_rtl_params[7]);
-    sim_cycles = *cycles_ptr;
-    cycles = sim_cycles;
-    cycles_ptr++;
-
-    fprintf(stderr, "sim_cycles: %" PRIu64, sim_cycles);
-    fprintf(stderr, "update_inp: %d", update_inp);
-    fprintf(stderr, "update_ctrl: %d", update_ctrl);
-    if(update_inp) {
-        inp_ptr =  (void*)cycles_ptr; 
-        input_sigs(cmodel);
-    }
-
-    if(update_ctrl) {
-        UInt<4>* rtl_inp_ptr = (UInt<4>*)inp_ptr;
-        ctrl_ptr = (void*)(&rtl_inp_ptr[5]);
-        control_sigs(cmodel);
-    }
-}
-
-input_sigs() {
-    //Update necessary input signals, at stimulus
-}
-
-ctrl_sigs() {
-    //Update necessary ctrl signals, at stimulus
-}