[STM32G031G8]: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870

[rxk08011]

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• I made serious effort to avoid creating duplicate or nearly similar issue

In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem.

• Programmer/board type: [ST-Link V3 mini] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3)
• Operating system an version: [Linux] (e.g Linux, macOS, Windows)
• stlink tools version and/or git commit hash: [1.7.0-120-gbeffed4-dirty] (e.g v1.6.1/git-d0416149)
• stlink commandline tool name: [st-flash] (e.g st-info, st-flash, st-trace, st-util)
• Target chip (and board, if applicable): [ STM32G031G8] (e.g STM32F103C8T6 (NUCLEO-F103RB))

Further we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template:

Commandline output:

./st-flash --debug write output.bin 0x1FFF7870

OUTPUT/ERROR of the commandline tool(s)

st-flash 1.7.0-120-gbeffed4-dirty
2021-10-18T09:03:32 DEBUG common.c: *** looking up stlink version
2021-10-18T09:03:32 DEBUG common.c: st vid = 0x0483 (expect 0x0483)
2021-10-18T09:03:32 DEBUG common.c: stlink pid = 0x374e
2021-10-18T09:03:32 DEBUG common.c: stlink version = 0x3
2021-10-18T09:03:32 DEBUG common.c: jtag version = 0x3
2021-10-18T09:03:32 DEBUG common.c: swim version = 0x0
2021-10-18T09:03:32 DEBUG common.c: stlink current mode: mass
2021-10-18T09:03:32 DEBUG usb.c: JTAG/SWD freq set to 0
2021-10-18T09:03:32 DEBUG common.c: stlink current mode: mass
2021-10-18T09:03:32 DEBUG common.c: *** stlink_enter_swd_mode ***
2021-10-18T09:03:32 DEBUG common.c: Loading device parameters....
2021-10-18T09:03:32 DEBUG common.c: *** stlink_core_id ***
2021-10-18T09:03:32 DEBUG common.c: core_id = 0x0bc11477
2021-10-18T09:03:32 DEBUG common.c: *** stlink_read_debug32 0x410cc601 at 0xe000ed00
2021-10-18T09:03:32 DEBUG common.c: *** stlink_read_debug32 0x10016466 at 0x40015800
---------- old ------------

Chip-ID file for G03x/G04x

chip_id 0x466
description G03x/G04x
flash_type 7
flash_size_reg 0x1fff75e0
flash_pagesize 0x800
sram_size 0x2000
bootrom_base 0x1fff0000
bootrom_size 0x2000
option_base 0x1fff7800
option_size 0x4
flags 0

---------- new ------------

Chip-ID file for G03x/G04x

chip_id 0x466
description G03x/G04x
flash_type 7
flash_size_reg 0x0
flash_pagesize 0x800
sram_size 0x2000
bootrom_base 0x1fff0000
bootrom_size 0x2000
option_base 0x1fff7800
option_size 0x4
flags 0

2021-10-18T09:03:32 DEBUG common.c: *** stlink_read_debug32 0xffffffff at 0000000000
2021-10-18T09:03:32 INFO common.c: G03x/G04x: 8 KiB SRAM, 65535 KiB flash in at least 2 KiB pages.
2021-10-18T09:03:32 DEBUG common.c: *** stlink_force_debug_mode ***
2021-10-18T09:03:32 DEBUG common.c: *** stlink_read_debug32 0000000000 at 0x40015808
2021-10-18T09:03:32 DEBUG common.c: *** stlink_write_debug32 0x00001800 to 0x40015808
2021-10-18T09:03:32 DEBUG common.c: *** stlink_status ***
2021-10-18T09:03:33 DEBUG usb.c: core status: 01030003
2021-10-18T09:03:33 DEBUG common.c: core status: halted
Unknown memory region
2021-10-18T09:03:33 DEBUG common.c: *** stlink_exit_debug_mode ***
2021-10-18T09:03:33 DEBUG common.c: *** stlink_write_debug32 0xa05f0000 to 0xe000edf0
2021-10-18T09:03:33 DEBUG common.c: *** stlink_close ***

Expected/description:

BOOT_LOCK is a flag/bit on address 0x1FFF7870. Due to hard coded option_size of 0x4, it is not possible to change this flag. I get an error "Unknown memory region".

I tried with increased option_size to 0x71, then I get an error "stlink_fwrite_option_bytes() == -1"

[spflieger]

The situation for the STM32G03 similar to the F446 #1156.
st-flash actually support only reading and writing the "USER" option byes.

[Ant-ON]

@spflieger Appropriate Memory map and register boundary addresses of RM0444 the options byte area have size of 0x80. Can you change option_size to 0x80 and try again?

[spflieger]

This works for reading, but not for writing. The option bytes are not contiguous in option byte area. There is a gap at 0x1FFF7868 and there is no option byte at 0x1FFF7878 either. So we have actual only 0x70 bytes. This can be seen in Table 16. Organization of option bytes in RM0444.

I reviewed the option write support. To write other registers than FLASH_OPTR requires a mayor rework of the code.

[Nightwalker-87]

@Ant-ON What is your opinion on that? How shall we proceed here?

[Ant-ON]

@Nightwalker-87 Need increase option_size from 0x4 to 0x80 in the https://github.com/stlink-org/stlink/blob/nightly/config/chips/G03x_G04x.chip. Flashing should work by st-flash --debug write output.bin 0x1FFF7870

[Nightwalker-87]

@Ant-ON: I'll push the change soon, maybe update the docs if necessary, needs testing then for verification.

[Nightwalker-87]

@Ant-ON: I had another look at this. @spflieger seems to have pointed out a relevant aspect with his last mention.
As far as I understand your last reply, only an explicit (manual) write to this address is possible.