diff --git a/CHANGELOG.md b/CHANGELOG.md
index 6916ed96..99c8c30f 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -8,6 +8,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [Unreleased]
 
 ### Breaking changes
+
+- Use bit-banding for Peripheral enable/reset.
+  Don't require APBs in initializers.
 - Rename `gpio::Edge::{RISING, FALLING, RISING_FALLING}` to `Rising`, `Falling`, `RisingFalling`, respectively
 
 ### Added
diff --git a/examples/adc-dma-circ.rs b/examples/adc-dma-circ.rs
index dc3a3a4a..da0378fd 100644
--- a/examples/adc-dma-circ.rs
+++ b/examples/adc-dma-circ.rs
@@ -15,7 +15,7 @@ fn main() -> ! {
     // Acquire peripherals
     let p = pac::Peripherals::take().unwrap();
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     // Configure ADC clocks
     // Default value is the slowest possible ADC clock: PCLK2 / 8. Meanwhile ADC
@@ -24,13 +24,13 @@ fn main() -> ! {
     // prescaler values 2/4/6/8.
     let clocks = rcc.cfgr.adcclk(2.mhz()).freeze(&mut flash.acr);
 
-    let dma_ch1 = p.DMA1.split(&mut rcc.ahb).1;
+    let dma_ch1 = p.DMA1.split().1;
 
     // Setup ADC
-    let adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2, clocks);
+    let adc1 = adc::Adc::adc1(p.ADC1, clocks);
 
     // Setup GPIOA
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
 
     // Configure pa0 as an analog input
     let adc_ch0 = gpioa.pa0.into_analog(&mut gpioa.crl);
diff --git a/examples/adc-dma-rx.rs b/examples/adc-dma-rx.rs
index be62425e..c9f679a6 100644
--- a/examples/adc-dma-rx.rs
+++ b/examples/adc-dma-rx.rs
@@ -15,7 +15,7 @@ fn main() -> ! {
     // Acquire peripherals
     let p = pac::Peripherals::take().unwrap();
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     // Configure ADC clocks
     // Default value is the slowest possible ADC clock: PCLK2 / 8. Meanwhile ADC
@@ -24,13 +24,13 @@ fn main() -> ! {
     // prescaler values 2/4/6/8.
     let clocks = rcc.cfgr.adcclk(2.mhz()).freeze(&mut flash.acr);
 
-    let dma_ch1 = p.DMA1.split(&mut rcc.ahb).1;
+    let dma_ch1 = p.DMA1.split().1;
 
     // Setup ADC
-    let adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2, clocks);
+    let adc1 = adc::Adc::adc1(p.ADC1, clocks);
 
     // Setup GPIOA
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
 
     // Configure pa0 as an analog input
     let adc_ch0 = gpioa.pa0.into_analog(&mut gpioa.crl);
diff --git a/examples/adc.rs b/examples/adc.rs
index 3979d543..fec13086 100644
--- a/examples/adc.rs
+++ b/examples/adc.rs
@@ -14,7 +14,7 @@ fn main() -> ! {
     // Acquire peripherals
     let p = pac::Peripherals::take().unwrap();
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     // Configure ADC clocks
     // Default value is the slowest possible ADC clock: PCLK2 / 8. Meanwhile ADC
@@ -25,13 +25,13 @@ fn main() -> ! {
     hprintln!("adc freq: {}", clocks.adcclk().0).unwrap();
 
     // Setup ADC
-    let mut adc1 = adc::Adc::adc1(p.ADC1, &mut rcc.apb2, clocks);
+    let mut adc1 = adc::Adc::adc1(p.ADC1, clocks);
 
     #[cfg(feature = "stm32f103")]
-    let mut adc2 = adc::Adc::adc2(p.ADC2, &mut rcc.apb2, clocks);
+    let mut adc2 = adc::Adc::adc2(p.ADC2, clocks);
 
     // Setup GPIOB
-    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpiob = p.GPIOB.split();
 
     // Configure pb0, pb1 as an analog input
     let mut ch0 = gpiob.pb0.into_analog(&mut gpiob.crl);
diff --git a/examples/adc_temperature.rs b/examples/adc_temperature.rs
index 2099ecad..a8d2068b 100644
--- a/examples/adc_temperature.rs
+++ b/examples/adc_temperature.rs
@@ -14,7 +14,7 @@ fn main() -> ! {
     // Acquire peripherals
     let p = pac::Peripherals::take().unwrap();
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc
         .cfgr
@@ -27,7 +27,7 @@ fn main() -> ! {
     hprintln!("adc freq: {}", clocks.adcclk().0).unwrap();
 
     // Setup ADC
-    let mut adc = adc::Adc::adc1(p.ADC1, &mut rcc.apb2, clocks);
+    let mut adc = adc::Adc::adc1(p.ADC1, clocks);
 
     // Read temperature sensor
     loop {
diff --git a/examples/blinky.rs b/examples/blinky.rs
index 353d5eb6..4adbf10d 100644
--- a/examples/blinky.rs
+++ b/examples/blinky.rs
@@ -26,14 +26,14 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Acquire the GPIOC peripheral
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
 
     // Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the function
     // in order to configure the port. For pins 0-7, crl should be passed instead.
diff --git a/examples/blinky_generic.rs b/examples/blinky_generic.rs
index 7b3b5fe9..9b510a65 100644
--- a/examples/blinky_generic.rs
+++ b/examples/blinky_generic.rs
@@ -17,13 +17,13 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Acquire the GPIO peripherals
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
+    let mut gpioc = dp.GPIOC.split();
 
     // Configure the syst timer to trigger an update every second
     let mut timer = Timer::syst(cp.SYST, &clocks).start_count_down(1.hz());
diff --git a/examples/blinky_rtc.rs b/examples/blinky_rtc.rs
index d23c01a0..ef92ba39 100644
--- a/examples/blinky_rtc.rs
+++ b/examples/blinky_rtc.rs
@@ -22,15 +22,15 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().unwrap();
 
     let mut pwr = dp.PWR;
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // Set up the GPIO pin
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
 
     // Set up the RTC
     // Enable writes to the backup domain
-    let mut backup_domain = rcc.bkp.constrain(dp.BKP, &mut rcc.apb1, &mut pwr);
+    let mut backup_domain = rcc.bkp.constrain(dp.BKP, &mut pwr);
     // Start the RTC
     let mut rtc = Rtc::rtc(dp.RTC, &mut backup_domain);
 
diff --git a/examples/blinky_rtcalarm_irq.rs b/examples/blinky_rtcalarm_irq.rs
index 4c263086..1e91c746 100644
--- a/examples/blinky_rtcalarm_irq.rs
+++ b/examples/blinky_rtcalarm_irq.rs
@@ -76,10 +76,10 @@ fn main() -> ! {
     let dp = Peripherals::take().unwrap();
 
     let mut pwr = dp.PWR;
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // Set up the GPIO pin
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
     let _ = led.set_high(); // Turn off
 
@@ -94,7 +94,7 @@ fn main() -> ! {
 
     // Set up the RTC
     // Enable writes to the backup domain
-    let mut backup_domain = rcc.bkp.constrain(dp.BKP, &mut rcc.apb1, &mut pwr);
+    let mut backup_domain = rcc.bkp.constrain(dp.BKP, &mut pwr);
     // Start the RTC
     let mut rtc = Rtc::rtc(dp.RTC, &mut backup_domain);
     rtc.set_time(0);
diff --git a/examples/blinky_timer_irq.rs b/examples/blinky_timer_irq.rs
index 0c0c0a6c..17b2b3fc 100644
--- a/examples/blinky_timer_irq.rs
+++ b/examples/blinky_timer_irq.rs
@@ -69,7 +69,7 @@ fn TIM2() {
 fn main() -> ! {
     let dp = Peripherals::take().unwrap();
 
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
     let mut flash = dp.FLASH.constrain();
     let clocks = rcc
         .cfgr
@@ -78,7 +78,7 @@ fn main() -> ! {
         .freeze(&mut flash.acr);
 
     // Configure PC13 pin to blink LED
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
     let _ = led.set_high(); // Turn off
 
@@ -86,7 +86,7 @@ fn main() -> ! {
     cortex_m::interrupt::free(|cs| *G_LED.borrow(cs).borrow_mut() = Some(led));
 
     // Set up a timer expiring after 1s
-    let mut timer = Timer::tim2(dp.TIM2, &clocks, &mut rcc.apb1).start_count_down(1.hz());
+    let mut timer = Timer::tim2(dp.TIM2, &clocks).start_count_down(1.hz());
 
     // Generate an interrupt when the timer expires
     timer.listen(Event::Update);
diff --git a/examples/can-echo.rs b/examples/can-echo.rs
index 8fa317b5..a57ca063 100644
--- a/examples/can-echo.rs
+++ b/examples/can-echo.rs
@@ -16,22 +16,22 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // To meet CAN clock accuracy requirements an external crystal or ceramic
     // resonator must be used. The blue pill has a 8MHz external crystal.
     // Other boards might have a crystal with another frequency or none at all.
     rcc.cfgr.use_hse(8.mhz()).freeze(&mut flash.acr);
 
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
 
     let mut can1 = {
         #[cfg(not(feature = "connectivity"))]
-        let can = Can::new(dp.CAN1, &mut rcc.apb1, dp.USB);
+        let can = Can::new(dp.CAN1, dp.USB);
         #[cfg(feature = "connectivity")]
-        let can = Can::new(dp.CAN1, &mut rcc.apb1);
+        let can = Can::new(dp.CAN1);
 
-        let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+        let mut gpioa = dp.GPIOA.split();
         let rx = gpioa.pa11.into_floating_input(&mut gpioa.crh);
         let tx = gpioa.pa12.into_alternate_push_pull(&mut gpioa.crh);
         can.assign_pins((tx, rx), &mut afio.mapr);
@@ -49,9 +49,9 @@ fn main() -> ! {
 
     #[cfg(feature = "connectivity")]
     let _can2 = {
-        let can = Can::new(dp.CAN2, &mut rcc.apb1);
+        let can = Can::new(dp.CAN2);
 
-        let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
+        let mut gpiob = dp.GPIOB.split();
         let rx = gpiob.pb5.into_floating_input(&mut gpiob.crl);
         let tx = gpiob.pb6.into_alternate_push_pull(&mut gpiob.crl);
         can.assign_pins((tx, rx), &mut afio.mapr);
diff --git a/examples/can-loopback.rs b/examples/can-loopback.rs
index e13c0ea3..010a47dd 100644
--- a/examples/can-loopback.rs
+++ b/examples/can-loopback.rs
@@ -19,17 +19,17 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // To meet CAN clock accuracy requirements, an external crystal or ceramic
     // resonator must be used.
     rcc.cfgr.use_hse(8.mhz()).freeze(&mut flash.acr);
 
     #[cfg(not(feature = "connectivity"))]
-    let can = Can::new(dp.CAN1, &mut rcc.apb1, dp.USB);
+    let can = Can::new(dp.CAN1, dp.USB);
 
     #[cfg(feature = "connectivity")]
-    let can = Can::new(dp.CAN1, &mut rcc.apb1);
+    let can = Can::new(dp.CAN1);
 
     let mut can = bxcan::Can::new(can);
 
@@ -108,7 +108,7 @@ fn main() -> ! {
         assert!(can.receive().is_err());
     }
 
-    let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
+    let mut gpiob = dp.GPIOB.split();
     let mut led = gpiob.pb9.into_push_pull_output(&mut gpiob.crh);
     led.set_high();
 
diff --git a/examples/can-rtic.rs b/examples/can-rtic.rs
index bc54cfde..26928f72 100644
--- a/examples/can-rtic.rs
+++ b/examples/can-rtic.rs
@@ -69,7 +69,7 @@ const APP: () = {
     #[init]
     fn init(cx: init::Context) -> init::LateResources {
         let mut flash = cx.device.FLASH.constrain();
-        let mut rcc = cx.device.RCC.constrain();
+        let rcc = cx.device.RCC.constrain();
 
         let _clocks = rcc
             .cfgr
@@ -81,16 +81,16 @@ const APP: () = {
             .freeze(&mut flash.acr);
 
         #[cfg(not(feature = "connectivity"))]
-        let can = Can::new(cx.device.CAN1, &mut rcc.apb1, cx.device.USB);
+        let can = Can::new(cx.device.CAN1, cx.device.USB);
 
         #[cfg(feature = "connectivity")]
-        let can = Can::new(cx.device.CAN1, &mut rcc.apb1);
+        let can = Can::new(cx.device.CAN1);
 
         // Select pins for CAN1.
-        let mut gpioa = cx.device.GPIOA.split(&mut rcc.apb2);
+        let mut gpioa = cx.device.GPIOA.split();
         let can_rx_pin = gpioa.pa11.into_floating_input(&mut gpioa.crh);
         let can_tx_pin = gpioa.pa12.into_alternate_push_pull(&mut gpioa.crh);
-        let mut afio = cx.device.AFIO.constrain(&mut rcc.apb2);
+        let mut afio = cx.device.AFIO.constrain();
         can.assign_pins((can_tx_pin, can_rx_pin), &mut afio.mapr);
 
         let mut can = bxcan::Can::new(can);
diff --git a/examples/crc.rs b/examples/crc.rs
index da58af53..4038dd77 100644
--- a/examples/crc.rs
+++ b/examples/crc.rs
@@ -14,14 +14,13 @@ use stm32f1xx_hal::{pac, prelude::*};
 fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
-    let mut rcc = p.RCC.constrain();
-    let mut crc = p.CRC.new(&mut rcc.ahb);
+    let mut crc = p.CRC.new();
 
     crc.reset();
     crc.write(0x12345678);
 
     let val = crc.read();
-    hprintln!("found={:08x}, expected={:08x}", val, 0xdf8a8a2bu32).ok();
+    hprintln!("found={:08x}, expected={:08x}", val, 0xdf8a8a2b_u32).ok();
 
     loop {}
 }
diff --git a/examples/delay.rs b/examples/delay.rs
index 073e1d0d..47d4c697 100644
--- a/examples/delay.rs
+++ b/examples/delay.rs
@@ -15,11 +15,11 @@ fn main() -> ! {
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
 
     #[cfg(feature = "stm32f100")]
     let mut led = gpioc.pc9.into_push_pull_output(&mut gpioc.crh);
diff --git a/examples/dynamic_gpio.rs b/examples/dynamic_gpio.rs
index 10e76fdf..503ac914 100644
--- a/examples/dynamic_gpio.rs
+++ b/examples/dynamic_gpio.rs
@@ -21,14 +21,14 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Acquire the GPIOC peripheral
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
 
     let mut pin = gpioc.pc13.into_dynamic(&mut gpioc.crh);
     // Configure the syst timer to trigger an update every second
diff --git a/examples/enc28j60-coap.rs.disabled b/examples/enc28j60-coap.rs.disabled
index 9dd25d2f..c4a33c8d 100644
--- a/examples/enc28j60-coap.rs.disabled
+++ b/examples/enc28j60-coap.rs.disabled
@@ -64,15 +64,15 @@ fn main() -> ! {
     let dp = stm32f103xx::Peripherals::take().unwrap();
 
     let mut rcc = dp.RCC.constrain();
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
     let mut flash = dp.FLASH.constrain();
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
     let _stim = &mut cp.ITM.stim[0];
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // LED
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
     // turn the LED off during initialization
     led.set_high();
@@ -92,7 +92,6 @@ fn main() -> ! {
         enc28j60::MODE,
         1.mhz(),
         clocks,
-        &mut rcc.apb2,
     );
 
     // ENC28J60
diff --git a/examples/enc28j60.rs.disabled b/examples/enc28j60.rs.disabled
index d79e7d54..2ba1cb49 100644
--- a/examples/enc28j60.rs.disabled
+++ b/examples/enc28j60.rs.disabled
@@ -56,9 +56,9 @@ fn main() -> ! {
     let dp = stm32f103xx::Peripherals::take().unwrap();
 
     let mut rcc = dp.RCC.constrain();
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
     let mut flash = dp.FLASH.constrain();
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
     let _stim = &mut cp.ITM.stim[0];
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
@@ -66,7 +66,7 @@ fn main() -> ! {
     cp.DWT.enable_cycle_counter();
 
     // LED
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
     // turn the LED off during initialization
     led.set_high();
@@ -84,7 +84,6 @@ fn main() -> ! {
         enc28j60::MODE,
         1.mhz(),
         clocks,
-        &mut rcc.apb2,
     );
 
     // ENC28J60
diff --git a/examples/exti.rs b/examples/exti.rs
index eaadf46b..a9489395 100644
--- a/examples/exti.rs
+++ b/examples/exti.rs
@@ -44,10 +44,9 @@ fn main() -> ! {
     {
         // the scope ensures that the int_pin reference is dropped before the first ISR can be executed.
 
-        let mut rcc = p.RCC.constrain();
-        let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-        let mut gpioc = p.GPIOC.split(&mut rcc.apb2);
-        let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+        let mut gpioa = p.GPIOA.split();
+        let mut gpioc = p.GPIOC.split();
+        let mut afio = p.AFIO.constrain();
 
         let led = unsafe { &mut *LED.as_mut_ptr() };
         *led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
diff --git a/examples/exti_rtic.rs b/examples/exti_rtic.rs
index 9c5b319f..b732afcb 100644
--- a/examples/exti_rtic.rs
+++ b/examples/exti_rtic.rs
@@ -21,13 +21,12 @@ const APP: () = {
 
     #[init]
     fn init(mut ctx: init::Context) -> init::LateResources {
-        let mut rcc = ctx.device.RCC.constrain();
-        let mut afio = ctx.device.AFIO.constrain(&mut rcc.apb2);
+        let mut afio = ctx.device.AFIO.constrain();
 
-        let mut gpioc = ctx.device.GPIOC.split(&mut rcc.apb2);
+        let mut gpioc = ctx.device.GPIOC.split();
         let led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
 
-        let mut gpioa = ctx.device.GPIOA.split(&mut rcc.apb2);
+        let mut gpioa = ctx.device.GPIOA.split();
         let mut button = gpioa.pa0.into_pull_down_input(&mut gpioa.crl);
         button.make_interrupt_source(&mut afio);
         button.enable_interrupt(&mut ctx.device.EXTI);
diff --git a/examples/gpio_input.rs b/examples/gpio_input.rs
index 5abede6c..426186df 100644
--- a/examples/gpio_input.rs
+++ b/examples/gpio_input.rs
@@ -25,14 +25,14 @@ fn main() -> ! {
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     let clock = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
-    let mut _gpiob = dp.GPIOB.split(&mut rcc.apb2);
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
-    let mut gpiod = dp.GPIOD.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
+    let mut _gpiob = dp.GPIOB.split();
+    let mut gpioc = dp.GPIOC.split();
+    let mut gpiod = dp.GPIOD.split();
 
     // red_led and green_led
     let mut red_led = gpioa
@@ -42,7 +42,7 @@ fn main() -> ! {
         .pd2
         .into_push_pull_output_with_state(&mut gpiod.crl, PinState::High);
 
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
     let (gpioa_pa15, _gpiob_pb3, _gpiob_pb4) =
         afio.mapr.disable_jtag(gpioa.pa15, _gpiob.pb3, _gpiob.pb4);
 
diff --git a/examples/led.rs b/examples/led.rs
index 86c995bc..69cd1e15 100644
--- a/examples/led.rs
+++ b/examples/led.rs
@@ -22,8 +22,7 @@ use stm32f1xx_hal::{pac, prelude::*};
 fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
-    let mut rcc = p.RCC.constrain();
-    let mut gpioc = p.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = p.GPIOC.split();
 
     #[cfg(feature = "stm32f100")]
     gpioc.pc9.into_push_pull_output(&mut gpioc.crh).set_high();
diff --git a/examples/mfrc522.rs b/examples/mfrc522.rs
index 9f1fa81e..6d607f38 100644
--- a/examples/mfrc522.rs
+++ b/examples/mfrc522.rs
@@ -17,11 +17,11 @@ fn main() -> ! {
     let dp = pac::Peripherals::take().unwrap();
 
     let _stim = &mut cp.ITM.stim[0];
-    let mut rcc = dp.RCC.constrain();
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let rcc = dp.RCC.constrain();
+    let mut afio = dp.AFIO.constrain();
     let mut flash = dp.FLASH.constrain();
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
+    let mut gpioc = dp.GPIOC.split();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
@@ -35,7 +35,6 @@ fn main() -> ! {
         mfrc522::MODE,
         1.mhz(),
         clocks,
-        &mut rcc.apb2,
     );
 
     let nss = gpioa.pa4.into_push_pull_output(&mut gpioa.crl);
diff --git a/examples/motor.rs.disabled b/examples/motor.rs.disabled
index a05bdc63..466394ce 100644
--- a/examples/motor.rs.disabled
+++ b/examples/motor.rs.disabled
@@ -31,9 +31,9 @@ fn main() -> ! {
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
 
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
 
     let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
     let rx = gpioa.pa10;
@@ -44,7 +44,6 @@ fn main() -> ! {
         &mut afio.mapr,
         115_200.bps(),
         clocks,
-        &mut rcc.apb2,
     );
 
     let mut rx = serial.split().1;
@@ -54,7 +53,6 @@ fn main() -> ! {
         &mut afio.mapr,
         1.khz(),
         clocks,
-        &mut rcc.apb1,
     );
 
     let max_duty = pwm.get_max_duty() as i16;
diff --git a/examples/mpu9250.rs.disabled b/examples/mpu9250.rs.disabled
index 740c3bd3..34cf55ed 100644
--- a/examples/mpu9250.rs.disabled
+++ b/examples/mpu9250.rs.disabled
@@ -29,10 +29,10 @@ fn main() -> ! {
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
 
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
-    // let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
+    // let mut gpiob = dp.GPIOB.split();
 
     let nss = gpioa.pa4.into_push_pull_output(&mut gpioa.crl);
 
@@ -53,7 +53,6 @@ fn main() -> ! {
         mpu9250::MODE,
         1.mhz(),
         clocks,
-        &mut rcc.apb2,
     );
 
     let mut delay = Delay::new(cp.SYST, clocks);
diff --git a/examples/multi_mode_gpio.rs b/examples/multi_mode_gpio.rs
index 56d15fd7..c991d10e 100644
--- a/examples/multi_mode_gpio.rs
+++ b/examples/multi_mode_gpio.rs
@@ -20,14 +20,14 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Acquire the GPIOC peripheral
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
 
     let mut pin = gpioc.pc13.into_floating_input(&mut gpioc.crh);
     // Configure the syst timer to trigger an update every second
diff --git a/examples/nojtag.rs b/examples/nojtag.rs
index d66167d6..b582ce7e 100644
--- a/examples/nojtag.rs
+++ b/examples/nojtag.rs
@@ -13,10 +13,9 @@ use stm32f1xx_hal::{pac, prelude::*};
 fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
-    let mut rcc = p.RCC.constrain();
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
+    let mut gpiob = p.GPIOB.split();
+    let mut afio = p.AFIO.constrain();
 
     let (pa15, pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
 
diff --git a/examples/pwm.rs b/examples/pwm.rs
index 16090885..7f569fc6 100644
--- a/examples/pwm.rs
+++ b/examples/pwm.rs
@@ -21,14 +21,14 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
 
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-    // let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
+    // let mut gpiob = p.GPIOB.split();
 
     // TIM2
     let c1 = gpioa.pa0.into_alternate_push_pull(&mut gpioa.crl);
@@ -50,11 +50,8 @@ fn main() -> ! {
     // let c3 = gpiob.pb8.into_alternate_push_pull(&mut gpiob.crh);
     // let c4 = gpiob.pb9.into_alternate_push_pull(&mut gpiob.crh);
 
-    let mut pwm = Timer::tim2(p.TIM2, &clocks, &mut rcc.apb1).pwm::<Tim2NoRemap, _, _, _>(
-        pins,
-        &mut afio.mapr,
-        1.khz(),
-    );
+    let mut pwm =
+        Timer::tim2(p.TIM2, &clocks).pwm::<Tim2NoRemap, _, _, _>(pins, &mut afio.mapr, 1.khz());
 
     // Enable clock on each of the channels
     pwm.enable(Channel::C1);
diff --git a/examples/pwm_custom.rs b/examples/pwm_custom.rs
index d48f058b..9befa710 100644
--- a/examples/pwm_custom.rs
+++ b/examples/pwm_custom.rs
@@ -16,20 +16,20 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
-    let gpioa = p.GPIOA.split(&mut rcc.apb2);
-    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
+    let gpioa = p.GPIOA.split();
+    let mut gpiob = p.GPIOB.split();
     let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
 
     // TIM3
     let p0 = pb4.into_alternate_push_pull(&mut gpiob.crl);
     let p1 = gpiob.pb5.into_alternate_push_pull(&mut gpiob.crl);
 
-    let pwm = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1).pwm((p0, p1), &mut afio.mapr, 1.khz());
+    let pwm = Timer::tim3(p.TIM3, &clocks).pwm((p0, p1), &mut afio.mapr, 1.khz());
 
     let max = pwm.get_max_duty();
 
diff --git a/examples/pwm_input.rs b/examples/pwm_input.rs
index 622a7ab0..d3166219 100644
--- a/examples/pwm_input.rs
+++ b/examples/pwm_input.rs
@@ -14,20 +14,20 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
     let mut dbg = p.DBGMCU;
 
-    let gpioa = p.GPIOA.split(&mut rcc.apb2);
-    let gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let gpioa = p.GPIOA.split();
+    let gpiob = p.GPIOB.split();
 
     let (_pa15, _pb3, pb4) = afio.mapr.disable_jtag(gpioa.pa15, gpiob.pb3, gpiob.pb4);
     let pb5 = gpiob.pb5;
 
-    let pwm_input = Timer::tim3(p.TIM3, &clocks, &mut rcc.apb1).pwm_input(
+    let pwm_input = Timer::tim3(p.TIM3, &clocks).pwm_input(
         (pb4, pb5),
         &mut afio.mapr,
         &mut dbg,
diff --git a/examples/qei.rs b/examples/qei.rs
index 8a4fce8a..78dc8af7 100644
--- a/examples/qei.rs
+++ b/examples/qei.rs
@@ -17,14 +17,14 @@ fn main() -> ! {
     let cp = cortex_m::Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
 
-    // let gpioa = dp.GPIOA.split(&mut rcc.apb2);
-    let gpiob = dp.GPIOB.split(&mut rcc.apb2);
+    // let gpioa = dp.GPIOA.split();
+    let gpiob = dp.GPIOB.split();
 
     // TIM2
     // let c1 = gpioa.pa0;
@@ -38,11 +38,7 @@ fn main() -> ! {
     let c1 = gpiob.pb6;
     let c2 = gpiob.pb7;
 
-    let qei = Timer::tim4(dp.TIM4, &clocks, &mut rcc.apb1).qei(
-        (c1, c2),
-        &mut afio.mapr,
-        QeiOptions::default(),
-    );
+    let qei = Timer::tim4(dp.TIM4, &clocks).qei((c1, c2), &mut afio.mapr, QeiOptions::default());
     let mut delay = Delay::new(cp.SYST, clocks);
 
     loop {
diff --git a/examples/rtc.rs b/examples/rtc.rs
index 0f2b3e9e..f9aa85e9 100644
--- a/examples/rtc.rs
+++ b/examples/rtc.rs
@@ -16,8 +16,8 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut pwr = p.PWR;
-    let mut rcc = p.RCC.constrain();
-    let mut backup_domain = rcc.bkp.constrain(p.BKP, &mut rcc.apb1, &mut pwr);
+    let rcc = p.RCC.constrain();
+    let mut backup_domain = rcc.bkp.constrain(p.BKP, &mut pwr);
 
     let rtc = Rtc::rtc(p.RTC, &mut backup_domain);
 
diff --git a/examples/serial-dma-circ.rs b/examples/serial-dma-circ.rs
index 956bb970..63bef0fd 100644
--- a/examples/serial-dma-circ.rs
+++ b/examples/serial-dma-circ.rs
@@ -21,15 +21,15 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
-    let channels = p.DMA1.split(&mut rcc.ahb);
+    let mut afio = p.AFIO.constrain();
+    let channels = p.DMA1.split();
 
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-    // let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
+    // let mut gpiob = p.GPIOB.split();
 
     // USART1
     let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -53,7 +53,6 @@ fn main() -> ! {
         &mut afio.mapr,
         Config::default().baudrate(9_600.bps()),
         clocks,
-        &mut rcc.apb2,
     );
 
     let rx = serial.split().1.with_dma(channels.5);
diff --git a/examples/serial-dma-peek.rs b/examples/serial-dma-peek.rs
index a4590636..20b566ca 100644
--- a/examples/serial-dma-peek.rs
+++ b/examples/serial-dma-peek.rs
@@ -20,15 +20,15 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
-    let channels = p.DMA1.split(&mut rcc.ahb);
+    let mut afio = p.AFIO.constrain();
+    let channels = p.DMA1.split();
 
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-    // let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
+    // let mut gpiob = p.GPIOB.split();
 
     // USART1
     let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -52,7 +52,6 @@ fn main() -> ! {
         &mut afio.mapr,
         Config::default(),
         clocks,
-        &mut rcc.apb2,
     );
 
     let rx = serial.split().1.with_dma(channels.5);
diff --git a/examples/serial-dma-rx.rs b/examples/serial-dma-rx.rs
index 1fb33610..225fcb79 100644
--- a/examples/serial-dma-rx.rs
+++ b/examples/serial-dma-rx.rs
@@ -20,15 +20,15 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
-    let channels = p.DMA1.split(&mut rcc.ahb);
+    let mut afio = p.AFIO.constrain();
+    let channels = p.DMA1.split();
 
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-    // let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
+    // let mut gpiob = p.GPIOB.split();
 
     // USART1
     let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -52,7 +52,6 @@ fn main() -> ! {
         &mut afio.mapr,
         Config::default().baudrate(9_600.bps()),
         clocks,
-        &mut rcc.apb2,
     );
 
     let rx = serial.split().1.with_dma(channels.5);
diff --git a/examples/serial-dma-tx.rs b/examples/serial-dma-tx.rs
index 98c5fc2d..dc9c7b56 100644
--- a/examples/serial-dma-tx.rs
+++ b/examples/serial-dma-tx.rs
@@ -20,15 +20,15 @@ fn main() -> ! {
     let p = pac::Peripherals::take().unwrap();
 
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
-    let channels = p.DMA1.split(&mut rcc.ahb);
+    let mut afio = p.AFIO.constrain();
+    let channels = p.DMA1.split();
 
-    let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
-    // let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpioa = p.GPIOA.split();
+    // let mut gpiob = p.GPIOB.split();
 
     // USART1
     let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -52,7 +52,6 @@ fn main() -> ! {
         &mut afio.mapr,
         Config::default().baudrate(9600.bps()),
         clocks,
-        &mut rcc.apb2,
     );
 
     let tx = serial.split().0.with_dma(channels.4);
diff --git a/examples/serial-fmt.rs b/examples/serial-fmt.rs
index 76f8582f..266719d3 100644
--- a/examples/serial-fmt.rs
+++ b/examples/serial-fmt.rs
@@ -26,17 +26,17 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Prepare the alternate function I/O registers
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
 
     // Prepare the GPIOB peripheral
-    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpiob = p.GPIOB.split();
 
     // USART1
     // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -64,7 +64,6 @@ fn main() -> ! {
         &mut afio.mapr,
         Config::default().baudrate(9600.bps()),
         clocks,
-        &mut rcc.apb1,
     );
 
     // Split the serial struct into a receiving and a transmitting part
diff --git a/examples/serial.rs b/examples/serial.rs
index c4944baf..c1b2ef49 100644
--- a/examples/serial.rs
+++ b/examples/serial.rs
@@ -27,17 +27,17 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Prepare the alternate function I/O registers
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
 
     // Prepare the GPIOB peripheral
-    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpiob = p.GPIOB.split();
 
     // USART1
     // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -65,7 +65,6 @@ fn main() -> ! {
         &mut afio.mapr,
         Config::default().baudrate(9600.bps()),
         clocks,
-        &mut rcc.apb1,
     );
 
     // Loopback test. Write `X` and wait until the write is successful.
diff --git a/examples/serial_config.rs b/examples/serial_config.rs
index 27ae3417..a28b37f6 100644
--- a/examples/serial_config.rs
+++ b/examples/serial_config.rs
@@ -25,17 +25,17 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = p.FLASH.constrain();
-    let mut rcc = p.RCC.constrain();
+    let rcc = p.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Prepare the alternate function I/O registers
-    let mut afio = p.AFIO.constrain(&mut rcc.apb2);
+    let mut afio = p.AFIO.constrain();
 
     // Prepare the GPIOB peripheral
-    let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
+    let mut gpiob = p.GPIOB.split();
 
     // USART1
     // let tx = gpioa.pa9.into_alternate_push_pull(&mut gpioa.crh);
@@ -66,7 +66,6 @@ fn main() -> ! {
             .stopbits(serial::StopBits::STOP2)
             .parity_odd(),
         clocks,
-        &mut rcc.apb1,
     );
 
     // Split the serial struct into a receiving and a transmitting part
diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs
index d1f42135..50e7f0c0 100644
--- a/examples/spi-dma.rs
+++ b/examples/spi-dma.rs
@@ -21,14 +21,14 @@ fn main() -> ! {
     // Take ownership over the raw flash and rcc devices and convert them into the corresponding
     // HAL structs
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     // Freeze the configuration of all the clocks in the system and store the frozen frequencies in
     // `clocks`
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
     // Acquire the GPIOB peripheral
-    let mut gpiob = dp.GPIOB.split(&mut rcc.apb2);
+    let mut gpiob = dp.GPIOB.split();
 
     let pins = (
         gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh),
@@ -40,10 +40,10 @@ fn main() -> ! {
         polarity: Polarity::IdleLow,
         phase: Phase::CaptureOnFirstTransition,
     };
-    let spi = Spi::spi2(dp.SPI2, pins, spi_mode, 100.khz(), clocks, &mut rcc.apb1);
+    let spi = Spi::spi2(dp.SPI2, pins, spi_mode, 100.khz(), clocks);
 
     // Set up the DMA device
-    let dma = dp.DMA1.split(&mut rcc.ahb);
+    let dma = dp.DMA1.split();
 
     // Connect the SPI device to the DMA
     let spi_dma = spi.with_tx_dma(dma.5);
diff --git a/examples/spi.rs b/examples/spi.rs
index 4ef51277..b57d1d43 100644
--- a/examples/spi.rs
+++ b/examples/spi.rs
@@ -26,12 +26,12 @@ fn setup() -> (
     let dp = Peripherals::take().unwrap();
 
     let mut flash = dp.FLASH.constrain();
-    let mut rcc = dp.RCC.constrain();
+    let rcc = dp.RCC.constrain();
 
     let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
-    let mut afio = dp.AFIO.constrain(&mut rcc.apb2);
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+    let mut afio = dp.AFIO.constrain();
+    let mut gpioa = dp.GPIOA.split();
 
     // SPI1
     let sck = gpioa.pa5.into_alternate_push_pull(&mut gpioa.crl);
@@ -46,7 +46,6 @@ fn setup() -> (
         MODE,
         1_u32.mhz(),
         clocks,
-        &mut rcc.apb2,
     );
 
     (spi, cs)
diff --git a/examples/timer-interrupt-rtic.rs b/examples/timer-interrupt-rtic.rs
index a103c1e5..598f8417 100644
--- a/examples/timer-interrupt-rtic.rs
+++ b/examples/timer-interrupt-rtic.rs
@@ -35,14 +35,14 @@ const APP: () = {
         // Take ownership over the raw flash and rcc devices and convert them into the corresponding
         // HAL structs
         let mut flash = cx.device.FLASH.constrain();
-        let mut rcc = cx.device.RCC.constrain();
+        let rcc = cx.device.RCC.constrain();
 
         // Freeze the configuration of all the clocks in the system and store the frozen frequencies
         // in `clocks`
         let clocks = rcc.cfgr.freeze(&mut flash.acr);
 
         // Acquire the GPIOC peripheral
-        let mut gpioc = cx.device.GPIOC.split(&mut rcc.apb2);
+        let mut gpioc = cx.device.GPIOC.split();
 
         // Configure gpio C pin 13 as a push-pull output. The `crh` register is passed to the
         // function in order to configure the port. For pins 0-7, crl should be passed instead
@@ -50,8 +50,7 @@ const APP: () = {
             .pc13
             .into_push_pull_output_with_state(&mut gpioc.crh, PinState::High);
         // Configure the syst timer to trigger an update every second and enables interrupt
-        let mut timer =
-            Timer::tim1(cx.device.TIM1, &clocks, &mut rcc.apb2).start_count_down(1.hz());
+        let mut timer = Timer::tim1(cx.device.TIM1, &clocks).start_count_down(1.hz());
         timer.listen(Event::Update);
 
         // Init the static resources to use them later through RTIC
diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs
index 703da87c..f4d57cc6 100644
--- a/examples/usb_serial.rs
+++ b/examples/usb_serial.rs
@@ -35,11 +35,11 @@ fn main() -> ! {
     assert!(clocks.usbclk_valid());
 
     // Configure the on-board LED (PC13, green)
-    let mut gpioc = dp.GPIOC.split(&mut rcc.apb2);
+    let mut gpioc = dp.GPIOC.split();
     let mut led = gpioc.pc13.into_push_pull_output(&mut gpioc.crh);
     led.set_high(); // Turn off
 
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
 
     // BluePill board has a pull-up resistor on the D+ line.
     // Pull the D+ pin down to send a RESET condition to the USB bus.
diff --git a/examples/usb_serial_interrupt.rs b/examples/usb_serial_interrupt.rs
index 123897ae..bafcd07f 100644
--- a/examples/usb_serial_interrupt.rs
+++ b/examples/usb_serial_interrupt.rs
@@ -34,7 +34,7 @@ fn main() -> ! {
 
     assert!(clocks.usbclk_valid());
 
-    let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+    let mut gpioa = dp.GPIOA.split();
 
     // BluePill board has a pull-up resistor on the D+ line.
     // Pull the D+ pin down to send a RESET condition to the USB bus.
diff --git a/examples/usb_serial_rtic.rs b/examples/usb_serial_rtic.rs
index ac0dc2da..d9b5eb77 100644
--- a/examples/usb_serial_rtic.rs
+++ b/examples/usb_serial_rtic.rs
@@ -37,7 +37,7 @@ const APP: () = {
 
         assert!(clocks.usbclk_valid());
 
-        let mut gpioa = cx.device.GPIOA.split(&mut rcc.apb2);
+        let mut gpioa = cx.device.GPIOA.split();
 
         // BluePill board has a pull-up resistor on the D+ line.
         // Pull the D+ pin down to send a RESET condition to the USB bus.
diff --git a/src/adc.rs b/src/adc.rs
index a0f3384a..eb7c6960 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -6,16 +6,16 @@ use embedded_hal::adc::{Channel, OneShot};
 use crate::dma::{dma1::C1, CircBuffer, Receive, RxDma, Transfer, TransferPayload, W};
 use crate::gpio::Analog;
 use crate::gpio::{gpioa, gpiob, gpioc};
-use crate::rcc::{Clocks, Enable, Reset, APB2};
+use crate::rcc::{Clocks, Enable, Reset};
 use core::sync::atomic::{self, Ordering};
 use cortex_m::asm::delay;
 use embedded_dma::StaticWriteBuffer;
 
-use crate::pac::ADC1;
 #[cfg(feature = "stm32f103")]
 use crate::pac::ADC2;
 #[cfg(all(feature = "stm32f103", feature = "high",))]
 use crate::pac::ADC3;
+use crate::pac::{ADC1, RCC};
 
 /// Continuous mode
 pub struct Continuous;
@@ -168,16 +168,16 @@ macro_rules! adc_hal {
                 ///
                 /// Sets all configurable parameters to one-shot defaults,
                 /// performs a boot-time calibration.
-                pub fn $adc(adc: $ADC, apb2: &mut APB2, clocks: Clocks) -> Self {
+                pub fn $adc(adc: $ADC, clocks: Clocks) -> Self {
                     let mut s = Self {
                         rb: adc,
                         sample_time: SampleTime::default(),
                         align: Align::default(),
                         clocks,
                     };
-                    s.enable_clock(apb2);
+                    s.enable_clock();
                     s.power_down();
-                    s.reset(apb2);
+                    s.reset();
                     s.setup_oneshot();
                     s.power_up();
 
@@ -255,16 +255,19 @@ macro_rules! adc_hal {
                     self.rb.cr2.modify(|_, w| w.adon().clear_bit());
                 }
 
-                fn reset(&mut self, apb2: &mut APB2) {
-                    $ADC::reset(apb2);
+                fn reset(&mut self) {
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $ADC::reset(rcc);
                 }
 
-                fn enable_clock(&mut self, apb2: &mut APB2) {
-                    $ADC::enable(apb2);
+                fn enable_clock(&mut self) {
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $ADC::enable(rcc);
                 }
 
-                fn disable_clock(&mut self, apb2: &mut APB2) {
-                    $ADC::disable(apb2);
+                fn disable_clock(&mut self) {
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $ADC::disable(rcc);
                 }
 
                 fn calibrate(&mut self) {
@@ -393,9 +396,9 @@ macro_rules! adc_hal {
                 }
 
                 /// Powers down the ADC, disables the ADC clock and releases the ADC Peripheral
-                pub fn release(mut self, apb2: &mut APB2) -> $ADC {
+                pub fn release(mut self) -> $ADC {
                     self.power_down();
-                    self.disable_clock(apb2);
+                    self.disable_clock();
                     self.rb
                 }
             }
diff --git a/src/afio.rs b/src/afio.rs
index 2c2e8772..5860d0eb 100644
--- a/src/afio.rs
+++ b/src/afio.rs
@@ -1,7 +1,7 @@
 //! # Alternate Function I/Os
-use crate::pac::{afio, AFIO};
+use crate::pac::{afio, AFIO, RCC};
 
-use crate::rcc::{Enable, Reset, APB2};
+use crate::rcc::{Enable, Reset};
 
 use crate::gpio::{
     gpioa::PA15,
@@ -10,13 +10,14 @@ use crate::gpio::{
 };
 
 pub trait AfioExt {
-    fn constrain(self, apb2: &mut APB2) -> Parts;
+    fn constrain(self) -> Parts;
 }
 
 impl AfioExt for AFIO {
-    fn constrain(self, apb2: &mut APB2) -> Parts {
-        AFIO::enable(apb2);
-        AFIO::reset(apb2);
+    fn constrain(self) -> Parts {
+        let rcc = unsafe { &(*RCC::ptr()) };
+        AFIO::enable(rcc);
+        AFIO::reset(rcc);
 
         Parts {
             evcr: EVCR { _0: () },
diff --git a/src/can.rs b/src/can.rs
index 0662be53..7ccf90a6 100644
--- a/src/can.rs
+++ b/src/can.rs
@@ -27,12 +27,11 @@ use crate::gpio::{
     gpiob::{PB8, PB9},
     Alternate, Floating, Input, PushPull,
 };
-use crate::pac::CAN1;
 #[cfg(feature = "connectivity")]
 use crate::pac::CAN2;
 #[cfg(not(feature = "connectivity"))]
 use crate::pac::USB;
-use crate::rcc::APB1;
+use crate::pac::{CAN1, RCC};
 
 mod sealed {
     pub trait Sealed {}
@@ -96,22 +95,26 @@ pub struct Can<Instance> {
 
 impl<Instance> Can<Instance>
 where
-    Instance: crate::rcc::Enable<Bus = APB1>,
+    Instance: crate::rcc::Enable,
 {
     /// Creates a CAN interaface.
     ///
     /// CAN shares SRAM with the USB peripheral. Take ownership of USB to
     /// prevent accidental shared usage.
     #[cfg(not(feature = "connectivity"))]
-    pub fn new(can: Instance, apb: &mut APB1, _usb: USB) -> Can<Instance> {
-        Instance::enable(apb);
+    pub fn new(can: Instance, _usb: USB) -> Can<Instance> {
+        let rcc = unsafe { &(*RCC::ptr()) };
+        Instance::enable(rcc);
+
         Can { _peripheral: can }
     }
 
     /// Creates a CAN interaface.
     #[cfg(feature = "connectivity")]
-    pub fn new(can: Instance, apb: &mut APB1) -> Can<Instance> {
-        Instance::enable(apb);
+    pub fn new(can: Instance) -> Can<Instance> {
+        let rcc = unsafe { &(*RCC::ptr()) };
+        Instance::enable(rcc);
+
         Can { _peripheral: can }
     }
 
diff --git a/src/crc.rs b/src/crc.rs
index a7736758..252ee171 100644
--- a/src/crc.rs
+++ b/src/crc.rs
@@ -1,18 +1,20 @@
 //! CRC
 
-use crate::pac::CRC;
-use crate::rcc::{Enable, AHB};
+use crate::pac::{CRC, RCC};
+use crate::rcc::Enable;
 
 /// Extension trait to constrain the CRC peripheral
 pub trait CrcExt {
     /// Constrains the CRC peripheral to play nicely with the other abstractions
     #[allow(clippy::wrong_self_convention, clippy::new_ret_no_self)]
-    fn new(self, ahb: &mut AHB) -> Crc;
+    fn new(self) -> Crc;
 }
 
 impl CrcExt for CRC {
-    fn new(self, ahb: &mut AHB) -> Crc {
-        CRC::enable(ahb);
+    fn new(self) -> Crc {
+        let rcc = unsafe { &(*RCC::ptr()) };
+        CRC::enable(rcc);
+
         Crc { crc: self }
     }
 }
diff --git a/src/dma.rs b/src/dma.rs
index dd9e8579..e04eca48 100644
--- a/src/dma.rs
+++ b/src/dma.rs
@@ -7,8 +7,6 @@ use core::{
 };
 use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
 
-use crate::rcc::AHB;
-
 #[derive(Debug)]
 #[non_exhaustive]
 pub enum Error {
@@ -52,7 +50,7 @@ where
 pub trait DmaExt {
     type Channels;
 
-    fn split(self, ahb: &mut AHB) -> Self::Channels;
+    fn split(self) -> Self::Channels;
 }
 
 pub trait TransferPayload {
@@ -126,10 +124,10 @@ macro_rules! dma {
             pub mod $dmaX {
                 use core::{sync::atomic::{self, Ordering}, ptr, mem};
 
-                use crate::pac::{$DMAX, dma1};
+                use crate::pac::{RCC, $DMAX, dma1};
 
                 use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, RxTxDma, TransferPayload};
-                use crate::rcc::{AHB, Enable};
+                use crate::rcc::Enable;
 
                 #[allow(clippy::manual_non_exhaustive)]
                 pub struct Channels((), $(pub $CX),+);
@@ -448,8 +446,9 @@ macro_rules! dma {
                 impl DmaExt for $DMAX {
                     type Channels = Channels;
 
-                    fn split(self, ahb: &mut AHB) -> Channels {
-                        $DMAX::enable(ahb);
+                    fn split(self) -> Channels {
+                        let rcc = unsafe { &(*RCC::ptr()) };
+                        $DMAX::enable(rcc);
 
                         // reset the DMA control registers (stops all on-going transfers)
                         $(
diff --git a/src/gpio.rs b/src/gpio.rs
index 1b3ed80e..faf3365e 100644
--- a/src/gpio.rs
+++ b/src/gpio.rs
@@ -6,12 +6,9 @@
 //! ```rust
 //! // Acquire the GPIOC peripheral
 //! // NOTE: `dp` is the device peripherals from the `PAC` crate
-//! let mut gpioa = dp.GPIOA.split(&mut rcc.apb2);
+//! let mut gpioa = dp.GPIOA.split();
 //! ```
 //!
-//! See the documentation for [rcc::APB2](../rcc/struct.APB2.html) for details about the input parameter to
-//! `split`.
-//!
 //! This gives you a struct containing two control registers `crl` and `crh`, and all the pins
 //! `px0..px15`. These structs are what you use to interract with the pins to change their modes,
 //! or their inputs or outputs. For example, to set `pa5` high, you would call
@@ -82,7 +79,6 @@ use core::marker::PhantomData;
 use crate::afio;
 use crate::hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
 use crate::pac::{self, EXTI};
-use crate::rcc::APB2;
 
 mod partially_erased;
 pub use partially_erased::{PEPin, PartiallyErasedPin};
@@ -121,7 +117,7 @@ pub trait GpioExt {
     type Parts;
 
     /// Splits the GPIO block into independent pins and registers
-    fn split(self, apb2: &mut APB2) -> Self::Parts;
+    fn split(self) -> Self::Parts;
 }
 
 /// Marker trait for active states.
@@ -349,8 +345,8 @@ macro_rules! gpio {
         /// GPIO
         pub mod $gpiox {
             use core::marker::PhantomData;
-            use crate::pac::$GPIOX;
-            use crate::rcc::{APB2, Enable, Reset};
+            use crate::pac::{$GPIOX, RCC};
+            use crate::rcc::{Enable, Reset};
             use super::{Active, Floating, GpioExt, Input, PartiallyErasedPin, ErasedPin, Pin, CRL, CRH, Cr};
             #[allow(unused)]
             use super::Debugger;
@@ -374,9 +370,10 @@ macro_rules! gpio {
             impl GpioExt for $GPIOX {
                 type Parts = Parts;
 
-                fn split(self, apb: &mut APB2) -> Parts {
-                    $GPIOX::enable(apb);
-                    $GPIOX::reset(apb);
+                fn split(self) -> Parts {
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $GPIOX::enable(rcc);
+                    $GPIOX::reset(rcc);
 
                     Parts {
                         crl: Cr::<CRL, $port_id> { _cr: PhantomData },
diff --git a/src/i2c.rs b/src/i2c.rs
index 56d22a4e..df045bbe 100644
--- a/src/i2c.rs
+++ b/src/i2c.rs
@@ -8,8 +8,8 @@ use crate::afio::MAPR;
 use crate::gpio::gpiob::{PB10, PB11, PB6, PB7, PB8, PB9};
 use crate::gpio::{Alternate, OpenDrain};
 use crate::hal::blocking::i2c::{Read, Write, WriteRead};
-use crate::pac::{DWT, I2C1, I2C2};
-use crate::rcc::{Clocks, Enable, GetBusFreq, Reset, APB1};
+use crate::pac::{DWT, I2C1, I2C2, RCC};
+use crate::rcc::{Clocks, Enable, GetBusFreq, Reset};
 use crate::time::Hertz;
 use core::ops::Deref;
 use nb::Error::{Other, WouldBlock};
@@ -110,19 +110,12 @@ pub struct BlockingI2c<I2C, PINS> {
 
 impl<PINS> I2c<I2C1, PINS> {
     /// Creates a generic I2C1 object on pins PB6 and PB7 or PB8 and PB9 (if remapped)
-    pub fn i2c1(
-        i2c: I2C1,
-        pins: PINS,
-        mapr: &mut MAPR,
-        mode: Mode,
-        clocks: Clocks,
-        apb: &mut APB1,
-    ) -> Self
+    pub fn i2c1(i2c: I2C1, pins: PINS, mapr: &mut MAPR, mode: Mode, clocks: Clocks) -> Self
     where
         PINS: Pins<I2C1>,
     {
         mapr.modify_mapr(|_, w| w.i2c1_remap().bit(PINS::REMAP));
-        I2c::<I2C1, _>::_i2c(i2c, pins, mode, clocks, apb)
+        I2c::<I2C1, _>::_i2c(i2c, pins, mode, clocks)
     }
 }
 
@@ -135,7 +128,6 @@ impl<PINS> BlockingI2c<I2C1, PINS> {
         mapr: &mut MAPR,
         mode: Mode,
         clocks: Clocks,
-        apb: &mut APB1,
         start_timeout_us: u32,
         start_retries: u8,
         addr_timeout_us: u32,
@@ -150,7 +142,6 @@ impl<PINS> BlockingI2c<I2C1, PINS> {
             pins,
             mode,
             clocks,
-            apb,
             start_timeout_us,
             start_retries,
             addr_timeout_us,
@@ -161,11 +152,11 @@ impl<PINS> BlockingI2c<I2C1, PINS> {
 
 impl<PINS> I2c<I2C2, PINS> {
     /// Creates a generic I2C2 object on pins PB10 and PB11 using the embedded-hal `BlockingI2c` trait.
-    pub fn i2c2(i2c: I2C2, pins: PINS, mode: Mode, clocks: Clocks, apb: &mut APB1) -> Self
+    pub fn i2c2(i2c: I2C2, pins: PINS, mode: Mode, clocks: Clocks) -> Self
     where
         PINS: Pins<I2C2>,
     {
-        I2c::<I2C2, _>::_i2c(i2c, pins, mode, clocks, apb)
+        I2c::<I2C2, _>::_i2c(i2c, pins, mode, clocks)
     }
 }
 
@@ -177,7 +168,6 @@ impl<PINS> BlockingI2c<I2C2, PINS> {
         pins: PINS,
         mode: Mode,
         clocks: Clocks,
-        apb: &mut APB1,
         start_timeout_us: u32,
         start_retries: u8,
         addr_timeout_us: u32,
@@ -191,7 +181,6 @@ impl<PINS> BlockingI2c<I2C2, PINS> {
             pins,
             mode,
             clocks,
-            apb,
             start_timeout_us,
             start_retries,
             addr_timeout_us,
@@ -276,9 +265,10 @@ where
     I2C::Bus: GetBusFreq,
 {
     /// Configures the I2C peripheral to work in master mode
-    fn _i2c(i2c: I2C, pins: PINS, mode: Mode, clocks: Clocks, apb: &mut I2C::Bus) -> Self {
-        I2C::enable(apb);
-        I2C::reset(apb);
+    fn _i2c(i2c: I2C, pins: PINS, mode: Mode, clocks: Clocks) -> Self {
+        let rcc = unsafe { &(*RCC::ptr()) };
+        I2C::enable(rcc);
+        I2C::reset(rcc);
 
         let pclk1 = I2C::Bus::get_frequency(&clocks).0;
 
@@ -407,14 +397,13 @@ where
         pins: PINS,
         mode: Mode,
         clocks: Clocks,
-        apb: &mut I2C::Bus,
         start_timeout_us: u32,
         start_retries: u8,
         addr_timeout_us: u32,
         data_timeout_us: u32,
     ) -> Self {
         blocking_i2c(
-            I2c::<I2C, _>::_i2c(i2c, pins, mode, clocks, apb),
+            I2c::<I2C, _>::_i2c(i2c, pins, mode, clocks),
             clocks,
             start_timeout_us,
             start_retries,
diff --git a/src/pwm_input.rs b/src/pwm_input.rs
index d3cb9109..8a4a5ac9 100644
--- a/src/pwm_input.rs
+++ b/src/pwm_input.rs
@@ -13,7 +13,7 @@ use crate::pac::{TIM2, TIM3};
 
 use crate::afio::MAPR;
 use crate::gpio::{self, Floating, Input};
-use crate::rcc::{sealed::RccBus, Clocks, GetBusFreq};
+use crate::rcc::{Clocks, GetBusFreq, RccBus};
 use crate::time::Hertz;
 use crate::timer::Timer;
 
diff --git a/src/rcc.rs b/src/rcc.rs
index 111b0fb6..a9e7ff78 100644
--- a/src/rcc.rs
+++ b/src/rcc.rs
@@ -10,6 +10,8 @@ use crate::time::Hertz;
 
 use crate::backup_domain::BackupDomain;
 
+mod enable;
+
 /// Extension trait that constrains the `RCC` peripheral
 pub trait RccExt {
     /// Constrains the `RCC` peripheral so it plays nicely with the other abstractions
@@ -19,9 +21,6 @@ pub trait RccExt {
 impl RccExt for RCC {
     fn constrain(self) -> Rcc {
         Rcc {
-            ahb: AHB { _0: () },
-            apb1: APB1 { _0: () },
-            apb2: APB2 { _0: () },
             cfgr: CFGR {
                 hse: None,
                 hclk: None,
@@ -45,92 +44,56 @@ impl RccExt for RCC {
 /// let mut rcc = dp.RCC.constrain();
 /// ```
 pub struct Rcc {
-    /// AMBA High-performance Bus (AHB) registers
-    pub ahb: AHB,
-    /// Advanced Peripheral Bus 1 (APB1) registers
-    pub apb1: APB1,
-    /// Advanced Peripheral Bus 2 (APB2) registers
-    pub apb2: APB2,
     pub cfgr: CFGR,
     pub bkp: BKP,
 }
 
 /// AMBA High-performance Bus (AHB) registers
-///
-/// Aquired through the `Rcc` registers:
-///
-/// ```rust
-/// let dp = pac::Peripherals::take().unwrap();
-/// let mut rcc = dp.RCC.constrain();
-/// function_that_uses_ahb(&mut rcc.ahb)
-/// ```
 pub struct AHB {
     _0: (),
 }
 
 impl AHB {
-    // TODO remove `allow`
-    #[allow(dead_code)]
-    pub(crate) fn enr(&mut self) -> &rcc::AHBENR {
-        // NOTE(unsafe) this proxy grants exclusive access to this register
-        unsafe { &(*RCC::ptr()).ahbenr }
+    fn enr(rcc: &rcc::RegisterBlock) -> &rcc::AHBENR {
+        &rcc.ahbenr
     }
 }
 
 /// Advanced Peripheral Bus 1 (APB1) registers
-///
-/// Aquired through the `Rcc` registers:
-///
-/// ```rust
-/// let dp = pac::Peripherals::take().unwrap();
-/// let mut rcc = dp.RCC.constrain();
-/// function_that_uses_apb1(&mut rcc.apb1)
-/// ```
 pub struct APB1 {
     _0: (),
 }
 
 impl APB1 {
-    pub(crate) fn enr(&mut self) -> &rcc::APB1ENR {
-        // NOTE(unsafe) this proxy grants exclusive access to this register
-        unsafe { &(*RCC::ptr()).apb1enr }
+    fn enr(rcc: &rcc::RegisterBlock) -> &rcc::APB1ENR {
+        &rcc.apb1enr
     }
 
-    pub(crate) fn rstr(&mut self) -> &rcc::APB1RSTR {
-        // NOTE(unsafe) this proxy grants exclusive access to this register
-        unsafe { &(*RCC::ptr()).apb1rstr }
+    fn rstr(rcc: &rcc::RegisterBlock) -> &rcc::APB1RSTR {
+        &rcc.apb1rstr
     }
 }
 
 impl APB1 {
     /// Set power interface clock (PWREN) bit in RCC_APB1ENR
-    pub fn set_pwren(&mut self) {
-        self.enr().modify(|_r, w| w.pwren().set_bit())
+    pub fn set_pwren() {
+        let rcc = unsafe { &*RCC::ptr() };
+        PWR::enable(rcc);
     }
 }
 
 /// Advanced Peripheral Bus 2 (APB2) registers
-///
-/// Aquired through the `Rcc` registers:
-///
-/// ```rust
-/// let dp = pac::Peripherals::take().unwrap();
-/// let mut rcc = dp.RCC.constrain();
-/// function_that_uses_apb2(&mut rcc.apb2);
-/// ```
 pub struct APB2 {
     _0: (),
 }
 
 impl APB2 {
-    pub(crate) fn enr(&mut self) -> &rcc::APB2ENR {
-        // NOTE(unsafe) this proxy grants exclusive access to this register
-        unsafe { &(*RCC::ptr()).apb2enr }
+    fn enr(rcc: &rcc::RegisterBlock) -> &rcc::APB2ENR {
+        &rcc.apb2enr
     }
 
-    pub(crate) fn rstr(&mut self) -> &rcc::APB2RSTR {
-        // NOTE(unsafe) this proxy grants exclusive access to this register
-        unsafe { &(*RCC::ptr()).apb2rstr }
+    fn rstr(rcc: &rcc::RegisterBlock) -> &rcc::APB2RSTR {
+        &rcc.apb2rstr
     }
 }
 
@@ -455,10 +418,10 @@ pub struct BKP {
 
 impl BKP {
     /// Enables write access to the registers in the backup domain
-    pub fn constrain(self, bkp: crate::pac::BKP, apb1: &mut APB1, pwr: &mut PWR) -> BackupDomain {
+    pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain {
         // Enable the backup interface by setting PWREN and BKPEN
-        apb1.enr()
-            .modify(|_r, w| w.bkpen().set_bit().pwren().set_bit());
+        let rcc = unsafe { &(*RCC::ptr()) };
+        crate::pac::BKP::enable(rcc);
 
         // Enable access to the backup registers
         pwr.cr.modify(|_r, w| w.dbp().set_bit());
@@ -577,190 +540,23 @@ impl GetBusFreq for APB2 {
 }
 
 pub(crate) mod sealed {
-    /// Bus associated to peripheral
-    pub trait RccBus {
-        /// Bus type;
-        type Bus;
-    }
+
+    pub trait Sealed {}
+}
+use sealed::Sealed;
+
+/// Bus associated to peripheral
+pub trait RccBus {
+    /// Bus type;
+    type Bus;
 }
-use sealed::RccBus;
 
 /// Enable/disable peripheral
 pub trait Enable: RccBus {
-    fn enable(apb: &mut Self::Bus);
-    fn disable(apb: &mut Self::Bus);
+    fn enable(rcc: &rcc::RegisterBlock);
+    fn disable(rcc: &rcc::RegisterBlock);
 }
-
 /// Reset peripheral
 pub trait Reset: RccBus {
-    fn reset(apb: &mut Self::Bus);
-}
-
-macro_rules! bus {
-    ($($PER:ident => ($apbX:ty, $peren:ident, $perrst:ident),)+) => {
-        $(
-            impl RccBus for crate::pac::$PER {
-                type Bus = $apbX;
-            }
-            impl Enable for crate::pac::$PER {
-                #[inline(always)]
-                fn enable(apb: &mut Self::Bus) {
-                    apb.enr().modify(|_, w| w.$peren().set_bit());
-                }
-                #[inline(always)]
-                fn disable(apb: &mut Self::Bus) {
-                    apb.enr().modify(|_, w| w.$peren().clear_bit());
-                }
-            }
-            impl Reset for crate::pac::$PER {
-                #[inline(always)]
-                fn reset(apb: &mut Self::Bus) {
-                    apb.rstr().modify(|_, w| w.$perrst().set_bit());
-                    apb.rstr().modify(|_, w| w.$perrst().clear_bit());
-                }
-            }
-        )+
-    }
-}
-
-macro_rules! ahb_bus {
-    ($($PER:ident => ($peren:ident),)+) => {
-        $(
-            impl RccBus for crate::pac::$PER {
-                type Bus = AHB;
-            }
-            impl Enable for crate::pac::$PER {
-                #[inline(always)]
-                fn enable(apb: &mut Self::Bus) {
-                    apb.enr().modify(|_, w| w.$peren().set_bit());
-                }
-                #[inline(always)]
-                fn disable(apb: &mut Self::Bus) {
-                    apb.enr().modify(|_, w| w.$peren().clear_bit());
-                }
-            }
-        )+
-    }
-}
-
-#[cfg(feature = "stm32f103")]
-bus! {
-    ADC2 => (APB2, adc2en, adc2rst),
-    CAN1 => (APB1, canen, canrst),
-}
-#[cfg(feature = "connectivity")]
-bus! {
-    ADC2 => (APB2, adc2en, adc2rst),
-    CAN1 => (APB1, can1en, can1rst),
-    CAN2 => (APB1, can2en, can2rst),
-}
-#[cfg(all(feature = "stm32f103", feature = "high",))]
-bus! {
-    ADC3 => (APB2, adc3en, adc3rst),
-    DAC => (APB1, dacen, dacrst),
-    UART4 => (APB1, uart4en, uart4rst),
-    UART5 => (APB1, uart5en, uart5rst),
-}
-bus! {
-    ADC1 => (APB2, adc1en, adc1rst),
-    AFIO => (APB2, afioen, afiorst),
-    GPIOA => (APB2, iopaen, ioparst),
-    GPIOB => (APB2, iopben, iopbrst),
-    GPIOC => (APB2, iopcen, iopcrst),
-    GPIOD => (APB2, iopden, iopdrst),
-    GPIOE => (APB2, iopeen, ioperst),
-    I2C1 => (APB1, i2c1en, i2c1rst),
-    I2C2 => (APB1, i2c2en, i2c2rst),
-    SPI1 => (APB2, spi1en, spi1rst),
-    SPI2 => (APB1, spi2en, spi2rst),
-    USART1 => (APB2, usart1en, usart1rst),
-    USART2 => (APB1, usart2en, usart2rst),
-    USART3 => (APB1, usart3en, usart3rst),
-    WWDG => (APB1, wwdgen, wwdgrst),
-}
-
-#[cfg(any(feature = "xl", feature = "high"))]
-bus! {
-    GPIOF => (APB2, iopfen, iopfrst),
-    GPIOG => (APB2, iopgen, iopgrst),
-}
-
-#[cfg(any(feature = "high", feature = "connectivity"))]
-bus! {
-    SPI3 => (APB1, spi3en, spi3rst),
-}
-
-ahb_bus! {
-    CRC => (crcen),
-    DMA1 => (dma1en),
-    DMA2 => (dma2en),
-}
-
-#[cfg(feature = "high")]
-ahb_bus! {
-    FSMC => (fsmcen),
-}
-
-bus! {
-    TIM2 => (APB1, tim2en, tim2rst),
-    TIM3 => (APB1, tim3en, tim3rst),
-}
-
-#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
-bus! {
-    TIM1 => (APB2, tim1en, tim1rst),
-}
-
-#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
-bus! {
-    TIM6 => (APB1, tim6en, tim6rst),
-}
-
-#[cfg(any(
-    all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
-    any(feature = "stm32f100", feature = "connectivity")
-))]
-bus! {
-    TIM7 => (APB1, tim7en, tim7rst),
-}
-
-#[cfg(feature = "stm32f100")]
-bus! {
-    TIM15 => (APB2, tim15en, tim15rst),
-    TIM16 => (APB2, tim16en, tim16rst),
-    TIM17 => (APB2, tim17en, tim17rst),
-}
-
-#[cfg(feature = "medium")]
-bus! {
-    TIM4 => (APB1, tim4en, tim4rst),
-}
-
-#[cfg(any(feature = "high", feature = "connectivity"))]
-bus! {
-    TIM5 => (APB1, tim5en, tim5rst),
-}
-
-#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
-bus! {
-    TIM12 => (APB1, tim12en, tim12rst),
-    TIM13 => (APB1, tim13en, tim13rst),
-    TIM14 => (APB1, tim14en, tim14rst),
-}
-
-#[cfg(all(feature = "stm32f103", feature = "high",))]
-bus! {
-    TIM8 => (APB2, tim8en, tim8rst),
-}
-
-#[cfg(feature = "xl")]
-bus! {
-    TIM9 => (APB2, tim9en, tim9rst),
-    TIM10 => (APB2, tim10en, tim10rst),
-    TIM11 => (APB2, tim11en, tim11rst),
-}
-
-#[cfg(any(feature = "stm32f102", feature = "stm32f103"))]
-bus! {
-    USB => (APB1, usben, usbrst),
+    fn reset(rcc: &rcc::RegisterBlock);
 }
diff --git a/src/rcc/enable.rs b/src/rcc/enable.rs
new file mode 100644
index 00000000..d09622c3
--- /dev/null
+++ b/src/rcc/enable.rs
@@ -0,0 +1,185 @@
+use super::*;
+use crate::bb;
+
+macro_rules! bus {
+    ($($PER:ident => ($apbX:ty, $bit:literal),)+) => {
+        $(
+            impl Sealed for crate::pac::$PER {}
+
+            impl RccBus for crate::pac::$PER {
+                type Bus = $apbX;
+            }
+            impl Enable for crate::pac::$PER {
+                #[inline(always)]
+                fn enable(rcc: &rcc::RegisterBlock) {
+                    unsafe {
+                        bb::set(Self::Bus::enr(rcc), $bit);
+                    }
+                }
+                #[inline(always)]
+                fn disable(rcc: &rcc::RegisterBlock) {
+                    unsafe {
+                        bb::clear(Self::Bus::enr(rcc), $bit);
+                    }
+                }
+            }
+            impl Reset for crate::pac::$PER {
+                #[inline(always)]
+                fn reset(rcc: &rcc::RegisterBlock) {
+                    unsafe {
+                        bb::set(Self::Bus::rstr(rcc), $bit);
+                        bb::clear(Self::Bus::rstr(rcc), $bit);
+                    }
+                }
+            }
+        )+
+    }
+}
+
+macro_rules! ahb_bus {
+    ($($PER:ident => ($bit:literal),)+) => {
+        $(
+            impl RccBus for crate::pac::$PER {
+                type Bus = AHB;
+            }
+            impl Enable for crate::pac::$PER {
+                #[inline(always)]
+                fn enable(rcc: &rcc::RegisterBlock) {
+                    unsafe {
+                        bb::set(Self::Bus::enr(rcc), $bit);
+                    }
+                }
+                #[inline(always)]
+                fn disable(rcc: &rcc::RegisterBlock) {
+                    unsafe {
+                        bb::clear(Self::Bus::enr(rcc), $bit);
+                    }
+                }
+            }
+        )+
+    }
+}
+
+#[cfg(feature = "stm32f103")]
+bus! {
+    ADC2 => (APB2, 10),
+    CAN1 => (APB1, 25),
+}
+#[cfg(feature = "connectivity")]
+bus! {
+    ADC2 => (APB2, 10),
+    CAN1 => (APB1, 25),
+    CAN2 => (APB1, 26),
+}
+#[cfg(all(feature = "stm32f103", feature = "high"))]
+bus! {
+    ADC3 => (APB2, 15),
+    DAC => (APB1, 29),
+    UART4 => (APB1, 19),
+    UART5 => (APB1, 20),
+}
+bus! {
+    ADC1 => (APB2, 9),
+    AFIO => (APB2, 0),
+    BKP => (APB1, 27),
+    GPIOA => (APB2, 2),
+    GPIOB => (APB2, 3),
+    GPIOC => (APB2, 4),
+    GPIOD => (APB2, 5),
+    GPIOE => (APB2, 6),
+    I2C1 => (APB1, 21),
+    I2C2 => (APB1, 22),
+    PWR => (APB1, 28),
+    SPI1 => (APB2, 12),
+    SPI2 => (APB1, 14),
+    USART1 => (APB2, 14),
+    USART2 => (APB1, 17),
+    USART3 => (APB1, 18),
+    WWDG => (APB1, 11),
+}
+
+#[cfg(any(feature = "xl", feature = "high"))]
+bus! {
+    GPIOF => (APB2, 7),
+    GPIOG => (APB2, 8),
+}
+
+#[cfg(any(feature = "high", feature = "connectivity"))]
+bus! {
+    SPI3 => (APB1, 15),
+}
+
+ahb_bus! {
+    CRC => (6),
+    DMA1 => (0),
+    DMA2 => (1),
+}
+
+#[cfg(feature = "high")]
+ahb_bus! {
+    FSMC => (8),
+}
+
+bus! {
+    TIM2 => (APB1, 0),
+    TIM3 => (APB1, 1),
+}
+
+#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
+bus! {
+    TIM1 => (APB2, 11),
+}
+
+#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
+bus! {
+    TIM6 => (APB1, 4),
+}
+
+#[cfg(any(
+    all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
+    any(feature = "stm32f100", feature = "connectivity")
+))]
+bus! {
+    TIM7 => (APB1, 5),
+}
+
+#[cfg(feature = "stm32f100")]
+bus! {
+    TIM15 => (APB2, 16),
+    TIM16 => (APB2, 17),
+    TIM17 => (APB2, 18),
+}
+
+#[cfg(feature = "medium")]
+bus! {
+    TIM4 => (APB1, 2),
+}
+
+#[cfg(any(feature = "high", feature = "connectivity"))]
+bus! {
+    TIM5 => (APB1, 3),
+}
+
+#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
+bus! {
+    TIM12 => (APB1, 6),
+    TIM13 => (APB1, 7),
+    TIM14 => (APB1, 8),
+}
+
+#[cfg(all(feature = "stm32f103", feature = "high",))]
+bus! {
+    TIM8 => (APB2, 13),
+}
+
+#[cfg(feature = "xl")]
+bus! {
+    TIM9 => (APB2, 19),
+    TIM10 => (APB2, 20),
+    TIM11 => (APB2, 21),
+}
+
+#[cfg(any(feature = "stm32f102", feature = "stm32f103"))]
+bus! {
+    USB => (APB1, 23),
+}
diff --git a/src/serial.rs b/src/serial.rs
index a9e0754a..70923887 100644
--- a/src/serial.rs
+++ b/src/serial.rs
@@ -42,7 +42,7 @@ use core::ops::Deref;
 use core::ptr;
 use core::sync::atomic::{self, Ordering};
 
-use crate::pac::{USART1, USART2, USART3};
+use crate::pac::{RCC, USART1, USART2, USART3};
 use core::convert::Infallible;
 use embedded_dma::{StaticReadBuffer, StaticWriteBuffer};
 use embedded_hal::serial::Write;
@@ -54,7 +54,7 @@ use crate::gpio::gpiob::{PB10, PB11, PB6, PB7};
 use crate::gpio::gpioc::{PC10, PC11};
 use crate::gpio::gpiod::{PD5, PD6, PD8, PD9};
 use crate::gpio::{Alternate, Floating, Input, PushPull};
-use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset, APB1, APB2};
+use crate::rcc::{Clocks, Enable, GetBusFreq, RccBus, Reset};
 use crate::time::{Bps, U32Ext};
 
 /// Interrupt event
@@ -295,14 +295,14 @@ macro_rules! hal {
                     mapr: &mut MAPR,
                     config: Config,
                     clocks: Clocks,
-                    apb: &mut $APBx,
                 ) -> Self
                 where
                     PINS: Pins<$USARTX>,
                 {
                     // enable and reset $USARTX
-                    $USARTX::enable(apb);
-                    $USARTX::reset(apb);
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $USARTX::enable(rcc);
+                    $USARTX::reset(rcc);
 
                     #[allow(unused_unsafe)]
                     mapr.modify_mapr(|_, w| unsafe{
diff --git a/src/spi.rs b/src/spi.rs
index 51f5ce76..c15f1fdc 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -39,7 +39,7 @@ use core::ptr;
 pub use crate::hal::spi::{FullDuplex, Mode, Phase, Polarity};
 #[cfg(any(feature = "high", feature = "connectivity"))]
 use crate::pac::SPI3;
-use crate::pac::{SPI1, SPI2};
+use crate::pac::{RCC, SPI1, SPI2};
 
 use crate::afio::MAPR;
 use crate::dma::dma1;
@@ -51,7 +51,7 @@ use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5};
 #[cfg(feature = "connectivity")]
 use crate::gpio::gpioc::{PC10, PC11, PC12};
 use crate::gpio::{Alternate, Floating, Input, OpenDrain, PushPull};
-use crate::rcc::{Clocks, Enable, GetBusFreq, Reset, APB1, APB2};
+use crate::rcc::{Clocks, Enable, GetBusFreq, Reset};
 use crate::time::Hertz;
 
 use core::sync::atomic::{self, Ordering};
@@ -158,7 +158,6 @@ impl<REMAP, PINS> Spi<SPI1, REMAP, PINS, u8> {
         mode: Mode,
         freq: F,
         clocks: Clocks,
-        apb: &mut APB2,
     ) -> Self
     where
         F: Into<Hertz>,
@@ -166,7 +165,7 @@ impl<REMAP, PINS> Spi<SPI1, REMAP, PINS, u8> {
         PINS: Pins<REMAP>,
     {
         mapr.modify_mapr(|_, w| w.spi1_remap().bit(REMAP::REMAP));
-        Spi::<SPI1, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
+        Spi::<SPI1, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks)
     }
 }
 
@@ -178,20 +177,13 @@ impl<REMAP, PINS> Spi<SPI2, REMAP, PINS, u8> {
 
       You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins
     */
-    pub fn spi2<F>(
-        spi: SPI2,
-        pins: PINS,
-        mode: Mode,
-        freq: F,
-        clocks: Clocks,
-        apb: &mut APB1,
-    ) -> Self
+    pub fn spi2<F>(spi: SPI2, pins: PINS, mode: Mode, freq: F, clocks: Clocks) -> Self
     where
         F: Into<Hertz>,
         REMAP: Remap<Periph = SPI2>,
         PINS: Pins<REMAP>,
     {
-        Spi::<SPI2, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
+        Spi::<SPI2, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks)
     }
 }
 
@@ -205,20 +197,13 @@ impl<REMAP, PINS> Spi<SPI3, REMAP, PINS, u8> {
       You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins
     */
     #[cfg(not(feature = "connectivity"))]
-    pub fn spi3<F>(
-        spi: SPI3,
-        pins: PINS,
-        mode: Mode,
-        freq: F,
-        clocks: Clocks,
-        apb: &mut APB1,
-    ) -> Self
+    pub fn spi3<F>(spi: SPI3, pins: PINS, mode: Mode, freq: F, clocks: Clocks) -> Self
     where
         F: Into<Hertz>,
         REMAP: Remap<Periph = SPI3>,
         PINS: Pins<REMAP>,
     {
-        Spi::<SPI3, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
+        Spi::<SPI3, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks)
     }
 
     /**
@@ -236,7 +221,6 @@ impl<REMAP, PINS> Spi<SPI3, REMAP, PINS, u8> {
         mode: Mode,
         freq: F,
         clocks: Clocks,
-        apb: &mut APB1,
     ) -> Self
     where
         F: Into<Hertz>,
@@ -244,7 +228,7 @@ impl<REMAP, PINS> Spi<SPI3, REMAP, PINS, u8> {
         PINS: Pins<REMAP>,
     {
         mapr.modify_mapr(|_, w| w.spi3_remap().bit(REMAP::REMAP));
-        Spi::<SPI3, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks, apb)
+        Spi::<SPI3, _, _, u8>::_spi(spi, pins, mode, freq.into(), clocks)
     }
 }
 
@@ -344,17 +328,11 @@ where
     SPI: Deref<Target = SpiRegisterBlock> + Enable + Reset,
     SPI::Bus: GetBusFreq,
 {
-    fn _spi(
-        spi: SPI,
-        pins: PINS,
-        mode: Mode,
-        freq: Hertz,
-        clocks: Clocks,
-        apb: &mut SPI::Bus,
-    ) -> Self {
+    fn _spi(spi: SPI, pins: PINS, mode: Mode, freq: Hertz, clocks: Clocks) -> Self {
         // enable or reset SPI
-        SPI::enable(apb);
-        SPI::reset(apb);
+        let rcc = unsafe { &(*RCC::ptr()) };
+        SPI::enable(rcc);
+        SPI::reset(rcc);
 
         // disable SS output
         spi.cr2.write(|w| w.ssoe().clear_bit());
diff --git a/src/timer.rs b/src/timer.rs
index c0f37df6..63f2c778 100644
--- a/src/timer.rs
+++ b/src/timer.rs
@@ -48,6 +48,7 @@
 */
 
 use crate::hal::timer::{Cancel, CountDown, Periodic};
+use crate::pac::RCC;
 #[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity",))]
 use crate::pac::TIM1;
 #[cfg(feature = "medium")]
@@ -67,9 +68,7 @@ use crate::pac::{DBGMCU as DBG, TIM2, TIM3};
 #[cfg(feature = "stm32f100")]
 use crate::pac::{TIM15, TIM16, TIM17};
 
-#[cfg(not(feature = "stm32f101"))]
-use crate::rcc::APB2;
-use crate::rcc::{sealed::RccBus, Clocks, Enable, GetBusFreq, Reset, APB1};
+use crate::rcc::{Clocks, Enable, GetBusFreq, RccBus, Reset};
 use cast::{u16, u32, u64};
 use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
@@ -281,10 +280,11 @@ macro_rules! hal {
         $(
             impl Timer<$TIMX> {
                 /// Initialize timer
-                pub fn $timX(tim: $TIMX, clocks: &Clocks, apb: &mut $APBx) -> Self {
+                pub fn $timX(tim: $TIMX, clocks: &Clocks) -> Self {
                     // enable and reset peripheral to a clean slate state
-                    $TIMX::enable(apb);
-                    $TIMX::reset(apb);
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $TIMX::enable(rcc);
+                    $TIMX::reset(rcc);
 
                     Self { tim, clk: <$TIMX as RccBus>::Bus::get_timer_frequency(&clocks) }
                 }
@@ -325,8 +325,9 @@ macro_rules! hal {
 
                 /// Resets timer peripheral
                 #[inline(always)]
-                pub fn clocking_reset(&mut self, apb: &mut <$TIMX as RccBus>::Bus) {
-                    $TIMX::reset(apb);
+                pub fn clocking_reset(&mut self) {
+                    let rcc = unsafe { &(*RCC::ptr()) };
+                    $TIMX::reset(rcc);
                 }
 
                 /// Stopping timer in debug mode can cause troubles when sampling the signal