Hardware_Acceleration

AMD Vitis™ Hardware Acceleration Tutorials See Vitis Development Environment on xilinx.com

Version: Vitis 2023.2

Introduction

The tutorials under the Hardware Acceleration category help you learn how to use the Vitis core development kit to build, analyze, and optimize an accelerated algorithm developed in C++, OpenCL, and even low-level hardware description languages (HDLs) like Verilog and VHDL. You may also learn how to optimize the CPU side of your application for efficient memory allocation, how to sequence system-level events, and more.

• The Hardware Acceleration Feature Tutorials illustrate specific features or flows of Vitis. Some features might not be required by all designs but are still useful for some use cases.

• The Hardware Acceleration Design Tutorials illustrate higher-level concepts or design flows, walk through specific examples or reference designs, and show more complex and complete designs or applications.

These tutorials target different boards including Alveo™ Data Center acceleration cards or MPSoC Evaluation Boards like ZCU104. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in.

Feature Tutorials

Tutorial	Board / Platform	Kernel	XRT APIs	Libraries Used	Highlighted Features	GUI Flow
Getting Started with RTL Kernels	U200	C/C++	Native		RTL kernel	Vivado Vitis IDE
Mixing C and RTL	U200	RTL + C/C++	OpenCL		Mixed C++ and RTL kernel
Dataflow Debug and Optimization	HLS Part	C/C++	HLS		HLS design and analysis	Vitis HLS XSim
Using Multiple DDR Banks	U200	C/C++	Native		DDR bank assignment
Using Multiple Compute Units	U200	C/C++	OpenCL		Multiple Compute Units
Controlling Vivado Implementation	U200	C/C++	OpenCL		Use Vivado in the Vitis flow
Optimizing for HBM	U200 / U50	C/C++	OpenCL		HBM and RAMA IP
Host Memory Access	U250	C/C++	OpenCL		Use Host Memory
Using GT Kernels and Ethernet IPs on Alveo	U200	RTL	Native		Ethernet Subsystem
Enabling FPGA to FPGA P2P Transfer	U50 / U200	C/C++	Native		PCIe P2P

Design Tutorials

Tutorial	Board / Platform	Kernel	XRT APIs	Libraries Used	Highlighted Features	GUI Flow
Convolution Example	U200	C/C++	OpenCL	Vision	Performance analysis and optimization	Vitis HLS
Bloom Filter Example	U200	C/C++	OpenCL		Performance analysis and optimization
RTL Systems Integration Example	U50 / 55C / U200 / U250 / U280	RTL + C/C++	Native	Vision	Mixed kernel
Traveling Salesperson Problem	U200	C/C++	HLS		HLS design and analysis	Vitis HLS
Bottom RTL Kernel Design Flow Example	U50 / 55C / U200 / U250 / U280	RTL + C/C++	Native		RTL kernel
Choleskey Algorithm Acceleration	U200	C/C++	OpenCL		Performance analysis and optimization
XRT Host Code Optimization	U200	C/C++	OpenCL		Host code optimization
Aurora Kernel on Alveo	U50 / 55C / U200 / U250 / U280	RTL + C/C++	Native		GT kernel
Single Source Shortest Path Application	U50	C/C++	OpenCL	Graph	Vitis Library	Vitis IDE
Get Moving with Alveo	U200	C/C++	OpenCL	Vision	System Optimization

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