diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index e8840a8..f5e98f3 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -145,7 +145,7 @@ jobs: rm -rf -- qemu # TODO: retry on failure # https://github.com/taiki-e/dockerfiles/pkgs/container/qemu-user - docker create --name qemu-user ghcr.io/taiki-e/qemu-user:8.1 # TODO: "qemu-armeb: Error mapping file: Operation not permitted" error in 8.2/9.0 + docker create --name qemu-user ghcr.io/taiki-e/qemu-user:8.1 # TODO: "qemu-armeb: Error mapping file: Operation not permitted" error in 8.2-9.1 mkdir -p -- qemu-user docker cp -- qemu-user:/usr/bin qemu-user/bin docker rm -f -- qemu-user >/dev/null diff --git a/CHANGELOG.md b/CHANGELOG.md index 13384f6..bd7d755 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -34,7 +34,7 @@ Note: In this file, do not use the hard wrap in the middle of a sentence for com ## [0.1.9] - 2024-04-21 -- Add `trap-hlt` feature to use `HLT` instruction on ARM A+R profile. See the [documentation](https://github.com/taiki-e/semihosting#optional-features-trap-hlt) for details. +- Add `trap-hlt` feature to use `HLT` instruction on Arm A+R profile. See the [documentation](https://github.com/taiki-e/semihosting#optional-features-trap-hlt) for details. ## [0.1.8] - 2024-04-21 diff --git a/Cargo.toml b/Cargo.toml index 4fa9a5e..70c2264 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -9,13 +9,13 @@ keywords = ["qemu"] categories = ["embedded", "hardware-support", "no-std", "no-std::no-alloc"] exclude = ["/.*", "/tools", "/target-specs"] description = """ -Semihosting for AArch64, ARM, RISC-V, MIPS32, MIPS64, and Xtensa. +Semihosting for AArch64, Arm, RISC-V, MIPS32, MIPS64, and Xtensa. """ [package.metadata.docs.rs] # NB: sync with env.TEST_FEATURES in .github/workflows/ci.yml features = ["alloc", "stdio", "fs", "args", "time"] -# Building documentation on any architectures that support ARM semihosting with +# Building documentation on any architectures that support Arm semihosting with # the above cfg will show all APIs with proper doc(cfg). targets = ["aarch64-unknown-linux-gnu"] @@ -77,7 +77,7 @@ backtrace = ["stdio", "unwinding", "unwinding/hide-trace"] # See readme for details. portable-atomic = ["dep:portable-atomic"] -# ARM-specific: Use HLT instruction on A+R profile. +# Arm-specific: Use HLT instruction on A+R profile. # # See readme for details. trap-hlt = [] diff --git a/README.md b/README.md index 68b846b..b95ead5 100644 --- a/README.md +++ b/README.md @@ -7,9 +7,9 @@ [![github actions](https://img.shields.io/github/actions/workflow/status/taiki-e/semihosting/ci.yml?branch=main&style=flat-square&logo=github)](https://github.com/taiki-e/semihosting/actions) -Semihosting for AArch64, ARM, RISC-V, MIPS32, MIPS64, and Xtensa. +Semihosting for AArch64, Arm, RISC-V, MIPS32, MIPS64, and Xtensa. -This library provides access to semihosting, a mechanism for programs running on the real or virtual (e.g., QEMU) target to communicate with I/O facilities on the host system. See the [ARM documentation](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst) for more information on semihosting. +This library provides access to semihosting, a mechanism for programs running on the real or virtual (e.g., QEMU) target to communicate with I/O facilities on the host system. See the [Arm documentation](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst) for more information on semihosting. APIs are categorized into the following four types: @@ -38,9 +38,9 @@ The following target architectures are supported: | target_arch | Specification | `semihosting::sys` module | Note | | ----------- | ------------- | ------------------------- | ---- | -| aarch64 | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst) | `sys::arm_compat` | | -| arm | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst) | `sys::arm_compat` | use `SVC` on A+R profile by default based on ARM's recommendation but it can be changed by [`trap-hlt` feature](#optional-features-trap-hlt). | -| riscv32/riscv64 | [RISC-V Semihosting](https://github.com/riscv-non-isa/riscv-semihosting/blob/HEAD/riscv-semihosting.adoc) | `sys::arm_compat` | | +| aarch64 | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst) | `sys::arm_compat` | | +| arm | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst) | `sys::arm_compat` | use `SVC` on A+R profile by default based on Arm's recommendation but it can be changed by [`trap-hlt` feature](#optional-features-trap-hlt). | +| riscv32/riscv64 | [RISC-V Semihosting](https://github.com/riscv-non-isa/riscv-semihosting/blob/0.5/riscv-semihosting.adoc) | `sys::arm_compat` | | | xtensa | [OpenOCD Semihosting](https://github.com/espressif/openocd-esp32/blob/HEAD/src/target/espressif/esp_xtensa_semihosting.c) | `sys::arm_compat` | requires [`openocd-semihosting` feature](#optional-features-openocd-semihosting) | | mips/mips32r6/mips64/mips64r6 | Unified Hosting Interface (MD01069) | `sys::mips` | | @@ -101,9 +101,9 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } location to stderr. - **`trap-hlt`**
- ARM-specific: Use HLT instruction on A+R profile. + Arm-specific: Use HLT instruction on A+R profile. - [ARM documentation](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#the-semihosting-interface) says: + [Arm documentation](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#the-semihosting-interface) says: > The `HLT` encodings are new in version 2.0 of the semihosting specification. > Where possible, have semihosting callers continue to use the previously existing @@ -116,9 +116,9 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } > on A32 and T32 as a configurable option. ARM strongly discourages semihosting > callers from mixing the `HLT` and `SVC` mechanisms within the same executable. - Based on the ARM's recommendation, this is implemented as an optional feature. + Based on the Arm's recommendation, this is implemented as an optional feature. - Enabling this feature on architectures other than ARM A+R profile will result in a compile error. + Enabling this feature on architectures other than Arm A+R profile will result in a compile error. - **`openocd-semihosting`**
Xtensa-specific: Use OpenOCD Semihosting. @@ -126,7 +126,7 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } Xtensa has two semihosting interfaces: - Tensilica ISS SIMCALL used in Cadence tools and [QEMU](https://www.qemu.org/docs/master/about/emulation.html#supported-targets). - - ARM-semihosting-compatible semihosting interface used in [OpenOCD](https://github.com/espressif/openocd-esp32/blob/HEAD/src/target/espressif/esp_xtensa_semihosting.c) and [probe-rs](https://github.com/probe-rs/probe-rs/pull/2303). (This crate calls it "OpenOCD Semihosting", which is the same as the option name in [newlib](https://github.com/espressif/newlib-esp32/blob/esp_based_on_4_1_0/libgloss/xtensa/syscalls.c#L23).) + - Arm-semihosting-compatible semihosting interface used in [OpenOCD](https://github.com/espressif/openocd-esp32/blob/HEAD/src/target/espressif/esp_xtensa_semihosting.c) and [probe-rs](https://github.com/probe-rs/probe-rs/pull/2303). (This crate calls it "OpenOCD Semihosting", which is the same as the option name in [newlib-esp32](https://github.com/espressif/newlib-esp32/blob/esp-4.3.0_20240530/libgloss/xtensa/syscalls.c#L21).) This crate does not currently support SIMCALL-based semihosting, but users need to explicitly enable the feature to avoid accidentally selecting a different one than one actually want to use. diff --git a/build.rs b/build.rs index 711ca1e..95724ff 100644 --- a/build.rs +++ b/build.rs @@ -23,20 +23,21 @@ fn main() { if version.minor >= 80 { // Custom cfgs set by build script. Not public API. - // grep -E 'cargo:rustc-cfg=' build.rs | grep -v '=//' | sed -E 's/^.*cargo:rustc-cfg=//; s/(=\\)?".*$//' | LC_ALL=C sort -u | tr '\n' ',' + // grep -F 'cargo:rustc-cfg=' build.rs | grep -Ev '^ *//' | sed -E 's/^.*cargo:rustc-cfg=//; s/(=\\)?".*$//' | LC_ALL=C sort -u | tr '\n' ',' | sed -E 's/,$/\n/' println!( "cargo:rustc-check-cfg=cfg(semihosting_no_error_in_core,semihosting_target_feature)" ); // TODO: handle multi-line target_feature_fallback - // grep -E 'target_feature_fallback\("' build.rs | sed -E 's/^.*target_feature_fallback\(//; s/",.*$/"/' | LC_ALL=C sort -u | tr '\n' ',' + // grep -F 'target_feature_fallback("' build.rs | grep -Ev '^ *//' | sed -E 's/^.*target_feature_fallback\(//; s/",.*$/"/' | LC_ALL=C sort -u | tr '\n' ',' | sed -E 's/,$/\n/' println!( r#"cargo:rustc-check-cfg=cfg(semihosting_target_feature,values("mclass","thumb-mode"))"# ); } - // Note that this is `no_`*, not `has_*`. This allows treating as the latest + // Note that cfgs are `no_`*, not `has_*`. This allows treating as the latest // stable rustc is used when the build script doesn't run. This is useful // for non-cargo build systems that don't run the build script. + // error_in_core stabilized in Rust 1.81 (nightly-2024-06-09): https://github.com/rust-lang/rust/pull/125951 if !version.probe(81, 2024, 6, 8) { println!("cargo:rustc-cfg=semihosting_no_error_in_core"); @@ -138,7 +139,7 @@ mod version { cmd.args(rustc); // Use verbose version output because the packagers add extra strings to the normal version output. // Do not use long flags (--version --verbose) because clippy-deriver doesn't handle them properly. - // -vV is also matched with that cargo internally uses: https://github.com/rust-lang/cargo/blob/14b46ecc62aa671d7477beba237ad9c6a209cf5d/src/cargo/util/rustc.rs#L65 + // -vV is also matched with that cargo internally uses: https://github.com/rust-lang/cargo/blob/0.80.0/src/cargo/util/rustc.rs#L65 let output = cmd.arg("-vV").output().ok()?; let verbose_version = str::from_utf8(&output.stdout).ok()?; Version::parse(verbose_version) diff --git a/src/io/mod.rs b/src/io/mod.rs index bf3a4ce..b6f1ce4 100644 --- a/src/io/mod.rs +++ b/src/io/mod.rs @@ -224,7 +224,7 @@ pub enum SeekFrom { /// It is possible to seek beyond the end of an object, but it's an error to /// seek before byte 0. End(i64), - // TODO: It appears that SeekFrom::Current cannot be implemented with APIs provided by ARM semihosting... + // TODO: It appears that SeekFrom::Current cannot be implemented with APIs provided by Arm semihosting... // /// Sets the offset to the current position plus the specified number of // /// bytes. // /// diff --git a/src/lib.rs b/src/lib.rs index b52714e..09cda24 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -2,9 +2,9 @@ /*! -Semihosting for AArch64, ARM, RISC-V, MIPS32, MIPS64, and Xtensa. +Semihosting for AArch64, Arm, RISC-V, MIPS32, MIPS64, and Xtensa. -This library provides access to semihosting, a mechanism for programs running on the real or virtual (e.g., QEMU) target to communicate with I/O facilities on the host system. See the [ARM documentation](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst) for more information on semihosting. +This library provides access to semihosting, a mechanism for programs running on the real or virtual (e.g., QEMU) target to communicate with I/O facilities on the host system. See the [Arm documentation](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst) for more information on semihosting. APIs are categorized into the following four types: @@ -33,9 +33,9 @@ The following target architectures are supported: | target_arch | Specification | `semihosting::sys` module | Note | | ----------- | ------------- | ------------------------- | ---- | -| aarch64 | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst) | `sys::arm_compat` | | -| arm | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst) | `sys::arm_compat` | use `SVC` on A+R profile by default based on ARM's recommendation but it can be changed by [`trap-hlt` feature](#optional-features-trap-hlt). | -| riscv32/riscv64 | [RISC-V Semihosting](https://github.com/riscv-non-isa/riscv-semihosting/blob/HEAD/riscv-semihosting.adoc) | `sys::arm_compat` | | +| aarch64 | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst) | `sys::arm_compat` | | +| arm | [Semihosting for AArch32 and AArch64](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst) | `sys::arm_compat` | use `SVC` on A+R profile by default based on Arm's recommendation but it can be changed by [`trap-hlt` feature](#optional-features-trap-hlt). | +| riscv32/riscv64 | [RISC-V Semihosting](https://github.com/riscv-non-isa/riscv-semihosting/blob/0.5/riscv-semihosting.adoc) | `sys::arm_compat` | | | xtensa | [OpenOCD Semihosting](https://github.com/espressif/openocd-esp32/blob/HEAD/src/target/espressif/esp_xtensa_semihosting.c) | `sys::arm_compat` | requires [`openocd-semihosting` feature](#optional-features-openocd-semihosting) | | mips/mips32r6/mips64/mips64r6 | Unified Hosting Interface (MD01069) | `sys::mips` | | @@ -96,9 +96,9 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } location to stderr. - **`trap-hlt`**
- ARM-specific: Use HLT instruction on A+R profile. + Arm-specific: Use HLT instruction on A+R profile. - [ARM documentation](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#the-semihosting-interface) says: + [Arm documentation](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#the-semihosting-interface) says: > The `HLT` encodings are new in version 2.0 of the semihosting specification. > Where possible, have semihosting callers continue to use the previously existing @@ -111,9 +111,9 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } > on A32 and T32 as a configurable option. ARM strongly discourages semihosting > callers from mixing the `HLT` and `SVC` mechanisms within the same executable. - Based on the ARM's recommendation, this is implemented as an optional feature. + Based on the Arm's recommendation, this is implemented as an optional feature. - Enabling this feature on architectures other than ARM A+R profile will result in a compile error. + Enabling this feature on architectures other than Arm A+R profile will result in a compile error. - **`openocd-semihosting`**
Xtensa-specific: Use OpenOCD Semihosting. @@ -121,7 +121,7 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } Xtensa has two semihosting interfaces: - Tensilica ISS SIMCALL used in Cadence tools and [QEMU](https://www.qemu.org/docs/master/about/emulation.html#supported-targets). - - ARM-semihosting-compatible semihosting interface used in [OpenOCD](https://github.com/espressif/openocd-esp32/blob/HEAD/src/target/espressif/esp_xtensa_semihosting.c) and [probe-rs](https://github.com/probe-rs/probe-rs/pull/2303). (This crate calls it "OpenOCD Semihosting", which is the same as the option name in [newlib](https://github.com/espressif/newlib-esp32/blob/esp_based_on_4_1_0/libgloss/xtensa/syscalls.c#L23).) + - Arm-semihosting-compatible semihosting interface used in [OpenOCD](https://github.com/espressif/openocd-esp32/blob/HEAD/src/target/espressif/esp_xtensa_semihosting.c) and [probe-rs](https://github.com/probe-rs/probe-rs/pull/2303). (This crate calls it "OpenOCD Semihosting", which is the same as the option name in [newlib-esp32](https://github.com/espressif/newlib-esp32/blob/esp-4.3.0_20240530/libgloss/xtensa/syscalls.c#L21).) This crate does not currently support SIMCALL-based semihosting, but users need to explicitly enable the feature to avoid accidentally selecting a different one than one actually want to use. @@ -252,7 +252,8 @@ semihosting = { version = "0.1", features = ["stdio", "panic-handler"] } // docs.rs only (cfg is enabled by docs.rs, not build script) #![cfg_attr(docsrs, feature(doc_cfg))] -// 64-bit architecture's 32-bit ABI (e.g., AArch64 ILP32 ABI) are also unsupported yet. +// 64-bit architecture's 32-bit ABI (e.g., AArch64 ILP32 ABI) are also +// unsupported yet (is there a semihosting interface defined for those ABIs?). #[cfg(not(any( all(target_arch = "aarch64", target_pointer_width = "64"), target_arch = "arm", diff --git a/src/sys/arm_compat/fs.rs b/src/sys/arm_compat/fs.rs index 13de114..157dd4d 100644 --- a/src/sys/arm_compat/fs.rs +++ b/src/sys/arm_compat/fs.rs @@ -51,7 +51,7 @@ pub(crate) fn open(path: &CStr, options: &crate::fs::OpenOptions) -> Result, pos: io::SeekFrom) -> Result { let abs_pos = match pos { diff --git a/src/sys/arm_compat/mod.rs b/src/sys/arm_compat/mod.rs index f5a651f..edcadcd 100644 --- a/src/sys/arm_compat/mod.rs +++ b/src/sys/arm_compat/mod.rs @@ -1,12 +1,12 @@ // SPDX-License-Identifier: Apache-2.0 OR MIT -//! Low-level access to semihosting interfaces for ARM (AArch32 and AArch64) and -//! RISC-V (which supports ARM-compatible semihosting interfaces). +//! Low-level access to semihosting interfaces for Arm (AArch32 and AArch64) and +//! RISC-V (which supports Arm-compatible semihosting interfaces). //! //! Refs: -//! - Semihosting for AArch32 and AArch64 -//! - RISC-V Semihosting -//! - +//! - Semihosting for AArch32 and AArch64 +//! - RISC-V Semihosting +//! - //! - #![allow(clippy::missing_safety_doc)] // TODO @@ -116,7 +116,7 @@ pub struct CommandLine { pub size: usize, } -/// [SYS_CLOCK (0x10)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_clock-0x10) +/// [SYS_CLOCK (0x10)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-clock-0x10) pub fn sys_clock() -> Result { let res = unsafe { syscall0(OperationNumber::SYS_CLOCK) }; if res.int() == -1 { @@ -126,7 +126,7 @@ pub fn sys_clock() -> Result { } } -/// [SYS_CLOSE (0x02)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_close-0x02) +/// [SYS_CLOSE (0x02)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-close-0x02) pub unsafe fn sys_close(fd: RawFd) -> Result<()> { let args = [ParamRegR::raw_fd(fd)]; let res = unsafe { syscall_readonly(OperationNumber::SYS_CLOSE, ParamRegR::block(&args)) }; @@ -139,7 +139,7 @@ pub unsafe fn sys_close(fd: RawFd) -> Result<()> { } pub(crate) use sys_close as close; -/// [SYS_ELAPSED (0x30)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_elapsed-0x30) +/// [SYS_ELAPSED (0x30)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-elapsed-0x30) pub fn sys_elapsed() -> Result { // On 32-bit, the parameter is a pointer to two 32-bit field data block // On 64-bit, the parameter is a pointer to one 64-bit field data block @@ -153,7 +153,7 @@ pub fn sys_elapsed() -> Result { } } -/// [SYS_ERRNO (0x13)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_errno-0x13) +/// [SYS_ERRNO (0x13)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-errno-0x13) pub fn sys_errno() -> RawOsError { let res = unsafe { syscall0(OperationNumber::SYS_ERRNO) }; res.errno() @@ -171,7 +171,7 @@ pub(crate) fn exit(code: i32) { }; sys_exit(reason); } -/// [SYS_EXIT (0x18)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_exit-0x18) +/// [SYS_EXIT (0x18)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-exit-0x18) pub fn sys_exit(reason: ExitReason) { #[cfg(target_pointer_width = "32")] let arg = ParamRegR::usize(reason as usize); @@ -184,7 +184,7 @@ pub fn sys_exit(reason: ExitReason) { } } -/// [SYS_EXIT_EXTENDED (0x20)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_exit_extended-0x20) +/// [SYS_EXIT_EXTENDED (0x20)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-exit-extended-0x20) pub fn sys_exit_extended(reason: ExitReason, subcode: usize) { let args = [ParamRegR::usize(reason as usize), ParamRegR::usize(subcode)]; #[cfg(target_pointer_width = "32")] @@ -197,7 +197,7 @@ pub fn sys_exit_extended(reason: ExitReason, subcode: usize) { } } -/// [SYS_FLEN (0x0C)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_flen-0x0c) +/// [SYS_FLEN (0x0C)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-flen-0x0c) pub fn sys_flen(fd: BorrowedFd<'_>) -> Result { let args = [ParamRegR::fd(fd)]; let res = unsafe { syscall_readonly(OperationNumber::SYS_FLEN, ParamRegR::block(&args)) }; @@ -208,7 +208,7 @@ pub fn sys_flen(fd: BorrowedFd<'_>) -> Result { } } -/// [SYS_GET_CMDLINE (0x15)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_get_cmdline-0x15) +/// [SYS_GET_CMDLINE (0x15)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-get-cmdline-0x15) /// /// # Safety /// @@ -223,21 +223,21 @@ pub unsafe fn sys_get_cmdline(cmdline: &mut CommandLine) -> Result<()> { } } -/// [SYS_HEAPINFO (0x16)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_heapinfo-0x16) +/// [SYS_HEAPINFO (0x16)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-heapinfo-0x16) pub fn sys_heapinfo() -> HeapInfo { let mut buf: HeapInfo = unsafe { mem::zeroed() }; unsafe { syscall(OperationNumber::SYS_HEAPINFO, ParamRegW::ref_(&mut buf)) }; buf } -/// [SYS_ISERROR (0x08)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_iserror-0x08) +/// [SYS_ISERROR (0x08)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-iserror-0x08) pub fn sys_iserror(res: isize) -> bool { let args = [ParamRegR::isize(res)]; let res = unsafe { syscall_readonly(OperationNumber::SYS_ISERROR, ParamRegR::block(&args)) }; res.usize() != 0 } -/// [SYS_ISTTY (0x09)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_istty-0x09) +/// [SYS_ISTTY (0x09)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-istty-0x09) pub fn sys_istty(fd: BorrowedFd<'_>) -> Result { let args = [ParamRegR::fd(fd)]; let res = unsafe { syscall_readonly(OperationNumber::SYS_ISTTY, ParamRegR::block(&args)) }; @@ -252,7 +252,7 @@ pub(crate) fn is_terminal(fd: BorrowedFd<'_>) -> bool { sys_istty(fd).unwrap_or(false) } -/// [SYS_OPEN (0x01)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_open-0x01) +/// [SYS_OPEN (0x01)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-open-0x01) pub fn sys_open(path: &CStr, mode: OpenMode) -> Result { let args = [ ParamRegR::c_str(path), @@ -268,7 +268,7 @@ pub fn sys_open(path: &CStr, mode: OpenMode) -> Result { None => Err(Error::from_raw_os_error(sys_errno())), } } -// From https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_open-0x01: +// From https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-open-0x01: // > ARM targets interpret the special path name `:tt` as meaning the console // > input stream, for an open-read or the console output stream, for an open-write. // > Opening these streams is performed as part of the standard startup code for @@ -293,12 +293,12 @@ pub(crate) fn stderr() -> Result { } #[inline] pub(crate) fn should_close(_fd: &OwnedFd) -> bool { - // In ARM semihosting, stdio streams are handled like normal fd. + // In Arm semihosting, stdio streams are handled like normal fd. true } // TODO: Add read_uninit? -/// [SYS_READ (0x06)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_read-0x06) +/// [SYS_READ (0x06)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-read-0x06) pub fn sys_read(fd: BorrowedFd<'_>, buf: &mut [MaybeUninit]) -> Result { let len = buf.len(); let mut args = [ParamRegW::fd(fd), ParamRegW::buf(buf), ParamRegW::usize(len)]; @@ -319,13 +319,13 @@ pub(crate) fn read(fd: BorrowedFd<'_>, buf: &mut [u8]) -> Result { sys_read(fd, buf) } -/// [SYS_READC (0x07)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_readc-0x07) +/// [SYS_READC (0x07)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-readc-0x07) pub fn sys_readc() -> u8 { let res = unsafe { syscall0(OperationNumber::SYS_READC) }; res.u8() } -/// [SYS_REMOVE (0x0E)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_remove-0x0e) +/// [SYS_REMOVE (0x0E)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-remove-0x0e) pub fn sys_remove(path: &CStr) -> Result<()> { let args = [ParamRegR::c_str(path), ParamRegR::usize(path.to_bytes().len())]; let res = unsafe { syscall_readonly(OperationNumber::SYS_REMOVE, ParamRegR::block(&args)) }; @@ -336,7 +336,7 @@ pub fn sys_remove(path: &CStr) -> Result<()> { } } -/// [SYS_RENAME (0x0F)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_rename-0x0f) +/// [SYS_RENAME (0x0F)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-rename-0x0f) pub fn sys_rename(from: &CStr, to: &CStr) -> Result<()> { let args = [ ParamRegR::c_str(from), @@ -354,7 +354,7 @@ pub fn sys_rename(from: &CStr, to: &CStr) -> Result<()> { // TODO: resolve safety // > The effect of seeking outside the current extent of the file object is undefined. -/// [SYS_SEEK (0x0A)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_seek-0x0a) +/// [SYS_SEEK (0x0A)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-seek-0x0a) pub unsafe fn sys_seek(fd: BorrowedFd<'_>, abs_pos: usize) -> Result<()> { let args = [ParamRegR::fd(fd), ParamRegR::usize(abs_pos)]; let res = unsafe { syscall_readonly(OperationNumber::SYS_SEEK, ParamRegR::block(&args)) }; @@ -365,14 +365,14 @@ pub unsafe fn sys_seek(fd: BorrowedFd<'_>, abs_pos: usize) -> Result<()> { } } -/// [SYS_SYSTEM (0x12)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_system-0x12) +/// [SYS_SYSTEM (0x12)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-system-0x12) pub fn sys_system(cmd: &CStr) -> usize { let args = [ParamRegR::c_str(cmd), ParamRegR::usize(cmd.to_bytes().len())]; let res = unsafe { syscall_readonly(OperationNumber::SYS_SYSTEM, ParamRegR::block(&args)) }; res.usize() } -/// [SYS_TICKFREQ (0x31)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_tickfreq-0x31) +/// [SYS_TICKFREQ (0x31)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-tickfreq-0x31) pub fn sys_tickfreq() -> Result { let res = unsafe { syscall0(OperationNumber::SYS_TICKFREQ) }; if res.int() == -1 { @@ -382,14 +382,14 @@ pub fn sys_tickfreq() -> Result { } } -/// [SYS_TIME (0x11)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_time-0x11) +/// [SYS_TIME (0x11)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-time-0x11) #[allow(clippy::unnecessary_wraps)] // TODO: change in next breaking release? pub fn sys_time() -> Result { let res = unsafe { syscall0(OperationNumber::SYS_TIME) }; Ok(res.usize()) } -/// [SYS_WRITE (0x05)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_write-0x05) +/// [SYS_WRITE (0x05)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-write-0x05) pub fn sys_write(fd: BorrowedFd<'_>, buf: &[u8]) -> Result { let args = [ParamRegR::fd(fd), ParamRegR::buf(buf), ParamRegR::usize(buf.len())]; let res = unsafe { syscall_readonly(OperationNumber::SYS_WRITE, ParamRegR::block(&args)) }; @@ -409,14 +409,14 @@ pub fn sys_write(fd: BorrowedFd<'_>, buf: &[u8]) -> Result { #[cfg(any(feature = "stdio", feature = "fs"))] pub(crate) use sys_write as write; -/// [SYS_WRITEC (0x03)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_writec-0x03) +/// [SYS_WRITEC (0x03)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-writec-0x03) pub fn sys_writec(b: u8) { unsafe { syscall_readonly(OperationNumber::SYS_WRITEC, ParamRegR::ref_(&b)); } } -/// [SYS_WRITE0 (0x04)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_write0-0x04) +/// [SYS_WRITE0 (0x04)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-write0-0x04) pub fn sys_write0(s: &CStr) { unsafe { syscall_readonly(OperationNumber::SYS_WRITE0, ParamRegR::c_str(s)); diff --git a/src/sys/arm_compat/syscall/arm.rs b/src/sys/arm_compat/syscall/arm.rs index 4a71ebf..d387895 100644 --- a/src/sys/arm_compat/syscall/arm.rs +++ b/src/sys/arm_compat/syscall/arm.rs @@ -30,7 +30,8 @@ macro_rules! trap { "svc 0x123456" }; } -// https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#the-semihosting-interface +// A+R Profile T32, HLT +// https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#the-semihosting-interface // > This requirement includes supporting the HLT encodings on ARMv7 and earlier processors, // > even though HLT is only defined as an instruction in ARMv8. This may require the semihosting // > implementation to trap the UNDEF exception. @@ -44,7 +45,6 @@ macro_rules! trap { // > ARM encourages semihosting callers to implement support for trapping using HLT on A32 and T32 // > as a configurable option. ARM strongly discourages semihosting callers from mixing the HLT and // > SVC mechanisms within the same executable. -// A+R Profile T32, HLT #[cfg(feature = "trap-hlt")] #[cfg(not(any(target_feature = "mclass", semihosting_target_feature = "mclass")))] #[cfg(any(target_feature = "thumb-mode", semihosting_target_feature = "thumb-mode"))] diff --git a/src/sys/arm_compat/syscall/mod.rs b/src/sys/arm_compat/syscall/mod.rs index 3b5be34..ed51f35 100644 --- a/src/sys/arm_compat/syscall/mod.rs +++ b/src/sys/arm_compat/syscall/mod.rs @@ -14,66 +14,66 @@ pub use crate::sys::reg::{ParamRegR, ParamRegW, RetReg}; /// Semihosting operation numbers. /// -/// - `0x00-0x31` Used by ARM. -/// - `0x32-0xFF` Reserved for future use by ARM. +/// - `0x00-0x31` Used by Arm. +/// - `0x32-0xFF` Reserved for future use by Arm. /// - `0x100-0x1FF` Reserved for user applications. /// - `0x200-0xFFFFFFFF` Undefined and currently unused. #[derive(Debug, Copy, Clone)] pub struct OperationNumber(u32); impl OperationNumber { - /// [SYS_OPEN (0x01)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_open-0x01) + /// [SYS_OPEN (0x01)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-open-0x01) pub const SYS_OPEN: Self = Self(0x01); - /// [SYS_CLOSE (0x02)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_close-0x02) + /// [SYS_CLOSE (0x02)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-close-0x02) pub const SYS_CLOSE: Self = Self(0x02); - /// [SYS_WRITEC (0x03)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_writec-0x03) + /// [SYS_WRITEC (0x03)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-writec-0x03) pub const SYS_WRITEC: Self = Self(0x03); - /// [SYS_WRITE0 (0x04)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_write0-0x04) + /// [SYS_WRITE0 (0x04)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-write0-0x04) pub const SYS_WRITE0: Self = Self(0x04); - /// [SYS_WRITE (0x05)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_write-0x05) + /// [SYS_WRITE (0x05)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-write-0x05) pub const SYS_WRITE: Self = Self(0x05); - /// [SYS_READ (0x06)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_read-0x06) + /// [SYS_READ (0x06)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-read-0x06) pub const SYS_READ: Self = Self(0x06); - /// [SYS_READC (0x07)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_readc-0x07) + /// [SYS_READC (0x07)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-readc-0x07) pub const SYS_READC: Self = Self(0x07); - /// [SYS_ISERROR (0x08)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_iserror-0x08) + /// [SYS_ISERROR (0x08)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-iserror-0x08) pub const SYS_ISERROR: Self = Self(0x08); - /// [SYS_ISTTY (0x09)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_istty-0x09) + /// [SYS_ISTTY (0x09)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-istty-0x09) pub const SYS_ISTTY: Self = Self(0x09); - /// [SYS_SEEK (0x0A)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_seek-0x0a) + /// [SYS_SEEK (0x0A)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-seek-0x0a) pub const SYS_SEEK: Self = Self(0x0A); - /// [SYS_FLEN (0x0C)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_flen-0x0c) + /// [SYS_FLEN (0x0C)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-flen-0x0c) pub const SYS_FLEN: Self = Self(0x0C); - // /// [SYS_TMPNAM (0x0D)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_tmpnam-0x0d) + // /// [SYS_TMPNAM (0x0D)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-tmpnam-0x0d) // #[deprecated = "tmpnam is deprecated as not secure on most host systems"] // pub const SYS_TMPNAM : Self = Self(0x0D); - /// [SYS_REMOVE (0x0E)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_remove-0x0e) + /// [SYS_REMOVE (0x0E)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-remove-0x0e) pub const SYS_REMOVE: Self = Self(0x0E); - /// [SYS_RENAME (0x0F)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_rename-0x0f) + /// [SYS_RENAME (0x0F)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-rename-0x0f) pub const SYS_RENAME: Self = Self(0x0F); - /// [SYS_CLOCK (0x10)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_clock-0x10) + /// [SYS_CLOCK (0x10)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-clock-0x10) pub const SYS_CLOCK: Self = Self(0x10); - /// [SYS_TIME (0x11)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_time-0x11) + /// [SYS_TIME (0x11)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-time-0x11) pub const SYS_TIME: Self = Self(0x11); - /// [SYS_SYSTEM (0x12)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_system-0x12) + /// [SYS_SYSTEM (0x12)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-system-0x12) pub const SYS_SYSTEM: Self = Self(0x12); - /// [SYS_ERRNO (0x13)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_errno-0x13) + /// [SYS_ERRNO (0x13)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-errno-0x13) pub const SYS_ERRNO: Self = Self(0x13); - /// [SYS_GET_CMDLINE (0x15)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_get_cmdline-0x15) + /// [SYS_GET_CMDLINE (0x15)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-get_cmdline-0x15) pub const SYS_GET_CMDLINE: Self = Self(0x15); - /// [SYS_HEAPINFO (0x16)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_heapinfo-0x16) + /// [SYS_HEAPINFO (0x16)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-heapinfo-0x16) pub const SYS_HEAPINFO: Self = Self(0x16); // #[deprecated = "obsoleted in semihosting specification version 2.0"] // pub const angel_SWIreason_EnterSVC : Self = Self(0x17); - /// [SYS_EXIT (0x18)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_exit-0x18) + /// [SYS_EXIT (0x18)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-exit-0x18) #[doc(alias = "angel_SWIreason_ReportException")] // old name pub const SYS_EXIT: Self = Self(0x18); // #[deprecated = "obsoleted in semihosting specification version 2.0"] // pub const angelSWI_Reason_SyncCacheRange : Self = Self(0x19); - /// [SYS_EXIT_EXTENDED (0x20)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_exit_extended-0x20) + /// [SYS_EXIT_EXTENDED (0x20)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-exit_extended-0x20) pub const SYS_EXIT_EXTENDED: Self = Self(0x20); - /// [SYS_ELAPSED (0x30)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_elapsed-0x30) + /// [SYS_ELAPSED (0x30)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-elapsed-0x30) pub const SYS_ELAPSED: Self = Self(0x30); - /// [SYS_TICKFREQ (0x31)](https://github.com/ARM-software/abi-aa/blob/HEAD/semihosting/semihosting.rst#sys_tickfreq-0x31) + /// [SYS_TICKFREQ (0x31)](https://github.com/ARM-software/abi-aa/blob/2024Q3/semihosting/semihosting.rst#sys-tickfreq-0x31) pub const SYS_TICKFREQ: Self = Self(0x31); #[inline] // inline to help compiler to remove assertion diff --git a/src/sys/mips/mod.rs b/src/sys/mips/mod.rs index 164db9d..44f806d 100644 --- a/src/sys/mips/mod.rs +++ b/src/sys/mips/mod.rs @@ -4,7 +4,7 @@ //! //! Refs: //! - Unified Hosting Interface. MD01069 Reference Manual -//! - +//! - #![allow(clippy::missing_safety_doc)] // TODO diff --git a/tests/no-std-rt/riscv-common.ld b/tests/no-std-rt/riscv-common.ld index c3b45ed..0624638 100644 --- a/tests/no-std-rt/riscv-common.ld +++ b/tests/no-std-rt/riscv-common.ld @@ -23,7 +23,7 @@ SECTIONS .eh_frame : { KEEP(*(.eh_frame)) *(.eh_frame.*) } /* https://github.com/riscv-non-isa/riscv-eabi-spec/blob/HEAD/EABI.adoc#eabi-stack-alignment */ - /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/HEAD/riscv-elf.adoc#tag_riscv_stack_align-4-uleb128value */ + /* https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/draft-20240829-13bfa9f54634cb60d86b9b333e109f077805b4b3/riscv-elf.adoc#tag_riscv_stack_align-4-uleb128value */ . = ALIGN(16); PROVIDE(_stack = . + 8M); } diff --git a/tests/no-std-rt/riscv32.ld b/tests/no-std-rt/riscv32.ld index 73654ff..99aff47 100644 --- a/tests/no-std-rt/riscv32.ld +++ b/tests/no-std-rt/riscv32.ld @@ -4,7 +4,7 @@ ENTRY(_start) -/* https://github.com/riscv-software-src/opensbi/blob/v1.4/platform/generic/objects.mk#L25-L34 */ -FW_JUMP_ADDR = 0x80000000 + 0x400000; +/* https://github.com/riscv-software-src/opensbi/blob/v1.5.1/platform/template/objects.mk#L73 */ +FW_JUMP_ADDR = 0x80400000; INCLUDE riscv-common.ld diff --git a/tests/no-std-rt/riscv64.ld b/tests/no-std-rt/riscv64.ld index 1d1bc75..8e9d2e3 100644 --- a/tests/no-std-rt/riscv64.ld +++ b/tests/no-std-rt/riscv64.ld @@ -4,7 +4,7 @@ ENTRY(_start) -/* https://github.com/riscv-software-src/opensbi/blob/v1.4/platform/generic/objects.mk#L25-L34 */ -FW_JUMP_ADDR = 0x80000000 + 0x200000; +/* https://github.com/riscv-software-src/opensbi/blob/v1.5.1/platform/template/objects.mk#L75 */ +FW_JUMP_ADDR = 0x80200000; INCLUDE riscv-common.ld diff --git a/tests/no-std/src/main.rs b/tests/no-std/src/main.rs index 97b40f7..d546e86 100644 --- a/tests/no-std/src/main.rs +++ b/tests/no-std/src/main.rs @@ -183,7 +183,7 @@ fn run() { let errno = file.read(&mut buf[..]).unwrap_err().raw_os_error().unwrap(); assert!(errno == 22 || errno == 9, "{}", errno); } else { - // TODO: if no read permission, arm semihosting handles it like eof. + // TODO: if no read permission, Arm semihosting handles it like eof. assert_eq!(file.read(&mut buf[..]).unwrap(), 0); } assert_eq!( diff --git a/tools/no-std.sh b/tools/no-std.sh index fb3b920..92555da 100755 --- a/tools/no-std.sh +++ b/tools/no-std.sh @@ -16,32 +16,31 @@ default_targets=( aarch64-unknown-none aarch64-unknown-none-softfloat - # armv4t + # arm + # v4T armv4t-none-eabi thumbv4t-none-eabi - # armv5te + # v5TE armv5te-none-eabi thumbv5te-none-eabi - - # armv7-a + # v7-A armv7a-none-eabi armv7a-none-eabihf - # armv7-r + # v7-R armv7r-none-eabi armv7r-none-eabihf armebv7r-none-eabi armebv7r-none-eabihf - # armv8-r + # v8-R armv8r-none-eabihf armebv8r-none-eabihf # custom target - - # armv6-m + # v6-M thumbv6m-none-eabi - # armv7-m + # v7-M thumbv7m-none-eabi thumbv7em-none-eabi thumbv7em-none-eabihf - # armv8-m + # v8-M thumbv8m.base-none-eabi thumbv8m.main-none-eabi thumbv8m.main-none-eabihf @@ -175,7 +174,7 @@ run() { ;; armebv7r*) if [[ "${llvm_version}" -lt 17 ]]; then - # pre-17 LLD doesn't support big-endian arm + # pre-17 LLD doesn't support big-endian Arm target_rustflags+=" -C linker=arm-none-eabi-ld -C link-arg=-EB" fi ;; diff --git a/tools/qemu-system-runner.sh b/tools/qemu-system-runner.sh index e03358e..1525b99 100755 --- a/tools/qemu-system-runner.sh +++ b/tools/qemu-system-runner.sh @@ -77,7 +77,7 @@ case "${target}" in qemu_system arm -M lm3s6965evb -cpu cortex-m4 ;; thumbv8m.base-*) - # TODO: As of QEMU 8.2, QEMU doesn't support -cpu cortex-m23 + # TODO: As of QEMU 9.1, QEMU doesn't support -cpu cortex-m23 qemu_system arm -M lm3s6965evb -cpu cortex-m33 ;; thumbv8m.main-*) @@ -89,16 +89,16 @@ case "${target}" in ;; # Cortex-R (AArch32) armv7r* | armebv7r*) - # TODO: As of qemu 7.2, qemu-system-arm doesn't support Cortex-R machine. - # TODO: mps3-an536 added in QEMU 9.0 is Cortex-R52 board (ARMv8-R AArch32) + # TODO: As of QEMU 8.2, qemu-system-arm doesn't support Cortex-R machine. + # TODO: mps3-an536 added in QEMU 9.0 is Cortex-R52 board (Armv8-R AArch32) qemu_system arm -M xilinx-zynq-a9 ;; armv8r* | armebv8r*) - # TODO: As of qemu 7.2, qemu-system-arm doesn't support Cortex-R machine. - # TODO: mps3-an536 added in QEMU 9.0 is Cortex-R52 board (ARMv8-R AArch32) + # TODO: As of QEMU 8.2, qemu-system-arm doesn't support Cortex-R machine. + # TODO: mps3-an536 added in QEMU 9.0 is Cortex-R52 board (Armv8-R AArch32) qemu_system arm -M xilinx-zynq-a9 ;; - # ARMv4T + # Armv4T armv4t* | thumbv4t*) # qemu-system-arm -M help | grep -E '9.*T|SA-|OMAP310' # all passed: N/A # TODO @@ -108,7 +108,7 @@ case "${target}" in # not worked: N/A qemu_system arm -M cheetah ;; - # ARMv5TE + # Armv5TE armv5te* | thumbv5te*) qemu_system arm -M versatilepb -cpu arm926 ;; diff --git a/tools/qemu-user-runner.sh b/tools/qemu-user-runner.sh index edc807c..6a6613e 100755 --- a/tools/qemu-user-runner.sh +++ b/tools/qemu-user-runner.sh @@ -50,7 +50,7 @@ case "${target}" in qemu_user arm -cpu cortex-m4 ;; thumbv8m.base-*) - # TODO: As of QEMU 8.2, QEMU doesn't support -cpu cortex-m23 + # TODO: As of QEMU 9.1, QEMU doesn't support -cpu cortex-m23 qemu_user arm -cpu cortex-m33 ;; thumbv8m.main-*) @@ -82,7 +82,7 @@ case "${target}" in armebv8r*) qemu_user armeb -cpu cortex-r52 ;; - # ARMv4T + # Armv4T armv4t* | thumbv4t*) # qemu-system-arm -cpu help | grep -E '9.*t|sa1' # all passed: @@ -90,10 +90,10 @@ case "${target}" in # exit-only passed: # - sa1110, sa1100 (StrongARM) # not worked: N/A - # https://github.com/qemu/qemu/blob/74c581b6452394e591f13beba9fea2ec0688e2f5/target/arm/cpu_tcg.c#L913 + # https://github.com/qemu/qemu/blob/v9.1.0/target/arm/tcg/cpu32.c#L778 qemu_user arm -cpu ti925t ;; - # ARMv5TE + # Armv5TE armv5te* | thumbv5te*) qemu_user arm -cpu arm926 ;;