Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
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Updated
Oct 12, 2024 - Python
Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
DRAMSim2: A cycle accurate DRAM simulator
**No Longer Maintained** Official RAMCloud repo
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
MCMC toolbox for Matlab
A High-Level DRAM Timing, Power and Area Exploration Tool
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
Experimental study and analysis on the effect of using a wide range of different supply voltage values on the reliability, latency, and retention characteristics of DDR3L DRAM SO-DIMMs
This is a repository for the ParaMonte library examples. For more information, visit:
Circuit-level model for the Capacity-Latency Reconfigurable DRAM (CLR-DRAM) architecture. This repository contains the SPICE models of the CLR-DRAM architecture and the baseline architecture used in our ISCA 2020 paper "Luo et al., CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off": https://people.inf.ethz.ch/omu…
A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
This repository provides characterization data collected over 96 DDR3 SO-DIMMs, related to the following paper: Lee et al., "Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms", SIGMETRICS 2017. https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf
Bayesian Inference. Parallel implementations of DREAM, DE-MC and DRAM.
Implementation of flush + reload attack to extract private key from the GnuPG implementation of RSA.
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
MIPS simulator, which implements reordering of DRAM requests during runtime to reduce the clock cycles during execution
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