Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)
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Updated
Sep 9, 2024 - Verilog
Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
Generate folded-cascode opamp parameters with interactive CLI.
This repository has code for a Python program that synthesizes an optical filter
Deadlines for Conferences which are relevant to the research topics of E&D
A Ngspice ASCII rawfile parser written in Javascript.
Blockdiagramm is a graphical block design tool for IC design
Design & Implementation of Multi Clock Domain System using Verilog HDL
NTUEE IC Design 24Spring Final
A tool for rendering GDS2 layout files to PDF (using cairographics) or to TikZ code.
NCTU 2022 Spring Integrated Circuit Design Laboratory
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