iverilog

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Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

simulation rtl risc-v iverilog

A MIPS softcore processor to average images together and output to VGA on a Nexys 4 DDR FPGA.

python opencv school fpga matlab verilog xilinx vivado vga iverilog mips-softcore-processor

Internship at VSD on RISC-V and VLSI using VSDSquadron Mini Board

embedded internship projects gcc-complier gtkwave vlsi verilog-hdl risc-v iverilog vlsi-design

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