modelsim

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Here are 192 public repositories matching this topic...

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Dec 12, 2024
Python

mshr-h / vscode-verilog-hdl-support

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HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Dec 7, 2024
TypeScript

tymonx / logic

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

loykylewong / FPGA-Application-Development-and-Simulation

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《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).

Updated Oct 18, 2024
SystemVerilog

Paebbels / JSON-for-VHDL

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A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Sep 5, 2022
VHDL

suoto / vim-hdl

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Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog modelsim

Updated Jun 1, 2021
Python

RomeoMe5 / DDLM

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Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

25th-engineer / HFUT_2020_MIPS_CPU

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合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

cpu verilog vivado modelsim mips-c3

Updated Sep 25, 2020
Assembly

prajwalgekkouga / AHB-to-APB-Bridge

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The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

fpga digital verilog modelsim amba apb ahb verilog-project

Updated Oct 7, 2022
Verilog

MJoergen / HyperRAM

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Portable HyperRAM controller

fpga vhdl intel xilinx vivado altera lattice modelsim questasim avalon quartus artix questa hyperram

Updated Dec 8, 2024
VHDL

arthurmteodoro / install-quartus-linux

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Tutorial de instalação do Quartus Prime no Linux

fpga install-script modelsim quartus-prime quartus-linux fpga-linux

Updated Oct 16, 2019
Shell

DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

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The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

fpga vivado modelsim canny