modelsim

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合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。

cpu verilog vivado modelsim mips-c3

A single cycle circuit design with additional instrucitons like JRS, ORI, BGZEAL, SLLV, JMSUB, BALV on ModelSim Simulator is implemented.

mips assembly modelsim computer-organization

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