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modelsim

Here are 64 public repositories matching this topic...

RomeoMe5 / DDLM

Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)

Updated Sep 15, 2023
Verilog

prajwalgekkouga / AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

fpga digital verilog modelsim amba apb ahb verilog-project

Updated Oct 7, 2022
Verilog

DOUDIU / Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm

The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA boards, including those from Xilinx and Altera.

fpga vivado modelsim canny

Updated Apr 22, 2024
Verilog

LamaNIkesh / MScFPGAStuff

My MSc Thesis: Low Latency Router Microarchitecture for Network-on-Chip Implemented on an FPGA

fpga verilog modelsim network-on-chip

Updated Jun 26, 2018
Verilog

kimianoorbakhsh / Verilog-Matrix-Multiplier

Final Project for Digital Systems Design Course, Fall 2020

verilog xilinx modelsim digital-system-design

Updated Jul 20, 2022
Verilog

Shahriar-0 / Computer-Architecture-Course-Projects-S2023

Verilog implementation of a DFS search and RISC-V processor in Single-Cycle, Multi-Cycle and Pipeline

verilog dfs modelsim riscv-assembly riscv-cpu

Updated Mar 25, 2024
Verilog

tharinduSamare / Multicore_processor_verilog_design

This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.

fpga simulation verilog modelsim quartus-prime

Updated Jan 8, 2022
Verilog

fardinabbasi / RISC-V_Processor_Pipelined

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

verilog computer-architecture modelsim risc-v digital-systems computer-arithmetic pipelined-processors

Updated Aug 13, 2024
Verilog

EmreKumas / Processor_Design

This is an implementation of a simple CPU in Logisim and Verilog.

cpu instructions assembler alu logisim modelsim control-unit cpu-design cpu-simulation register-file data-memory address-memory

Updated Jan 11, 2019
Verilog

Bennyaw / SimpleProcessor_Verilog

A simple processor designed using Verilog and Altera DE1 development board.

simple modelsim verilog-hdl quartus processor-design altera-de1

Updated Apr 22, 2020
Verilog

erfanasgari21 / Computer_Architecture_Lab_ARM

Implementation of ARM968E-S processor for Computer Architecture Lab [Spring 2024]

arm verilog computer-architecture modelsim quartus

Updated Jul 15, 2024
Verilog

Daniyar1239 / AES-encryption-in-Verilog

AES encryption and decryption algorithms implemented in Verilog programming language

cryptography encryption aes aes-256 aes-128 verilog aes-encryption encryption-algorithm modelsim encryption-decryption decryption-algorithm verilog-project

Updated Dec 15, 2022
Verilog

Shahriar-0 / Computer-Aided-Design-Course-Projects-F2024

Implementing different neural networks using hardware and ModelSim.

neural-network cnn synthesis modelsim maxnet actel

Updated Feb 9, 2024
Verilog

OmarAmer01 / VP_Harvard_MIPS

A 32-bit microprocessor with 42 instructions (including multiplication and division) and 8 X 32 registers and 2048 X 32 Ram with shared stack. An assembler is also available to write programs on the microprocessor using 8086-like assembly.

mips verilog computer-architecture vlsi modelsim single-cycle-processor

Updated Feb 19, 2022
Verilog

EslamAsHhraf / Serial-Peripheral-Interface

📡 In this project, we only focus on the Multi-Slave Regular Mode. We design and implement the following components of the SPI modules using Verilog such that they match the requirements of the development testbench and match the SPI specifications (Master - Slave - Self-Checking Testbenches for the Master and Slave)

master-slave verilog modelsim cufe-2024

Updated Oct 16, 2023
Verilog

Kanishk-K-U / AHB2APB-Bridge-Controller

Designed AHB to APB Bridge Controller using Verilog and simulated it on ModelSIM

bus rtl verilog modelsim verilog-hdl bridge-controller

Updated Nov 29, 2022
Verilog

RDSik / verilog-transceiver

Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

python docker fpga chocolatey verilog make vivado icarus-verilog modelsim testbench winget cocotb hdlmake

Updated Dec 4, 2024
Verilog

KevinWang96 / EE577b-HW

modelsim verilog-hdl synopsys-dc cadence-conformal

Updated Apr 3, 2020
Verilog

ayushgupta98 / Ascii-to-Binary-Converter

ASCII to Binary Converter

ascii verilog modelsim ascii-to-binary

Updated Nov 22, 2018
Verilog

Saadia-Hassan / Traffic-Light-Controller-Using-FSM

An automatic traffic light controller is designed and simulated using the concept of Finite State Machine in ModelSim.

simulation finite-state-machine modelsim verilog-hdl moore-machine sequential-circuits

Updated Jul 27, 2020
Verilog

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