A sample design of Nios with on-board SDRAM for CYC1000 (a low cost Cyclone10 FPGA board)
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Jul 8, 2021 - Verilog
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nios2
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FPGA SOC Mario NES in SystemVerilog. Built on a DE-10 Lite FPGA, synthesized in Quartus Prime 18.1
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Dec 16, 2021 - Verilog
Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.
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Apr 13, 2017 - Verilog
Designing a simple processor system on FPGA. This is demo project to test FPGA DE10-Standard and develop a simpe Nios2 app.
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Aug 19, 2021 - Verilog
Hardware acceleration of image scaling
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Feb 15, 2024 - Verilog
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