#

pipelined-processors

Here are 34 public repositories matching this topic...

Chaosinflesh / tagged-branch-predictor

Investigating the use of hint bits in JUMP statements for pipelined CPU branch predictors

high-performance-computing code-optimization branch-prediction pipelined-processors

Updated Oct 6, 2022

helcsnewsxd / famaf-computer_science-computer_architecture-lab2

Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

python c processor-architecture analysis optimization processor assembly lab university-project qemu out-of-order system-verilog armv8 quartus hardware-description-language pipelined-processors in-order-pipeline-architecture processor-simulation famaf-unc

Updated Jul 23, 2024
Assembly

anasdeis / MIPS-Pipelined-Processor

Standard five-stage pipelined 32-bit MIPS processor with hazard detection

vhdl mips-architecture pipelined-processors

Updated Sep 16, 2021
VHDL

bori00 / DataForwardingMIPS

hazard-detection risc pipelined-processors

Updated Jan 10, 2022
VHDL

tylerfeldman321 / Crane-Game

Crane Game using Custom Pipelined Processor

arduino mechanical-engineering assembly-language verilog-hdl 3d-printing stepper-motor-control laser-cutting circuit-design pipelined-processors

Updated Sep 17, 2022
VHDL

helcsnewsxd / famaf-computer_science-computer_architecture

Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

processor-architecture optimization labs theory computer-architecture system-verilog armv8 quartus hardware-description-language pipelined-processors university-subjects famaf-unc

Updated Jul 24, 2024
SystemVerilog

ce-box / CE4302-vector-processor

Vector ASIP for the application of filters to an image 🖼️

fpga vhdl computer-architecture vector-processor pipelined-processors

Updated May 19, 2022
SystemVerilog

valerii-martell / Pipelined-Calculators-FPGA

A set of pipelined calculators for computing various complex mathematical functions

fpga pipeline vhdl pipelined-processors

Updated Aug 22, 2022
VHDL

abdulkhan94 / Computer-Design-and-Prototyping

MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency

multicore pipelined-processors cache-coherency

Updated Jun 1, 2017
SystemVerilog

bori00 / TomasuloAlgorithm

concurrency hazard-detection tomasulo-algorithm pipelined-processors

Updated Jan 10, 2022
VHDL

AbdelrahmanHamdyy / RISC-Pipelined-Processor

5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.

memory assembler verilog systemverilog computer-architecture interrupts hazards pipelined-processors alu-digital-circuit

Updated Jan 7, 2023
SystemVerilog

avikram2 / RISCVPipelinedProcessor

Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.

cache riscv32 victim-cache pipelined-processors set-associative-cache pipelined-risc

Updated Dec 23, 2022
Verilog

Cambrian34 / Cs-385-Semester-Project

16-bit 5 stage pipelined Mips processor

mips project verilog 16-bit risc-v pipelined-processors

Updated Sep 16, 2024
Verilog

anyakara / MIPS32-Pipelined-Processor

High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in course on organization of computers.

verilog mips32 pipelined-processors vivado-vitis pipelined-memory

Updated Jun 9, 2024
Verilog

bori00 / StalledMIPS

Structure of Computer Systems course (3rd year, 1st semester)

hazard-detection risc pipelined-processors

Updated Jan 10, 2022
VHDL

sarthakmittal92 / risc-proc

Repository for the course project done as part of CS-230 (Digital Logic Design & Computer Architecture) course at IIT Bombay in Spring 2022.

processor-architecture vhdl risc quartus pipelined-processors

Updated Oct 9, 2022
VHDL

sts08015 / risc-v-lab

Extended Version of COSE222 Lab

verilog systemverilog risc-v pipelined-processors single-cycle-processor

Updated Feb 12, 2023
SystemVerilog

meeeeet / 5-Stage-Pipelined-RISC-V-Processor

risc-v rv32i risc-processor pipelined-processors

Updated Jun 24, 2024
Verilog

DoniaGameel / Pipelined-Processor-using-verilog

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

assembler hazard-detection alu branch-prediction control-unit pipelined-processors full-forwarding

Updated Jan 29, 2023
Verilog

francoriba / MIPSPipeline

Repository for development of lab3

debugging uart mips-architecture mips-simulator pipelined-processors

Updated Oct 27, 2024
Verilog

Improve this page

Add a description, image, and links to the pipelined-processors topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the pipelined-processors topic, visit your repo's landing page and select "manage topics."