The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Unit tests generator for RVV 1.0

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

A translator from ARM NEON intrinsics to RISCV-V Extension implementation

A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)

RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Compliance test).

Examples of Halide language algorithms running on RISC-V

RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite

Chisel RISC-V Vector 1.0 Implementation

Examples of Halide language algorithms running on RISC-V

x86-64, ARM, and RVV intrinsics viewer

MagicMirror² module: Departure monitor for the RVV (Regensburger Verkehrsverbund) bus system (ÖPNV, public transport)

Implements kernels with RISC-V Vector

RISCV Vector Kernel C/LLVM-IR generator

Nuclei AI Library Optimized For RISC-V Vector

Patched version of LLVM to unblock RISC-V vectorization with 0.7.1 ISA

Hair recoloring on RISC-V with OpenCV

Resources for RISC-V Summit Europe 2024 and ORConf 2024 with topic: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study