Model of a noncontiguous segmented memory management unit.

Simulating TLB and its interfacing with Page Table (Virtual memory concepts)

A collection of problem set solutions for NYU CSCI 201 Computer Systems Organization

21Summer-VE370-Intro-to-Computer-Organization-Projects: -Project1: RISC-V Assembly, simluating c code. -Project2: 1.RISC-V64 single cycle processor. 2.RISC-V64 five-stage pipelined processor. -Project3: Virtual memory, TLB, cache, memory simulator. -Project4: Literature review on Computer Organization.

💻 Cache Simulator in Typescript (CLI)

2-level TLB Controller

TLB (Translation Lookaside Buffer) Simulator

Simulates a memory-subsystem encompassing a bi-level TLB and a bi-level cache system along with a main memory following segmentation with paging with all different replacement policies

Operating Systems Laboratory (Semester 5): Includes a Shell, a Page Table and a Translation Lookaside Buffer

Implementation of the Cortex-A53 memory system using a virtual memory simulator to reveal the key steps such as instruction fetch, address generation and computation, tag searches in caches, TLBs and virtual to physical address translations.

A C-Program that simulates Virtual Memory Management based on a text file input of logical addresses which represents sequential instructions with address range 0 thru 2^16 - 1. See the Project Report for more details regarding usage.

Implement Virtual Page Yable Register(VPTR, known as page table, CAM, TLB..etc) in memory.

TLB simulator. LRU priority.